PGMAllBth.h@ 85938

Last change on this file since 85938 was 82968, checked in by vboxsync, 5 years ago
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1	/* $Id: PGMAllBth.h 82968 2020-02-04 10:35:17Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
6	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
7	* bird: WTF does this mean these days? Looking at PGMAll.cpp it's
8	*
9	* @remarks This file is one big \#ifdef-orgy!
10	*
11	*/
12
13	/*
14	* Copyright (C) 2006-2020 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25	#ifdef _MSC_VER
26	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
27	* real/prot-guest+RC mode. */
28	# pragma warning(disable: 4505)
29	#endif
30
31
32	/*********************************************************************************************************************************
33	* Internal Functions *
34	*********************************************************************************************************************************/
35	RT_C_DECLS_BEGIN
36	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
37	#ifndef IN_RING3
38	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
39	#endif
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	#else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu);
57
58	#ifdef IN_RING3
59	PGM_BTH_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
60	#endif
61	RT_C_DECLS_END
62
63
64
65
66	/*
67	* Filter out some illegal combinations of guest and shadow paging, so we can
68	* remove redundant checks inside functions.
69	*/
70	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE \
71	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
72	# error "Invalid combination; PAE guest implies PAE shadow"
73	#endif
74
75	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
76	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \
77	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
78	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
79	#endif
80
81	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
82	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
83	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
84	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
85	#endif
86
87	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE) \
88	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
89	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
90	#endif
91
92
93	/**
94	* Enters the shadow+guest mode.
95	*
96	* @returns VBox status code.
97	* @param pVCpu The cross context virtual CPU structure.
98	* @param GCPhysCR3 The physical address from the CR3 register.
99	*/
100	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
101	{
102	/* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
103	* Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
104	*/
105	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
106	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
107	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
108	&& ( PGM_GST_TYPE == PGM_TYPE_REAL \
109	\|\| PGM_GST_TYPE == PGM_TYPE_PROT))
110
111	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
112
113	Assert((HMIsNestedPagingActive(pVM) \|\| VM_IS_NEM_ENABLED(pVM)) == pVM->pgm.s.fNestedPaging);
114	Assert(!pVM->pgm.s.fNestedPaging);
115
116	pgmLock(pVM);
117	/* Note: we only really need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes),
118	* but any calls to GC need a proper shadow page setup as well.
119	*/
120	/* Free the previous root mapping if still active. */
121	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
122	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
123	if (pOldShwPageCR3)
124	{
125	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
126
127	/* Mark the page as unlocked; allow flushing again. */
128	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
129
130	# ifndef PGM_WITHOUT_MAPPINGS
131	/* Remove the hypervisor mappings from the shadow page table. */
132	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
133	# endif
134
135	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
136	pVCpu->pgm.s.pShwPageCR3R3 = NIL_RTR3PTR;
137	pVCpu->pgm.s.pShwPageCR3R0 = NIL_RTR0PTR;
138	}
139
140	/* construct a fake address. */
141	GCPhysCR3 = RT_BIT_64(63);
142	PPGMPOOLPAGE pNewShwPageCR3;
143	int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
144	NIL_PGMPOOL_IDX, UINT32_MAX, false /fLockPage/,
145	&pNewShwPageCR3);
146	AssertRCReturn(rc, rc);
147
148	pVCpu->pgm.s.pShwPageCR3R3 = (R3PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR3(pVM, pNewShwPageCR3);
149	pVCpu->pgm.s.pShwPageCR3R0 = (R0PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR0(pVM, pNewShwPageCR3);
150
151	/* Mark the page as locked; disallow flushing. */
152	pgmPoolLockPage(pPool, pNewShwPageCR3);
153
154	/* Set the current hypervisor CR3. */
155	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
156
157	# ifndef PGM_WITHOUT_MAPPINGS
158	/* Apply all hypervisor mappings to the new CR3. */
159	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
160	# endif
161
162	pgmUnlock(pVM);
163	return rc;
164	#else
165	NOREF(pVCpu); NOREF(GCPhysCR3);
166	return VINF_SUCCESS;
167	#endif
168	}
169
170
171	#ifndef IN_RING3
172
173	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
174	/**
175	* Deal with a guest page fault.
176	*
177	* @returns Strict VBox status code.
178	* @retval VINF_EM_RAW_GUEST_TRAP
179	* @retval VINF_EM_RAW_EMULATE_INSTR
180	*
181	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
182	* @param pGstWalk The guest page table walk result.
183	* @param uErr The error code.
184	*/
185	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPUCC pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
186	{
187	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
188	/*
189	* Check for write conflicts with our hypervisor mapping.
190	*
191	* If the guest happens to access a non-present page, where our hypervisor
192	* is currently mapped, then we'll create a #PF storm in the guest.
193	*/
194	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
195	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
196	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
197	{
198	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
199	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
200	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
201	return VINF_EM_RAW_EMULATE_INSTR;
202	}
203	# endif
204
205	/*
206	* Calc the error code for the guest trap.
207	*/
208	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
209	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
210	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
211	if ( pGstWalk->Core.fRsvdError
212	\|\| pGstWalk->Core.fBadPhysAddr)
213	{
214	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
215	Assert(!pGstWalk->Core.fNotPresent);
216	}
217	else if (!pGstWalk->Core.fNotPresent)
218	uNewErr \|= X86_TRAP_PF_P;
219	TRPMSetErrorCode(pVCpu, uNewErr);
220
221	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
222	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
223	return VINF_EM_RAW_GUEST_TRAP;
224	}
225	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
226
227
228	#if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
229	/**
230	* Deal with a guest page fault.
231	*
232	* The caller has taken the PGM lock.
233	*
234	* @returns Strict VBox status code.
235	*
236	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
237	* @param uErr The error code.
238	* @param pRegFrame The register frame.
239	* @param pvFault The fault address.
240	* @param pPage The guest page at @a pvFault.
241	* @param pGstWalk The guest page table walk result.
242	* @param pfLockTaken PGM lock taken here or not (out). This is true
243	* when we're called.
244	*/
245	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
246	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
247	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
248	, PGSTPTWALK pGstWalk
249	# endif
250	)
251	{
252	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
253	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
254	# endif
255	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
256	VBOXSTRICTRC rcStrict;
257
258	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
259	{
260	/*
261	* Physical page access handler.
262	*/
263	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
264	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
265	# else
266	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
267	# endif
268	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
269	if (pCur)
270	{
271	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
272
273	# ifdef PGM_SYNC_N_PAGES
274	/*
275	* If the region is write protected and we got a page not present fault, then sync
276	* the pages. If the fault was caused by a read, then restart the instruction.
277	* In case of write access continue to the GC write handler.
278	*
279	* ASSUMES that there is only one handler per page or that they have similar write properties.
280	*/
281	if ( !(uErr & X86_TRAP_PF_P)
282	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
283	{
284	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
285	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
286	# else
287	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
288	# endif
289	if ( RT_FAILURE(rcStrict)
290	\|\| !(uErr & X86_TRAP_PF_RW)
291	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
292	{
293	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
294	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
295	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
296	return rcStrict;
297	}
298	}
299	# endif
300	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
301	/*
302	* If the access was not thru a #PF(RSVD\|...) resync the page.
303	*/
304	if ( !(uErr & X86_TRAP_PF_RSVD)
305	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
306	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
307	&& pGstWalk->Core.fEffectiveRW
308	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
309	# endif
310	)
311	{
312	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
313	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
314	# else
315	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
316	# endif
317	if ( RT_FAILURE(rcStrict)
318	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
319	{
320	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
321	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
322	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
323	return rcStrict;
324	}
325	}
326	# endif
327
328	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
329	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
330	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
331	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
332	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
333	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
334	else
335	{
336	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
337	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
338	}
339
340	if (pCurType->CTX_SUFF(pfnPfHandler))
341	{
342	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
343	void *pvUser = pCur->CTX_SUFF(pvUser);
344
345	STAM_PROFILE_START(&pCur->Stat, h);
346	if (pCur->hType != pPool->hAccessHandlerType)
347	{
348	pgmUnlock(pVM);
349	*pfLockTaken = false;
350	}
351
352	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
353
354	# ifdef VBOX_WITH_STATISTICS
355	pgmLock(pVM);
356	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
357	if (pCur)
358	STAM_PROFILE_STOP(&pCur->Stat, h);
359	pgmUnlock(pVM);
360	# endif
361	}
362	else
363	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
364
365	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
366	return rcStrict;
367	}
368	}
369
370	/*
371	* There is a handled area of the page, but this fault doesn't belong to it.
372	* We must emulate the instruction.
373	*
374	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
375	* we first check if this was a page-not-present fault for a page with only
376	* write access handlers. Restart the instruction if it wasn't a write access.
377	*/
378	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
379
380	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
381	&& !(uErr & X86_TRAP_PF_P))
382	{
383	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
384	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
385	# else
386	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
387	# endif
388	if ( RT_FAILURE(rcStrict)
389	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
390	\|\| !(uErr & X86_TRAP_PF_RW))
391	{
392	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
393	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
394	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
395	return rcStrict;
396	}
397	}
398
399	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
400	* It's writing to an unhandled part of the LDT page several million times.
401	*/
402	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
403	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
404	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
405	return rcStrict;
406	} /* if any kind of handler */
407	# endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE*/
408
409
410	/**
411	* \#PF Handler for raw-mode guest execution.
412	*
413	* @returns VBox status code (appropriate for trap handling and GC return).
414	*
415	* @param pVCpu The cross context virtual CPU structure.
416	* @param uErr The trap error code.
417	* @param pRegFrame Trap register frame.
418	* @param pvFault The fault address.
419	* @param pfLockTaken PGM lock taken here or not (out)
420	*/
421	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
422	{
423	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
424
425	*pfLockTaken = false;
426
427	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
428	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
429	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
430	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
431	&& PGM_SHW_TYPE != PGM_TYPE_NONE
432	int rc;
433
434	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
435	/*
436	* Walk the guest page translation tables and check if it's a guest fault.
437	*/
438	GSTPTWALK GstWalk;
439	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
440	if (RT_FAILURE_NP(rc))
441	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
442
443	/* assert some GstWalk sanity. */
444	# if PGM_GST_TYPE == PGM_TYPE_AMD64
445	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
446	# endif
447	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
448	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
449	# endif
450	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
451	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
452	Assert(GstWalk.Core.fSucceeded);
453
454	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
455	{
456	if ( ( (uErr & X86_TRAP_PF_RW)
457	&& !GstWalk.Core.fEffectiveRW
458	&& ( (uErr & X86_TRAP_PF_US)
459	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
460	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
461	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
462	)
463	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
464	}
465
466	/*
467	* Set the accessed and dirty flags.
468	*/
469	# if PGM_GST_TYPE == PGM_TYPE_AMD64
470	GstWalk.Pml4e.u \|= X86_PML4E_A;
471	GstWalk.pPml4e->u \|= X86_PML4E_A;
472	GstWalk.Pdpe.u \|= X86_PDPE_A;
473	GstWalk.pPdpe->u \|= X86_PDPE_A;
474	# endif
475	if (GstWalk.Core.fBigPage)
476	{
477	Assert(GstWalk.Pde.b.u1Size);
478	if (uErr & X86_TRAP_PF_RW)
479	{
480	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
481	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
482	}
483	else
484	{
485	GstWalk.Pde.u \|= X86_PDE4M_A;
486	GstWalk.pPde->u \|= X86_PDE4M_A;
487	}
488	}
489	else
490	{
491	Assert(!GstWalk.Pde.b.u1Size);
492	GstWalk.Pde.u \|= X86_PDE_A;
493	GstWalk.pPde->u \|= X86_PDE_A;
494	if (uErr & X86_TRAP_PF_RW)
495	{
496	# ifdef VBOX_WITH_STATISTICS
497	if (!GstWalk.Pte.n.u1Dirty)
498	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
499	else
500	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
501	# endif
502	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
503	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
504	}
505	else
506	{
507	GstWalk.Pte.u \|= X86_PTE_A;
508	GstWalk.pPte->u \|= X86_PTE_A;
509	}
510	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
511	}
512	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
513	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
514	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
515	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
516	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
517
518	/* Take the big lock now. */
519	*pfLockTaken = true;
520	pgmLock(pVM);
521
522	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
523	/*
524	* If it is a reserved bit fault we know that it is an MMIO (access
525	* handler) related fault and can skip some 200 lines of code.
526	*/
527	if (uErr & X86_TRAP_PF_RSVD)
528	{
529	Assert(uErr & X86_TRAP_PF_P);
530	PPGMPAGE pPage;
531	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
532	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
533	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
534	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
535	pfLockTaken, &GstWalk));
536	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
537	# else
538	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
539	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
540	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
541	pfLockTaken));
542	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
543	# endif
544	AssertRC(rc);
545	PGM_INVL_PG(pVCpu, pvFault);
546	return rc; /* Restart with the corrected entry. */
547	}
548	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
549
550	/*
551	* Fetch the guest PDE, PDPE and PML4E.
552	*/
553	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
554	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
555	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
556
557	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
558	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
559	PX86PDPAE pPDDst;
560	# if PGM_GST_TYPE == PGM_TYPE_PAE
561	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
562	# else
563	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
564	# endif
565	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
566
567	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
568	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
569	PX86PDPAE pPDDst;
570	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
571	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
572	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
573	# else
574	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
575	# endif
576	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
577
578	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
579	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
580	PEPTPD pPDDst;
581	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
582	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
583	# endif
584	Assert(pPDDst);
585
586	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
587	/*
588	* Dirty page handling.
589	*
590	* If we successfully correct the write protection fault due to dirty bit
591	* tracking, then return immediately.
592	*/
593	if (uErr & X86_TRAP_PF_RW) /* write fault? */
594	{
595	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
596	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
597	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
598	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
599	{
600	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
601	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
602	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
603	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
604	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
605	return VINF_SUCCESS;
606	}
607	#ifdef DEBUG_bird
608	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
609	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
610	#endif
611	}
612
613	# if 0 /* rarely useful; leave for debugging. */
614	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
615	# endif
616	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
617
618	/*
619	* A common case is the not-present error caused by lazy page table syncing.
620	*
621	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
622	* here so we can safely assume that the shadow PT is present when calling
623	* SyncPage later.
624	*
625	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
626	* of mapping conflict and defer to SyncCR3 in R3.
627	* (Again, we do NOT support access handlers for non-present guest pages.)
628	*
629	*/
630	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
631	Assert(GstWalk.Pde.n.u1Present);
632	# endif
633	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
634	&& !pPDDst->a[iPDDst].n.u1Present)
635	{
636	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
637	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
638	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
639	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
640	# else
641	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
642	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
643	# endif
644	if (RT_SUCCESS(rc))
645	return rc;
646	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
647	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
648	return VINF_PGM_SYNC_CR3;
649	}
650
651	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
652	/*
653	* Check if this address is within any of our mappings.
654	*
655	* This is very fast and it's gonna save us a bit of effort below and prevent
656	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
657	* (BTW, it's impossible to have physical access handlers in a mapping.)
658	*/
659	if (pgmMapAreMappingsEnabled(pVM))
660	{
661	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
662	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
663	{
664	if (pvFault < pMapping->GCPtr)
665	break;
666	if (pvFault - pMapping->GCPtr < pMapping->cb)
667	{
668	/*
669	* The first thing we check is if we've got an undetected conflict.
670	*/
671	if (pgmMapAreMappingsFloating(pVM))
672	{
673	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
674	while (iPT-- > 0)
675	if (GstWalk.pPde[iPT].n.u1Present)
676	{
677	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
678	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
679	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
680	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
681	return VINF_PGM_SYNC_CR3;
682	}
683	}
684
685	/*
686	* Pretend we're not here and let the guest handle the trap.
687	*/
688	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
689	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
690	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
691	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
692	return VINF_EM_RAW_GUEST_TRAP;
693	}
694	}
695	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
696	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
697
698	/*
699	* Check if this fault address is flagged for special treatment,
700	* which means we'll have to figure out the physical address and
701	* check flags associated with it.
702	*
703	* ASSUME that we can limit any special access handling to pages
704	* in page tables which the guest believes to be present.
705	*/
706	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
707	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
708	# else
709	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
710	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
711	PPGMPAGE pPage;
712	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
713	if (RT_FAILURE(rc))
714	{
715	/*
716	* When the guest accesses invalid physical memory (e.g. probing
717	* of RAM or accessing a remapped MMIO range), then we'll fall
718	* back to the recompiler to emulate the instruction.
719	*/
720	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
721	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
722	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
723	return VINF_EM_RAW_EMULATE_INSTR;
724	}
725
726	/*
727	* Any handlers for this page?
728	*/
729	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
730	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
731	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
732	&GstWalk));
733	# else
734	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
735	# endif
736
737	/*
738	* We are here only if page is present in Guest page tables and
739	* trap is not handled by our handlers.
740	*
741	* Check it for page out-of-sync situation.
742	*/
743	if (!(uErr & X86_TRAP_PF_P))
744	{
745	/*
746	* Page is not present in our page tables. Try to sync it!
747	*/
748	if (uErr & X86_TRAP_PF_US)
749	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
750	else /* supervisor */
751	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
752
753	if (PGM_PAGE_IS_BALLOONED(pPage))
754	{
755	/* Emulate reads from ballooned pages as they are not present in
756	our shadow page tables. (Required for e.g. Solaris guests; soft
757	ecc, random nr generator.) */
758	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
759	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
760	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
761	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
762	return rc;
763	}
764
765	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
766	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
767	# else
768	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
769	# endif
770	if (RT_SUCCESS(rc))
771	{
772	/* The page was successfully synced, return to the guest. */
773	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
774	return VINF_SUCCESS;
775	}
776	}
777	else /* uErr & X86_TRAP_PF_P: */
778	{
779	/*
780	* Write protected pages are made writable when the guest makes the
781	* first write to it. This happens for pages that are shared, write
782	* monitored or not yet allocated.
783	*
784	* We may also end up here when CR0.WP=0 in the guest.
785	*
786	* Also, a side effect of not flushing global PDEs are out of sync
787	* pages due to physical monitored regions, that are no longer valid.
788	* Assume for now it only applies to the read/write flag.
789	*/
790	if (uErr & X86_TRAP_PF_RW)
791	{
792	/*
793	* Check if it is a read-only page.
794	*/
795	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
796	{
797	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
798	Assert(!PGM_PAGE_IS_ZERO(pPage));
799	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
800	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
801
802	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
803	if (rc != VINF_SUCCESS)
804	{
805	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
806	return rc;
807	}
808	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
809	return VINF_EM_NO_MEMORY;
810	}
811
812	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
813	/*
814	* Check to see if we need to emulate the instruction if CR0.WP=0.
815	*/
816	if ( !GstWalk.Core.fEffectiveRW
817	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
818	&& CPUMGetGuestCPL(pVCpu) < 3)
819	{
820	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
821
822	/*
823	* The Netware WP0+RO+US hack.
824	*
825	* Netware sometimes(/always?) runs with WP0. It has been observed doing
826	* excessive write accesses to pages which are mapped with US=1 and RW=0
827	* while WP=0. This causes a lot of exits and extremely slow execution.
828	* To avoid trapping and emulating every write here, we change the shadow
829	* page table entry to map it as US=0 and RW=1 until user mode tries to
830	* access it again (see further below). We count these shadow page table
831	* changes so we can avoid having to clear the page pool every time the WP
832	* bit changes to 1 (see PGMCr0WpEnabled()).
833	*/
834	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
835	if ( GstWalk.Core.fEffectiveUS
836	&& !GstWalk.Core.fEffectiveRW
837	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
838	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
839	{
840	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
841	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
842	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
843	{
844	PGM_INVL_PG(pVCpu, pvFault);
845	pVCpu->pgm.s.cNetwareWp0Hacks++;
846	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
847	return rc;
848	}
849	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
850	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
851	}
852	# endif
853
854	/* Interpret the access. */
855	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
856	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
857	if (RT_SUCCESS(rc))
858	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
859	else
860	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
861	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
862	return rc;
863	}
864	# endif
865	/// @todo count the above case; else
866	if (uErr & X86_TRAP_PF_US)
867	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
868	else /* supervisor */
869	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
870
871	/*
872	* Sync the page.
873	*
874	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
875	* page is not present, which is not true in this case.
876	*/
877	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
878	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
879	# else
880	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
881	# endif
882	if (RT_SUCCESS(rc))
883	{
884	/*
885	* Page was successfully synced, return to guest but invalidate
886	* the TLB first as the page is very likely to be in it.
887	*/
888	# if PGM_SHW_TYPE == PGM_TYPE_EPT
889	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
890	# else
891	PGM_INVL_PG(pVCpu, pvFault);
892	# endif
893	# ifdef VBOX_STRICT
894	RTGCPHYS GCPhys2 = RTGCPHYS_MAX;
895	uint64_t fPageGst = UINT64_MAX;
896	if (!pVM->pgm.s.fNestedPaging)
897	{
898	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
899	AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
900	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
901	}
902	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
903	uint64_t fPageShw = 0;
904	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
905	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
906	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GCPhys2, fPageGst, pvFault));
907	# endif
908	# endif /* VBOX_STRICT */
909	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
910	return VINF_SUCCESS;
911	}
912	}
913	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
914	/*
915	* Check for Netware WP0+RO+US hack from above and undo it when user
916	* mode accesses the page again.
917	*/
918	else if ( GstWalk.Core.fEffectiveUS
919	&& !GstWalk.Core.fEffectiveRW
920	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
921	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
922	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
923	&& CPUMGetGuestCPL(pVCpu) == 3
924	&& pVM->cCpus == 1
925	)
926	{
927	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
928	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
929	if (RT_SUCCESS(rc))
930	{
931	PGM_INVL_PG(pVCpu, pvFault);
932	pVCpu->pgm.s.cNetwareWp0Hacks--;
933	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
934	return VINF_SUCCESS;
935	}
936	}
937	# endif /* PGM_WITH_PAGING */
938
939	/** @todo else: why are we here? */
940
941	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
942	/*
943	* Check for VMM page flags vs. Guest page flags consistency.
944	* Currently only for debug purposes.
945	*/
946	if (RT_SUCCESS(rc))
947	{
948	/* Get guest page flags. */
949	uint64_t fPageGst;
950	int rc2 = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
951	if (RT_SUCCESS(rc2))
952	{
953	uint64_t fPageShw = 0;
954	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
955
956	#if 0
957	/*
958	* Compare page flags.
959	* Note: we have AVL, A, D bits desynced.
960	*/
961	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
962	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
963	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
964	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
965	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
966	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
967	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
968	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
969	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
970	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
971	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
972
973	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
974	01:01:15.625516 00:08:43.268051 Location :
975	e:\vbox\svn\trunk\srcPage flags mismatch!
976	pvFault=fffff801b0d7b000
977	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
978	GCPhys=0000000019b52000
979	fPageShw=0
980	fPageGst=77b0000000000121
981	rc=0
982	#endif
983
984	}
985	else
986	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
987	}
988	else
989	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
990	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
991	}
992
993
994	/*
995	* If we get here it is because something failed above, i.e. most like guru
996	* meditiation time.
997	*/
998	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
999	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1000	return rc;
1001
1002	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE. */
1003	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1004	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1005	return VERR_PGM_NOT_USED_IN_MODE;
1006	# endif
1007	}
1008
1009	#endif /* !IN_RING3 */
1010
1011
1012	/**
1013	* Emulation of the invlpg instruction.
1014	*
1015	*
1016	* @returns VBox status code.
1017	*
1018	* @param pVCpu The cross context virtual CPU structure.
1019	* @param GCPtrPage Page to invalidate.
1020	*
1021	* @remark ASSUMES that the guest is updating before invalidating. This order
1022	* isn't required by the CPU, so this is speculative and could cause
1023	* trouble.
1024	* @remark No TLB shootdown is done on any other VCPU as we assume that
1025	* invlpg emulation is the only reason for calling this function.
1026	* (The guest has to shoot down TLB entries on other CPUs itself)
1027	* Currently true, but keep in mind!
1028	*
1029	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1030	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1031	*/
1032	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1033	{
1034	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1035	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
1036	&& PGM_SHW_TYPE != PGM_TYPE_NONE
1037	int rc;
1038	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1039	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1040
1041	PGM_LOCK_ASSERT_OWNER(pVM);
1042
1043	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1044
1045	/*
1046	* Get the shadow PD entry and skip out if this PD isn't present.
1047	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1048	*/
1049	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1050	const unsigned iPDDst = (uint32_t)GCPtrPage >> SHW_PD_SHIFT;
1051	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1052
1053	/* Fetch the pgm pool shadow descriptor. */
1054	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1055	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1056	if (!pShwPde)
1057	{
1058	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1059	return VINF_SUCCESS;
1060	}
1061	# else
1062	Assert(pShwPde);
1063	# endif
1064
1065	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1066	const unsigned iPdpt = (uint32_t)GCPtrPage >> X86_PDPT_SHIFT;
1067	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1068
1069	/* If the shadow PDPE isn't present, then skip the invalidate. */
1070	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1071	if (!pPdptDst \|\| !pPdptDst->a[iPdpt].n.u1Present)
1072	# else
1073	if (!pPdptDst->a[iPdpt].n.u1Present)
1074	# endif
1075	{
1076	Assert(!pPdptDst \|\| !(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1077	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1078	PGM_INVL_PG(pVCpu, GCPtrPage);
1079	return VINF_SUCCESS;
1080	}
1081
1082	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1083	PPGMPOOLPAGE pShwPde = NULL;
1084	PX86PDPAE pPDDst;
1085
1086	/* Fetch the pgm pool shadow descriptor. */
1087	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1088	AssertRCSuccessReturn(rc, rc);
1089	Assert(pShwPde);
1090
1091	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1092	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1093
1094	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1095	/* PML4 */
1096	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1097	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1098	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1099	PX86PDPAE pPDDst;
1100	PX86PDPT pPdptDst;
1101	PX86PML4E pPml4eDst;
1102	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1103	if (rc != VINF_SUCCESS)
1104	{
1105	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1106	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1107	PGM_INVL_PG(pVCpu, GCPtrPage);
1108	return VINF_SUCCESS;
1109	}
1110	Assert(pPDDst);
1111
1112	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1113	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1114
1115	if (!pPdpeDst->n.u1Present)
1116	{
1117	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1118	PGM_INVL_PG(pVCpu, GCPtrPage);
1119	return VINF_SUCCESS;
1120	}
1121
1122	/* Fetch the pgm pool shadow descriptor. */
1123	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1124	Assert(pShwPde);
1125
1126	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1127
1128	const SHWPDE PdeDst = *pPdeDst;
1129	if (!PdeDst.n.u1Present)
1130	{
1131	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1132	PGM_INVL_PG(pVCpu, GCPtrPage);
1133	return VINF_SUCCESS;
1134	}
1135
1136	/*
1137	* Get the guest PD entry and calc big page.
1138	*/
1139	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1140	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1141	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
1142	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1143	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1144	unsigned iPDSrc = 0;
1145	# if PGM_GST_TYPE == PGM_TYPE_PAE
1146	X86PDPE PdpeSrcIgn;
1147	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1148	# else /* AMD64 */
1149	PX86PML4E pPml4eSrcIgn;
1150	X86PDPE PdpeSrcIgn;
1151	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1152	# endif
1153	GSTPDE PdeSrc;
1154
1155	if (pPDSrc)
1156	PdeSrc = pPDSrc->a[iPDSrc];
1157	else
1158	PdeSrc.u = 0;
1159	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1160	const bool fWasBigPage = RT_BOOL(PdeDst.u & PGM_PDFLAGS_BIG_PAGE);
1161	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1162	if (fWasBigPage != fIsBigPage)
1163	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1164
1165	# ifdef IN_RING3
1166	/*
1167	* If a CR3 Sync is pending we may ignore the invalidate page operation
1168	* depending on the kind of sync and if it's a global page or not.
1169	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1170	*/
1171	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1172	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1173	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1174	&& fIsBigPage
1175	&& PdeSrc.b.u1Global
1176	)
1177	)
1178	# else
1179	if (VM_FF_IS_ANY_SET(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1180	# endif
1181	{
1182	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1183	return VINF_SUCCESS;
1184	}
1185	# endif /* IN_RING3 */
1186
1187	/*
1188	* Deal with the Guest PDE.
1189	*/
1190	rc = VINF_SUCCESS;
1191	if (PdeSrc.n.u1Present)
1192	{
1193	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1194	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1195	# ifndef PGM_WITHOUT_MAPPING
1196	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1197	{
1198	/*
1199	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1200	*/
1201	Assert(pgmMapAreMappingsEnabled(pVM));
1202	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1203	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1204	}
1205	else
1206	# endif /* !PGM_WITHOUT_MAPPING */
1207	if (!fIsBigPage)
1208	{
1209	/*
1210	* 4KB - page.
1211	*/
1212	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1213	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1214
1215	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1216	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1217	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1218	# endif
1219	if (pShwPage->GCPhys == GCPhys)
1220	{
1221	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1222	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1223
1224	PGSTPT pPTSrc;
1225	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1226	if (RT_SUCCESS(rc))
1227	{
1228	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1229	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1230	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1231	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1232	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1233	GCPtrPage, PteSrc.n.u1Present,
1234	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1235	PteSrc.n.u1User & PdeSrc.n.u1User,
1236	(uint64_t)PteSrc.u,
1237	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1238	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1239	}
1240	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1241	PGM_INVL_PG(pVCpu, GCPtrPage);
1242	}
1243	else
1244	{
1245	/*
1246	* The page table address changed.
1247	*/
1248	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1249	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1250	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1251	ASMAtomicWriteSize(pPdeDst, 0);
1252	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1253	PGM_INVL_VCPU_TLBS(pVCpu);
1254	}
1255	}
1256	else
1257	{
1258	/*
1259	* 2/4MB - page.
1260	*/
1261	/* Before freeing the page, check if anything really changed. */
1262	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1263	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1264	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1265	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1266	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1267	# endif
1268	if ( pShwPage->GCPhys == GCPhys
1269	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1270	{
1271	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1272	/** @todo This test is wrong as it cannot check the G bit!
1273	* FIXME */
1274	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1275	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1276	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1277	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1278	{
1279	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1280	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1281	return VINF_SUCCESS;
1282	}
1283	}
1284
1285	/*
1286	* Ok, the page table is present and it's been changed in the guest.
1287	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1288	* We could do this for some flushes in GC too, but we need an algorithm for
1289	* deciding which 4MB pages containing code likely to be executed very soon.
1290	*/
1291	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1292	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1293	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1294	ASMAtomicWriteSize(pPdeDst, 0);
1295	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1296	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1297	}
1298	}
1299	else
1300	{
1301	/*
1302	* Page directory is not present, mark shadow PDE not present.
1303	*/
1304	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1305	{
1306	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1307	ASMAtomicWriteSize(pPdeDst, 0);
1308	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1309	PGM_INVL_PG(pVCpu, GCPtrPage);
1310	}
1311	else
1312	{
1313	Assert(pgmMapAreMappingsEnabled(pVM));
1314	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1315	}
1316	}
1317	return rc;
1318
1319	#else /* guest real and protected mode, nested + ept, none. */
1320	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1321	NOREF(pVCpu); NOREF(GCPtrPage);
1322	return VINF_SUCCESS;
1323	#endif
1324	}
1325
1326	#if PGM_SHW_TYPE != PGM_TYPE_NONE
1327
1328	/**
1329	* Update the tracking of shadowed pages.
1330	*
1331	* @param pVCpu The cross context virtual CPU structure.
1332	* @param pShwPage The shadow page.
1333	* @param HCPhys The physical page we is being dereferenced.
1334	* @param iPte Shadow PTE index
1335	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1336	*/
1337	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1338	RTGCPHYS GCPhysPage)
1339	{
1340	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1341
1342	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1343	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1344	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1345
1346	/* Use the hint we retrieved from the cached guest PT. */
1347	if (pShwPage->fDirty)
1348	{
1349	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1350
1351	Assert(pShwPage->cPresent);
1352	Assert(pPool->cPresent);
1353	pShwPage->cPresent--;
1354	pPool->cPresent--;
1355
1356	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1357	AssertRelease(pPhysPage);
1358	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1359	return;
1360	}
1361	# else
1362	NOREF(GCPhysPage);
1363	# endif
1364
1365	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1366	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1367
1368	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1369	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1370	* 2. write protect all shadowed pages. I.e. implement caching.
1371	*/
1372	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1373
1374	/*
1375	* Find the guest address.
1376	*/
1377	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1378	pRam;
1379	pRam = pRam->CTX_SUFF(pNext))
1380	{
1381	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1382	while (iPage-- > 0)
1383	{
1384	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1385	{
1386	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1387
1388	Assert(pShwPage->cPresent);
1389	Assert(pPool->cPresent);
1390	pShwPage->cPresent--;
1391	pPool->cPresent--;
1392
1393	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1394	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1395	return;
1396	}
1397	}
1398	}
1399
1400	for (;;)
1401	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1402	}
1403
1404
1405	/**
1406	* Update the tracking of shadowed pages.
1407	*
1408	* @param pVCpu The cross context virtual CPU structure.
1409	* @param pShwPage The shadow page.
1410	* @param u16 The top 16-bit of the pPage->HCPhys.
1411	* @param pPage Pointer to the guest page. this will be modified.
1412	* @param iPTDst The index into the shadow table.
1413	*/
1414	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1415	{
1416	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1417
1418	/*
1419	* Just deal with the simple first time here.
1420	*/
1421	if (!u16)
1422	{
1423	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1424	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1425	/* Save the page table index. */
1426	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1427	}
1428	else
1429	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1430
1431	/* write back */
1432	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1433	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1434
1435	/* update statistics. */
1436	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1437	pShwPage->cPresent++;
1438	if (pShwPage->iFirstPresent > iPTDst)
1439	pShwPage->iFirstPresent = iPTDst;
1440	}
1441
1442
1443	/**
1444	* Modifies a shadow PTE to account for access handlers.
1445	*
1446	* @param pVM The cross context VM structure.
1447	* @param pPage The page in question.
1448	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1449	* A (accessed) bit so it can be emulated correctly.
1450	* @param pPteDst The shadow PTE (output). This is temporary storage and
1451	* does not need to be set atomically.
1452	*/
1453	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVMCC pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1454	{
1455	NOREF(pVM); RT_NOREF_PV(fPteSrc);
1456
1457	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1458	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1459	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1460	{
1461	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1462	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1463	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1464	pPteDst->n.u1Present = 1;
1465	pPteDst->n.u1Execute = 1;
1466	pPteDst->n.u1IgnorePAT = 1;
1467	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1468	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1469	# else
1470	if (fPteSrc & X86_PTE_A)
1471	{
1472	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1473	SHW_PTE_SET_RO(*pPteDst);
1474	}
1475	else
1476	SHW_PTE_SET(*pPteDst, 0);
1477	# endif
1478	}
1479	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1480	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1481	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1482	&& ( BTH_IS_NP_ACTIVE(pVM)
1483	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1484	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1485	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1486	# endif
1487	)
1488	{
1489	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1490	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1491	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1492	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1493	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1494	pPteDst->n.u1Present = 0;
1495	pPteDst->n.u1Write = 1;
1496	pPteDst->n.u1Execute = 0;
1497	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1498	pPteDst->n.u3EMT = 7;
1499	# else
1500	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1501	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1502	# endif
1503	}
1504	# endif
1505	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1506	else
1507	{
1508	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1509	SHW_PTE_SET(*pPteDst, 0);
1510	}
1511	/** @todo count these kinds of entries. */
1512	}
1513
1514
1515	/**
1516	* Creates a 4K shadow page for a guest page.
1517	*
1518	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1519	* physical address. The PdeSrc argument only the flags are used. No page
1520	* structured will be mapped in this function.
1521	*
1522	* @param pVCpu The cross context virtual CPU structure.
1523	* @param pPteDst Destination page table entry.
1524	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1525	* Can safely assume that only the flags are being used.
1526	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1527	* @param pShwPage Pointer to the shadow page.
1528	* @param iPTDst The index into the shadow table.
1529	*
1530	* @remark Not used for 2/4MB pages!
1531	*/
1532	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1533	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1534	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1535	# else
1536	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1537	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1538	# endif
1539	{
1540	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1541	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1542
1543	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1544	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1545	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1546
1547	if (pShwPage->fDirty)
1548	{
1549	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1550	PGSTPT pGstPT;
1551
1552	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1553	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1554	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1555	pGstPT->a[iPTDst].u = PteSrc.u;
1556	}
1557	# else
1558	Assert(!pShwPage->fDirty);
1559	# endif
1560
1561	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1562	if ( PteSrc.n.u1Present
1563	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1564	# endif
1565	{
1566	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1567	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1568	# endif
1569	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1570
1571	/*
1572	* Find the ram range.
1573	*/
1574	PPGMPAGE pPage;
1575	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1576	if (RT_SUCCESS(rc))
1577	{
1578	/* Ignore ballooned pages.
1579	Don't return errors or use a fatal assert here as part of a
1580	shadow sync range might included ballooned pages. */
1581	if (PGM_PAGE_IS_BALLOONED(pPage))
1582	{
1583	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1584	return;
1585	}
1586
1587	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1588	/* Make the page writable if necessary. */
1589	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1590	&& ( PGM_PAGE_IS_ZERO(pPage)
1591	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1592	\|\| ( PteSrc.n.u1Write
1593	# else
1594	\|\| ( 1
1595	# endif
1596	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1597	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1598	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1599	# endif
1600	# ifdef VBOX_WITH_PAGE_SHARING
1601	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1602	# endif
1603	)
1604	)
1605	)
1606	{
1607	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1608	AssertRC(rc);
1609	}
1610	# endif
1611
1612	/*
1613	* Make page table entry.
1614	*/
1615	SHWPTE PteDst;
1616	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1617	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1618	# else
1619	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1620	# endif
1621	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1622	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1623	else
1624	{
1625	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1626	/*
1627	* If the page or page directory entry is not marked accessed,
1628	* we mark the page not present.
1629	*/
1630	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1631	{
1632	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1633	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1634	SHW_PTE_SET(PteDst, 0);
1635	}
1636	/*
1637	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1638	* when the page is modified.
1639	*/
1640	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1641	{
1642	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1643	SHW_PTE_SET(PteDst,
1644	fGstShwPteFlags
1645	\| PGM_PAGE_GET_HCPHYS(pPage)
1646	\| PGM_PTFLAGS_TRACK_DIRTY);
1647	SHW_PTE_SET_RO(PteDst);
1648	}
1649	else
1650	# endif
1651	{
1652	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1653	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1654	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1655	PteDst.n.u1Present = 1;
1656	PteDst.n.u1Write = 1;
1657	PteDst.n.u1Execute = 1;
1658	PteDst.n.u1IgnorePAT = 1;
1659	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1660	/* PteDst.n.u1Size = 0 */
1661	# else
1662	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1663	# endif
1664	}
1665
1666	/*
1667	* Make sure only allocated pages are mapped writable.
1668	*/
1669	if ( SHW_PTE_IS_P_RW(PteDst)
1670	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1671	{
1672	/* Still applies to shared pages. */
1673	Assert(!PGM_PAGE_IS_ZERO(pPage));
1674	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1675	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1676	}
1677	}
1678
1679	/*
1680	* Keep user track up to date.
1681	*/
1682	if (SHW_PTE_IS_P(PteDst))
1683	{
1684	if (!SHW_PTE_IS_P(*pPteDst))
1685	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1686	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1687	{
1688	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1689	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1690	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1691	}
1692	}
1693	else if (SHW_PTE_IS_P(*pPteDst))
1694	{
1695	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1696	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1697	}
1698
1699	/*
1700	* Update statistics and commit the entry.
1701	*/
1702	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1703	if (!PteSrc.n.u1Global)
1704	pShwPage->fSeenNonGlobal = true;
1705	# endif
1706	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1707	return;
1708	}
1709
1710	/** @todo count these three different kinds. */
1711	Log2(("SyncPageWorker: invalid address in Pte\n"));
1712	}
1713	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1714	else if (!PteSrc.n.u1Present)
1715	Log2(("SyncPageWorker: page not present in Pte\n"));
1716	else
1717	Log2(("SyncPageWorker: invalid Pte\n"));
1718	# endif
1719
1720	/*
1721	* The page is not present or the PTE is bad. Replace the shadow PTE by
1722	* an empty entry, making sure to keep the user tracking up to date.
1723	*/
1724	if (SHW_PTE_IS_P(*pPteDst))
1725	{
1726	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1727	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1728	}
1729	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1730	}
1731
1732
1733	/**
1734	* Syncs a guest OS page.
1735	*
1736	* There are no conflicts at this point, neither is there any need for
1737	* page table allocations.
1738	*
1739	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1740	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1741	*
1742	* @returns VBox status code.
1743	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1744	* @param pVCpu The cross context virtual CPU structure.
1745	* @param PdeSrc Page directory entry of the guest.
1746	* @param GCPtrPage Guest context page address.
1747	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1748	* @param uErr Fault error (X86_TRAP_PF_*).
1749	*/
1750	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1751	{
1752	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1753	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1754	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1755	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
1756
1757	PGM_LOCK_ASSERT_OWNER(pVM);
1758
1759	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1760	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1761	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1762	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
1763
1764	/*
1765	* Assert preconditions.
1766	*/
1767	Assert(PdeSrc.n.u1Present);
1768	Assert(cPages);
1769	# if 0 /* rarely useful; leave for debugging. */
1770	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1771	# endif
1772
1773	/*
1774	* Get the shadow PDE, find the shadow page table in the pool.
1775	*/
1776	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1777	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1778	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1779
1780	/* Fetch the pgm pool shadow descriptor. */
1781	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1782	Assert(pShwPde);
1783
1784	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1785	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1786	PPGMPOOLPAGE pShwPde = NULL;
1787	PX86PDPAE pPDDst;
1788
1789	/* Fetch the pgm pool shadow descriptor. */
1790	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1791	AssertRCSuccessReturn(rc2, rc2);
1792	Assert(pShwPde);
1793
1794	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1795	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1796
1797	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1798	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1799	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1800	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1801	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1802
1803	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1804	AssertRCSuccessReturn(rc2, rc2);
1805	Assert(pPDDst && pPdptDst);
1806	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1807	# endif
1808	SHWPDE PdeDst = *pPdeDst;
1809
1810	/*
1811	* - In the guest SMP case we could have blocked while another VCPU reused
1812	* this page table.
1813	* - With W7-64 we may also take this path when the A bit is cleared on
1814	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1815	* relevant TLB entries. If we're write monitoring any page mapped by
1816	* the modified entry, we may end up here with a "stale" TLB entry.
1817	*/
1818	if (!PdeDst.n.u1Present)
1819	{
1820	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1821	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1822	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1823	if (uErr & X86_TRAP_PF_P)
1824	PGM_INVL_PG(pVCpu, GCPtrPage);
1825	return VINF_SUCCESS; /* force the instruction to be executed again. */
1826	}
1827
1828	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1829	Assert(pShwPage);
1830
1831	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1832	/* Fetch the pgm pool shadow descriptor. */
1833	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1834	Assert(pShwPde);
1835	# endif
1836
1837	/*
1838	* Check that the page is present and that the shadow PDE isn't out of sync.
1839	*/
1840	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1841	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1842	RTGCPHYS GCPhys;
1843	if (!fBigPage)
1844	{
1845	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1846	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1847	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1848	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1849	# endif
1850	}
1851	else
1852	{
1853	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1854	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1855	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1856	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1857	# endif
1858	}
1859	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1860	if ( fPdeValid
1861	&& pShwPage->GCPhys == GCPhys
1862	&& PdeSrc.n.u1Present
1863	&& PdeSrc.n.u1User == PdeDst.n.u1User
1864	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1865	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1866	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1867	# endif
1868	)
1869	{
1870	/*
1871	* Check that the PDE is marked accessed already.
1872	* Since we set the accessed bit before getting here on a #PF, this
1873	* check is only meant for dealing with non-#PF'ing paths.
1874	*/
1875	if (PdeSrc.n.u1Accessed)
1876	{
1877	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1878	if (!fBigPage)
1879	{
1880	/*
1881	* 4KB Page - Map the guest page table.
1882	*/
1883	PGSTPT pPTSrc;
1884	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1885	if (RT_SUCCESS(rc))
1886	{
1887	# ifdef PGM_SYNC_N_PAGES
1888	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1889	if ( cPages > 1
1890	&& !(uErr & X86_TRAP_PF_P)
1891	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1892	{
1893	/*
1894	* This code path is currently only taken when the caller is PGMTrap0eHandler
1895	* for non-present pages!
1896	*
1897	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1898	* deal with locality.
1899	*/
1900	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1901	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1902	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1903	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1904	# else
1905	const unsigned offPTSrc = 0;
1906	# endif
1907	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1908	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1909	iPTDst = 0;
1910	else
1911	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1912
1913	for (; iPTDst < iPTDstEnd; iPTDst++)
1914	{
1915	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1916
1917	if ( pPteSrc->n.u1Present
1918	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1919	{
1920	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1921	NOREF(GCPtrCurPage);
1922	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
1923	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1924	GCPtrCurPage, pPteSrc->n.u1Present,
1925	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
1926	pPteSrc->n.u1User & PdeSrc.n.u1User,
1927	(uint64_t)pPteSrc->u,
1928	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1929	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1930	}
1931	}
1932	}
1933	else
1934	# endif /* PGM_SYNC_N_PAGES */
1935	{
1936	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1937	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1938	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1939	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1940	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1941	GCPtrPage, PteSrc.n.u1Present,
1942	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1943	PteSrc.n.u1User & PdeSrc.n.u1User,
1944	(uint64_t)PteSrc.u,
1945	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1946	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1947	}
1948	}
1949	else /* MMIO or invalid page: emulated in #PF handler. */
1950	{
1951	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1952	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1953	}
1954	}
1955	else
1956	{
1957	/*
1958	* 4/2MB page - lazy syncing shadow 4K pages.
1959	* (There are many causes of getting here, it's no longer only CSAM.)
1960	*/
1961	/* Calculate the GC physical address of this 4KB shadow page. */
1962	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
1963	/* Find ram range. */
1964	PPGMPAGE pPage;
1965	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1966	if (RT_SUCCESS(rc))
1967	{
1968	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1969
1970	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1971	/* Try to make the page writable if necessary. */
1972	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1973	&& ( PGM_PAGE_IS_ZERO(pPage)
1974	\|\| ( PdeSrc.n.u1Write
1975	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1976	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1977	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1978	# endif
1979	# ifdef VBOX_WITH_PAGE_SHARING
1980	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1981	# endif
1982	)
1983	)
1984	)
1985	{
1986	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1987	AssertRC(rc);
1988	}
1989	# endif
1990
1991	/*
1992	* Make shadow PTE entry.
1993	*/
1994	SHWPTE PteDst;
1995	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1996	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
1997	else
1998	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
1999
2000	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2001	if ( SHW_PTE_IS_P(PteDst)
2002	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2003	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2004
2005	/* Make sure only allocated pages are mapped writable. */
2006	if ( SHW_PTE_IS_P_RW(PteDst)
2007	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2008	{
2009	/* Still applies to shared pages. */
2010	Assert(!PGM_PAGE_IS_ZERO(pPage));
2011	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2012	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2013	}
2014
2015	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2016
2017	/*
2018	* If the page is not flagged as dirty and is writable, then make it read-only
2019	* at PD level, so we can set the dirty bit when the page is modified.
2020	*
2021	* ASSUMES that page access handlers are implemented on page table entry level.
2022	* Thus we will first catch the dirty access and set PDE.D and restart. If
2023	* there is an access handler, we'll trap again and let it work on the problem.
2024	*/
2025	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2026	* As for invlpg, it simply frees the whole shadow PT.
2027	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2028	if ( !PdeSrc.b.u1Dirty
2029	&& PdeSrc.b.u1Write)
2030	{
2031	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2032	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2033	PdeDst.n.u1Write = 0;
2034	}
2035	else
2036	{
2037	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2038	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2039	}
2040	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2041	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2042	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2043	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2044	}
2045	else
2046	{
2047	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2048	/** @todo must wipe the shadow page table entry in this
2049	* case. */
2050	}
2051	}
2052	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2053	return VINF_SUCCESS;
2054	}
2055
2056	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2057	}
2058	else if (fPdeValid)
2059	{
2060	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2061	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2062	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2063	}
2064	else
2065	{
2066	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2067	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2068	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2069	}
2070
2071	/*
2072	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2073	* Yea, I'm lazy.
2074	*/
2075	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2076	ASMAtomicWriteSize(pPdeDst, 0);
2077
2078	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2079	PGM_INVL_VCPU_TLBS(pVCpu);
2080	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2081
2082
2083	# elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2084	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2085	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2086	NOREF(PdeSrc);
2087
2088	# ifdef PGM_SYNC_N_PAGES
2089	/*
2090	* Get the shadow PDE, find the shadow page table in the pool.
2091	*/
2092	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2093	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2094
2095	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2096	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2097
2098	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2099	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2100	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2101	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2102	X86PDEPAE PdeDst;
2103	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2104
2105	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2106	AssertRCSuccessReturn(rc, rc);
2107	Assert(pPDDst && pPdptDst);
2108	PdeDst = pPDDst->a[iPDDst];
2109	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2110	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2111	PEPTPD pPDDst;
2112	EPTPDE PdeDst;
2113
2114	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2115	if (rc != VINF_SUCCESS)
2116	{
2117	AssertRC(rc);
2118	return rc;
2119	}
2120	Assert(pPDDst);
2121	PdeDst = pPDDst->a[iPDDst];
2122	# endif
2123	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2124	if (!PdeDst.n.u1Present)
2125	{
2126	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2127	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2128	return VINF_SUCCESS; /* force the instruction to be executed again. */
2129	}
2130
2131	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2132	if (PdeDst.n.u1Size)
2133	{
2134	Assert(pVM->pgm.s.fNestedPaging);
2135	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2136	return VINF_SUCCESS;
2137	}
2138
2139	/* Mask away the page offset. */
2140	GCPtrPage &= ~((RTGCPTR)0xfff);
2141
2142	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2143	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2144
2145	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2146	if ( cPages > 1
2147	&& !(uErr & X86_TRAP_PF_P)
2148	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2149	{
2150	/*
2151	* This code path is currently only taken when the caller is PGMTrap0eHandler
2152	* for non-present pages!
2153	*
2154	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2155	* deal with locality.
2156	*/
2157	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2158	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2159	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2160	iPTDst = 0;
2161	else
2162	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2163	for (; iPTDst < iPTDstEnd; iPTDst++)
2164	{
2165	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2166	{
2167	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2168	\| (iPTDst << PAGE_SHIFT));
2169
2170	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2171	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2172	GCPtrCurPage,
2173	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2174	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2175
2176	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2177	break;
2178	}
2179	else
2180	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2181	}
2182	}
2183	else
2184	# endif /* PGM_SYNC_N_PAGES */
2185	{
2186	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2187	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2188	\| (iPTDst << PAGE_SHIFT));
2189
2190	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2191
2192	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2193	GCPtrPage,
2194	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2195	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2196	}
2197	return VINF_SUCCESS;
2198
2199	# else
2200	NOREF(PdeSrc);
2201	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2202	return VERR_PGM_NOT_USED_IN_MODE;
2203	# endif
2204	}
2205
2206	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
2207	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
2208
2209	/**
2210	* CheckPageFault helper for returning a page fault indicating a non-present
2211	* (NP) entry in the page translation structures.
2212	*
2213	* @returns VINF_EM_RAW_GUEST_TRAP.
2214	* @param pVCpu The cross context virtual CPU structure.
2215	* @param uErr The error code of the shadow fault. Corrections to
2216	* TRPM's copy will be made if necessary.
2217	* @param GCPtrPage For logging.
2218	* @param uPageFaultLevel For logging.
2219	*/
2220	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPUCC pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2221	{
2222	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2223	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2224	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2225	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2226	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2227
2228	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2229	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2230	return VINF_EM_RAW_GUEST_TRAP;
2231	}
2232
2233
2234	/**
2235	* CheckPageFault helper for returning a page fault indicating a reserved bit
2236	* (RSVD) error in the page translation structures.
2237	*
2238	* @returns VINF_EM_RAW_GUEST_TRAP.
2239	* @param pVCpu The cross context virtual CPU structure.
2240	* @param uErr The error code of the shadow fault. Corrections to
2241	* TRPM's copy will be made if necessary.
2242	* @param GCPtrPage For logging.
2243	* @param uPageFaultLevel For logging.
2244	*/
2245	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPUCC pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2246	{
2247	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2248	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2249	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2250
2251	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2252	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2253	return VINF_EM_RAW_GUEST_TRAP;
2254	}
2255
2256
2257	/**
2258	* CheckPageFault helper for returning a page protection fault (P).
2259	*
2260	* @returns VINF_EM_RAW_GUEST_TRAP.
2261	* @param pVCpu The cross context virtual CPU structure.
2262	* @param uErr The error code of the shadow fault. Corrections to
2263	* TRPM's copy will be made if necessary.
2264	* @param GCPtrPage For logging.
2265	* @param uPageFaultLevel For logging.
2266	*/
2267	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPUCC pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2268	{
2269	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2270	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2271	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2272	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2273
2274	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2275	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2276	return VINF_EM_RAW_GUEST_TRAP;
2277	}
2278
2279
2280	/**
2281	* Handle dirty bit tracking faults.
2282	*
2283	* @returns VBox status code.
2284	* @param pVCpu The cross context virtual CPU structure.
2285	* @param uErr Page fault error code.
2286	* @param pPdeSrc Guest page directory entry.
2287	* @param pPdeDst Shadow page directory entry.
2288	* @param GCPtrPage Guest context page address.
2289	*/
2290	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2291	RTGCPTR GCPtrPage)
2292	{
2293	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2294	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2295	NOREF(uErr);
2296
2297	PGM_LOCK_ASSERT_OWNER(pVM);
2298
2299	/*
2300	* Handle big page.
2301	*/
2302	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2303	{
2304	if ( pPdeDst->n.u1Present
2305	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2306	{
2307	SHWPDE PdeDst = *pPdeDst;
2308
2309	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2310	Assert(pPdeSrc->b.u1Write);
2311
2312	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2313	* fault again and take this path to only invalidate the entry (see below).
2314	*/
2315	PdeDst.n.u1Write = 1;
2316	PdeDst.n.u1Accessed = 1;
2317	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2318	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2319	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2320	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2321	}
2322
2323	# ifdef IN_RING0
2324	/* Check for stale TLB entry; only applies to the SMP guest case. */
2325	if ( pVM->cCpus > 1
2326	&& pPdeDst->n.u1Write
2327	&& pPdeDst->n.u1Accessed)
2328	{
2329	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2330	if (pShwPage)
2331	{
2332	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2333	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2334	if (SHW_PTE_IS_P_RW(*pPteDst))
2335	{
2336	/* Stale TLB entry. */
2337	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2338	PGM_INVL_PG(pVCpu, GCPtrPage);
2339	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2340	}
2341	}
2342	}
2343	# endif /* IN_RING0 */
2344	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2345	}
2346
2347	/*
2348	* Map the guest page table.
2349	*/
2350	PGSTPT pPTSrc;
2351	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2352	if (RT_FAILURE(rc))
2353	{
2354	AssertRC(rc);
2355	return rc;
2356	}
2357
2358	if (pPdeDst->n.u1Present)
2359	{
2360	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2361	const GSTPTE PteSrc = *pPteSrc;
2362
2363	/*
2364	* Map shadow page table.
2365	*/
2366	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2367	if (pShwPage)
2368	{
2369	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2370	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2371	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2372	{
2373	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2374	{
2375	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2376	SHWPTE PteDst = *pPteDst;
2377
2378	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2380
2381	Assert(PteSrc.n.u1Write);
2382
2383	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2384	* entry will not harm; write access will simply fault again and
2385	* take this path to only invalidate the entry.
2386	*/
2387	if (RT_LIKELY(pPage))
2388	{
2389	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2390	{
2391	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2392	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2393	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2394	SHW_PTE_SET_RO(PteDst);
2395	}
2396	else
2397	{
2398	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2399	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2400	{
2401	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2402	AssertRC(rc);
2403	}
2404	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2405	SHW_PTE_SET_RW(PteDst);
2406	else
2407	{
2408	/* Still applies to shared pages. */
2409	Assert(!PGM_PAGE_IS_ZERO(pPage));
2410	SHW_PTE_SET_RO(PteDst);
2411	}
2412	}
2413	}
2414	else
2415	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2416
2417	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2418	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2419	PGM_INVL_PG(pVCpu, GCPtrPage);
2420	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2421	}
2422
2423	# ifdef IN_RING0
2424	/* Check for stale TLB entry; only applies to the SMP guest case. */
2425	if ( pVM->cCpus > 1
2426	&& SHW_PTE_IS_RW(*pPteDst)
2427	&& SHW_PTE_IS_A(*pPteDst))
2428	{
2429	/* Stale TLB entry. */
2430	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2431	PGM_INVL_PG(pVCpu, GCPtrPage);
2432	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2433	}
2434	# endif
2435	}
2436	}
2437	else
2438	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2439	}
2440
2441	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2442	}
2443
2444	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
2445
2446	/**
2447	* Sync a shadow page table.
2448	*
2449	* The shadow page table is not present in the shadow PDE.
2450	*
2451	* Handles mapping conflicts.
2452	*
2453	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2454	* conflict), and Trap0eHandler.
2455	*
2456	* A precondition for this method is that the shadow PDE is not present. The
2457	* caller must take the PGM lock before checking this and continue to hold it
2458	* when calling this method.
2459	*
2460	* @returns VBox status code.
2461	* @param pVCpu The cross context virtual CPU structure.
2462	* @param iPDSrc Page directory index.
2463	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2464	* Assume this is a temporary mapping.
2465	* @param GCPtrPage GC Pointer of the page that caused the fault
2466	*/
2467	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2468	{
2469	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2470	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2471
2472	#if 0 /* rarely useful; leave for debugging. */
2473	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2474	#endif
2475	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
2476
2477	PGM_LOCK_ASSERT_OWNER(pVM);
2478
2479	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2480	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2481	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2482	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
2483	&& PGM_SHW_TYPE != PGM_TYPE_NONE
2484	int rc = VINF_SUCCESS;
2485
2486	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2487
2488	/*
2489	* Some input validation first.
2490	*/
2491	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2492
2493	/*
2494	* Get the relevant shadow PDE entry.
2495	*/
2496	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2497	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2498	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2499
2500	/* Fetch the pgm pool shadow descriptor. */
2501	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2502	Assert(pShwPde);
2503
2504	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2505	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2506	PPGMPOOLPAGE pShwPde = NULL;
2507	PX86PDPAE pPDDst;
2508	PSHWPDE pPdeDst;
2509
2510	/* Fetch the pgm pool shadow descriptor. */
2511	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2512	AssertRCSuccessReturn(rc, rc);
2513	Assert(pShwPde);
2514
2515	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2516	pPdeDst = &pPDDst->a[iPDDst];
2517
2518	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2519	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2520	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2521	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2522	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2523	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2524	AssertRCSuccessReturn(rc, rc);
2525	Assert(pPDDst);
2526	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2527	# endif
2528	SHWPDE PdeDst = *pPdeDst;
2529
2530	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2531	/* Fetch the pgm pool shadow descriptor. */
2532	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2533	Assert(pShwPde);
2534	# endif
2535
2536	# ifndef PGM_WITHOUT_MAPPINGS
2537	/*
2538	* Check for conflicts.
2539	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2540	* R3: Simply resolve the conflict.
2541	*/
2542	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2543	{
2544	Assert(pgmMapAreMappingsEnabled(pVM));
2545	# ifndef IN_RING3
2546	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2547	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2548	return VERR_ADDRESS_CONFLICT;
2549
2550	# else /* IN_RING3 */
2551	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2552	Assert(pMapping);
2553	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2554	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2555	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2556	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2557	# else
2558	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2559	# endif
2560	if (RT_FAILURE(rc))
2561	{
2562	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2563	return rc;
2564	}
2565	PdeDst = *pPdeDst;
2566	# endif /* IN_RING3 */
2567	}
2568	# endif /* !PGM_WITHOUT_MAPPINGS */
2569	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2570
2571	/*
2572	* Sync the page directory entry.
2573	*/
2574	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2575	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2576	if ( PdeSrc.n.u1Present
2577	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2578	{
2579	/*
2580	* Allocate & map the page table.
2581	*/
2582	PSHWPT pPTDst;
2583	PPGMPOOLPAGE pShwPage;
2584	RTGCPHYS GCPhys;
2585	if (fPageTable)
2586	{
2587	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2588	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2589	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2590	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2591	# endif
2592	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2593	pShwPde->idx, iPDDst, false /fLockPage/,
2594	&pShwPage);
2595	}
2596	else
2597	{
2598	PGMPOOLACCESS enmAccess;
2599	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2600	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2601	# else
2602	const bool fNoExecute = false;
2603	# endif
2604
2605	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2606	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2607	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2608	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2609	# endif
2610	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2611	if (PdeSrc.n.u1User)
2612	{
2613	if (PdeSrc.n.u1Write)
2614	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2615	else
2616	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2617	}
2618	else
2619	{
2620	if (PdeSrc.n.u1Write)
2621	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2622	else
2623	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2624	}
2625	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2626	pShwPde->idx, iPDDst, false /fLockPage/,
2627	&pShwPage);
2628	}
2629	if (rc == VINF_SUCCESS)
2630	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2631	else if (rc == VINF_PGM_CACHED_PAGE)
2632	{
2633	/*
2634	* The PT was cached, just hook it up.
2635	*/
2636	if (fPageTable)
2637	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2638	else
2639	{
2640	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2641	/* (see explanation and assumptions further down.) */
2642	if ( !PdeSrc.b.u1Dirty
2643	&& PdeSrc.b.u1Write)
2644	{
2645	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2646	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2647	PdeDst.b.u1Write = 0;
2648	}
2649	}
2650	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2651	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2652	return VINF_SUCCESS;
2653	}
2654	else
2655	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2656	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2657	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2658	* irrelevant at this point. */
2659	PdeDst.u &= X86_PDE_AVL_MASK;
2660	PdeDst.u \|= pShwPage->Core.Key;
2661
2662	/*
2663	* Page directory has been accessed (this is a fault situation, remember).
2664	*/
2665	/** @todo
2666	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2667	* fault situation. What's more, the Trap0eHandler has already set the
2668	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2669	* might need setting the accessed flag.
2670	*
2671	* The best idea is to leave this change to the caller and add an
2672	* assertion that it's set already. */
2673	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2674	if (fPageTable)
2675	{
2676	/*
2677	* Page table - 4KB.
2678	*
2679	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2680	*/
2681	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2682	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2683	PGSTPT pPTSrc;
2684	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2685	if (RT_SUCCESS(rc))
2686	{
2687	/*
2688	* Start by syncing the page directory entry so CSAM's TLB trick works.
2689	*/
2690	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2691	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2692	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2693	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2694
2695	/*
2696	* Directory/page user or supervisor privilege: (same goes for read/write)
2697	*
2698	* Directory Page Combined
2699	* U/S U/S U/S
2700	* 0 0 0
2701	* 0 1 0
2702	* 1 0 0
2703	* 1 1 1
2704	*
2705	* Simple AND operation. Table listed for completeness.
2706	*
2707	*/
2708	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2709	# ifdef PGM_SYNC_N_PAGES
2710	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2711	unsigned iPTDst = iPTBase;
2712	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2713	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2714	iPTDst = 0;
2715	else
2716	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2717	# else /* !PGM_SYNC_N_PAGES */
2718	unsigned iPTDst = 0;
2719	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2720	# endif /* !PGM_SYNC_N_PAGES */
2721	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2722	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2723	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2724	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2725	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2726	# else
2727	const unsigned offPTSrc = 0;
2728	# endif
2729	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2730	{
2731	const unsigned iPTSrc = iPTDst + offPTSrc;
2732	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2733
2734	if (PteSrc.n.u1Present)
2735	{
2736	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2737	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2738	GCPtrCur,
2739	PteSrc.n.u1Present,
2740	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2741	PteSrc.n.u1User & PdeSrc.n.u1User,
2742	(uint64_t)PteSrc.u,
2743	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2744	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2745	}
2746	/* else: the page table was cleared by the pool */
2747	} /* for PTEs */
2748	}
2749	}
2750	else
2751	{
2752	/*
2753	* Big page - 2/4MB.
2754	*
2755	* We'll walk the ram range list in parallel and optimize lookups.
2756	* We will only sync one shadow page table at a time.
2757	*/
2758	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2759
2760	/**
2761	* @todo It might be more efficient to sync only a part of the 4MB
2762	* page (similar to what we do for 4KB PDs).
2763	*/
2764
2765	/*
2766	* Start by syncing the page directory entry.
2767	*/
2768	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2769	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2770
2771	/*
2772	* If the page is not flagged as dirty and is writable, then make it read-only
2773	* at PD level, so we can set the dirty bit when the page is modified.
2774	*
2775	* ASSUMES that page access handlers are implemented on page table entry level.
2776	* Thus we will first catch the dirty access and set PDE.D and restart. If
2777	* there is an access handler, we'll trap again and let it work on the problem.
2778	*/
2779	/** @todo move the above stuff to a section in the PGM documentation. */
2780	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2781	if ( !PdeSrc.b.u1Dirty
2782	&& PdeSrc.b.u1Write)
2783	{
2784	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2785	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2786	PdeDst.b.u1Write = 0;
2787	}
2788	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2789	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2790
2791	/*
2792	* Fill the shadow page table.
2793	*/
2794	/* Get address and flags from the source PDE. */
2795	SHWPTE PteDstBase;
2796	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2797
2798	/* Loop thru the entries in the shadow PT. */
2799	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2800	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2801	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2802	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2803	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2804	unsigned iPTDst = 0;
2805	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2806	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2807	{
2808	if (pRam && GCPhys >= pRam->GCPhys)
2809	{
2810	# ifndef PGM_WITH_A20
2811	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2812	# endif
2813	do
2814	{
2815	/* Make shadow PTE. */
2816	# ifdef PGM_WITH_A20
2817	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2818	# else
2819	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2820	# endif
2821	SHWPTE PteDst;
2822
2823	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2824	/* Try to make the page writable if necessary. */
2825	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2826	&& ( PGM_PAGE_IS_ZERO(pPage)
2827	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2828	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2829	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2830	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2831	# endif
2832	# ifdef VBOX_WITH_PAGE_SHARING
2833	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2834	# endif
2835	&& !PGM_PAGE_IS_BALLOONED(pPage))
2836	)
2837	)
2838	{
2839	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2840	AssertRCReturn(rc, rc);
2841	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2842	break;
2843	}
2844	# endif
2845
2846	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2847	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2848	else if (PGM_PAGE_IS_BALLOONED(pPage))
2849	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2850	else
2851	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2852
2853	/* Only map writable pages writable. */
2854	if ( SHW_PTE_IS_P_RW(PteDst)
2855	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2856	{
2857	/* Still applies to shared pages. */
2858	Assert(!PGM_PAGE_IS_ZERO(pPage));
2859	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2860	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2861	}
2862
2863	if (SHW_PTE_IS_P(PteDst))
2864	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2865
2866	/* commit it (not atomic, new table) */
2867	pPTDst->a[iPTDst] = PteDst;
2868	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2869	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2870	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2871
2872	/* advance */
2873	GCPhys += PAGE_SIZE;
2874	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
2875	# ifndef PGM_WITH_A20
2876	iHCPage++;
2877	# endif
2878	iPTDst++;
2879	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2880	&& GCPhys <= pRam->GCPhysLast);
2881
2882	/* Advance ram range list. */
2883	while (pRam && GCPhys > pRam->GCPhysLast)
2884	pRam = pRam->CTX_SUFF(pNext);
2885	}
2886	else if (pRam)
2887	{
2888	Log(("Invalid pages at %RGp\n", GCPhys));
2889	do
2890	{
2891	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2892	GCPhys += PAGE_SIZE;
2893	iPTDst++;
2894	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2895	&& GCPhys < pRam->GCPhys);
2896	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
2897	}
2898	else
2899	{
2900	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2901	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2902	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2903	}
2904	} /* while more PTEs */
2905	} /* 4KB / 4MB */
2906	}
2907	else
2908	AssertRelease(!PdeDst.n.u1Present);
2909
2910	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2911	if (RT_FAILURE(rc))
2912	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2913	return rc;
2914
2915	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2916	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2917	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2918	&& PGM_SHW_TYPE != PGM_TYPE_NONE
2919	NOREF(iPDSrc); NOREF(pPDSrc);
2920
2921	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2922
2923	/*
2924	* Validate input a little bit.
2925	*/
2926	int rc = VINF_SUCCESS;
2927	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2928	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2929	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2930
2931	/* Fetch the pgm pool shadow descriptor. */
2932	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2933	Assert(pShwPde);
2934
2935	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2936	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2937	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2938	PX86PDPAE pPDDst;
2939	PSHWPDE pPdeDst;
2940
2941	/* Fetch the pgm pool shadow descriptor. */
2942	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2943	AssertRCSuccessReturn(rc, rc);
2944	Assert(pShwPde);
2945
2946	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2947	pPdeDst = &pPDDst->a[iPDDst];
2948
2949	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2950	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2951	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2952	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2953	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2954	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2955	AssertRCSuccessReturn(rc, rc);
2956	Assert(pPDDst);
2957	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2958
2959	/* Fetch the pgm pool shadow descriptor. */
2960	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2961	Assert(pShwPde);
2962
2963	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2964	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2965	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2966	PEPTPD pPDDst;
2967	PEPTPDPT pPdptDst;
2968
2969	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2970	if (rc != VINF_SUCCESS)
2971	{
2972	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2973	AssertRC(rc);
2974	return rc;
2975	}
2976	Assert(pPDDst);
2977	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2978
2979	/* Fetch the pgm pool shadow descriptor. */
2980	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2981	Assert(pShwPde);
2982	# endif
2983	SHWPDE PdeDst = *pPdeDst;
2984
2985	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2986	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2987
2988	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2989	if ( BTH_IS_NP_ACTIVE(pVM)
2990	&& !VM_IS_NEM_ENABLED(pVM)) /** @todo NEM: Large page support. */
2991	{
2992	/* Check if we allocated a big page before for this 2 MB range. */
2993	PPGMPAGE pPage;
2994	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
2995	if (RT_SUCCESS(rc))
2996	{
2997	RTHCPHYS HCPhys = NIL_RTHCPHYS;
2998	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
2999	{
3000	if (PGM_A20_IS_ENABLED(pVCpu))
3001	{
3002	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3003	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3004	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3005	}
3006	else
3007	{
3008	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3009	pVM->pgm.s.cLargePagesDisabled++;
3010	}
3011	}
3012	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3013	&& PGM_A20_IS_ENABLED(pVCpu))
3014	{
3015	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3016	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3017	if (RT_SUCCESS(rc))
3018	{
3019	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3020	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3021	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3022	}
3023	}
3024	else if ( PGMIsUsingLargePages(pVM)
3025	&& PGM_A20_IS_ENABLED(pVCpu))
3026	{
3027	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3028	if (RT_SUCCESS(rc))
3029	{
3030	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3031	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3032	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3033	}
3034	else
3035	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3036	}
3037
3038	if (HCPhys != NIL_RTHCPHYS)
3039	{
3040	PdeDst.u &= X86_PDE_AVL_MASK;
3041	PdeDst.u \|= HCPhys;
3042	PdeDst.n.u1Present = 1;
3043	PdeDst.n.u1Write = 1;
3044	PdeDst.b.u1Size = 1;
3045	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3046	PdeDst.n.u1Execute = 1;
3047	PdeDst.b.u1IgnorePAT = 1;
3048	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3049	# else
3050	PdeDst.n.u1User = 1;
3051	# endif
3052	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3053
3054	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3055	/* Add a reference to the first page only. */
3056	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3057
3058	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3059	return VINF_SUCCESS;
3060	}
3061	}
3062	}
3063	# endif /* defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE */
3064
3065	/*
3066	* Allocate & map the page table.
3067	*/
3068	PSHWPT pPTDst;
3069	PPGMPOOLPAGE pShwPage;
3070	RTGCPHYS GCPhys;
3071
3072	/* Virtual address = physical address */
3073	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3074	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3075	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3076	&pShwPage);
3077	if ( rc == VINF_SUCCESS
3078	\|\| rc == VINF_PGM_CACHED_PAGE)
3079	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3080	else
3081	{
3082	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3083	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3084	}
3085
3086	if (rc == VINF_SUCCESS)
3087	{
3088	/* New page table; fully set it up. */
3089	Assert(pPTDst);
3090
3091	/* Mask away the page offset. */
3092	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3093
3094	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3095	{
3096	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3097	\| (iPTDst << PAGE_SHIFT));
3098
3099	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3100	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3101	GCPtrCurPage,
3102	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3103	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3104
3105	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3106	break;
3107	}
3108	}
3109	else
3110	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3111
3112	/* Save the new PDE. */
3113	PdeDst.u &= X86_PDE_AVL_MASK;
3114	PdeDst.u \|= pShwPage->Core.Key;
3115	PdeDst.n.u1Present = 1;
3116	PdeDst.n.u1Write = 1;
3117	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3118	PdeDst.n.u1Execute = 1;
3119	# else
3120	PdeDst.n.u1User = 1;
3121	PdeDst.n.u1Accessed = 1;
3122	# endif
3123	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3124
3125	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3126	if (RT_FAILURE(rc))
3127	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3128	return rc;
3129
3130	#else
3131	NOREF(iPDSrc); NOREF(pPDSrc);
3132	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3133	return VERR_PGM_NOT_USED_IN_MODE;
3134	#endif
3135	}
3136
3137
3138
3139	/**
3140	* Prefetch a page/set of pages.
3141	*
3142	* Typically used to sync commonly used pages before entering raw mode
3143	* after a CR3 reload.
3144	*
3145	* @returns VBox status code.
3146	* @param pVCpu The cross context virtual CPU structure.
3147	* @param GCPtrPage Page to invalidate.
3148	*/
3149	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
3150	{
3151	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3152	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3153	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3154	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3155	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3156	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3157	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3158	/*
3159	* Check that all Guest levels thru the PDE are present, getting the
3160	* PD and PDE in the processes.
3161	*/
3162	int rc = VINF_SUCCESS;
3163	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3164	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3165	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
3166	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3167	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3168	unsigned iPDSrc;
3169	X86PDPE PdpeSrc;
3170	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3171	if (!pPDSrc)
3172	return VINF_SUCCESS; /* not present */
3173	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3174	unsigned iPDSrc;
3175	PX86PML4E pPml4eSrc;
3176	X86PDPE PdpeSrc;
3177	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3178	if (!pPDSrc)
3179	return VINF_SUCCESS; /* not present */
3180	# endif
3181	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3182	# else
3183	PGSTPD pPDSrc = NULL;
3184	const unsigned iPDSrc = 0;
3185	GSTPDE PdeSrc;
3186
3187	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3188	PdeSrc.n.u1Present = 1;
3189	PdeSrc.n.u1Write = 1;
3190	PdeSrc.n.u1Accessed = 1;
3191	PdeSrc.n.u1User = 1;
3192	# endif
3193
3194	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3195	{
3196	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3197	pgmLock(pVM);
3198
3199	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3200	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3201	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3202	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3203	PX86PDPAE pPDDst;
3204	X86PDEPAE PdeDst;
3205	# if PGM_GST_TYPE != PGM_TYPE_PAE
3206	X86PDPE PdpeSrc;
3207
3208	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3209	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3210	# endif
3211	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3212	if (rc != VINF_SUCCESS)
3213	{
3214	pgmUnlock(pVM);
3215	AssertRC(rc);
3216	return rc;
3217	}
3218	Assert(pPDDst);
3219	PdeDst = pPDDst->a[iPDDst];
3220
3221	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3222	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3223	PX86PDPAE pPDDst;
3224	X86PDEPAE PdeDst;
3225
3226	# if PGM_GST_TYPE == PGM_TYPE_PROT
3227	/* AMD-V nested paging */
3228	X86PML4E Pml4eSrc;
3229	X86PDPE PdpeSrc;
3230	PX86PML4E pPml4eSrc = &Pml4eSrc;
3231
3232	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3233	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3234	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3235	# endif
3236
3237	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3238	if (rc != VINF_SUCCESS)
3239	{
3240	pgmUnlock(pVM);
3241	AssertRC(rc);
3242	return rc;
3243	}
3244	Assert(pPDDst);
3245	PdeDst = pPDDst->a[iPDDst];
3246	# endif
3247	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3248	{
3249	if (!PdeDst.n.u1Present)
3250	{
3251	/** @todo r=bird: This guy will set the A bit on the PDE,
3252	* probably harmless. */
3253	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3254	}
3255	else
3256	{
3257	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3258	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3259	* makes no sense to prefetch more than one page.
3260	*/
3261	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3262	if (RT_SUCCESS(rc))
3263	rc = VINF_SUCCESS;
3264	}
3265	}
3266	pgmUnlock(pVM);
3267	}
3268	return rc;
3269
3270	#elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
3271	NOREF(pVCpu); NOREF(GCPtrPage);
3272	return VINF_SUCCESS; /* ignore */
3273	#else
3274	AssertCompile(0);
3275	#endif
3276	}
3277
3278
3279
3280
3281	/**
3282	* Syncs a page during a PGMVerifyAccess() call.
3283	*
3284	* @returns VBox status code (informational included).
3285	* @param pVCpu The cross context virtual CPU structure.
3286	* @param GCPtrPage The address of the page to sync.
3287	* @param fPage The effective guest page flags.
3288	* @param uErr The trap error code.
3289	* @remarks This will normally never be called on invalid guest page
3290	* translation entries.
3291	*/
3292	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3293	{
3294	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3295
3296	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3297	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
3298
3299	Assert(!pVM->pgm.s.fNestedPaging);
3300	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3301	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3302	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3303	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3304	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3305	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3306	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3307
3308	/*
3309	* Get guest PD and index.
3310	*/
3311	/** @todo Performance: We've done all this a jiffy ago in the
3312	* PGMGstGetPage call. */
3313	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3314	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3315	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
3316	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3317
3318	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3319	unsigned iPDSrc = 0;
3320	X86PDPE PdpeSrc;
3321	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3322	if (RT_UNLIKELY(!pPDSrc))
3323	{
3324	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3325	return VINF_EM_RAW_GUEST_TRAP;
3326	}
3327
3328	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3329	unsigned iPDSrc = 0; /* shut up gcc */
3330	PX86PML4E pPml4eSrc = NULL; /* ditto */
3331	X86PDPE PdpeSrc;
3332	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3333	if (RT_UNLIKELY(!pPDSrc))
3334	{
3335	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3336	return VINF_EM_RAW_GUEST_TRAP;
3337	}
3338	# endif
3339
3340	# else /* !PGM_WITH_PAGING */
3341	PGSTPD pPDSrc = NULL;
3342	const unsigned iPDSrc = 0;
3343	# endif /* !PGM_WITH_PAGING */
3344	int rc = VINF_SUCCESS;
3345
3346	pgmLock(pVM);
3347
3348	/*
3349	* First check if the shadow pd is present.
3350	*/
3351	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3352	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3353
3354	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3355	PX86PDEPAE pPdeDst;
3356	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3357	PX86PDPAE pPDDst;
3358	# if PGM_GST_TYPE != PGM_TYPE_PAE
3359	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3360	X86PDPE PdpeSrc;
3361	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3362	# endif
3363	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3364	if (rc != VINF_SUCCESS)
3365	{
3366	pgmUnlock(pVM);
3367	AssertRC(rc);
3368	return rc;
3369	}
3370	Assert(pPDDst);
3371	pPdeDst = &pPDDst->a[iPDDst];
3372
3373	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3374	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3375	PX86PDPAE pPDDst;
3376	PX86PDEPAE pPdeDst;
3377
3378	# if PGM_GST_TYPE == PGM_TYPE_PROT
3379	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3380	X86PML4E Pml4eSrc;
3381	X86PDPE PdpeSrc;
3382	PX86PML4E pPml4eSrc = &Pml4eSrc;
3383	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3384	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3385	# endif
3386
3387	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3388	if (rc != VINF_SUCCESS)
3389	{
3390	pgmUnlock(pVM);
3391	AssertRC(rc);
3392	return rc;
3393	}
3394	Assert(pPDDst);
3395	pPdeDst = &pPDDst->a[iPDDst];
3396	# endif
3397
3398	if (!pPdeDst->n.u1Present)
3399	{
3400	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3401	if (rc != VINF_SUCCESS)
3402	{
3403	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3404	pgmUnlock(pVM);
3405	AssertRC(rc);
3406	return rc;
3407	}
3408	}
3409
3410	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3411	/* Check for dirty bit fault */
3412	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3413	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3414	Log(("PGMVerifyAccess: success (dirty)\n"));
3415	else
3416	# endif
3417	{
3418	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3419	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3420	# else
3421	GSTPDE PdeSrc;
3422	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3423	PdeSrc.n.u1Present = 1;
3424	PdeSrc.n.u1Write = 1;
3425	PdeSrc.n.u1Accessed = 1;
3426	PdeSrc.n.u1User = 1;
3427	# endif
3428
3429	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3430	if (uErr & X86_TRAP_PF_US)
3431	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3432	else /* supervisor */
3433	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3434
3435	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3436	if (RT_SUCCESS(rc))
3437	{
3438	/* Page was successfully synced */
3439	Log2(("PGMVerifyAccess: success (sync)\n"));
3440	rc = VINF_SUCCESS;
3441	}
3442	else
3443	{
3444	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3445	rc = VINF_EM_RAW_GUEST_TRAP;
3446	}
3447	}
3448	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3449	pgmUnlock(pVM);
3450	return rc;
3451
3452	#else /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
3453
3454	AssertLogRelMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3455	return VERR_PGM_NOT_USED_IN_MODE;
3456	#endif /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
3457	}
3458
3459
3460	/**
3461	* Syncs the paging hierarchy starting at CR3.
3462	*
3463	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
3464	* informational status codes.
3465	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
3466	* the VMM into guest context.
3467	* @param pVCpu The cross context virtual CPU structure.
3468	* @param cr0 Guest context CR0 register.
3469	* @param cr3 Guest context CR3 register. Not subjected to the A20
3470	* mask.
3471	* @param cr4 Guest context CR4 register.
3472	* @param fGlobal Including global page directories or not
3473	*/
3474	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3475	{
3476	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3477	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3478
3479	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3480
3481	#if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
3482	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3483	pgmLock(pVM);
3484	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3485	if (pPool->cDirtyPages)
3486	pgmPoolResetDirtyPages(pVM);
3487	pgmUnlock(pVM);
3488	# endif
3489	#endif /* !NESTED && !EPT */
3490
3491	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
3492	/*
3493	* Nested / EPT / None - No work.
3494	*/
3495	Assert(!pgmMapAreMappingsEnabled(pVM));
3496	return VINF_SUCCESS;
3497
3498	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3499	/*
3500	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3501	* out the shadow parts when the guest modifies its tables.
3502	*/
3503	Assert(!pgmMapAreMappingsEnabled(pVM));
3504	return VINF_SUCCESS;
3505
3506	#else /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3507
3508	# ifndef PGM_WITHOUT_MAPPINGS
3509	/*
3510	* Check for and resolve conflicts with our guest mappings if they
3511	* are enabled and not fixed.
3512	*/
3513	if (pgmMapAreMappingsFloating(pVM))
3514	{
3515	int rc = pgmMapResolveConflicts(pVM);
3516	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3517	if (rc == VINF_SUCCESS)
3518	{ /* likely */ }
3519	else if (rc == VINF_PGM_SYNC_CR3)
3520	{
3521	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3522	return VINF_PGM_SYNC_CR3;
3523	}
3524	else if (RT_FAILURE(rc))
3525	return rc;
3526	else
3527	AssertMsgFailed(("%Rrc\n", rc));
3528	}
3529	# else
3530	Assert(!pgmMapAreMappingsEnabled(pVM));
3531	# endif
3532	return VINF_SUCCESS;
3533	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3534	}
3535
3536
3537
3538
3539	#ifdef VBOX_STRICT
3540
3541	/**
3542	* Checks that the shadow page table is in sync with the guest one.
3543	*
3544	* @returns The number of errors.
3545	* @param pVCpu The cross context virtual CPU structure.
3546	* @param cr3 Guest context CR3 register.
3547	* @param cr4 Guest context CR4 register.
3548	* @param GCPtr Where to start. Defaults to 0.
3549	* @param cb How much to check. Defaults to everything.
3550	*/
3551	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3552	{
3553	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3554	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
3555	return 0;
3556	#else
3557	unsigned cErrors = 0;
3558	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3559	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3560
3561	# if PGM_GST_TYPE == PGM_TYPE_PAE
3562	/** @todo currently broken; crashes below somewhere */
3563	AssertFailed();
3564	# endif
3565
3566	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3567	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3568	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3569
3570	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3571	PPGMCPU pPGM = &pVCpu->pgm.s;
3572	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3573	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3574	# ifndef IN_RING0
3575	RTHCPHYS HCPhys; /* general usage. */
3576	# endif
3577	int rc;
3578
3579	/*
3580	* Check that the Guest CR3 and all its mappings are correct.
3581	*/
3582	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3583	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3584	false);
3585	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3586	# if 0
3587	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3588	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3589	# else
3590	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3591	# endif
3592	AssertRCReturn(rc, 1);
3593	HCPhys = NIL_RTHCPHYS;
3594	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3595	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3596	# endif
3597	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3598	pgmGstGet32bitPDPtr(pVCpu);
3599	RTGCPHYS GCPhys;
3600	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3601	AssertRCReturn(rc, 1);
3602	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3603	# endif
3604	# endif /* !IN_RING0 */
3605
3606	/*
3607	* Get and check the Shadow CR3.
3608	*/
3609	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3610	unsigned cPDEs = X86_PG_ENTRIES;
3611	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3612	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3613	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3614	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3615	# else
3616	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3617	# endif
3618	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3619	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3620	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3621	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3622	# endif
3623	if (cb != ~(RTGCPTR)0)
3624	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3625
3626	/** @todo call the other two PGMAssert() functions. /
3627
3628	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3629	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3630
3631	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3632	{
3633	PPGMPOOLPAGE pShwPdpt = NULL;
3634	PX86PML4E pPml4eSrc;
3635	PX86PML4E pPml4eDst;
3636	RTGCPHYS GCPhysPdptSrc;
3637
3638	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3639	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3640
3641	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3642	if (!pPml4eDst->n.u1Present)
3643	{
3644	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3645	continue;
3646	}
3647
3648	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3649	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3650
3651	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3652	{
3653	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3654	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3655	cErrors++;
3656	continue;
3657	}
3658
3659	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3660	{
3661	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3662	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3663	cErrors++;
3664	continue;
3665	}
3666
3667	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3668	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3669	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3670	{
3671	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3672	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3673	cErrors++;
3674	continue;
3675	}
3676	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3677	{
3678	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3679
3680	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3681	/*
3682	* Check the PDPTEs too.
3683	*/
3684	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3685
3686	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3687	{
3688	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3689	PPGMPOOLPAGE pShwPde = NULL;
3690	PX86PDPE pPdpeDst;
3691	RTGCPHYS GCPhysPdeSrc;
3692	X86PDPE PdpeSrc;
3693	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3694	# if PGM_GST_TYPE == PGM_TYPE_PAE
3695	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3696	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3697	# else
3698	PX86PML4E pPml4eSrcIgn;
3699	PX86PDPT pPdptDst;
3700	PX86PDPAE pPDDst;
3701	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3702
3703	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3704	if (rc != VINF_SUCCESS)
3705	{
3706	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3707	GCPtr += 512 * _2M;
3708	continue; /* next PDPTE */
3709	}
3710	Assert(pPDDst);
3711	# endif
3712	Assert(iPDSrc == 0);
3713
3714	pPdpeDst = &pPdptDst->a[iPdpt];
3715
3716	if (!pPdpeDst->n.u1Present)
3717	{
3718	GCPtr += 512 * _2M;
3719	continue; /* next PDPTE */
3720	}
3721
3722	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3723	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3724
3725	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3726	{
3727	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3728	GCPtr += 512 * _2M;
3729	cErrors++;
3730	continue;
3731	}
3732
3733	if (GCPhysPdeSrc != pShwPde->GCPhys)
3734	{
3735	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3736	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3737	# else
3738	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3739	# endif
3740	GCPtr += 512 * _2M;
3741	cErrors++;
3742	continue;
3743	}
3744
3745	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3746	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3747	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3748	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3749	{
3750	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3751	GCPtr += 512 * _2M;
3752	cErrors++;
3753	continue;
3754	}
3755	# endif
3756
3757	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3758	{
3759	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3760	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3761	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3762	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3763	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3764	# endif
3765	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3766	/*
3767	* Iterate the shadow page directory.
3768	*/
3769	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3770	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3771
3772	for (;
3773	iPDDst < cPDEs;
3774	iPDDst++, GCPtr += cIncrement)
3775	{
3776	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3777	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3778	# else
3779	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3780	# endif
3781	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3782	{
3783	Assert(pgmMapAreMappingsEnabled(pVM));
3784	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3785	{
3786	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3787	cErrors++;
3788	continue;
3789	}
3790	}
3791	else if ( (PdeDst.u & X86_PDE_P)
3792	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3793	)
3794	{
3795	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3796	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3797	if (!pPoolPage)
3798	{
3799	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3800	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3801	cErrors++;
3802	continue;
3803	}
3804	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3805
3806	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3807	{
3808	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3809	GCPtr, (uint64_t)PdeDst.u));
3810	cErrors++;
3811	}
3812
3813	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3814	{
3815	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3816	GCPtr, (uint64_t)PdeDst.u));
3817	cErrors++;
3818	}
3819
3820	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3821	if (!PdeSrc.n.u1Present)
3822	{
3823	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3824	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3825	cErrors++;
3826	continue;
3827	}
3828
3829	if ( !PdeSrc.b.u1Size
3830	\|\| !fBigPagesSupported)
3831	{
3832	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3833	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3834	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
3835	# endif
3836	}
3837	else
3838	{
3839	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3840	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3841	{
3842	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3843	GCPtr, (uint64_t)PdeSrc.u));
3844	cErrors++;
3845	continue;
3846	}
3847	# endif
3848	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3849	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3850	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
3851	# endif
3852	}
3853
3854	if ( pPoolPage->enmKind
3855	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3856	{
3857	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3858	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3859	cErrors++;
3860	}
3861
3862	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
3863	if (!pPhysPage)
3864	{
3865	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3866	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3867	cErrors++;
3868	continue;
3869	}
3870
3871	if (GCPhysGst != pPoolPage->GCPhys)
3872	{
3873	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3874	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3875	cErrors++;
3876	continue;
3877	}
3878
3879	if ( !PdeSrc.b.u1Size
3880	\|\| !fBigPagesSupported)
3881	{
3882	/*
3883	* Page Table.
3884	*/
3885	const GSTPT *pPTSrc;
3886	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
3887	&pPTSrc);
3888	if (RT_FAILURE(rc))
3889	{
3890	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3891	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3892	cErrors++;
3893	continue;
3894	}
3895	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3896	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3897	{
3898	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3899	// (This problem will go away when/if we shadow multiple CR3s.)
3900	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3901	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3902	cErrors++;
3903	continue;
3904	}
3905	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3906	{
3907	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3908	GCPtr, (uint64_t)PdeDst.u));
3909	cErrors++;
3910	continue;
3911	}
3912
3913	/* iterate the page table. */
3914	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3915	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3916	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3917	# else
3918	const unsigned offPTSrc = 0;
3919	# endif
3920	for (unsigned iPT = 0, off = 0;
3921	iPT < RT_ELEMENTS(pPTDst->a);
3922	iPT++, off += PAGE_SIZE)
3923	{
3924	const SHWPTE PteDst = pPTDst->a[iPT];
3925
3926	/* skip not-present and dirty tracked entries. */
3927	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3928	continue;
3929	Assert(SHW_PTE_IS_P(PteDst));
3930
3931	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3932	if (!PteSrc.n.u1Present)
3933	{
3934	# ifdef IN_RING3
3935	PGMAssertHandlerAndFlagsInSync(pVM);
3936	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
3937	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
3938	0, 0, UINT64_MAX, 99, NULL);
3939	# endif
3940	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3941	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3942	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
3943	cErrors++;
3944	continue;
3945	}
3946
3947	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3948	# if 1 /** @todo sync accessed bit properly... */
3949	fIgnoreFlags \|= X86_PTE_A;
3950	# endif
3951
3952	/* match the physical addresses */
3953	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
3954	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
3955
3956	# ifdef IN_RING3
3957	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3958	if (RT_FAILURE(rc))
3959	{
3960	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3961	{
3962	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3963	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3964	cErrors++;
3965	continue;
3966	}
3967	}
3968	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3969	{
3970	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3971	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3972	cErrors++;
3973	continue;
3974	}
3975	# endif
3976
3977	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
3978	if (!pPhysPage)
3979	{
3980	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3981	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3982	{
3983	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3984	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3985	cErrors++;
3986	continue;
3987	}
3988	# endif
3989	if (SHW_PTE_IS_RW(PteDst))
3990	{
3991	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3992	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3993	cErrors++;
3994	}
3995	fIgnoreFlags \|= X86_PTE_RW;
3996	}
3997	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3998	{
3999	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4000	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4001	cErrors++;
4002	continue;
4003	}
4004
4005	/* flags */
4006	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4007	{
4008	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4009	{
4010	if (SHW_PTE_IS_RW(PteDst))
4011	{
4012	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4013	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4014	cErrors++;
4015	continue;
4016	}
4017	fIgnoreFlags \|= X86_PTE_RW;
4018	}
4019	else
4020	{
4021	if ( SHW_PTE_IS_P(PteDst)
4022	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4023	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4024	# endif
4025	)
4026	{
4027	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4029	cErrors++;
4030	continue;
4031	}
4032	fIgnoreFlags \|= X86_PTE_P;
4033	}
4034	}
4035	else
4036	{
4037	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4038	{
4039	if (SHW_PTE_IS_RW(PteDst))
4040	{
4041	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4042	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4043	cErrors++;
4044	continue;
4045	}
4046	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4047	{
4048	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4049	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4050	cErrors++;
4051	continue;
4052	}
4053	if (SHW_PTE_IS_D(PteDst))
4054	{
4055	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4056	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4057	cErrors++;
4058	}
4059	# if 0 /** @todo sync access bit properly... */
4060	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4061	{
4062	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4063	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4064	cErrors++;
4065	}
4066	fIgnoreFlags \|= X86_PTE_RW;
4067	# else
4068	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4069	# endif
4070	}
4071	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4072	{
4073	/* access bit emulation (not implemented). */
4074	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4075	{
4076	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4077	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4078	cErrors++;
4079	continue;
4080	}
4081	if (!SHW_PTE_IS_A(PteDst))
4082	{
4083	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4084	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4085	cErrors++;
4086	}
4087	fIgnoreFlags \|= X86_PTE_P;
4088	}
4089	# ifdef DEBUG_sandervl
4090	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4091	# endif
4092	}
4093
4094	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4095	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4096	)
4097	{
4098	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4100	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4101	cErrors++;
4102	continue;
4103	}
4104	} /* foreach PTE */
4105	}
4106	else
4107	{
4108	/*
4109	* Big Page.
4110	*/
4111	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4112	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4113	{
4114	if (PdeDst.n.u1Write)
4115	{
4116	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4117	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4118	cErrors++;
4119	continue;
4120	}
4121	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4122	{
4123	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4124	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4125	cErrors++;
4126	continue;
4127	}
4128	# if 0 /** @todo sync access bit properly... */
4129	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4130	{
4131	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4132	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4133	cErrors++;
4134	}
4135	fIgnoreFlags \|= X86_PTE_RW;
4136	# else
4137	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4138	# endif
4139	}
4140	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4141	{
4142	/* access bit emulation (not implemented). */
4143	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4144	{
4145	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4146	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4147	cErrors++;
4148	continue;
4149	}
4150	if (!PdeDst.n.u1Accessed)
4151	{
4152	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4153	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4154	cErrors++;
4155	}
4156	fIgnoreFlags \|= X86_PTE_P;
4157	}
4158
4159	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4160	{
4161	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4162	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4163	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4164	cErrors++;
4165	}
4166
4167	/* iterate the page table. */
4168	for (unsigned iPT = 0, off = 0;
4169	iPT < RT_ELEMENTS(pPTDst->a);
4170	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4171	{
4172	const SHWPTE PteDst = pPTDst->a[iPT];
4173
4174	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4175	{
4176	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4177	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4178	cErrors++;
4179	}
4180
4181	/* skip not-present entries. */
4182	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4183	continue;
4184
4185	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4186
4187	/* match the physical addresses */
4188	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4189
4190	# ifdef IN_RING3
4191	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4192	if (RT_FAILURE(rc))
4193	{
4194	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4195	{
4196	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4197	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4198	cErrors++;
4199	}
4200	}
4201	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4202	{
4203	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4204	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4205	cErrors++;
4206	continue;
4207	}
4208	# endif
4209	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4210	if (!pPhysPage)
4211	{
4212	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4213	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4214	{
4215	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4216	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4217	cErrors++;
4218	continue;
4219	}
4220	# endif
4221	if (SHW_PTE_IS_RW(PteDst))
4222	{
4223	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4224	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4225	cErrors++;
4226	}
4227	fIgnoreFlags \|= X86_PTE_RW;
4228	}
4229	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4230	{
4231	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4232	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4233	cErrors++;
4234	continue;
4235	}
4236
4237	/* flags */
4238	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4239	{
4240	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4241	{
4242	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4243	{
4244	if (SHW_PTE_IS_RW(PteDst))
4245	{
4246	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4247	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4248	cErrors++;
4249	continue;
4250	}
4251	fIgnoreFlags \|= X86_PTE_RW;
4252	}
4253	}
4254	else
4255	{
4256	if ( SHW_PTE_IS_P(PteDst)
4257	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4258	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4259	# endif
4260	)
4261	{
4262	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4263	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4264	cErrors++;
4265	continue;
4266	}
4267	fIgnoreFlags \|= X86_PTE_P;
4268	}
4269	}
4270
4271	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4272	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4273	)
4274	{
4275	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4276	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4277	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4278	cErrors++;
4279	continue;
4280	}
4281	} /* for each PTE */
4282	}
4283	}
4284	/* not present */
4285
4286	} /* for each PDE */
4287
4288	} /* for each PDPTE */
4289
4290	} /* for each PML4E */
4291
4292	# ifdef DEBUG
4293	if (cErrors)
4294	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4295	# endif
4296	# endif /* GST is in {32BIT, PAE, AMD64} */
4297	return cErrors;
4298	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
4299	}
4300	#endif /* VBOX_STRICT */
4301
4302
4303	/**
4304	* Sets up the CR3 for shadow paging
4305	*
4306	* @returns Strict VBox status code.
4307	* @retval VINF_SUCCESS.
4308	*
4309	* @param pVCpu The cross context virtual CPU structure.
4310	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4311	* mask already applied.)
4312	*/
4313	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
4314	{
4315	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4316
4317	/* Update guest paging info. */
4318	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4319	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4320	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4321
4322	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4323	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4324
4325	/*
4326	* Map the page CR3 points at.
4327	*/
4328	RTHCPTR HCPtrGuestCR3;
4329	pgmLock(pVM);
4330	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4331	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4332	/** @todo this needs some reworking wrt. locking? */
4333	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4334	HCPtrGuestCR3 = NIL_RTHCPTR;
4335	int rc = VINF_SUCCESS;
4336	# else
4337	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4338	# endif
4339	pgmUnlock(pVM);
4340	if (RT_SUCCESS(rc))
4341	{
4342	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4343	# ifdef VBOX_WITH_RAM_IN_KERNEL
4344	# ifdef IN_RING3
4345	pVCpu->pgm.s.pGst32BitPdR3 = (PX86PD)HCPtrGuestCR3;
4346	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
4347	# else
4348	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR3PTR;
4349	pVCpu->pgm.s.pGst32BitPdR0 = (PX86PD)HCPtrGuestCR3;
4350	# endif
4351	# else
4352	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4353	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4354	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4355	# endif
4356	# endif
4357
4358	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4359	# ifdef VBOX_WITH_RAM_IN_KERNEL
4360	# ifdef IN_RING3
4361	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCR3;
4362	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
4363	# else
4364	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
4365	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCR3;
4366	# endif
4367	# else
4368	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4369	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4370	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4371	# endif
4372	# endif
4373
4374	/*
4375	* Map the 4 PDs too.
4376	*/
4377	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4378	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4379	{
4380	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4381	if (pGuestPDPT->a[i].n.u1Present)
4382	{
4383	RTHCPTR HCPtr;
4384	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4385	pgmLock(pVM);
4386	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4387	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4388	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4389	HCPtr = NIL_RTHCPTR;
4390	int rc2 = VINF_SUCCESS;
4391	# else
4392	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4393	# endif
4394	pgmUnlock(pVM);
4395	if (RT_SUCCESS(rc2))
4396	{
4397	# ifdef VBOX_WITH_RAM_IN_KERNEL
4398	# ifdef IN_RING3
4399	pVCpu->pgm.s.apGstPaePDsR3[i] = (PX86PDPAE)HCPtr;
4400	pVCpu->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
4401	# else
4402	pVCpu->pgm.s.apGstPaePDsR3[i] = NIL_RTR3PTR;
4403	pVCpu->pgm.s.apGstPaePDsR0[i] = (PX86PDPAE)HCPtr;
4404	# endif
4405	# else
4406	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4407	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4408	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4409	# endif
4410	# endif
4411	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4412	continue;
4413	}
4414	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4415	}
4416
4417	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4418	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4419	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4420	# endif
4421	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4422	}
4423
4424	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4425	# ifdef VBOX_WITH_RAM_IN_KERNEL
4426	# ifdef IN_RING3
4427	pVCpu->pgm.s.pGstAmd64Pml4R3 = (PX86PML4)HCPtrGuestCR3;
4428	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
4429	# else
4430	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
4431	pVCpu->pgm.s.pGstAmd64Pml4R0 = (PX86PML4)HCPtrGuestCR3;
4432	# endif
4433	# else
4434	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4435	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4436	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4437	# endif
4438	# endif
4439	# endif
4440	}
4441	else
4442	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4443
4444	#else /* prot/real stub */
4445	int rc = VINF_SUCCESS;
4446	#endif
4447
4448	/*
4449	* Update shadow paging info for guest modes with paging (32-bit, PAE, AMD64).
4450	*/
4451	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4452	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4453	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4454	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4455	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4456
4457	Assert(!pVM->pgm.s.fNestedPaging);
4458	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4459
4460	/*
4461	* Update the shadow root page as well since that's not fixed.
4462	*/
4463	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4464	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4465	PPGMPOOLPAGE pNewShwPageCR3;
4466
4467	pgmLock(pVM);
4468
4469	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4470	if (pPool->cDirtyPages)
4471	pgmPoolResetDirtyPages(pVM);
4472	# endif
4473
4474	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4475	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4476	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4477	&pNewShwPageCR3);
4478	AssertFatalRC(rc);
4479	rc = VINF_SUCCESS;
4480
4481	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4482	# ifdef IN_RING0
4483	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4484	# else
4485	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4486	# endif
4487
4488	# ifndef PGM_WITHOUT_MAPPINGS
4489	/*
4490	* Apply all hypervisor mappings to the new CR3.
4491	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4492	* make sure we check for conflicts in the new CR3 root.
4493	*/
4494	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4495	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4496	# endif
4497	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4498	AssertRCReturn(rc, rc);
4499	# endif
4500
4501	/* Set the current hypervisor CR3. */
4502	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4503
4504	/* Clean up the old CR3 root. */
4505	if ( pOldShwPageCR3
4506	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4507	{
4508	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4509	# ifndef PGM_WITHOUT_MAPPINGS
4510	/* Remove the hypervisor mappings from the shadow page table. */
4511	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4512	# endif
4513	/* Mark the page as unlocked; allow flushing again. */
4514	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4515
4516	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4517	}
4518	pgmUnlock(pVM);
4519	# else
4520	NOREF(GCPhysCR3);
4521	# endif
4522
4523	return rc;
4524	}
4525
4526	/**
4527	* Unmaps the shadow CR3.
4528	*
4529	* @returns VBox status, no specials.
4530	* @param pVCpu The cross context virtual CPU structure.
4531	*/
4532	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu)
4533	{
4534	LogFlow(("UnmapCR3\n"));
4535
4536	int rc = VINF_SUCCESS;
4537	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4538
4539	/*
4540	* Update guest paging info.
4541	*/
4542	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4543	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4544	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4545	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4546	# endif
4547
4548	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4549	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4550	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4551	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4552	# endif
4553	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4554	{
4555	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4556	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4557	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4558	# endif
4559	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4560	}
4561
4562	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4563	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4564	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4565	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4566	# endif
4567
4568	#else /* prot/real mode stub */
4569	/* nothing to do */
4570	#endif
4571
4572	/*
4573	* Update shadow paging info.
4574	*/
4575	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4576	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4577	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4578	# if PGM_GST_TYPE != PGM_TYPE_REAL
4579	Assert(!pVM->pgm.s.fNestedPaging);
4580	# endif
4581	pgmLock(pVM);
4582
4583	# ifndef PGM_WITHOUT_MAPPINGS
4584	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4585	/* Remove the hypervisor mappings from the shadow page table. */
4586	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4587	# endif
4588
4589	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4590	{
4591	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4592
4593	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4594	if (pPool->cDirtyPages)
4595	pgmPoolResetDirtyPages(pVM);
4596	# endif
4597
4598	/* Mark the page as unlocked; allow flushing again. */
4599	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4600
4601	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4602	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4603	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4604	}
4605
4606	pgmUnlock(pVM);
4607	#endif
4608
4609	return rc;
4610	}
4611

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 85938

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