PGMAllBth.h@ 93305

Last change on this file since 93305 was 93159, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Assertion to ensure Walk effective attributes are sane on success.
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1	/* $Id: PGMAllBth.h 93159 2022-01-10 07:58:36Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
6	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
7	* bird: WTF does this mean these days? Looking at PGMAll.cpp it's
8	*
9	* @remarks This file is one big \#ifdef-orgy!
10	*
11	*/
12
13	/*
14	* Copyright (C) 2006-2022 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25	#ifdef _MSC_VER
26	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
27	* real/prot-guest+RC mode. */
28	# pragma warning(disable: 4505)
29	#endif
30
31
32	/*********************************************************************************************************************************
33	* Internal Functions *
34	*********************************************************************************************************************************/
35	RT_C_DECLS_BEGIN
36	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
37	#ifndef IN_RING3
38	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
39	#endif
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	#else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu);
57
58	#ifdef IN_RING3
59	PGM_BTH_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
60	#endif
61	RT_C_DECLS_END
62
63
64
65
66	/*
67	* Filter out some illegal combinations of guest and shadow paging, so we can
68	* remove redundant checks inside functions.
69	*/
70	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE \
71	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
72	# error "Invalid combination; PAE guest implies PAE shadow"
73	#endif
74
75	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
76	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \
77	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
78	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
79	#endif
80
81	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
82	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
83	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
84	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
85	#endif
86
87	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE) \
88	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
89	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
90	#endif
91
92
93	/**
94	* Enters the shadow+guest mode.
95	*
96	* @returns VBox status code.
97	* @param pVCpu The cross context virtual CPU structure.
98	* @param GCPhysCR3 The physical address from the CR3 register.
99	*/
100	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
101	{
102	/* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
103	* Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
104	*/
105	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
106	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
107	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
108	&& ( PGM_GST_TYPE == PGM_TYPE_REAL \
109	\|\| PGM_GST_TYPE == PGM_TYPE_PROT))
110
111	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
112
113	Assert((HMIsNestedPagingActive(pVM) \|\| VM_IS_NEM_ENABLED(pVM)) == pVM->pgm.s.fNestedPaging);
114	Assert(!pVM->pgm.s.fNestedPaging);
115
116	PGM_LOCK_VOID(pVM);
117	/* Note: we only really need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes),
118	* but any calls to GC need a proper shadow page setup as well.
119	*/
120	/* Free the previous root mapping if still active. */
121	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
122	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
123	if (pOldShwPageCR3)
124	{
125	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
126
127	/* Mark the page as unlocked; allow flushing again. */
128	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
129
130	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
131	pVCpu->pgm.s.pShwPageCR3R3 = NIL_RTR3PTR;
132	pVCpu->pgm.s.pShwPageCR3R0 = NIL_RTR0PTR;
133	}
134
135	/* construct a fake address. */
136	GCPhysCR3 = RT_BIT_64(63);
137	PPGMPOOLPAGE pNewShwPageCR3;
138	int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
139	NIL_PGMPOOL_IDX, UINT32_MAX, false /fLockPage/,
140	&pNewShwPageCR3);
141	AssertRCReturn(rc, rc);
142
143	pVCpu->pgm.s.pShwPageCR3R3 = (R3PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR3(pVM, pNewShwPageCR3);
144	pVCpu->pgm.s.pShwPageCR3R0 = (R0PTRTYPE(PPGMPOOLPAGE))MMHyperCCToR0(pVM, pNewShwPageCR3);
145
146	/* Mark the page as locked; disallow flushing. */
147	pgmPoolLockPage(pPool, pNewShwPageCR3);
148
149	/* Set the current hypervisor CR3. */
150	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
151
152	PGM_UNLOCK(pVM);
153	return rc;
154	#else
155	NOREF(pVCpu); NOREF(GCPhysCR3);
156	return VINF_SUCCESS;
157	#endif
158	}
159
160
161	#ifndef IN_RING3
162
163	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
164	/**
165	* Deal with a guest page fault.
166	*
167	* @returns Strict VBox status code.
168	* @retval VINF_EM_RAW_GUEST_TRAP
169	* @retval VINF_EM_RAW_EMULATE_INSTR
170	*
171	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
172	* @param pWalk The guest page table walk result.
173	* @param uErr The error code.
174	*/
175	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, RTGCUINT uErr)
176	{
177	/*
178	* Calc the error code for the guest trap.
179	*/
180	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
181	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
182	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
183	if ( pWalk->fRsvdError
184	\|\| pWalk->fBadPhysAddr)
185	{
186	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
187	Assert(!pWalk->fNotPresent);
188	}
189	else if (!pWalk->fNotPresent)
190	uNewErr \|= X86_TRAP_PF_P;
191	TRPMSetErrorCode(pVCpu, uNewErr);
192
193	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pWalk->GCPtr, uErr, pWalk->uLevel));
194	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
195	return VINF_EM_RAW_GUEST_TRAP;
196	}
197	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
198
199
200	#if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
201	/**
202	* Deal with a guest page fault.
203	*
204	* The caller has taken the PGM lock.
205	*
206	* @returns Strict VBox status code.
207	*
208	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
209	* @param uErr The error code.
210	* @param pRegFrame The register frame.
211	* @param pvFault The fault address.
212	* @param pPage The guest page at @a pvFault.
213	* @param pWalk The guest page table walk result.
214	* @param pGstWalk The guest paging-mode specific walk information.
215	* @param pfLockTaken PGM lock taken here or not (out). This is true
216	* when we're called.
217	*/
218	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
219	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
220	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
221	, PPGMPTWALK pWalk
222	, PGSTPTWALK pGstWalk
223	# endif
224	)
225	{
226	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
227	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
228	# endif
229	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
230	VBOXSTRICTRC rcStrict;
231
232	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
233	{
234	/*
235	* Physical page access handler.
236	*/
237	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
238	const RTGCPHYS GCPhysFault = pWalk->GCPhys;
239	# else
240	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
241	# endif
242	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
243	if (pCur)
244	{
245	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
246
247	# ifdef PGM_SYNC_N_PAGES
248	/*
249	* If the region is write protected and we got a page not present fault, then sync
250	* the pages. If the fault was caused by a read, then restart the instruction.
251	* In case of write access continue to the GC write handler.
252	*
253	* ASSUMES that there is only one handler per page or that they have similar write properties.
254	*/
255	if ( !(uErr & X86_TRAP_PF_P)
256	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
257	{
258	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
259	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
260	# else
261	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
262	# endif
263	if ( RT_FAILURE(rcStrict)
264	\|\| !(uErr & X86_TRAP_PF_RW)
265	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
266	{
267	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
268	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
269	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
270	return rcStrict;
271	}
272	}
273	# endif
274	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
275	/*
276	* If the access was not thru a #PF(RSVD\|...) resync the page.
277	*/
278	if ( !(uErr & X86_TRAP_PF_RSVD)
279	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
280	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
281	&& (pWalk->fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK))
282	== PGM_PTATTRS_W_MASK /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
283	# endif
284	)
285	{
286	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
287	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
288	# else
289	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
290	# endif
291	if ( RT_FAILURE(rcStrict)
292	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
293	{
294	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
295	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
296	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
297	return rcStrict;
298	}
299	}
300	# endif
301
302	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
303	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
304	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
305	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
306	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
307	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
308	else
309	{
310	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
311	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
312	}
313
314	if (pCurType->CTX_SUFF(pfnPfHandler))
315	{
316	STAM_PROFILE_START(&pCur->Stat, h);
317
318	if (pCurType->fKeepPgmLock)
319	{
320	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault,
321	pCur->CTX_SUFF(pvUser));
322
323	# ifdef VBOX_WITH_STATISTICS
324	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault); /* paranoia in case the handler deregistered itself */
325	if (pCur)
326	STAM_PROFILE_STOP(&pCur->Stat, h);
327	# endif
328	}
329	else
330	{
331	void * const pvUser = pCur->CTX_SUFF(pvUser);
332	PGM_UNLOCK(pVM);
333	*pfLockTaken = false;
334
335	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
336
337	# ifdef VBOX_WITH_STATISTICS
338	PGM_LOCK_VOID(pVM);
339	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
340	if (pCur)
341	STAM_PROFILE_STOP(&pCur->Stat, h);
342	PGM_UNLOCK(pVM);
343	# endif
344	}
345	}
346	else
347	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
348
349	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
350	return rcStrict;
351	}
352	}
353
354	/*
355	* There is a handled area of the page, but this fault doesn't belong to it.
356	* We must emulate the instruction.
357	*
358	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
359	* we first check if this was a page-not-present fault for a page with only
360	* write access handlers. Restart the instruction if it wasn't a write access.
361	*/
362	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersUnhandled);
363
364	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
365	&& !(uErr & X86_TRAP_PF_P))
366	{
367	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
368	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
369	# else
370	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
371	# endif
372	if ( RT_FAILURE(rcStrict)
373	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
374	\|\| !(uErr & X86_TRAP_PF_RW))
375	{
376	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
377	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
378	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
379	return rcStrict;
380	}
381	}
382
383	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
384	* It's writing to an unhandled part of the LDT page several million times.
385	*/
386	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
387	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
388	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndUnhandled; });
389	return rcStrict;
390	} /* if any kind of handler */
391	# endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE*/
392
393
394	/**
395	* \#PF Handler for raw-mode guest execution.
396	*
397	* @returns VBox status code (appropriate for trap handling and GC return).
398	*
399	* @param pVCpu The cross context virtual CPU structure.
400	* @param uErr The trap error code.
401	* @param pRegFrame Trap register frame.
402	* @param pvFault The fault address.
403	* @param pfLockTaken PGM lock taken here or not (out)
404	*/
405	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
406	{
407	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
408
409	*pfLockTaken = false;
410
411	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
412	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
413	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
414	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
415	&& PGM_SHW_TYPE != PGM_TYPE_NONE
416	int rc;
417
418	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
419	/*
420	* Walk the guest page translation tables and check if it's a guest fault.
421	*/
422	PGMPTWALK Walk;
423	GSTPTWALK GstWalk;
424	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &Walk, &GstWalk);
425	if (RT_FAILURE_NP(rc))
426	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
427
428	/* assert some GstWalk sanity. */
429	# if PGM_GST_TYPE == PGM_TYPE_AMD64
430	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
431	# endif
432	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
433	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
434	# endif
435	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
436	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
437	Assert(Walk.fSucceeded);
438	Assert(Walk.fEffective & PGM_PTATTRS_R_MASK);
439
440	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
441	{
442	if ( ( (uErr & X86_TRAP_PF_RW)
443	&& !(Walk.fEffective & PGM_PTATTRS_W_MASK)
444	&& ( (uErr & X86_TRAP_PF_US)
445	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
446	\|\| ((uErr & X86_TRAP_PF_US) && !(Walk.fEffective & PGM_PTATTRS_US_MASK))
447	\|\| ((uErr & X86_TRAP_PF_ID) && (Walk.fEffective & PGM_PTATTRS_NX_MASK))
448	)
449	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
450	}
451
452	/* Take the big lock now before we update flags. */
453	*pfLockTaken = true;
454	PGM_LOCK_VOID(pVM);
455
456	/*
457	* Set the accessed and dirty flags.
458	*/
459	/** @todo Should probably use cmpxchg logic here as we're potentially racing
460	* other CPUs in SMP configs. (the lock isn't enough, since we take it
461	* after walking and the page tables could be stale already) */
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64
463	if (!(GstWalk.Pml4e.u & X86_PML4E_A))
464	{
465	GstWalk.Pml4e.u \|= X86_PML4E_A;
466	GST_ATOMIC_OR(&GstWalk.pPml4e->u, X86_PML4E_A);
467	}
468	if (!(GstWalk.Pdpe.u & X86_PDPE_A))
469	{
470	GstWalk.Pdpe.u \|= X86_PDPE_A;
471	GST_ATOMIC_OR(&GstWalk.pPdpe->u, X86_PDPE_A);
472	}
473	# endif
474	if (Walk.fBigPage)
475	{
476	Assert(GstWalk.Pde.u & X86_PDE_PS);
477	if (uErr & X86_TRAP_PF_RW)
478	{
479	if ((GstWalk.Pde.u & (X86_PDE4M_A \| X86_PDE4M_D)) != (X86_PDE4M_A \| X86_PDE4M_D))
480	{
481	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
482	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A \| X86_PDE4M_D);
483	}
484	}
485	else
486	{
487	if (!(GstWalk.Pde.u & X86_PDE4M_A))
488	{
489	GstWalk.Pde.u \|= X86_PDE4M_A;
490	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A);
491	}
492	}
493	}
494	else
495	{
496	Assert(!(GstWalk.Pde.u & X86_PDE_PS));
497	if (!(GstWalk.Pde.u & X86_PDE_A))
498	{
499	GstWalk.Pde.u \|= X86_PDE_A;
500	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE_A);
501	}
502
503	if (uErr & X86_TRAP_PF_RW)
504	{
505	# ifdef VBOX_WITH_STATISTICS
506	if (GstWalk.Pte.u & X86_PTE_D)
507	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageAlreadyDirty));
508	else
509	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtiedPage));
510	# endif
511	if ((GstWalk.Pte.u & (X86_PTE_A \| X86_PTE_D)) != (X86_PTE_A \| X86_PTE_D))
512	{
513	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
514	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A \| X86_PTE_D);
515	}
516	}
517	else
518	{
519	if (!(GstWalk.Pte.u & X86_PTE_A))
520	{
521	GstWalk.Pte.u \|= X86_PTE_A;
522	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A);
523	}
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	#if 0
528	/* Disabling this since it's not reliable for SMP, see @bugref{10092#c22}. */
529	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
530	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
531	#endif
532
533	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
534	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
535
536	/* Take the big lock now. */
537	*pfLockTaken = true;
538	PGM_LOCK_VOID(pVM);
539	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
540
541	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
542	/*
543	* If it is a reserved bit fault we know that it is an MMIO (access
544	* handler) related fault and can skip some 200 lines of code.
545	*/
546	if (uErr & X86_TRAP_PF_RSVD)
547	{
548	Assert(uErr & X86_TRAP_PF_P);
549	PPGMPAGE pPage;
550	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
551	rc = pgmPhysGetPageEx(pVM, Walk.GCPhys, &pPage);
552	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
553	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
554	pfLockTaken, &Walk, &GstWalk));
555	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
556	# else
557	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
558	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
559	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
560	pfLockTaken));
561	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
562	# endif
563	AssertRC(rc);
564	PGM_INVL_PG(pVCpu, pvFault);
565	return rc; /* Restart with the corrected entry. */
566	}
567	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
568
569	/*
570	* Fetch the guest PDE, PDPE and PML4E.
571	*/
572	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
573	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
574	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
575
576	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
577	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
578	PX86PDPAE pPDDst;
579	# if PGM_GST_TYPE == PGM_TYPE_PAE
580	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
581	# else
582	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
583	# endif
584	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
585
586	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
587	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
588	PX86PDPAE pPDDst;
589	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
590	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
591	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
592	# else
593	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
594	# endif
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
596
597	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
598	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
599	PEPTPD pPDDst;
600	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
601	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
602	# endif
603	Assert(pPDDst);
604
605	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
606	/*
607	* Dirty page handling.
608	*
609	* If we successfully correct the write protection fault due to dirty bit
610	* tracking, then return immediately.
611	*/
612	if (uErr & X86_TRAP_PF_RW) /* write fault? */
613	{
614	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
615	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
616	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
617	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
618	{
619	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0
620	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
621	? &pVCpu->pgm.s.Stats.StatRZTrap0eTime2DirtyAndAccessed
622	: &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
623	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
624	return VINF_SUCCESS;
625	}
626	#ifdef DEBUG_bird
627	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
628	AssertMsg(Walk.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
629	#endif
630	}
631
632	# if 0 /* rarely useful; leave for debugging. */
633	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
634	# endif
635	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
636
637	/*
638	* A common case is the not-present error caused by lazy page table syncing.
639	*
640	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
641	* here so we can safely assume that the shadow PT is present when calling
642	* SyncPage later.
643	*
644	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
645	* of mapping conflict and defer to SyncCR3 in R3.
646	* (Again, we do NOT support access handlers for non-present guest pages.)
647	*
648	*/
649	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
650	Assert(GstWalk.Pde.u & X86_PDE_P);
651	# endif
652	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
653	&& !SHW_PDE_IS_P(pPDDst->a[iPDDst]))
654	{
655	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
656	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
657	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
658	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
659	# else
660	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
661	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
662	# endif
663	if (RT_SUCCESS(rc))
664	return rc;
665	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
666	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
667	return VINF_PGM_SYNC_CR3;
668	}
669
670	/*
671	* Check if this fault address is flagged for special treatment,
672	* which means we'll have to figure out the physical address and
673	* check flags associated with it.
674	*
675	* ASSUME that we can limit any special access handling to pages
676	* in page tables which the guest believes to be present.
677	*/
678	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
679	RTGCPHYS GCPhys = Walk.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
680	# else
681	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
682	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
683	PPGMPAGE pPage;
684	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
685	if (RT_FAILURE(rc))
686	{
687	/*
688	* When the guest accesses invalid physical memory (e.g. probing
689	* of RAM or accessing a remapped MMIO range), then we'll fall
690	* back to the recompiler to emulate the instruction.
691	*/
692	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
693	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
694	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
695	return VINF_EM_RAW_EMULATE_INSTR;
696	}
697
698	/*
699	* Any handlers for this page?
700	*/
701	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
702	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
703	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
704	&Walk, &GstWalk));
705	# else
706	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
707	# endif
708
709	/*
710	* We are here only if page is present in Guest page tables and
711	* trap is not handled by our handlers.
712	*
713	* Check it for page out-of-sync situation.
714	*/
715	if (!(uErr & X86_TRAP_PF_P))
716	{
717	/*
718	* Page is not present in our page tables. Try to sync it!
719	*/
720	if (uErr & X86_TRAP_PF_US)
721	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
722	else /* supervisor */
723	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
724
725	if (PGM_PAGE_IS_BALLOONED(pPage))
726	{
727	/* Emulate reads from ballooned pages as they are not present in
728	our shadow page tables. (Required for e.g. Solaris guests; soft
729	ecc, random nr generator.) */
730	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
731	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
732	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncBallloon));
733	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Ballooned; });
734	return rc;
735	}
736
737	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
738	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
739	# else
740	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
741	# endif
742	if (RT_SUCCESS(rc))
743	{
744	/* The page was successfully synced, return to the guest. */
745	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
746	return VINF_SUCCESS;
747	}
748	}
749	else /* uErr & X86_TRAP_PF_P: */
750	{
751	/*
752	* Write protected pages are made writable when the guest makes the
753	* first write to it. This happens for pages that are shared, write
754	* monitored or not yet allocated.
755	*
756	* We may also end up here when CR0.WP=0 in the guest.
757	*
758	* Also, a side effect of not flushing global PDEs are out of sync
759	* pages due to physical monitored regions, that are no longer valid.
760	* Assume for now it only applies to the read/write flag.
761	*/
762	if (uErr & X86_TRAP_PF_RW)
763	{
764	/*
765	* Check if it is a read-only page.
766	*/
767	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
768	{
769	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
770	Assert(!PGM_PAGE_IS_ZERO(pPage));
771	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
772	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
773
774	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
775	if (rc != VINF_SUCCESS)
776	{
777	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
778	return rc;
779	}
780	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
781	return VINF_EM_NO_MEMORY;
782	}
783
784	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
785	/*
786	* Check to see if we need to emulate the instruction if CR0.WP=0.
787	*/
788	if ( !(Walk.fEffective & PGM_PTATTRS_W_MASK)
789	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
790	&& CPUMGetGuestCPL(pVCpu) < 3)
791	{
792	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
793
794	/*
795	* The Netware WP0+RO+US hack.
796	*
797	* Netware sometimes(/always?) runs with WP0. It has been observed doing
798	* excessive write accesses to pages which are mapped with US=1 and RW=0
799	* while WP=0. This causes a lot of exits and extremely slow execution.
800	* To avoid trapping and emulating every write here, we change the shadow
801	* page table entry to map it as US=0 and RW=1 until user mode tries to
802	* access it again (see further below). We count these shadow page table
803	* changes so we can avoid having to clear the page pool every time the WP
804	* bit changes to 1 (see PGMCr0WpEnabled()).
805	*/
806	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
807	if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
808	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
809	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
810	{
811	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, Walk.fBigPage));
812	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, Walk.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
813	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
814	{
815	PGM_INVL_PG(pVCpu, pvFault);
816	pVCpu->pgm.s.cNetwareWp0Hacks++;
817	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsHack; });
818	return rc;
819	}
820	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
821	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
822	}
823	# endif
824
825	/* Interpret the access. */
826	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
827	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), Walk.fBigPage, !!(Walk.fEffective & PGM_PTATTRS_US_MASK)));
828	if (RT_SUCCESS(rc))
829	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulInRZ);
830	else
831	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulToR3);
832	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2WPEmulation; });
833	return rc;
834	}
835	# endif
836	/// @todo count the above case; else
837	if (uErr & X86_TRAP_PF_US)
838	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
839	else /* supervisor */
840	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
841
842	/*
843	* Sync the page.
844	*
845	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
846	* page is not present, which is not true in this case.
847	*/
848	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
849	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
850	# else
851	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
852	# endif
853	if (RT_SUCCESS(rc))
854	{
855	/*
856	* Page was successfully synced, return to guest but invalidate
857	* the TLB first as the page is very likely to be in it.
858	*/
859	# if PGM_SHW_TYPE == PGM_TYPE_EPT
860	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
861	# else
862	PGM_INVL_PG(pVCpu, pvFault);
863	# endif
864	# ifdef VBOX_STRICT
865	PGMPTWALK GstPageWalk;
866	GstPageWalk.GCPhys = RTGCPHYS_MAX;
867	if (!pVM->pgm.s.fNestedPaging)
868	{
869	rc = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
870	AssertMsg(RT_SUCCESS(rc) && ((GstPageWalk.fEffective & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, GstPageWalk.fEffective));
871	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GstPageWalk.GCPhys, GstPageWalk.fEffective));
872	}
873	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
874	uint64_t fPageShw = 0;
875	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
876	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
877	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GstPageWalk.GCPhys, fPageGst, pvFault));
878	# endif
879	# endif /* VBOX_STRICT */
880	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
881	return VINF_SUCCESS;
882	}
883	}
884	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
885	/*
886	* Check for Netware WP0+RO+US hack from above and undo it when user
887	* mode accesses the page again.
888	*/
889	else if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
890	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
891	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
892	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
893	&& CPUMGetGuestCPL(pVCpu) == 3
894	&& pVM->cCpus == 1
895	)
896	{
897	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
898	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
899	if (RT_SUCCESS(rc))
900	{
901	PGM_INVL_PG(pVCpu, pvFault);
902	pVCpu->pgm.s.cNetwareWp0Hacks--;
903	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsUnhack; });
904	return VINF_SUCCESS;
905	}
906	}
907	# endif /* PGM_WITH_PAGING */
908
909	/** @todo else: why are we here? */
910
911	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
912	/*
913	* Check for VMM page flags vs. Guest page flags consistency.
914	* Currently only for debug purposes.
915	*/
916	if (RT_SUCCESS(rc))
917	{
918	/* Get guest page flags. */
919	PGMPTWALK GstPageWalk;
920	int rc2 = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
921	if (RT_SUCCESS(rc2))
922	{
923	uint64_t fPageShw = 0;
924	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
925
926	#if 0
927	/*
928	* Compare page flags.
929	* Note: we have AVL, A, D bits desynced.
930	*/
931	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
932	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
933	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
934	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
935	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
936	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
937	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
938	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
939	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
940	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
941	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
942
943	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
944	01:01:15.625516 00:08:43.268051 Location :
945	e:\vbox\svn\trunk\srcPage flags mismatch!
946	pvFault=fffff801b0d7b000
947	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
948	GCPhys=0000000019b52000
949	fPageShw=0
950	fPageGst=77b0000000000121
951	rc=0
952	#endif
953
954	}
955	else
956	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
957	}
958	else
959	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
960	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
961	}
962
963
964	/*
965	* If we get here it is because something failed above, i.e. most like guru
966	* meditiation time.
967	*/
968	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
969	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
970	return rc;
971
972	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE. */
973	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
974	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
975	return VERR_PGM_NOT_USED_IN_MODE;
976	# endif
977	}
978
979	#endif /* !IN_RING3 */
980
981
982	/**
983	* Emulation of the invlpg instruction.
984	*
985	*
986	* @returns VBox status code.
987	*
988	* @param pVCpu The cross context virtual CPU structure.
989	* @param GCPtrPage Page to invalidate.
990	*
991	* @remark ASSUMES that the guest is updating before invalidating. This order
992	* isn't required by the CPU, so this is speculative and could cause
993	* trouble.
994	* @remark No TLB shootdown is done on any other VCPU as we assume that
995	* invlpg emulation is the only reason for calling this function.
996	* (The guest has to shoot down TLB entries on other CPUs itself)
997	* Currently true, but keep in mind!
998	*
999	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1000	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1001	*/
1002	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1003	{
1004	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1005	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
1006	&& PGM_SHW_TYPE != PGM_TYPE_NONE
1007	int rc;
1008	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1009	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1010
1011	PGM_LOCK_ASSERT_OWNER(pVM);
1012
1013	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1014
1015	/*
1016	* Get the shadow PD entry and skip out if this PD isn't present.
1017	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1018	*/
1019	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1020	const unsigned iPDDst = (uint32_t)GCPtrPage >> SHW_PD_SHIFT;
1021	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1022
1023	/* Fetch the pgm pool shadow descriptor. */
1024	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1025	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1026	if (!pShwPde)
1027	{
1028	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1029	return VINF_SUCCESS;
1030	}
1031	# else
1032	Assert(pShwPde);
1033	# endif
1034
1035	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1036	const unsigned iPdpt = (uint32_t)GCPtrPage >> X86_PDPT_SHIFT;
1037	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1038
1039	/* If the shadow PDPE isn't present, then skip the invalidate. */
1040	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1041	if (!pPdptDst \|\| !(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1042	# else
1043	if (!(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1044	# endif
1045	{
1046	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1047	PGM_INVL_PG(pVCpu, GCPtrPage);
1048	return VINF_SUCCESS;
1049	}
1050
1051	/* Fetch the pgm pool shadow descriptor. */
1052	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1053	AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1054
1055	PX86PDPAE pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1056	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1057	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1058
1059	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1060	/* PML4 */
1061	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1062	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1063	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1064	PX86PDPAE pPDDst;
1065	PX86PDPT pPdptDst;
1066	PX86PML4E pPml4eDst;
1067	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1068	if (rc != VINF_SUCCESS)
1069	{
1070	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1071	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1072	PGM_INVL_PG(pVCpu, GCPtrPage);
1073	return VINF_SUCCESS;
1074	}
1075	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1076	Assert(pPDDst);
1077	Assert(pPdptDst->a[iPdpt].u & X86_PDPE_P);
1078
1079	/* Fetch the pgm pool shadow descriptor. */
1080	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1081	Assert(pShwPde);
1082
1083	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1084
1085	const SHWPDE PdeDst = *pPdeDst;
1086	if (!(PdeDst.u & X86_PDE_P))
1087	{
1088	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1089	PGM_INVL_PG(pVCpu, GCPtrPage);
1090	return VINF_SUCCESS;
1091	}
1092
1093	/*
1094	* Get the guest PD entry and calc big page.
1095	*/
1096	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1097	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1098	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
1099	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1100	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1101	unsigned iPDSrc = 0;
1102	# if PGM_GST_TYPE == PGM_TYPE_PAE
1103	X86PDPE PdpeSrcIgn;
1104	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1105	# else /* AMD64 */
1106	PX86PML4E pPml4eSrcIgn;
1107	X86PDPE PdpeSrcIgn;
1108	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1109	# endif
1110	GSTPDE PdeSrc;
1111
1112	if (pPDSrc)
1113	PdeSrc = pPDSrc->a[iPDSrc];
1114	else
1115	PdeSrc.u = 0;
1116	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1117	const bool fWasBigPage = RT_BOOL(PdeDst.u & PGM_PDFLAGS_BIG_PAGE);
1118	const bool fIsBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
1119	if (fWasBigPage != fIsBigPage)
1120	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1121
1122	# ifdef IN_RING3
1123	/*
1124	* If a CR3 Sync is pending we may ignore the invalidate page operation
1125	* depending on the kind of sync and if it's a global page or not.
1126	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1127	*/
1128	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1129	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1130	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1131	&& fIsBigPage
1132	&& (PdeSrc.u & X86_PDE4M_G)
1133	)
1134	)
1135	# else
1136	if (VM_FF_IS_ANY_SET(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1137	# endif
1138	{
1139	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1140	return VINF_SUCCESS;
1141	}
1142	# endif /* IN_RING3 */
1143
1144	/*
1145	* Deal with the Guest PDE.
1146	*/
1147	rc = VINF_SUCCESS;
1148	if (PdeSrc.u & X86_PDE_P)
1149	{
1150	Assert( (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
1151	&& ((PdeSrc.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW) \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1152	if (!fIsBigPage)
1153	{
1154	/*
1155	* 4KB - page.
1156	*/
1157	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1158	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1159
1160	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1161	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1162	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1163	# endif
1164	if (pShwPage->GCPhys == GCPhys)
1165	{
1166	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1167	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1168
1169	PGSTPT pPTSrc;
1170	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1171	if (RT_SUCCESS(rc))
1172	{
1173	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1174	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1175	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1176	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1177	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1178	GCPtrPage, PteSrc.u & X86_PTE_P,
1179	(PteSrc.u & PdeSrc.u & X86_PTE_RW),
1180	(PteSrc.u & PdeSrc.u & X86_PTE_US),
1181	(uint64_t)PteSrc.u,
1182	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1183	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1184	}
1185	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1186	PGM_INVL_PG(pVCpu, GCPtrPage);
1187	}
1188	else
1189	{
1190	/*
1191	* The page table address changed.
1192	*/
1193	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1194	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1195	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1196	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1197	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1198	PGM_INVL_VCPU_TLBS(pVCpu);
1199	}
1200	}
1201	else
1202	{
1203	/*
1204	* 2/4MB - page.
1205	*/
1206	/* Before freeing the page, check if anything really changed. */
1207	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1208	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1209	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1210	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1211	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1212	# endif
1213	if ( pShwPage->GCPhys == GCPhys
1214	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1215	{
1216	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1217	/** @todo This test is wrong as it cannot check the G bit!
1218	* FIXME */
1219	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1220	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1221	&& ( (PdeSrc.u & X86_PDE4M_D) /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1222	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1223	{
1224	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1225	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1226	return VINF_SUCCESS;
1227	}
1228	}
1229
1230	/*
1231	* Ok, the page table is present and it's been changed in the guest.
1232	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1233	* We could do this for some flushes in GC too, but we need an algorithm for
1234	* deciding which 4MB pages containing code likely to be executed very soon.
1235	*/
1236	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1237	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1238	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1239	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1240	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1241	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1242	}
1243	}
1244	else
1245	{
1246	/*
1247	* Page directory is not present, mark shadow PDE not present.
1248	*/
1249	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1250	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1251	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1252	PGM_INVL_PG(pVCpu, GCPtrPage);
1253	}
1254	return rc;
1255
1256	#else /* guest real and protected mode, nested + ept, none. */
1257	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1258	NOREF(pVCpu); NOREF(GCPtrPage);
1259	return VINF_SUCCESS;
1260	#endif
1261	}
1262
1263	#if PGM_SHW_TYPE != PGM_TYPE_NONE
1264
1265	/**
1266	* Update the tracking of shadowed pages.
1267	*
1268	* @param pVCpu The cross context virtual CPU structure.
1269	* @param pShwPage The shadow page.
1270	* @param HCPhys The physical page we is being dereferenced.
1271	* @param iPte Shadow PTE index
1272	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1273	*/
1274	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1275	RTGCPHYS GCPhysPage)
1276	{
1277	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1278
1279	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1280	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1281	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1282
1283	/* Use the hint we retrieved from the cached guest PT. */
1284	if (pShwPage->fDirty)
1285	{
1286	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1287
1288	Assert(pShwPage->cPresent);
1289	Assert(pPool->cPresent);
1290	pShwPage->cPresent--;
1291	pPool->cPresent--;
1292
1293	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1294	AssertRelease(pPhysPage);
1295	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1296	return;
1297	}
1298	# else
1299	NOREF(GCPhysPage);
1300	# endif
1301
1302	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatTrackDeref, a);
1303	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1304
1305	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1306	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1307	* 2. write protect all shadowed pages. I.e. implement caching.
1308	*/
1309	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1310
1311	/*
1312	* Find the guest address.
1313	*/
1314	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1315	pRam;
1316	pRam = pRam->CTX_SUFF(pNext))
1317	{
1318	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1319	while (iPage-- > 0)
1320	{
1321	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1322	{
1323	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1324
1325	Assert(pShwPage->cPresent);
1326	Assert(pPool->cPresent);
1327	pShwPage->cPresent--;
1328	pPool->cPresent--;
1329
1330	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1331	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatTrackDeref, a);
1332	return;
1333	}
1334	}
1335	}
1336
1337	for (;;)
1338	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1339	}
1340
1341
1342	/**
1343	* Update the tracking of shadowed pages.
1344	*
1345	* @param pVCpu The cross context virtual CPU structure.
1346	* @param pShwPage The shadow page.
1347	* @param u16 The top 16-bit of the pPage->HCPhys.
1348	* @param pPage Pointer to the guest page. this will be modified.
1349	* @param iPTDst The index into the shadow table.
1350	*/
1351	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16,
1352	PPGMPAGE pPage, const unsigned iPTDst)
1353	{
1354	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1355
1356	/*
1357	* Just deal with the simple first time here.
1358	*/
1359	if (!u16)
1360	{
1361	STAM_COUNTER_INC(&pVM->pgm.s.Stats.StatTrackVirgin);
1362	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1363	/* Save the page table index. */
1364	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1365	}
1366	else
1367	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1368
1369	/* write back */
1370	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1371	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1372
1373	/* update statistics. */
1374	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1375	pShwPage->cPresent++;
1376	if (pShwPage->iFirstPresent > iPTDst)
1377	pShwPage->iFirstPresent = iPTDst;
1378	}
1379
1380
1381	/**
1382	* Modifies a shadow PTE to account for access handlers.
1383	*
1384	* @param pVM The cross context VM structure.
1385	* @param pPage The page in question.
1386	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1387	* A (accessed) bit so it can be emulated correctly.
1388	* @param pPteDst The shadow PTE (output). This is temporary storage and
1389	* does not need to be set atomically.
1390	*/
1391	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVMCC pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1392	{
1393	NOREF(pVM); RT_NOREF_PV(fPteSrc);
1394
1395	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1396	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1397	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1398	{
1399	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1400	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1401	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) \| EPT_E_READ \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1402	# else
1403	if (fPteSrc & X86_PTE_A)
1404	{
1405	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1406	SHW_PTE_SET_RO(*pPteDst);
1407	}
1408	else
1409	SHW_PTE_SET(*pPteDst, 0);
1410	# endif
1411	}
1412	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1413	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1414	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1415	&& ( BTH_IS_NP_ACTIVE(pVM)
1416	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1417	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1418	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1419	# endif
1420	)
1421	{
1422	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1423	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1424	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1425	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg
1426	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1427	\| EPT_E_WRITE
1428	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1429	\| EPT_E_MEMTYPE_INVALID_3;
1430	# else
1431	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1432	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1433	# endif
1434	}
1435	# endif
1436	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1437	else
1438	{
1439	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1440	SHW_PTE_SET(*pPteDst, 0);
1441	}
1442	/** @todo count these kinds of entries. */
1443	}
1444
1445
1446	/**
1447	* Creates a 4K shadow page for a guest page.
1448	*
1449	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1450	* physical address. The PdeSrc argument only the flags are used. No page
1451	* structured will be mapped in this function.
1452	*
1453	* @param pVCpu The cross context virtual CPU structure.
1454	* @param pPteDst Destination page table entry.
1455	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1456	* Can safely assume that only the flags are being used.
1457	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1458	* @param pShwPage Pointer to the shadow page.
1459	* @param iPTDst The index into the shadow table.
1460	*
1461	* @remark Not used for 2/4MB pages!
1462	*/
1463	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1464	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1465	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1466	# else
1467	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1468	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1469	# endif
1470	{
1471	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1472	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1473
1474	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1475	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1476	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1477
1478	if (pShwPage->fDirty)
1479	{
1480	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1481	PGSTPT pGstPT;
1482
1483	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1484	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1485	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1486	pGstPT->a[iPTDst].u = PteSrc.u;
1487	}
1488	# else
1489	Assert(!pShwPage->fDirty);
1490	# endif
1491
1492	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1493	if ( (PteSrc.u & X86_PTE_P)
1494	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1495	# endif
1496	{
1497	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1498	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1499	# endif
1500	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1501
1502	/*
1503	* Find the ram range.
1504	*/
1505	PPGMPAGE pPage;
1506	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1507	if (RT_SUCCESS(rc))
1508	{
1509	/* Ignore ballooned pages.
1510	Don't return errors or use a fatal assert here as part of a
1511	shadow sync range might included ballooned pages. */
1512	if (PGM_PAGE_IS_BALLOONED(pPage))
1513	{
1514	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1515	return;
1516	}
1517
1518	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1519	/* Make the page writable if necessary. */
1520	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1521	&& ( PGM_PAGE_IS_ZERO(pPage)
1522	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1523	\|\| ( (PteSrc.u & X86_PTE_RW)
1524	# else
1525	\|\| ( 1
1526	# endif
1527	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1528	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1529	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1530	# endif
1531	# ifdef VBOX_WITH_PAGE_SHARING
1532	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1533	# endif
1534	)
1535	)
1536	)
1537	{
1538	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1539	AssertRC(rc);
1540	}
1541	# endif
1542
1543	/*
1544	* Make page table entry.
1545	*/
1546	SHWPTE PteDst;
1547	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1548	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1549	# else
1550	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1551	# endif
1552	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1553	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1554	else
1555	{
1556	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1557	/*
1558	* If the page or page directory entry is not marked accessed,
1559	* we mark the page not present.
1560	*/
1561	if (!(PteSrc.u & X86_PTE_A) \|\| !(PdeSrc.u & X86_PDE_A))
1562	{
1563	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1564	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,AccessedPage));
1565	SHW_PTE_SET(PteDst, 0);
1566	}
1567	/*
1568	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1569	* when the page is modified.
1570	*/
1571	else if (!(PteSrc.u & X86_PTE_D) && (PdeSrc.u & PteSrc.u & X86_PTE_RW))
1572	{
1573	AssertCompile(X86_PTE_RW == X86_PDE_RW);
1574	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPage));
1575	SHW_PTE_SET(PteDst,
1576	fGstShwPteFlags
1577	\| PGM_PAGE_GET_HCPHYS(pPage)
1578	\| PGM_PTFLAGS_TRACK_DIRTY);
1579	SHW_PTE_SET_RO(PteDst);
1580	}
1581	else
1582	# endif
1583	{
1584	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageSkipped));
1585	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1586	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage)
1587	\| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1588	# else
1589	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1590	# endif
1591	}
1592
1593	/*
1594	* Make sure only allocated pages are mapped writable.
1595	*/
1596	if ( SHW_PTE_IS_P_RW(PteDst)
1597	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1598	{
1599	/* Still applies to shared pages. */
1600	Assert(!PGM_PAGE_IS_ZERO(pPage));
1601	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1602	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1603	}
1604	}
1605
1606	/*
1607	* Keep user track up to date.
1608	*/
1609	if (SHW_PTE_IS_P(PteDst))
1610	{
1611	if (!SHW_PTE_IS_P(*pPteDst))
1612	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1613	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1614	{
1615	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1616	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1617	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1618	}
1619	}
1620	else if (SHW_PTE_IS_P(*pPteDst))
1621	{
1622	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1623	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1624	}
1625
1626	/*
1627	* Update statistics and commit the entry.
1628	*/
1629	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1630	if (!(PteSrc.u & X86_PTE_G))
1631	pShwPage->fSeenNonGlobal = true;
1632	# endif
1633	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1634	return;
1635	}
1636
1637	/** @todo count these three different kinds. */
1638	Log2(("SyncPageWorker: invalid address in Pte\n"));
1639	}
1640	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1641	else if (!(PteSrc.u & X86_PTE_P))
1642	Log2(("SyncPageWorker: page not present in Pte\n"));
1643	else
1644	Log2(("SyncPageWorker: invalid Pte\n"));
1645	# endif
1646
1647	/*
1648	* The page is not present or the PTE is bad. Replace the shadow PTE by
1649	* an empty entry, making sure to keep the user tracking up to date.
1650	*/
1651	if (SHW_PTE_IS_P(*pPteDst))
1652	{
1653	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1654	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1655	}
1656	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1657	}
1658
1659
1660	/**
1661	* Syncs a guest OS page.
1662	*
1663	* There are no conflicts at this point, neither is there any need for
1664	* page table allocations.
1665	*
1666	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1667	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1668	*
1669	* @returns VBox status code.
1670	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1671	* @param pVCpu The cross context virtual CPU structure.
1672	* @param PdeSrc Page directory entry of the guest.
1673	* @param GCPtrPage Guest context page address.
1674	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1675	* @param uErr Fault error (X86_TRAP_PF_*).
1676	*/
1677	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1678	{
1679	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1680	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1681	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1682	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
1683
1684	PGM_LOCK_ASSERT_OWNER(pVM);
1685
1686	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1687	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1688	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1689	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
1690
1691	/*
1692	* Assert preconditions.
1693	*/
1694	Assert(PdeSrc.u & X86_PDE_P);
1695	Assert(cPages);
1696	# if 0 /* rarely useful; leave for debugging. */
1697	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1698	# endif
1699
1700	/*
1701	* Get the shadow PDE, find the shadow page table in the pool.
1702	*/
1703	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1704	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1705	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1706
1707	/* Fetch the pgm pool shadow descriptor. */
1708	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1709	Assert(pShwPde);
1710
1711	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1712	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1713	PPGMPOOLPAGE pShwPde = NULL;
1714	PX86PDPAE pPDDst;
1715
1716	/* Fetch the pgm pool shadow descriptor. */
1717	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1718	AssertRCSuccessReturn(rc2, rc2);
1719	Assert(pShwPde);
1720
1721	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1722	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1723
1724	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1725	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1726	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1727	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1728	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1729
1730	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1731	AssertRCSuccessReturn(rc2, rc2);
1732	Assert(pPDDst && pPdptDst);
1733	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1734	# endif
1735	SHWPDE PdeDst = *pPdeDst;
1736
1737	/*
1738	* - In the guest SMP case we could have blocked while another VCPU reused
1739	* this page table.
1740	* - With W7-64 we may also take this path when the A bit is cleared on
1741	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1742	* relevant TLB entries. If we're write monitoring any page mapped by
1743	* the modified entry, we may end up here with a "stale" TLB entry.
1744	*/
1745	if (!(PdeDst.u & X86_PDE_P))
1746	{
1747	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1748	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1749	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1750	if (uErr & X86_TRAP_PF_P)
1751	PGM_INVL_PG(pVCpu, GCPtrPage);
1752	return VINF_SUCCESS; /* force the instruction to be executed again. */
1753	}
1754
1755	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1756	Assert(pShwPage);
1757
1758	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1759	/* Fetch the pgm pool shadow descriptor. */
1760	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1761	Assert(pShwPde);
1762	# endif
1763
1764	/*
1765	* Check that the page is present and that the shadow PDE isn't out of sync.
1766	*/
1767	const bool fBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
1768	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1769	RTGCPHYS GCPhys;
1770	if (!fBigPage)
1771	{
1772	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1773	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1774	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1775	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1776	# endif
1777	}
1778	else
1779	{
1780	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1781	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1782	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1783	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1784	# endif
1785	}
1786	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1787	if ( fPdeValid
1788	&& pShwPage->GCPhys == GCPhys
1789	&& (PdeSrc.u & X86_PDE_P)
1790	&& (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
1791	&& ((PdeSrc.u & X86_PDE_RW) == (PdeDst.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW))
1792	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1793	&& ((PdeSrc.u & X86_PDE_PAE_NX) == (PdeDst.u & X86_PDE_PAE_NX) \|\| !GST_IS_NX_ACTIVE(pVCpu))
1794	# endif
1795	)
1796	{
1797	/*
1798	* Check that the PDE is marked accessed already.
1799	* Since we set the accessed bit before getting here on a #PF, this
1800	* check is only meant for dealing with non-#PF'ing paths.
1801	*/
1802	if (PdeSrc.u & X86_PDE_A)
1803	{
1804	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1805	if (!fBigPage)
1806	{
1807	/*
1808	* 4KB Page - Map the guest page table.
1809	*/
1810	PGSTPT pPTSrc;
1811	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1812	if (RT_SUCCESS(rc))
1813	{
1814	# ifdef PGM_SYNC_N_PAGES
1815	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1816	if ( cPages > 1
1817	&& !(uErr & X86_TRAP_PF_P)
1818	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1819	{
1820	/*
1821	* This code path is currently only taken when the caller is PGMTrap0eHandler
1822	* for non-present pages!
1823	*
1824	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1825	* deal with locality.
1826	*/
1827	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1828	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1829	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1830	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1831	# else
1832	const unsigned offPTSrc = 0;
1833	# endif
1834	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1835	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1836	iPTDst = 0;
1837	else
1838	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1839
1840	for (; iPTDst < iPTDstEnd; iPTDst++)
1841	{
1842	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1843
1844	if ( (pPteSrc->u & X86_PTE_P)
1845	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1846	{
1847	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1848	NOREF(GCPtrCurPage);
1849	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
1850	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1851	GCPtrCurPage, pPteSrc->u & X86_PTE_P,
1852	!!(pPteSrc->u & PdeSrc.u & X86_PTE_RW),
1853	!!(pPteSrc->u & PdeSrc.u & X86_PTE_US),
1854	(uint64_t)pPteSrc->u,
1855	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1856	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1857	}
1858	}
1859	}
1860	else
1861	# endif /* PGM_SYNC_N_PAGES */
1862	{
1863	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1864	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1865	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1866	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1867	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1868	GCPtrPage, PteSrc.u & X86_PTE_P,
1869	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
1870	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
1871	(uint64_t)PteSrc.u,
1872	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1873	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1874	}
1875	}
1876	else /* MMIO or invalid page: emulated in #PF handler. */
1877	{
1878	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1879	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1880	}
1881	}
1882	else
1883	{
1884	/*
1885	* 4/2MB page - lazy syncing shadow 4K pages.
1886	* (There are many causes of getting here, it's no longer only CSAM.)
1887	*/
1888	/* Calculate the GC physical address of this 4KB shadow page. */
1889	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
1890	/* Find ram range. */
1891	PPGMPAGE pPage;
1892	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
1893	if (RT_SUCCESS(rc))
1894	{
1895	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1896
1897	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1898	/* Try to make the page writable if necessary. */
1899	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1900	&& ( PGM_PAGE_IS_ZERO(pPage)
1901	\|\| ( (PdeSrc.u & X86_PDE_RW)
1902	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1903	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1904	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1905	# endif
1906	# ifdef VBOX_WITH_PAGE_SHARING
1907	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1908	# endif
1909	)
1910	)
1911	)
1912	{
1913	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1914	AssertRC(rc);
1915	}
1916	# endif
1917
1918	/*
1919	* Make shadow PTE entry.
1920	*/
1921	SHWPTE PteDst;
1922	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1923	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
1924	else
1925	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
1926
1927	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1928	if ( SHW_PTE_IS_P(PteDst)
1929	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1930	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1931
1932	/* Make sure only allocated pages are mapped writable. */
1933	if ( SHW_PTE_IS_P_RW(PteDst)
1934	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1935	{
1936	/* Still applies to shared pages. */
1937	Assert(!PGM_PAGE_IS_ZERO(pPage));
1938	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
1939	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1940	}
1941
1942	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
1943
1944	/*
1945	* If the page is not flagged as dirty and is writable, then make it read-only
1946	* at PD level, so we can set the dirty bit when the page is modified.
1947	*
1948	* ASSUMES that page access handlers are implemented on page table entry level.
1949	* Thus we will first catch the dirty access and set PDE.D and restart. If
1950	* there is an access handler, we'll trap again and let it work on the problem.
1951	*/
1952	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1953	* As for invlpg, it simply frees the whole shadow PT.
1954	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1955	if ((PdeSrc.u & (X86_PDE4M_D \| X86_PDE_RW)) == X86_PDE_RW)
1956	{
1957	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
1958	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1959	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
1960	}
1961	else
1962	{
1963	PdeDst.u &= ~(SHWUINT)(PGM_PDFLAGS_TRACK_DIRTY \| X86_PDE_RW);
1964	PdeDst.u \|= PdeSrc.u & X86_PDE_RW;
1965	}
1966	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
1967	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1968	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US),
1969	(uint64_t)PdeSrc.u, GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1970	}
1971	else
1972	{
1973	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1974	/** @todo must wipe the shadow page table entry in this
1975	* case. */
1976	}
1977	}
1978	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
1979	return VINF_SUCCESS;
1980	}
1981
1982	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDNAs));
1983	}
1984	else if (fPdeValid)
1985	{
1986	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1987	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1988	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1989	}
1990	else
1991	{
1992	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
1993	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1994	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1995	}
1996
1997	/*
1998	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1999	* Yea, I'm lazy.
2000	*/
2001	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2002	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
2003
2004	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2005	PGM_INVL_VCPU_TLBS(pVCpu);
2006	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2007
2008
2009	# elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2010	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2011	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2012	NOREF(PdeSrc);
2013
2014	# ifdef PGM_SYNC_N_PAGES
2015	/*
2016	* Get the shadow PDE, find the shadow page table in the pool.
2017	*/
2018	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2019	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2020
2021	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2022	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2023
2024	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2025	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2026	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2027	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2028	X86PDEPAE PdeDst;
2029	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2030
2031	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2032	AssertRCSuccessReturn(rc, rc);
2033	Assert(pPDDst && pPdptDst);
2034	PdeDst = pPDDst->a[iPDDst];
2035
2036	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2037	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2038	PEPTPD pPDDst;
2039	EPTPDE PdeDst;
2040
2041	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2042	if (rc != VINF_SUCCESS)
2043	{
2044	AssertRC(rc);
2045	return rc;
2046	}
2047	Assert(pPDDst);
2048	PdeDst = pPDDst->a[iPDDst];
2049	# endif
2050	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2051	if (!SHW_PDE_IS_P(PdeDst))
2052	{
2053	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2054	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2055	return VINF_SUCCESS; /* force the instruction to be executed again. */
2056	}
2057
2058	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2059	if (SHW_PDE_IS_BIG(PdeDst))
2060	{
2061	Assert(pVM->pgm.s.fNestedPaging);
2062	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2063	return VINF_SUCCESS;
2064	}
2065
2066	/* Mask away the page offset. */
2067	GCPtrPage &= ~((RTGCPTR)0xfff);
2068
2069	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2070	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2071
2072	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2073	if ( cPages > 1
2074	&& !(uErr & X86_TRAP_PF_P)
2075	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2076	{
2077	/*
2078	* This code path is currently only taken when the caller is PGMTrap0eHandler
2079	* for non-present pages!
2080	*
2081	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2082	* deal with locality.
2083	*/
2084	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2085	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2086	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2087	iPTDst = 0;
2088	else
2089	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2090	for (; iPTDst < iPTDstEnd; iPTDst++)
2091	{
2092	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2093	{
2094	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2095	\| (iPTDst << PAGE_SHIFT));
2096
2097	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2098	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2099	GCPtrCurPage,
2100	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2101	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2102
2103	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2104	break;
2105	}
2106	else
2107	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2108	}
2109	}
2110	else
2111	# endif /* PGM_SYNC_N_PAGES */
2112	{
2113	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2114	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2115	\| (iPTDst << PAGE_SHIFT));
2116
2117	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2118
2119	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2120	GCPtrPage,
2121	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2122	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2123	}
2124	return VINF_SUCCESS;
2125
2126	# else
2127	NOREF(PdeSrc);
2128	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2129	return VERR_PGM_NOT_USED_IN_MODE;
2130	# endif
2131	}
2132
2133	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
2134	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
2135
2136	/**
2137	* CheckPageFault helper for returning a page fault indicating a non-present
2138	* (NP) entry in the page translation structures.
2139	*
2140	* @returns VINF_EM_RAW_GUEST_TRAP.
2141	* @param pVCpu The cross context virtual CPU structure.
2142	* @param uErr The error code of the shadow fault. Corrections to
2143	* TRPM's copy will be made if necessary.
2144	* @param GCPtrPage For logging.
2145	* @param uPageFaultLevel For logging.
2146	*/
2147	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPUCC pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2148	{
2149	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyTrackRealPF));
2150	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2151	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2152	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2153	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2154
2155	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2156	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2157	return VINF_EM_RAW_GUEST_TRAP;
2158	}
2159
2160
2161	/**
2162	* CheckPageFault helper for returning a page fault indicating a reserved bit
2163	* (RSVD) error in the page translation structures.
2164	*
2165	* @returns VINF_EM_RAW_GUEST_TRAP.
2166	* @param pVCpu The cross context virtual CPU structure.
2167	* @param uErr The error code of the shadow fault. Corrections to
2168	* TRPM's copy will be made if necessary.
2169	* @param GCPtrPage For logging.
2170	* @param uPageFaultLevel For logging.
2171	*/
2172	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPUCC pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2173	{
2174	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyTrackRealPF));
2175	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2176	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2177
2178	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2179	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2180	return VINF_EM_RAW_GUEST_TRAP;
2181	}
2182
2183
2184	/**
2185	* CheckPageFault helper for returning a page protection fault (P).
2186	*
2187	* @returns VINF_EM_RAW_GUEST_TRAP.
2188	* @param pVCpu The cross context virtual CPU structure.
2189	* @param uErr The error code of the shadow fault. Corrections to
2190	* TRPM's copy will be made if necessary.
2191	* @param GCPtrPage For logging.
2192	* @param uPageFaultLevel For logging.
2193	*/
2194	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPUCC pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2195	{
2196	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyTrackRealPF));
2197	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2198	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2199	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2200
2201	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2202	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2203	return VINF_EM_RAW_GUEST_TRAP;
2204	}
2205
2206
2207	/**
2208	* Handle dirty bit tracking faults.
2209	*
2210	* @returns VBox status code.
2211	* @param pVCpu The cross context virtual CPU structure.
2212	* @param uErr Page fault error code.
2213	* @param pPdeSrc Guest page directory entry.
2214	* @param pPdeDst Shadow page directory entry.
2215	* @param GCPtrPage Guest context page address.
2216	*/
2217	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2218	RTGCPTR GCPtrPage)
2219	{
2220	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2221	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2222	NOREF(uErr);
2223
2224	PGM_LOCK_ASSERT_OWNER(pVM);
2225
2226	/*
2227	* Handle big page.
2228	*/
2229	if ((pPdeSrc->u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
2230	{
2231	if ((pPdeDst->u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
2232	{
2233	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
2234	Assert(pPdeSrc->u & X86_PDE_RW);
2235
2236	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2237	* fault again and take this path to only invalidate the entry (see below). */
2238	SHWPDE PdeDst = *pPdeDst;
2239	PdeDst.u &= ~(SHWUINT)PGM_PDFLAGS_TRACK_DIRTY;
2240	PdeDst.u \|= X86_PDE_RW \| X86_PDE_A;
2241	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2242	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2243	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2244	}
2245
2246	# ifdef IN_RING0
2247	/* Check for stale TLB entry; only applies to the SMP guest case. */
2248	if ( pVM->cCpus > 1
2249	&& (pPdeDst->u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A))
2250	{
2251	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2252	if (pShwPage)
2253	{
2254	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2255	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2256	if (SHW_PTE_IS_P_RW(*pPteDst))
2257	{
2258	/* Stale TLB entry. */
2259	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
2260	PGM_INVL_PG(pVCpu, GCPtrPage);
2261	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2262	}
2263	}
2264	}
2265	# endif /* IN_RING0 */
2266	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2267	}
2268
2269	/*
2270	* Map the guest page table.
2271	*/
2272	PGSTPT pPTSrc;
2273	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2274	AssertRCReturn(rc, rc);
2275
2276	if (SHW_PDE_IS_P(*pPdeDst))
2277	{
2278	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2279	const GSTPTE PteSrc = *pPteSrc;
2280
2281	/*
2282	* Map shadow page table.
2283	*/
2284	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2285	if (pShwPage)
2286	{
2287	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2288	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2289	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2290	{
2291	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2292	{
2293	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2294	SHWPTE PteDst = *pPteDst;
2295
2296	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2297	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
2298
2299	Assert(PteSrc.u & X86_PTE_RW);
2300
2301	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2302	* entry will not harm; write access will simply fault again and
2303	* take this path to only invalidate the entry.
2304	*/
2305	if (RT_LIKELY(pPage))
2306	{
2307	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2308	{
2309	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2310	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2311	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2312	SHW_PTE_SET_RO(PteDst);
2313	}
2314	else
2315	{
2316	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2317	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2318	{
2319	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2320	AssertRC(rc);
2321	}
2322	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2323	SHW_PTE_SET_RW(PteDst);
2324	else
2325	{
2326	/* Still applies to shared pages. */
2327	Assert(!PGM_PAGE_IS_ZERO(pPage));
2328	SHW_PTE_SET_RO(PteDst);
2329	}
2330	}
2331	}
2332	else
2333	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2334
2335	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2336	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2337	PGM_INVL_PG(pVCpu, GCPtrPage);
2338	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2339	}
2340
2341	# ifdef IN_RING0
2342	/* Check for stale TLB entry; only applies to the SMP guest case. */
2343	if ( pVM->cCpus > 1
2344	&& SHW_PTE_IS_RW(*pPteDst)
2345	&& SHW_PTE_IS_A(*pPteDst))
2346	{
2347	/* Stale TLB entry. */
2348	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
2349	PGM_INVL_PG(pVCpu, GCPtrPage);
2350	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2351	}
2352	# endif
2353	}
2354	}
2355	else
2356	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2357	}
2358
2359	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2360	}
2361
2362	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
2363
2364	/**
2365	* Sync a shadow page table.
2366	*
2367	* The shadow page table is not present in the shadow PDE.
2368	*
2369	* Handles mapping conflicts.
2370	*
2371	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2372	* conflict), and Trap0eHandler.
2373	*
2374	* A precondition for this method is that the shadow PDE is not present. The
2375	* caller must take the PGM lock before checking this and continue to hold it
2376	* when calling this method.
2377	*
2378	* @returns VBox status code.
2379	* @param pVCpu The cross context virtual CPU structure.
2380	* @param iPDSrc Page directory index.
2381	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2382	* Assume this is a temporary mapping.
2383	* @param GCPtrPage GC Pointer of the page that caused the fault
2384	*/
2385	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2386	{
2387	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2388	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2389
2390	#if 0 /* rarely useful; leave for debugging. */
2391	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2392	#endif
2393	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
2394
2395	PGM_LOCK_ASSERT_OWNER(pVM);
2396
2397	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2398	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2399	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2400	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
2401	&& PGM_SHW_TYPE != PGM_TYPE_NONE
2402	int rc = VINF_SUCCESS;
2403
2404	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2405
2406	/*
2407	* Some input validation first.
2408	*/
2409	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2410
2411	/*
2412	* Get the relevant shadow PDE entry.
2413	*/
2414	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2415	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2416	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2417
2418	/* Fetch the pgm pool shadow descriptor. */
2419	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2420	Assert(pShwPde);
2421
2422	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2423	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2424	PPGMPOOLPAGE pShwPde = NULL;
2425	PX86PDPAE pPDDst;
2426	PSHWPDE pPdeDst;
2427
2428	/* Fetch the pgm pool shadow descriptor. */
2429	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2430	AssertRCSuccessReturn(rc, rc);
2431	Assert(pShwPde);
2432
2433	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2434	pPdeDst = &pPDDst->a[iPDDst];
2435
2436	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2437	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2438	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2439	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2440	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2441	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2442	AssertRCSuccessReturn(rc, rc);
2443	Assert(pPDDst);
2444	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2445
2446	# endif
2447	SHWPDE PdeDst = *pPdeDst;
2448
2449	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2450	/* Fetch the pgm pool shadow descriptor. */
2451	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2452	Assert(pShwPde);
2453	# endif
2454
2455	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P.*/
2456
2457	/*
2458	* Sync the page directory entry.
2459	*/
2460	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2461	const bool fPageTable = !(PdeSrc.u & X86_PDE_PS) \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2462	if ( (PdeSrc.u & X86_PDE_P)
2463	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2464	{
2465	/*
2466	* Allocate & map the page table.
2467	*/
2468	PSHWPT pPTDst;
2469	PPGMPOOLPAGE pShwPage;
2470	RTGCPHYS GCPhys;
2471	if (fPageTable)
2472	{
2473	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2474	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2475	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2476	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2477	# endif
2478	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2479	pShwPde->idx, iPDDst, false /fLockPage/,
2480	&pShwPage);
2481	}
2482	else
2483	{
2484	PGMPOOLACCESS enmAccess;
2485	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2486	const bool fNoExecute = (PdeSrc.u & X86_PDE_PAE_NX) && GST_IS_NX_ACTIVE(pVCpu);
2487	# else
2488	const bool fNoExecute = false;
2489	# endif
2490
2491	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2492	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2493	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2494	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2495	# endif
2496	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2497	if (PdeSrc.u & X86_PDE_US)
2498	{
2499	if (PdeSrc.u & X86_PDE_RW)
2500	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2501	else
2502	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2503	}
2504	else
2505	{
2506	if (PdeSrc.u & X86_PDE_RW)
2507	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2508	else
2509	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2510	}
2511	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2512	pShwPde->idx, iPDDst, false /fLockPage/,
2513	&pShwPage);
2514	}
2515	if (rc == VINF_SUCCESS)
2516	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2517	else if (rc == VINF_PGM_CACHED_PAGE)
2518	{
2519	/*
2520	* The PT was cached, just hook it up.
2521	*/
2522	if (fPageTable)
2523	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2524	else
2525	{
2526	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2527	/* (see explanation and assumptions further down.) */
2528	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
2529	{
2530	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
2531	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2532	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
2533	}
2534	}
2535	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2536	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2537	return VINF_SUCCESS;
2538	}
2539	else
2540	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2541	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2542	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2543	* irrelevant at this point. */
2544	PdeDst.u &= X86_PDE_AVL_MASK;
2545	PdeDst.u \|= pShwPage->Core.Key;
2546
2547	/*
2548	* Page directory has been accessed (this is a fault situation, remember).
2549	*/
2550	/** @todo
2551	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2552	* fault situation. What's more, the Trap0eHandler has already set the
2553	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2554	* might need setting the accessed flag.
2555	*
2556	* The best idea is to leave this change to the caller and add an
2557	* assertion that it's set already. */
2558	pPDSrc->a[iPDSrc].u \|= X86_PDE_A;
2559	if (fPageTable)
2560	{
2561	/*
2562	* Page table - 4KB.
2563	*
2564	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2565	*/
2566	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2567	GCPtrPage, PdeSrc.u & X86_PTE_P, !!(PdeSrc.u & X86_PTE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u));
2568	PGSTPT pPTSrc;
2569	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2570	if (RT_SUCCESS(rc))
2571	{
2572	/*
2573	* Start by syncing the page directory entry so CSAM's TLB trick works.
2574	*/
2575	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2576	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2577	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2578	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2579
2580	/*
2581	* Directory/page user or supervisor privilege: (same goes for read/write)
2582	*
2583	* Directory Page Combined
2584	* U/S U/S U/S
2585	* 0 0 0
2586	* 0 1 0
2587	* 1 0 0
2588	* 1 1 1
2589	*
2590	* Simple AND operation. Table listed for completeness.
2591	*
2592	*/
2593	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4K));
2594	# ifdef PGM_SYNC_N_PAGES
2595	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2596	unsigned iPTDst = iPTBase;
2597	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2598	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2599	iPTDst = 0;
2600	else
2601	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2602	# else /* !PGM_SYNC_N_PAGES */
2603	unsigned iPTDst = 0;
2604	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2605	# endif /* !PGM_SYNC_N_PAGES */
2606	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2607	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2608	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2609	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2610	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2611	# else
2612	const unsigned offPTSrc = 0;
2613	# endif
2614	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2615	{
2616	const unsigned iPTSrc = iPTDst + offPTSrc;
2617	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2618	if (PteSrc.u & X86_PTE_P)
2619	{
2620	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2621	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2622	GCPtrCur,
2623	PteSrc.u & X86_PTE_P,
2624	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
2625	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
2626	(uint64_t)PteSrc.u,
2627	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2628	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2629	}
2630	/* else: the page table was cleared by the pool */
2631	} /* for PTEs */
2632	}
2633	}
2634	else
2635	{
2636	/*
2637	* Big page - 2/4MB.
2638	*
2639	* We'll walk the ram range list in parallel and optimize lookups.
2640	* We will only sync one shadow page table at a time.
2641	*/
2642	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4M));
2643
2644	/**
2645	* @todo It might be more efficient to sync only a part of the 4MB
2646	* page (similar to what we do for 4KB PDs).
2647	*/
2648
2649	/*
2650	* Start by syncing the page directory entry.
2651	*/
2652	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2653	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2654
2655	/*
2656	* If the page is not flagged as dirty and is writable, then make it read-only
2657	* at PD level, so we can set the dirty bit when the page is modified.
2658	*
2659	* ASSUMES that page access handlers are implemented on page table entry level.
2660	* Thus we will first catch the dirty access and set PDE.D and restart. If
2661	* there is an access handler, we'll trap again and let it work on the problem.
2662	*/
2663	/** @todo move the above stuff to a section in the PGM documentation. */
2664	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2665	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
2666	{
2667	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
2668	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2669	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
2670	}
2671	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2672	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2673
2674	/*
2675	* Fill the shadow page table.
2676	*/
2677	/* Get address and flags from the source PDE. */
2678	SHWPTE PteDstBase;
2679	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2680
2681	/* Loop thru the entries in the shadow PT. */
2682	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2683	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2684	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u, GCPtr,
2685	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2686	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2687	unsigned iPTDst = 0;
2688	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2689	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2690	{
2691	if (pRam && GCPhys >= pRam->GCPhys)
2692	{
2693	# ifndef PGM_WITH_A20
2694	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2695	# endif
2696	do
2697	{
2698	/* Make shadow PTE. */
2699	# ifdef PGM_WITH_A20
2700	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2701	# else
2702	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2703	# endif
2704	SHWPTE PteDst;
2705
2706	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2707	/* Try to make the page writable if necessary. */
2708	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2709	&& ( PGM_PAGE_IS_ZERO(pPage)
2710	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2711	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2712	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2713	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2714	# endif
2715	# ifdef VBOX_WITH_PAGE_SHARING
2716	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2717	# endif
2718	&& !PGM_PAGE_IS_BALLOONED(pPage))
2719	)
2720	)
2721	{
2722	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2723	AssertRCReturn(rc, rc);
2724	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2725	break;
2726	}
2727	# endif
2728
2729	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2730	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2731	else if (PGM_PAGE_IS_BALLOONED(pPage))
2732	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2733	else
2734	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2735
2736	/* Only map writable pages writable. */
2737	if ( SHW_PTE_IS_P_RW(PteDst)
2738	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2739	{
2740	/* Still applies to shared pages. */
2741	Assert(!PGM_PAGE_IS_ZERO(pPage));
2742	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2743	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2744	}
2745
2746	if (SHW_PTE_IS_P(PteDst))
2747	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2748
2749	/* commit it (not atomic, new table) */
2750	pPTDst->a[iPTDst] = PteDst;
2751	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2752	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2753	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2754
2755	/* advance */
2756	GCPhys += PAGE_SIZE;
2757	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
2758	# ifndef PGM_WITH_A20
2759	iHCPage++;
2760	# endif
2761	iPTDst++;
2762	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2763	&& GCPhys <= pRam->GCPhysLast);
2764
2765	/* Advance ram range list. */
2766	while (pRam && GCPhys > pRam->GCPhysLast)
2767	pRam = pRam->CTX_SUFF(pNext);
2768	}
2769	else if (pRam)
2770	{
2771	Log(("Invalid pages at %RGp\n", GCPhys));
2772	do
2773	{
2774	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2775	GCPhys += PAGE_SIZE;
2776	iPTDst++;
2777	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2778	&& GCPhys < pRam->GCPhys);
2779	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
2780	}
2781	else
2782	{
2783	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2784	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2785	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2786	}
2787	} /* while more PTEs */
2788	} /* 4KB / 4MB */
2789	}
2790	else
2791	AssertRelease(!SHW_PDE_IS_P(PdeDst));
2792
2793	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2794	if (RT_FAILURE(rc))
2795	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
2796	return rc;
2797
2798	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2799	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2800	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2801	&& PGM_SHW_TYPE != PGM_TYPE_NONE
2802	NOREF(iPDSrc); NOREF(pPDSrc);
2803
2804	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2805
2806	/*
2807	* Validate input a little bit.
2808	*/
2809	int rc = VINF_SUCCESS;
2810	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2811	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2812	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2813
2814	/* Fetch the pgm pool shadow descriptor. */
2815	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2816	Assert(pShwPde);
2817
2818	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2819	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2820	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2821	PX86PDPAE pPDDst;
2822	PSHWPDE pPdeDst;
2823
2824	/* Fetch the pgm pool shadow descriptor. */
2825	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2826	AssertRCSuccessReturn(rc, rc);
2827	Assert(pShwPde);
2828
2829	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2830	pPdeDst = &pPDDst->a[iPDDst];
2831
2832	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2833	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2834	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2835	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2836	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2837	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2838	AssertRCSuccessReturn(rc, rc);
2839	Assert(pPDDst);
2840	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2841
2842	/* Fetch the pgm pool shadow descriptor. */
2843	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2844	Assert(pShwPde);
2845
2846	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2847	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2848	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2849	PEPTPD pPDDst;
2850	PEPTPDPT pPdptDst;
2851
2852	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2853	if (rc != VINF_SUCCESS)
2854	{
2855	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2856	AssertRC(rc);
2857	return rc;
2858	}
2859	Assert(pPDDst);
2860	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2861
2862	/* Fetch the pgm pool shadow descriptor. */
2863	/** @todo r=bird: didn't pgmShwGetEPTPDPtr just do this lookup already? */
2864	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2865	Assert(pShwPde);
2866	# endif
2867	SHWPDE PdeDst = *pPdeDst;
2868
2869	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2870
2871	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2872	if ( BTH_IS_NP_ACTIVE(pVM)
2873	&& !VM_IS_NEM_ENABLED(pVM)) /** @todo NEM: Large page support. */
2874	{
2875	/* Check if we allocated a big page before for this 2 MB range. */
2876	PPGMPAGE pPage;
2877	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
2878	if (RT_SUCCESS(rc))
2879	{
2880	RTHCPHYS HCPhys = NIL_RTHCPHYS;
2881	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
2882	{
2883	if (PGM_A20_IS_ENABLED(pVCpu))
2884	{
2885	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
2886	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2887	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2888	}
2889	else
2890	{
2891	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
2892	pVM->pgm.s.cLargePagesDisabled++;
2893	}
2894	}
2895	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
2896	&& PGM_A20_IS_ENABLED(pVCpu))
2897	{
2898	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
2899	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
2900	if (RT_SUCCESS(rc))
2901	{
2902	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2903	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2904	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2905	}
2906	}
2907	else if ( PGMIsUsingLargePages(pVM)
2908	&& PGM_A20_IS_ENABLED(pVCpu))
2909	{
2910	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
2911	if (RT_SUCCESS(rc))
2912	{
2913	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2914	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2915	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2916	}
2917	else
2918	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
2919	}
2920
2921	if (HCPhys != NIL_RTHCPHYS)
2922	{
2923	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2924	PdeDst.u = HCPhys \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_LEAF \| EPT_E_IGNORE_PAT \| EPT_E_MEMTYPE_WB
2925	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo do we need this? */;
2926	# else
2927	PdeDst.u = HCPhys \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PS
2928	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo PGM_PD_FLAGS? */;
2929	# endif
2930	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2931
2932	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
2933	/* Add a reference to the first page only. */
2934	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
2935
2936	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2937	return VINF_SUCCESS;
2938	}
2939	}
2940	}
2941	# endif /* defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE */
2942
2943	/*
2944	* Allocate & map the page table.
2945	*/
2946	PSHWPT pPTDst;
2947	PPGMPOOLPAGE pShwPage;
2948	RTGCPHYS GCPhys;
2949
2950	/* Virtual address = physical address */
2951	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
2952	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
2953	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
2954	&pShwPage);
2955	if ( rc == VINF_SUCCESS
2956	\|\| rc == VINF_PGM_CACHED_PAGE)
2957	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2958	else
2959	{
2960	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2961	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2962	}
2963
2964	if (rc == VINF_SUCCESS)
2965	{
2966	/* New page table; fully set it up. */
2967	Assert(pPTDst);
2968
2969	/* Mask away the page offset. */
2970	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
2971
2972	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2973	{
2974	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2975	\| (iPTDst << PAGE_SHIFT));
2976
2977	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2978	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2979	GCPtrCurPage,
2980	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2981	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2982
2983	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2984	break;
2985	}
2986	}
2987	else
2988	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
2989
2990	/* Save the new PDE. */
2991	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2992	PdeDst.u = pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE
2993	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo do we really need this? */);
2994	# else
2995	PdeDst.u = pShwPage->Core.Key \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A
2996	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo use a PGM_PD_FLAGS define */);
2997	# endif
2998	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2999
3000	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3001	if (RT_FAILURE(rc))
3002	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3003	return rc;
3004
3005	#else
3006	NOREF(iPDSrc); NOREF(pPDSrc);
3007	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3008	return VERR_PGM_NOT_USED_IN_MODE;
3009	#endif
3010	}
3011
3012
3013
3014	/**
3015	* Prefetch a page/set of pages.
3016	*
3017	* Typically used to sync commonly used pages before entering raw mode
3018	* after a CR3 reload.
3019	*
3020	* @returns VBox status code.
3021	* @param pVCpu The cross context virtual CPU structure.
3022	* @param GCPtrPage Page to invalidate.
3023	*/
3024	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
3025	{
3026	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3027	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3028	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3029	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3030	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3031	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3032	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3033	/*
3034	* Check that all Guest levels thru the PDE are present, getting the
3035	* PD and PDE in the processes.
3036	*/
3037	int rc = VINF_SUCCESS;
3038	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3039	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3040	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
3041	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3042	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3043	unsigned iPDSrc;
3044	X86PDPE PdpeSrc;
3045	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3046	if (!pPDSrc)
3047	return VINF_SUCCESS; /* not present */
3048	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3049	unsigned iPDSrc;
3050	PX86PML4E pPml4eSrc;
3051	X86PDPE PdpeSrc;
3052	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3053	if (!pPDSrc)
3054	return VINF_SUCCESS; /* not present */
3055	# endif
3056	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3057	# else
3058	PGSTPD pPDSrc = NULL;
3059	const unsigned iPDSrc = 0;
3060	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
3061	# endif
3062
3063	if ((PdeSrc.u & (X86_PDE_P \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_A))
3064	{
3065	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3066	PGM_LOCK_VOID(pVM);
3067
3068	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3069	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3070	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3071	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3072	PX86PDPAE pPDDst;
3073	X86PDEPAE PdeDst;
3074	# if PGM_GST_TYPE != PGM_TYPE_PAE
3075	X86PDPE PdpeSrc;
3076
3077	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3078	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3079	# endif
3080	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3081	if (rc != VINF_SUCCESS)
3082	{
3083	PGM_UNLOCK(pVM);
3084	AssertRC(rc);
3085	return rc;
3086	}
3087	Assert(pPDDst);
3088	PdeDst = pPDDst->a[iPDDst];
3089
3090	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3091	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3092	PX86PDPAE pPDDst;
3093	X86PDEPAE PdeDst;
3094
3095	# if PGM_GST_TYPE == PGM_TYPE_PROT
3096	/* AMD-V nested paging */
3097	X86PML4E Pml4eSrc;
3098	X86PDPE PdpeSrc;
3099	PX86PML4E pPml4eSrc = &Pml4eSrc;
3100
3101	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3102	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3103	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3104	# endif
3105
3106	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3107	if (rc != VINF_SUCCESS)
3108	{
3109	PGM_UNLOCK(pVM);
3110	AssertRC(rc);
3111	return rc;
3112	}
3113	Assert(pPDDst);
3114	PdeDst = pPDDst->a[iPDDst];
3115	# endif
3116	if (!(PdeDst.u & X86_PDE_P))
3117	{
3118	/** @todo r=bird: This guy will set the A bit on the PDE,
3119	* probably harmless. */
3120	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3121	}
3122	else
3123	{
3124	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3125	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3126	* makes no sense to prefetch more than one page.
3127	*/
3128	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3129	if (RT_SUCCESS(rc))
3130	rc = VINF_SUCCESS;
3131	}
3132	PGM_UNLOCK(pVM);
3133	}
3134	return rc;
3135
3136	#elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
3137	NOREF(pVCpu); NOREF(GCPtrPage);
3138	return VINF_SUCCESS; /* ignore */
3139	#else
3140	AssertCompile(0);
3141	#endif
3142	}
3143
3144
3145
3146
3147	/**
3148	* Syncs a page during a PGMVerifyAccess() call.
3149	*
3150	* @returns VBox status code (informational included).
3151	* @param pVCpu The cross context virtual CPU structure.
3152	* @param GCPtrPage The address of the page to sync.
3153	* @param fPage The effective guest page flags.
3154	* @param uErr The trap error code.
3155	* @remarks This will normally never be called on invalid guest page
3156	* translation entries.
3157	*/
3158	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3159	{
3160	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3161
3162	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3163	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
3164
3165	Assert(!pVM->pgm.s.fNestedPaging);
3166	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3167	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3168	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3169	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3170	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3171	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3172	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3173
3174	/*
3175	* Get guest PD and index.
3176	*/
3177	/** @todo Performance: We've done all this a jiffy ago in the
3178	* PGMGstGetPage call. */
3179	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3180	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3181	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
3182	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3183
3184	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3185	unsigned iPDSrc = 0;
3186	X86PDPE PdpeSrc;
3187	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3188	if (RT_UNLIKELY(!pPDSrc))
3189	{
3190	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3191	return VINF_EM_RAW_GUEST_TRAP;
3192	}
3193
3194	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3195	unsigned iPDSrc = 0; /* shut up gcc */
3196	PX86PML4E pPml4eSrc = NULL; /* ditto */
3197	X86PDPE PdpeSrc;
3198	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3199	if (RT_UNLIKELY(!pPDSrc))
3200	{
3201	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3202	return VINF_EM_RAW_GUEST_TRAP;
3203	}
3204	# endif
3205
3206	# else /* !PGM_WITH_PAGING */
3207	PGSTPD pPDSrc = NULL;
3208	const unsigned iPDSrc = 0;
3209	# endif /* !PGM_WITH_PAGING */
3210	int rc = VINF_SUCCESS;
3211
3212	PGM_LOCK_VOID(pVM);
3213
3214	/*
3215	* First check if the shadow pd is present.
3216	*/
3217	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3218	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3219
3220	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3221	PX86PDEPAE pPdeDst;
3222	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3223	PX86PDPAE pPDDst;
3224	# if PGM_GST_TYPE != PGM_TYPE_PAE
3225	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3226	X86PDPE PdpeSrc;
3227	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3228	# endif
3229	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3230	if (rc != VINF_SUCCESS)
3231	{
3232	PGM_UNLOCK(pVM);
3233	AssertRC(rc);
3234	return rc;
3235	}
3236	Assert(pPDDst);
3237	pPdeDst = &pPDDst->a[iPDDst];
3238
3239	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3240	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3241	PX86PDPAE pPDDst;
3242	PX86PDEPAE pPdeDst;
3243
3244	# if PGM_GST_TYPE == PGM_TYPE_PROT
3245	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3246	X86PML4E Pml4eSrc;
3247	X86PDPE PdpeSrc;
3248	PX86PML4E pPml4eSrc = &Pml4eSrc;
3249	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3250	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3251	# endif
3252
3253	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3254	if (rc != VINF_SUCCESS)
3255	{
3256	PGM_UNLOCK(pVM);
3257	AssertRC(rc);
3258	return rc;
3259	}
3260	Assert(pPDDst);
3261	pPdeDst = &pPDDst->a[iPDDst];
3262	# endif
3263
3264	if (!(pPdeDst->u & X86_PDE_P))
3265	{
3266	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3267	if (rc != VINF_SUCCESS)
3268	{
3269	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3270	PGM_UNLOCK(pVM);
3271	AssertRC(rc);
3272	return rc;
3273	}
3274	}
3275
3276	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3277	/* Check for dirty bit fault */
3278	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3279	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3280	Log(("PGMVerifyAccess: success (dirty)\n"));
3281	else
3282	# endif
3283	{
3284	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3285	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3286	# else
3287	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
3288	# endif
3289
3290	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3291	if (uErr & X86_TRAP_PF_US)
3292	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
3293	else /* supervisor */
3294	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3295
3296	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3297	if (RT_SUCCESS(rc))
3298	{
3299	/* Page was successfully synced */
3300	Log2(("PGMVerifyAccess: success (sync)\n"));
3301	rc = VINF_SUCCESS;
3302	}
3303	else
3304	{
3305	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3306	rc = VINF_EM_RAW_GUEST_TRAP;
3307	}
3308	}
3309	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3310	PGM_UNLOCK(pVM);
3311	return rc;
3312
3313	#else /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
3314
3315	AssertLogRelMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3316	return VERR_PGM_NOT_USED_IN_MODE;
3317	#endif /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
3318	}
3319
3320
3321	/**
3322	* Syncs the paging hierarchy starting at CR3.
3323	*
3324	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
3325	* informational status codes.
3326	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
3327	* the VMM into guest context.
3328	* @param pVCpu The cross context virtual CPU structure.
3329	* @param cr0 Guest context CR0 register.
3330	* @param cr3 Guest context CR3 register. Not subjected to the A20
3331	* mask.
3332	* @param cr4 Guest context CR4 register.
3333	* @param fGlobal Including global page directories or not
3334	*/
3335	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3336	{
3337	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3338	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3339
3340	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3341
3342	#if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
3343	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3344	PGM_LOCK_VOID(pVM);
3345	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3346	if (pPool->cDirtyPages)
3347	pgmPoolResetDirtyPages(pVM);
3348	PGM_UNLOCK(pVM);
3349	# endif
3350	#endif /* !NESTED && !EPT */
3351
3352	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
3353	/*
3354	* Nested / EPT / None - No work.
3355	*/
3356	return VINF_SUCCESS;
3357
3358	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3359	/*
3360	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3361	* out the shadow parts when the guest modifies its tables.
3362	*/
3363	return VINF_SUCCESS;
3364
3365	#else /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3366
3367	return VINF_SUCCESS;
3368	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3369	}
3370
3371
3372
3373
3374	#ifdef VBOX_STRICT
3375
3376	/**
3377	* Checks that the shadow page table is in sync with the guest one.
3378	*
3379	* @returns The number of errors.
3380	* @param pVCpu The cross context virtual CPU structure.
3381	* @param cr3 Guest context CR3 register.
3382	* @param cr4 Guest context CR4 register.
3383	* @param GCPtr Where to start. Defaults to 0.
3384	* @param cb How much to check. Defaults to everything.
3385	*/
3386	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3387	{
3388	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3389	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
3390	return 0;
3391	#else
3392	unsigned cErrors = 0;
3393	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3394	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3395
3396	# if PGM_GST_TYPE == PGM_TYPE_PAE
3397	/** @todo currently broken; crashes below somewhere */
3398	AssertFailed();
3399	# endif
3400
3401	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3402	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3403	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3404
3405	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3406	PPGMCPU pPGM = &pVCpu->pgm.s;
3407	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3408	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3409	# ifndef IN_RING0
3410	RTHCPHYS HCPhys; /* general usage. */
3411	# endif
3412	int rc;
3413
3414	/*
3415	* Check that the Guest CR3 and all its mappings are correct.
3416	*/
3417	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3418	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3419	false);
3420	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3421	# if 0
3422	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3423	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3424	# else
3425	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3426	# endif
3427	AssertRCReturn(rc, 1);
3428	HCPhys = NIL_RTHCPHYS;
3429	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3430	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3431	# endif
3432	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3433	pgmGstGet32bitPDPtr(pVCpu);
3434	RTGCPHYS GCPhys;
3435	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3436	AssertRCReturn(rc, 1);
3437	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3438	# endif
3439	# endif /* !IN_RING0 */
3440
3441	/*
3442	* Get and check the Shadow CR3.
3443	*/
3444	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3445	unsigned cPDEs = X86_PG_ENTRIES;
3446	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3447	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3448	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3449	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3450	# else
3451	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3452	# endif
3453	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3454	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3455	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3456	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3457	# endif
3458	if (cb != ~(RTGCPTR)0)
3459	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3460
3461	/** @todo call the other two PGMAssert() functions. /
3462
3463	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3464	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3465
3466	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3467	{
3468	PPGMPOOLPAGE pShwPdpt = NULL;
3469	PX86PML4E pPml4eSrc;
3470	PX86PML4E pPml4eDst;
3471	RTGCPHYS GCPhysPdptSrc;
3472
3473	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3474	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3475
3476	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3477	if (!(pPml4eDst->u & X86_PML4E_P))
3478	{
3479	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3480	continue;
3481	}
3482
3483	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3484	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3485
3486	if ((pPml4eSrc->u & X86_PML4E_P) != (pPml4eDst->u & X86_PML4E_P))
3487	{
3488	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3489	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3490	cErrors++;
3491	continue;
3492	}
3493
3494	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3495	{
3496	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3497	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3498	cErrors++;
3499	continue;
3500	}
3501
3502	if ( (pPml4eDst->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX))
3503	!= (pPml4eSrc->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX)))
3504	{
3505	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3506	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3507	cErrors++;
3508	continue;
3509	}
3510	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3511	{
3512	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3513
3514	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3515	/*
3516	* Check the PDPTEs too.
3517	*/
3518	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3519
3520	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3521	{
3522	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3523	PPGMPOOLPAGE pShwPde = NULL;
3524	PX86PDPE pPdpeDst;
3525	RTGCPHYS GCPhysPdeSrc;
3526	X86PDPE PdpeSrc;
3527	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3528	# if PGM_GST_TYPE == PGM_TYPE_PAE
3529	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3530	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3531	# else
3532	PX86PML4E pPml4eSrcIgn;
3533	PX86PDPT pPdptDst;
3534	PX86PDPAE pPDDst;
3535	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3536
3537	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3538	if (rc != VINF_SUCCESS)
3539	{
3540	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3541	GCPtr += 512 * _2M;
3542	continue; /* next PDPTE */
3543	}
3544	Assert(pPDDst);
3545	# endif
3546	Assert(iPDSrc == 0);
3547
3548	pPdpeDst = &pPdptDst->a[iPdpt];
3549
3550	if (!(pPdpeDst->u & X86_PDPE_P))
3551	{
3552	GCPtr += 512 * _2M;
3553	continue; /* next PDPTE */
3554	}
3555
3556	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3557	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3558
3559	if ((pPdpeDst->u & X86_PDPE_P) != (PdpeSrc.u & X86_PDPE_P))
3560	{
3561	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3562	GCPtr += 512 * _2M;
3563	cErrors++;
3564	continue;
3565	}
3566
3567	if (GCPhysPdeSrc != pShwPde->GCPhys)
3568	{
3569	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3570	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3571	# else
3572	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3573	# endif
3574	GCPtr += 512 * _2M;
3575	cErrors++;
3576	continue;
3577	}
3578
3579	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3580	if ( (pPdpeDst->u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX))
3581	!= (PdpeSrc.u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX)))
3582	{
3583	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3584	GCPtr += 512 * _2M;
3585	cErrors++;
3586	continue;
3587	}
3588	# endif
3589
3590	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3591	{
3592	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3593	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3594	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3595	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3596	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3597	# endif
3598	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3599	/*
3600	* Iterate the shadow page directory.
3601	*/
3602	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3603	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3604
3605	for (;
3606	iPDDst < cPDEs;
3607	iPDDst++, GCPtr += cIncrement)
3608	{
3609	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3610	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3611	# else
3612	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3613	# endif
3614	if ( (PdeDst.u & X86_PDE_P)
3615	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) )
3616	{
3617	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3618	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3619	if (!pPoolPage)
3620	{
3621	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3622	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3623	cErrors++;
3624	continue;
3625	}
3626	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3627
3628	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3629	{
3630	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3631	GCPtr, (uint64_t)PdeDst.u));
3632	cErrors++;
3633	}
3634
3635	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3636	{
3637	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3638	GCPtr, (uint64_t)PdeDst.u));
3639	cErrors++;
3640	}
3641
3642	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3643	if (!(PdeSrc.u & X86_PDE_P))
3644	{
3645	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3646	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3647	cErrors++;
3648	continue;
3649	}
3650
3651	if ( !(PdeSrc.u & X86_PDE_PS)
3652	\|\| !fBigPagesSupported)
3653	{
3654	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3655	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3656	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
3657	# endif
3658	}
3659	else
3660	{
3661	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3662	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3663	{
3664	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3665	GCPtr, (uint64_t)PdeSrc.u));
3666	cErrors++;
3667	continue;
3668	}
3669	# endif
3670	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3671	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3672	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
3673	# endif
3674	}
3675
3676	if ( pPoolPage->enmKind
3677	!= (!(PdeSrc.u & X86_PDE_PS) \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3678	{
3679	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3680	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3681	cErrors++;
3682	}
3683
3684	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
3685	if (!pPhysPage)
3686	{
3687	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3688	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3689	cErrors++;
3690	continue;
3691	}
3692
3693	if (GCPhysGst != pPoolPage->GCPhys)
3694	{
3695	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3696	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3697	cErrors++;
3698	continue;
3699	}
3700
3701	if ( !(PdeSrc.u & X86_PDE_PS)
3702	\|\| !fBigPagesSupported)
3703	{
3704	/*
3705	* Page Table.
3706	*/
3707	const GSTPT *pPTSrc;
3708	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
3709	&pPTSrc);
3710	if (RT_FAILURE(rc))
3711	{
3712	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3713	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3714	cErrors++;
3715	continue;
3716	}
3717	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3718	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3719	{
3720	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3721	// (This problem will go away when/if we shadow multiple CR3s.)
3722	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3723	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3724	cErrors++;
3725	continue;
3726	}
3727	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3728	{
3729	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3730	GCPtr, (uint64_t)PdeDst.u));
3731	cErrors++;
3732	continue;
3733	}
3734
3735	/* iterate the page table. */
3736	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3737	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3738	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3739	# else
3740	const unsigned offPTSrc = 0;
3741	# endif
3742	for (unsigned iPT = 0, off = 0;
3743	iPT < RT_ELEMENTS(pPTDst->a);
3744	iPT++, off += PAGE_SIZE)
3745	{
3746	const SHWPTE PteDst = pPTDst->a[iPT];
3747
3748	/* skip not-present and dirty tracked entries. */
3749	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3750	continue;
3751	Assert(SHW_PTE_IS_P(PteDst));
3752
3753	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3754	if (!(PteSrc.u & X86_PTE_P))
3755	{
3756	# ifdef IN_RING3
3757	PGMAssertHandlerAndFlagsInSync(pVM);
3758	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
3759	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
3760	0, 0, UINT64_MAX, 99, NULL);
3761	# endif
3762	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3763	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3764	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
3765	cErrors++;
3766	continue;
3767	}
3768
3769	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3770	# if 1 /** @todo sync accessed bit properly... */
3771	fIgnoreFlags \|= X86_PTE_A;
3772	# endif
3773
3774	/* match the physical addresses */
3775	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
3776	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
3777
3778	# ifdef IN_RING3
3779	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3780	if (RT_FAILURE(rc))
3781	{
3782	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3783	{
3784	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3785	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3786	cErrors++;
3787	continue;
3788	}
3789	}
3790	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3791	{
3792	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3793	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3794	cErrors++;
3795	continue;
3796	}
3797	# endif
3798
3799	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
3800	if (!pPhysPage)
3801	{
3802	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3803	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3804	{
3805	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3806	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3807	cErrors++;
3808	continue;
3809	}
3810	# endif
3811	if (SHW_PTE_IS_RW(PteDst))
3812	{
3813	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3814	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3815	cErrors++;
3816	}
3817	fIgnoreFlags \|= X86_PTE_RW;
3818	}
3819	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3820	{
3821	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3822	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3823	cErrors++;
3824	continue;
3825	}
3826
3827	/* flags */
3828	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3829	{
3830	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3831	{
3832	if (SHW_PTE_IS_RW(PteDst))
3833	{
3834	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3835	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3836	cErrors++;
3837	continue;
3838	}
3839	fIgnoreFlags \|= X86_PTE_RW;
3840	}
3841	else
3842	{
3843	if ( SHW_PTE_IS_P(PteDst)
3844	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3845	&& !PGM_PAGE_IS_MMIO(pPhysPage)
3846	# endif
3847	)
3848	{
3849	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3850	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3851	cErrors++;
3852	continue;
3853	}
3854	fIgnoreFlags \|= X86_PTE_P;
3855	}
3856	}
3857	else
3858	{
3859	if ((PteSrc.u & (X86_PTE_RW \| X86_PTE_D)) == X86_PTE_RW)
3860	{
3861	if (SHW_PTE_IS_RW(PteDst))
3862	{
3863	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3864	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3865	cErrors++;
3866	continue;
3867	}
3868	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
3869	{
3870	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3871	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3872	cErrors++;
3873	continue;
3874	}
3875	if (SHW_PTE_IS_D(PteDst))
3876	{
3877	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3878	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3879	cErrors++;
3880	}
3881	# if 0 /** @todo sync access bit properly... */
3882	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3883	{
3884	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3885	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3886	cErrors++;
3887	}
3888	fIgnoreFlags \|= X86_PTE_RW;
3889	# else
3890	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3891	# endif
3892	}
3893	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
3894	{
3895	/* access bit emulation (not implemented). */
3896	if ((PteSrc.u & X86_PTE_A) \|\| SHW_PTE_IS_P(PteDst))
3897	{
3898	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3899	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3900	cErrors++;
3901	continue;
3902	}
3903	if (!SHW_PTE_IS_A(PteDst))
3904	{
3905	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3906	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3907	cErrors++;
3908	}
3909	fIgnoreFlags \|= X86_PTE_P;
3910	}
3911	# ifdef DEBUG_sandervl
3912	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3913	# endif
3914	}
3915
3916	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
3917	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
3918	)
3919	{
3920	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3921	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
3922	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3923	cErrors++;
3924	continue;
3925	}
3926	} /* foreach PTE */
3927	}
3928	else
3929	{
3930	/*
3931	* Big Page.
3932	*/
3933	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3934	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3935	{
3936	if (PdeDst.u & X86_PDE_RW)
3937	{
3938	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3939	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3940	cErrors++;
3941	continue;
3942	}
3943	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3944	{
3945	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3946	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3947	cErrors++;
3948	continue;
3949	}
3950	# if 0 /** @todo sync access bit properly... */
3951	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3952	{
3953	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3954	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3955	cErrors++;
3956	}
3957	fIgnoreFlags \|= X86_PTE_RW;
3958	# else
3959	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3960	# endif
3961	}
3962	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3963	{
3964	/* access bit emulation (not implemented). */
3965	if ((PdeSrc.u & X86_PDE_A) \|\| SHW_PDE_IS_P(PdeDst))
3966	{
3967	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3968	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3969	cErrors++;
3970	continue;
3971	}
3972	if (!SHW_PDE_IS_A(PdeDst))
3973	{
3974	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3975	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3976	cErrors++;
3977	}
3978	fIgnoreFlags \|= X86_PTE_P;
3979	}
3980
3981	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3982	{
3983	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3984	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3985	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3986	cErrors++;
3987	}
3988
3989	/* iterate the page table. */
3990	for (unsigned iPT = 0, off = 0;
3991	iPT < RT_ELEMENTS(pPTDst->a);
3992	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
3993	{
3994	const SHWPTE PteDst = pPTDst->a[iPT];
3995
3996	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
3997	{
3998	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3999	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4000	cErrors++;
4001	}
4002
4003	/* skip not-present entries. */
4004	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4005	continue;
4006
4007	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4008
4009	/* match the physical addresses */
4010	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4011
4012	# ifdef IN_RING3
4013	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4014	if (RT_FAILURE(rc))
4015	{
4016	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4017	{
4018	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4019	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4020	cErrors++;
4021	}
4022	}
4023	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4024	{
4025	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4026	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4027	cErrors++;
4028	continue;
4029	}
4030	# endif
4031	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4032	if (!pPhysPage)
4033	{
4034	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4035	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4036	{
4037	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4038	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4039	cErrors++;
4040	continue;
4041	}
4042	# endif
4043	if (SHW_PTE_IS_RW(PteDst))
4044	{
4045	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4046	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4047	cErrors++;
4048	}
4049	fIgnoreFlags \|= X86_PTE_RW;
4050	}
4051	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4052	{
4053	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4054	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4055	cErrors++;
4056	continue;
4057	}
4058
4059	/* flags */
4060	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4061	{
4062	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4063	{
4064	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4065	{
4066	if (SHW_PTE_IS_RW(PteDst))
4067	{
4068	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4069	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4070	cErrors++;
4071	continue;
4072	}
4073	fIgnoreFlags \|= X86_PTE_RW;
4074	}
4075	}
4076	else
4077	{
4078	if ( SHW_PTE_IS_P(PteDst)
4079	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4080	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4081	# endif
4082	)
4083	{
4084	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4085	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4086	cErrors++;
4087	continue;
4088	}
4089	fIgnoreFlags \|= X86_PTE_P;
4090	}
4091	}
4092
4093	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4094	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4095	)
4096	{
4097	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4098	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4099	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4100	cErrors++;
4101	continue;
4102	}
4103	} /* for each PTE */
4104	}
4105	}
4106	/* not present */
4107
4108	} /* for each PDE */
4109
4110	} /* for each PDPTE */
4111
4112	} /* for each PML4E */
4113
4114	# ifdef DEBUG
4115	if (cErrors)
4116	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4117	# endif
4118	# endif /* GST is in {32BIT, PAE, AMD64} */
4119	return cErrors;
4120	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
4121	}
4122	#endif /* VBOX_STRICT */
4123
4124
4125	/**
4126	* Sets up the CR3 for shadow paging
4127	*
4128	* @returns Strict VBox status code.
4129	* @retval VINF_SUCCESS.
4130	*
4131	* @param pVCpu The cross context virtual CPU structure.
4132	* @param GCPhysCR3 The physical address in the CR3 register. (A20 mask
4133	* already applied.)
4134	*/
4135	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
4136	{
4137	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4138	int rc = VINF_SUCCESS;
4139
4140	/* Update guest paging info. */
4141	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4142	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4143	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4144
4145	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4146	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4147
4148	# if PGM_GST_TYPE == PGM_TYPE_PAE
4149	if (!pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped))
4150	# endif
4151	{
4152	/*
4153	* Map the page CR3 points at.
4154	*/
4155	RTHCPTR HCPtrGuestCR3;
4156	rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCR3);
4157	if (RT_SUCCESS(rc))
4158	{
4159	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4160	# ifdef IN_RING3
4161	pVCpu->pgm.s.pGst32BitPdR3 = (PX86PD)HCPtrGuestCR3;
4162	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
4163	# else
4164	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR3PTR;
4165	pVCpu->pgm.s.pGst32BitPdR0 = (PX86PD)HCPtrGuestCR3;
4166	# endif
4167
4168	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4169	# ifdef IN_RING3
4170	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCR3;
4171	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
4172	# else
4173	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
4174	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCR3;
4175	# endif
4176
4177	/*
4178	* Update CPUM and map the 4 PDs too.
4179	*/
4180	X86PDPE aGstPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
4181	memcpy(&aGstPaePdpes, HCPtrGuestCR3, sizeof(aGstPaePdpes));
4182	CPUMSetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
4183	PGMGstMapPaePdpes(pVCpu, &aGstPaePdpes[0]);
4184
4185	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4186	# ifdef IN_RING3
4187	pVCpu->pgm.s.pGstAmd64Pml4R3 = (PX86PML4)HCPtrGuestCR3;
4188	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
4189	# else
4190	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
4191	pVCpu->pgm.s.pGstAmd64Pml4R0 = (PX86PML4)HCPtrGuestCR3;
4192	# endif
4193	# endif
4194	}
4195	else
4196	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4197	}
4198
4199	/*
4200	* Reset fPaePdpesAndCr3Mapped for all modes as there's no guarantee that
4201	* we were called in the correct sequence of PAE followed by other modes
4202	* without CR3 changing in between.
4203	*/
4204	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
4205	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
4206	#endif
4207
4208	/*
4209	* Update shadow paging info for guest modes with paging (32-bit, PAE, AMD64).
4210	*/
4211	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4212	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4213	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4214	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4215	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4216
4217	Assert(!pVM->pgm.s.fNestedPaging);
4218	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4219
4220	/*
4221	* Update the shadow root page as well since that's not fixed.
4222	*/
4223	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4224	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4225	PPGMPOOLPAGE pNewShwPageCR3;
4226
4227	PGM_LOCK_VOID(pVM);
4228
4229	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4230	if (pPool->cDirtyPages)
4231	pgmPoolResetDirtyPages(pVM);
4232	# endif
4233
4234	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4235	int const rc2 = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE,
4236	PGM_A20_IS_ENABLED(pVCpu), NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/, &pNewShwPageCR3);
4237	AssertFatalRC(rc2);
4238
4239	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4240	# ifdef IN_RING0
4241	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4242	# else
4243	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4244	# endif
4245
4246	/* Set the current hypervisor CR3. */
4247	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4248
4249	/* Clean up the old CR3 root. */
4250	if ( pOldShwPageCR3
4251	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4252	{
4253	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4254
4255	/* Mark the page as unlocked; allow flushing again. */
4256	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4257
4258	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4259	}
4260	PGM_UNLOCK(pVM);
4261	# else
4262	NOREF(GCPhysCR3);
4263	# endif
4264
4265	return rc;
4266	}
4267
4268	/**
4269	* Unmaps the shadow CR3.
4270	*
4271	* @returns VBox status, no specials.
4272	* @param pVCpu The cross context virtual CPU structure.
4273	*/
4274	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu)
4275	{
4276	LogFlow(("UnmapCR3\n"));
4277
4278	int rc = VINF_SUCCESS;
4279	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4280
4281	/*
4282	* Update guest paging info.
4283	*/
4284	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4285	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4286	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4287
4288	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4289	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4290	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4291	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4292	{
4293	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4294	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4295	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4296	}
4297
4298	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4299	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4300	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4301
4302	#else /* prot/real mode stub */
4303	/* nothing to do */
4304	#endif
4305
4306	/*
4307	* Update second-level address translation info.
4308	*/
4309	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
4310	pVCpu->pgm.s.pGstEptPml4R3 = 0;
4311	pVCpu->pgm.s.pGstEptPml4R0 = 0;
4312	#endif
4313
4314	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
4315	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
4316
4317	/*
4318	* Update shadow paging info.
4319	*/
4320	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4321	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4322	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4323	# if PGM_GST_TYPE != PGM_TYPE_REAL
4324	Assert(!pVM->pgm.s.fNestedPaging);
4325	# endif
4326	PGM_LOCK_VOID(pVM);
4327
4328	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4329	{
4330	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4331
4332	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4333	if (pPool->cDirtyPages)
4334	pgmPoolResetDirtyPages(pVM);
4335	# endif
4336
4337	/* Mark the page as unlocked; allow flushing again. */
4338	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4339
4340	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4341	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4342	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4343	}
4344
4345	PGM_UNLOCK(pVM);
4346	#endif
4347
4348	return rc;
4349	}
4350

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 93305

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