PGMAllBth.h@ 9966

Last change on this file since 9966 was 9966, checked in by vboxsync, 16 years ago
AssertCR3: ignore X86_PTE_PAE_NX as well in big pages (PDE bit is sufficient to override all pte entries)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 186.3 KB

Line
1	/* $Id: PGMAllBth.h 9966 2008-06-26 15:50:58Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69	/**
70	* #PF Handler for raw-mode guest execution.
71	*
72	* @returns VBox status code (appropriate for trap handling and GC return).
73	* @param pVM VM Handle.
74	* @param uErr The trap error code.
75	* @param pRegFrame Trap register frame.
76	* @param pvFault The fault address.
77	*/
78	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
79	{
80	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
81	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
82
83	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
84	/*
85	* Hide the instruction fetch trap indicator for now.
86	*/
87	/** @todo NXE will change this and we must fix NXE in the switcher too! */
88	if (uErr & X86_TRAP_PF_ID)
89	{
90	uErr &= ~X86_TRAP_PF_ID;
91	TRPMSetErrorCode(pVM, uErr);
92	}
93	# endif
94
95	/*
96	* Get PDs.
97	*/
98	int rc;
99	# if PGM_WITH_PAGING(PGM_GST_TYPE)
100	# if PGM_GST_TYPE == PGM_TYPE_32BIT
101	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
102	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
103
104	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
105
106	# if PGM_GST_TYPE == PGM_TYPE_PAE
107	unsigned iPDSrc;
108	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
109
110	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
111	unsigned iPDSrc;
112	PX86PML4E pPml4eSrc;
113	X86PDPE PdpeSrc;
114	PGSTPD pPDSrc;
115
116	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
117	Assert(pPml4eSrc);
118	# endif
119	/* Quick check for a valid guest trap. */
120	if (!pPDSrc)
121	{
122	LogFlow(("Trap0eHandler: guest PDPTR not present CR3=%VGp\n", (CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK)));
123	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eGuestTrap; });
124	TRPMSetErrorCode(pVM, uErr);
125	return VINF_EM_RAW_GUEST_TRAP;
126	}
127	# endif
128	# else
129	PGSTPD pPDSrc = NULL;
130	const unsigned iPDSrc = 0;
131	# endif
132
133	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
134	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
135	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
136	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
137	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
138	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
139
140	# if PGM_GST_TYPE == PGM_TYPE_PAE
141	/* Did we mark the PDPT as not present in SyncCR3? */
142	unsigned iPdpte = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
143	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
144	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 1;
145
146	# endif
147
148	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
149	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
150	PX86PDPAE pPDDst;
151	# if PGM_GST_TYPE == PGM_TYPE_PROT
152	/* AMD-V nested paging */
153	X86PML4E Pml4eSrc;
154	X86PDPE PdpeSrc;
155	PX86PML4E pPml4eSrc = &Pml4eSrc;
156
157	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
158	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
159	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
160	# endif
161
162	rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
163	if (rc != VINF_SUCCESS)
164	{
165	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
166	return rc;
167	}
168	Assert(pPDDst);
169	# endif
170
171	# if PGM_WITH_PAGING(PGM_GST_TYPE)
172	/*
173	* If we successfully correct the write protection fault due to dirty bit
174	* tracking, or this page fault is a genuine one, then return immediately.
175	*/
176	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
177	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
178	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
179	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
180	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
181	{
182	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
183	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
184	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
185	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
186	}
187
188	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
189	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
190
191	/*
192	* A common case is the not-present error caused by lazy page table syncing.
193	*
194	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
195	* so we can safely assume that the shadow PT is present when calling SyncPage later.
196	*
197	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
198	* of mapping conflict and defer to SyncCR3 in R3.
199	* (Again, we do NOT support access handlers for non-present guest pages.)
200	*
201	*/
202	# if PGM_WITH_PAGING(PGM_GST_TYPE)
203	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
204	# else
205	GSTPDE PdeSrc;
206	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
207	PdeSrc.n.u1Present = 1;
208	PdeSrc.n.u1Write = 1;
209	PdeSrc.n.u1Accessed = 1;
210	PdeSrc.n.u1User = 1;
211	# endif
212	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
213	&& !pPDDst->a[iPDDst].n.u1Present
214	&& PdeSrc.n.u1Present
215	)
216
217	{
218	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
219	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
220	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
221	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
222	if (VBOX_SUCCESS(rc))
223	{
224	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
225	return rc;
226	}
227	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
228	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
229	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
230	return VINF_PGM_SYNC_CR3;
231	}
232
233	# if PGM_WITH_PAGING(PGM_GST_TYPE)
234	/*
235	* Check if this address is within any of our mappings.
236	*
237	* This is very fast and it's gonna save us a bit of effort below and prevent
238	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
239	* (BTW, it's impossible to have physical access handlers in a mapping.)
240	*/
241	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
242	{
243	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
244	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
245	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
246	{
247	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
248	break;
249	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
250	{
251	/*
252	* The first thing we check is if we've got an undetected conflict.
253	*/
254	if (!pVM->pgm.s.fMappingsFixed)
255	{
256	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
257	while (iPT-- > 0)
258	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
259	{
260	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
261	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
262	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
263	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
264	return VINF_PGM_SYNC_CR3;
265	}
266	}
267
268	/*
269	* Check if the fault address is in a virtual page access handler range.
270	*/
271	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
272	if ( pCur
273	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
274	&& uErr & X86_TRAP_PF_RW)
275	{
276	# ifdef IN_GC
277	STAM_PROFILE_START(&pCur->Stat, h);
278	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
279	STAM_PROFILE_STOP(&pCur->Stat, h);
280	# else
281	AssertFailed();
282	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
283	# endif
284	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
285	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
286	return rc;
287	}
288
289	/*
290	* Pretend we're not here and let the guest handle the trap.
291	*/
292	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
293	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
294	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
295	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
296	return VINF_EM_RAW_GUEST_TRAP;
297	}
298	}
299	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
300	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
301	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
302
303	/*
304	* Check if this fault address is flagged for special treatment,
305	* which means we'll have to figure out the physical address and
306	* check flags associated with it.
307	*
308	* ASSUME that we can limit any special access handling to pages
309	* in page tables which the guest believes to be present.
310	*/
311	if (PdeSrc.n.u1Present)
312	{
313	RTGCPHYS GCPhys = NIL_RTGCPHYS;
314
315	# if PGM_WITH_PAGING(PGM_GST_TYPE)
316	# if PGM_GST_TYPE == PGM_TYPE_AMD64
317	bool fBigPagesSupported = true;
318	# else
319	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
320	# endif
321	if ( PdeSrc.b.u1Size
322	&& fBigPagesSupported)
323	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
324	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
325	else
326	{
327	PGSTPT pPTSrc;
328	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
329	if (VBOX_SUCCESS(rc))
330	{
331	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
332	if (pPTSrc->a[iPTESrc].n.u1Present)
333	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
334	}
335	}
336	# else
337	/* No paging so the fault address is the physical address */
338	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
339	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
340
341	/*
342	* If we have a GC address we'll check if it has any flags set.
343	*/
344	if (GCPhys != NIL_RTGCPHYS)
345	{
346	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
347
348	PPGMPAGE pPage;
349	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
350	if (VBOX_SUCCESS(rc))
351	{
352	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
353	{
354	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
355	{
356	/*
357	* Physical page access handler.
358	*/
359	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
360	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
361	if (pCur)
362	{
363	# ifdef PGM_SYNC_N_PAGES
364	/*
365	* If the region is write protected and we got a page not present fault, then sync
366	* the pages. If the fault was caused by a read, then restart the instruction.
367	* In case of write access continue to the GC write handler.
368	*
369	* ASSUMES that there is only one handler per page or that they have similar write properties.
370	*/
371	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
372	&& !(uErr & X86_TRAP_PF_P))
373	{
374	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
375	if ( VBOX_FAILURE(rc)
376	\|\| !(uErr & X86_TRAP_PF_RW)
377	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
378	{
379	AssertRC(rc);
380	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
381	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
382	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
383	return rc;
384	}
385	}
386	# endif
387
388	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
389	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
390	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
391
392	#if defined(IN_GC) \|\| defined(IN_RING0)
393	if (CTXALLSUFF(pCur->pfnHandler))
394	{
395	STAM_PROFILE_START(&pCur->Stat, h);
396	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
397	STAM_PROFILE_STOP(&pCur->Stat, h);
398	}
399	else
400	#endif
401	rc = VINF_EM_RAW_EMULATE_INSTR;
402	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
403	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
404	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
405	return rc;
406	}
407	}
408	# if PGM_WITH_PAGING(PGM_GST_TYPE)
409	else
410	{
411	# ifdef PGM_SYNC_N_PAGES
412	/*
413	* If the region is write protected and we got a page not present fault, then sync
414	* the pages. If the fault was caused by a read, then restart the instruction.
415	* In case of write access continue to the GC write handler.
416	*/
417	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
418	&& !(uErr & X86_TRAP_PF_P))
419	{
420	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
421	if ( VBOX_FAILURE(rc)
422	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
423	\|\| !(uErr & X86_TRAP_PF_RW))
424	{
425	AssertRC(rc);
426	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
427	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
428	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
429	return rc;
430	}
431	}
432	# endif
433	/*
434	* Ok, it's an virtual page access handler.
435	*
436	* Since it's faster to search by address, we'll do that first
437	* and then retry by GCPhys if that fails.
438	*/
439	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
440	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
441	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
442	*/
443	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
444	if (pCur)
445	{
446	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
447	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
448	\|\| !(uErr & X86_TRAP_PF_P)
449	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
450	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
451
452	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
453	&& ( uErr & X86_TRAP_PF_RW
454	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
455	{
456	# ifdef IN_GC
457	STAM_PROFILE_START(&pCur->Stat, h);
458	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
459	STAM_PROFILE_STOP(&pCur->Stat, h);
460	# else
461	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
462	# endif
463	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
464	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
465	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
466	return rc;
467	}
468	/* Unhandled part of a monitored page */
469	}
470	else
471	{
472	/* Check by physical address. */
473	PPGMVIRTHANDLER pCur;
474	unsigned iPage;
475	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
476	&pCur, &iPage);
477	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
478	if ( pCur
479	&& ( uErr & X86_TRAP_PF_RW
480	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
481	{
482	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
483	# ifdef IN_GC
484	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
485	Assert(off < pCur->cb);
486	STAM_PROFILE_START(&pCur->Stat, h);
487	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
488	STAM_PROFILE_STOP(&pCur->Stat, h);
489	# else
490	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
491	# endif
492	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
493	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
494	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
495	return rc;
496	}
497	}
498	}
499	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
500
501	/*
502	* There is a handled area of the page, but this fault doesn't belong to it.
503	* We must emulate the instruction.
504	*
505	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
506	* we first check if this was a page-not-present fault for a page with only
507	* write access handlers. Restart the instruction if it wasn't a write access.
508	*/
509	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
510
511	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
512	&& !(uErr & X86_TRAP_PF_P))
513	{
514	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
515	if ( VBOX_FAILURE(rc)
516	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
517	\|\| !(uErr & X86_TRAP_PF_RW))
518	{
519	AssertRC(rc);
520	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
521	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
522	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
523	return rc;
524	}
525	}
526
527	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
528	* It's writing to an unhandled part of the LDT page several million times.
529	*/
530	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
531	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
532	rc, pPage->HCPhys,
533	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
534	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
535	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
536	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
537	return rc;
538	} /* if any kind of handler */
539
540	# if PGM_WITH_PAGING(PGM_GST_TYPE)
541	if (uErr & X86_TRAP_PF_P)
542	{
543	/*
544	* The page isn't marked, but it might still be monitored by a virtual page access handler.
545	* (ASSUMES no temporary disabling of virtual handlers.)
546	*/
547	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
548	* we should correct both the shadow page table and physical memory flags, and not only check for
549	* accesses within the handler region but for access to pages with virtual handlers. */
550	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
551	if (pCur)
552	{
553	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
554	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
555	\|\| !(uErr & X86_TRAP_PF_P)
556	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
557	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
558
559	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
560	&& ( uErr & X86_TRAP_PF_RW
561	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
562	{
563	# ifdef IN_GC
564	STAM_PROFILE_START(&pCur->Stat, h);
565	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
566	STAM_PROFILE_STOP(&pCur->Stat, h);
567	# else
568	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
569	# endif
570	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
571	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
572	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
573	return rc;
574	}
575	}
576	}
577	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
578	}
579	else
580	{
581	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
582	* back to the recompiler to emulate the instruction.
583	*/
584	LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
585	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersInvalid);
586	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
587	return VINF_EM_RAW_EMULATE_INSTR;
588	}
589
590	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
591
592	# ifdef PGM_OUT_OF_SYNC_IN_GC
593	/*
594	* We are here only if page is present in Guest page tables and trap is not handled
595	* by our handlers.
596	* Check it for page out-of-sync situation.
597	*/
598	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
599
600	if (!(uErr & X86_TRAP_PF_P))
601	{
602	/*
603	* Page is not present in our page tables.
604	* Try to sync it!
605	* BTW, fPageShw is invalid in this branch!
606	*/
607	if (uErr & X86_TRAP_PF_US)
608	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
609	else /* supervisor */
610	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
611
612	# if defined(LOG_ENABLED) && !defined(IN_RING0)
613	RTGCPHYS GCPhys;
614	uint64_t fPageGst;
615	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
616	Log(("Page out of sync: %VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
617	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
618	# endif /* LOG_ENABLED */
619
620	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
621	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
622	{
623	uint64_t fPageGst;
624	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
625	if ( VBOX_SUCCESS(rc)
626	&& !(fPageGst & X86_PTE_US))
627	{
628	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
629	if ( pvFault == (RTGCPTR)pRegFrame->eip
630	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
631	# ifdef CSAM_DETECT_NEW_CODE_PAGES
632	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
633	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
634	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
635	)
636	{
637	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
638	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
639	if (rc != VINF_SUCCESS)
640	{
641	/*
642	* CSAM needs to perform a job in ring 3.
643	*
644	* Sync the page before going to the host context; otherwise we'll end up in a loop if
645	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
646	*/
647	LogFlow(("CSAM ring 3 job\n"));
648	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
649	AssertRC(rc2);
650
651	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
652	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
653	return rc;
654	}
655	}
656	# ifdef CSAM_DETECT_NEW_CODE_PAGES
657	else
658	if ( uErr == X86_TRAP_PF_RW
659	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
660	&& pRegFrame->ecx < 0x10000
661	)
662	{
663	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
664	* to detect loading of new code pages.
665	*/
666
667	/*
668	* Decode the instruction.
669	*/
670	RTGCPTR PC;
671	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
672	if (rc == VINF_SUCCESS)
673	{
674	DISCPUSTATE Cpu;
675	uint32_t cbOp;
676	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
677
678	/* For now we'll restrict this to rep movsw/d instructions */
679	if ( rc == VINF_SUCCESS
680	&& Cpu.pCurInstr->opcode == OP_MOVSWD
681	&& (Cpu.prefix & PREFIX_REP))
682	{
683	CSAMMarkPossibleCodePage(pVM, pvFault);
684	}
685	}
686	}
687	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
688
689	/*
690	* Mark this page as safe.
691	*/
692	/** @todo not correct for pages that contain both code and data!! */
693	Log2(("CSAMMarkPage %VGv; scanned=%d\n", pvFault, true));
694	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
695	}
696	}
697	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
698	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
699	if (VBOX_SUCCESS(rc))
700	{
701	/* The page was successfully synced, return to the guest. */
702	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
703	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
704	return VINF_SUCCESS;
705	}
706	}
707	else
708	{
709	/*
710	* A side effect of not flushing global PDEs are out of sync pages due
711	* to physical monitored regions, that are no longer valid.
712	* Assume for now it only applies to the read/write flag
713	*/
714	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
715	{
716	if (uErr & X86_TRAP_PF_US)
717	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
718	else /* supervisor */
719	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
720
721
722	/*
723	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
724	*/
725	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
726	if (VBOX_SUCCESS(rc))
727	{
728	/*
729	* Page was successfully synced, return to guest.
730	*/
731	# ifdef VBOX_STRICT
732	RTGCPHYS GCPhys;
733	uint64_t fPageGst;
734	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
735	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
736	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
737
738	uint64_t fPageShw;
739	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
740	AssertMsg(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Vrc fPageShw=%VX64\n", rc, fPageShw));
741	# endif /* VBOX_STRICT */
742	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
743	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
744	return VINF_SUCCESS;
745	}
746
747	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
748	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
749	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
750	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
751	{
752	uint64_t fPageGst;
753	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
754	if ( VBOX_SUCCESS(rc)
755	&& !(fPageGst & X86_PTE_RW))
756	{
757	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
758	if (VBOX_SUCCESS(rc))
759	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
760	else
761	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
762	return rc;
763	}
764	else
765	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
766	}
767
768	}
769
770	# if PGM_WITH_PAGING(PGM_GST_TYPE)
771	# ifdef VBOX_STRICT
772	/*
773	* Check for VMM page flags vs. Guest page flags consistency.
774	* Currently only for debug purposes.
775	*/
776	if (VBOX_SUCCESS(rc))
777	{
778	/* Get guest page flags. */
779	uint64_t fPageGst;
780	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
781	if (VBOX_SUCCESS(rc))
782	{
783	uint64_t fPageShw;
784	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
785
786	/*
787	* Compare page flags.
788	* Note: we have AVL, A, D bits desynched.
789	*/
790	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
791	("Page flags mismatch! pvFault=%VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
792	}
793	else
794	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
795	}
796	else
797	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
798	# endif /* VBOX_STRICT */
799	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
800	}
801	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
802	# endif /* PGM_OUT_OF_SYNC_IN_GC */
803	}
804	else
805	{
806	/*
807	* Page not present in Guest OS or invalid page table address.
808	* This is potential virtual page access handler food.
809	*
810	* For the present we'll say that our access handlers don't
811	* work for this case - we've already discarded the page table
812	* not present case which is identical to this.
813	*
814	* When we perchance find we need this, we will probably have AVL
815	* trees (offset based) to operate on and we can measure their speed
816	* agains mapping a page table and probably rearrange this handling
817	* a bit. (Like, searching virtual ranges before checking the
818	* physical address.)
819	*/
820	}
821	}
822
823
824	# if PGM_WITH_PAGING(PGM_GST_TYPE)
825	/*
826	* Conclusion, this is a guest trap.
827	*/
828	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
829	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
830	return VINF_EM_RAW_GUEST_TRAP;
831	# else
832	/* present, but not a monitored page; perhaps the guest is probing physical memory */
833	return VINF_EM_RAW_EMULATE_INSTR;
834	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
835
836
837	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
838
839	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
840	return VERR_INTERNAL_ERROR;
841	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
842	}
843
844
845	/**
846	* Emulation of the invlpg instruction.
847	*
848	*
849	* @returns VBox status code.
850	*
851	* @param pVM VM handle.
852	* @param GCPtrPage Page to invalidate.
853	*
854	* @remark ASSUMES that the guest is updating before invalidating. This order
855	* isn't required by the CPU, so this is speculative and could cause
856	* trouble.
857	*
858	* @todo Flush page or page directory only if necessary!
859	* @todo Add a #define for simply invalidating the page.
860	*/
861	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
862	{
863	#if PGM_WITH_PAGING(PGM_GST_TYPE) \
864	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
865	int rc;
866
867	LogFlow(("InvalidatePage %VGv\n", GCPtrPage));
868	/*
869	* Get the shadow PD entry and skip out if this PD isn't present.
870	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
871	*/
872	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
873	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
874	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
875	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
876	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
877	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT);
878	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
879	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
880	# else /* AMD64 */
881	/* PML4 */
882	AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
883
884	const unsigned iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
885	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
886	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
887	PX86PDPAE pPDDst;
888	PX86PDPT pPdptDst;
889	PX86PML4E pPml4eDst = &pVM->pgm.s.pHCPaePML4->a[iPml4e];
890	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
891	if (rc != VINF_SUCCESS)
892	{
893	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
894	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
895	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
896	PGM_INVL_GUEST_TLBS();
897	return VINF_SUCCESS;
898	}
899	Assert(pPDDst);
900
901	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
902	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpte];
903
904	if (!pPdpeDst->n.u1Present)
905	{
906	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
907	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
908	PGM_INVL_GUEST_TLBS();
909	return VINF_SUCCESS;
910	}
911
912	# endif
913
914	const SHWPDE PdeDst = *pPdeDst;
915	if (!PdeDst.n.u1Present)
916	{
917	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
918	return VINF_SUCCESS;
919	}
920
921	/*
922	* Get the guest PD entry and calc big page.
923	*/
924	# if PGM_GST_TYPE == PGM_TYPE_32BIT
925	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
926	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
927	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
928	# else
929	unsigned iPDSrc;
930	# if PGM_GST_TYPE == PGM_TYPE_PAE
931	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
932	# else /* AMD64 */
933	PX86PML4E pPml4eSrc;
934	X86PDPE PdpeSrc;
935	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
936	# endif
937	GSTPDE PdeSrc;
938
939	if (pPDSrc)
940	PdeSrc = pPDSrc->a[iPDSrc];
941	else
942	PdeSrc.u = 0;
943	# endif
944
945	# if PGM_GST_TYPE == PGM_TYPE_AMD64
946	const bool fIsBigPage = PdeSrc.b.u1Size;
947	# else
948	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
949	# endif
950
951	# ifdef IN_RING3
952	/*
953	* If a CR3 Sync is pending we may ignore the invalidate page operation
954	* depending on the kind of sync and if it's a global page or not.
955	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
956	*/
957	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
958	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
959	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
960	&& fIsBigPage
961	&& PdeSrc.b.u1Global
962	)
963	)
964	# else
965	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
966	# endif
967	{
968	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
969	return VINF_SUCCESS;
970	}
971	# endif /* IN_RING3 */
972
973	# if PGM_GST_TYPE == PGM_TYPE_AMD64
974	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
975
976	/* Fetch the pgm pool shadow descriptor. */
977	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
978	Assert(pShwPdpt);
979
980	/* Fetch the pgm pool shadow descriptor. */
981	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & SHW_PDPE_PG_MASK);
982	Assert(pShwPde);
983
984	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
985	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
986
987	if ( !pPml4eSrc->n.u1Present
988	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
989	{
990	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
991	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
992	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
993	pPml4eDst->u = 0;
994	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
995	PGM_INVL_GUEST_TLBS();
996	return VINF_SUCCESS;
997	}
998	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
999	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1000	{
1001	/*
1002	* Mark not present so we can resync the PML4E when it's used.
1003	*/
1004	LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1005	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1006	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
1007	pPml4eDst->u = 0;
1008	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1009	PGM_INVL_GUEST_TLBS();
1010	}
1011	else if (!pPml4eSrc->n.u1Accessed)
1012	{
1013	/*
1014	* Mark not present so we can set the accessed bit.
1015	*/
1016	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1017	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1018	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
1019	pPml4eDst->u = 0;
1020	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1021	PGM_INVL_GUEST_TLBS();
1022	}
1023
1024	/* Check if the PDPT entry has changed. */
1025	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1026	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1027	if ( !PdpeSrc.n.u1Present
1028	\|\| pShwPde->GCPhys != GCPhysPd)
1029	{
1030	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1031	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1032	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1033	pPdpeDst->u = 0;
1034	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1035	PGM_INVL_GUEST_TLBS();
1036	return VINF_SUCCESS;
1037	}
1038	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1039	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1040	{
1041	/*
1042	* Mark not present so we can resync the PDPTE when it's used.
1043	*/
1044	LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1045	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1046	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1047	pPdpeDst->u = 0;
1048	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1049	PGM_INVL_GUEST_TLBS();
1050	}
1051	else if (!PdpeSrc.lm.u1Accessed)
1052	{
1053	/*
1054	* Mark not present so we can set the accessed bit.
1055	*/
1056	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1057	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1058	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1059	pPdpeDst->u = 0;
1060	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1061	PGM_INVL_GUEST_TLBS();
1062	}
1063	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
1064
1065	# if PGM_GST_TYPE == PGM_TYPE_PAE
1066
1067	# endif
1068
1069
1070	/*
1071	* Deal with the Guest PDE.
1072	*/
1073	rc = VINF_SUCCESS;
1074	if (PdeSrc.n.u1Present)
1075	{
1076	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1077	{
1078	/*
1079	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1080	*/
1081	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1082	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1083	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1084	}
1085	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1086	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1087	{
1088	/*
1089	* Mark not present so we can resync the PDE when it's used.
1090	*/
1091	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1092	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1093	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1094	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1095	# else
1096	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1097	# endif
1098	pPdeDst->u = 0;
1099	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1100	PGM_INVL_GUEST_TLBS();
1101	}
1102	else if (!PdeSrc.n.u1Accessed)
1103	{
1104	/*
1105	* Mark not present so we can set the accessed bit.
1106	*/
1107	LogFlow(("InvalidatePage: Out-of-sync (A) at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1108	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1109	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1110	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1111	# else
1112	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1113	# endif
1114	pPdeDst->u = 0;
1115	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1116	PGM_INVL_GUEST_TLBS();
1117	}
1118	else if (!fIsBigPage)
1119	{
1120	/*
1121	* 4KB - page.
1122	*/
1123	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1124	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1125	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1126	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1127	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1128	# endif
1129	if (pShwPage->GCPhys == GCPhys)
1130	{
1131	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1132	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1133	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1134	if (pPT->a[iPTEDst].n.u1Present)
1135	{
1136	# ifdef PGMPOOL_WITH_USER_TRACKING
1137	/* This is very unlikely with caching/monitoring enabled. */
1138	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1139	# endif
1140	pPT->a[iPTEDst].u = 0;
1141	}
1142	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1143	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1144	if (VBOX_SUCCESS(rc))
1145	rc = VINF_SUCCESS;
1146	# endif
1147	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
1148	PGM_INVL_PG(GCPtrPage);
1149	}
1150	else
1151	{
1152	/*
1153	* The page table address changed.
1154	*/
1155	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
1156	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1157	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1158	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1159	# else
1160	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1161	# endif
1162	pPdeDst->u = 0;
1163	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1164	PGM_INVL_GUEST_TLBS();
1165	}
1166	}
1167	else
1168	{
1169	/*
1170	* 2/4MB - page.
1171	*/
1172	/* Before freeing the page, check if anything really changed. */
1173	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1174	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1175	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1176	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1177	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1178	# endif
1179	if ( pShwPage->GCPhys == GCPhys
1180	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1181	{
1182	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1183	/** @todo PAT */
1184	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1185	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1186	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1187	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1188	{
1189	LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1190	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
1191	return VINF_SUCCESS;
1192	}
1193	}
1194
1195	/*
1196	* Ok, the page table is present and it's been changed in the guest.
1197	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1198	* We could do this for some flushes in GC too, but we need an algorithm for
1199	* deciding which 4MB pages containing code likely to be executed very soon.
1200	*/
1201	LogFlow(("InvalidatePage: Out-of-sync PD at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1202	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1203	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1204	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1205	# else
1206	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1207	# endif
1208	pPdeDst->u = 0;
1209	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1210	PGM_INVL_BIG_PG(GCPtrPage);
1211	}
1212	}
1213	else
1214	{
1215	/*
1216	* Page directory is not present, mark shadow PDE not present.
1217	*/
1218	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1219	{
1220	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1221	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1222	# else
1223	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1224	# endif
1225	pPdeDst->u = 0;
1226	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1227	PGM_INVL_PG(GCPtrPage);
1228	}
1229	else
1230	{
1231	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1232	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1233	}
1234	}
1235
1236	return rc;
1237
1238	#else /* guest real and protected mode */
1239	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1240	return VINF_SUCCESS;
1241	#endif
1242	}
1243
1244
1245	#ifdef PGMPOOL_WITH_USER_TRACKING
1246	/**
1247	* Update the tracking of shadowed pages.
1248	*
1249	* @param pVM The VM handle.
1250	* @param pShwPage The shadow page.
1251	* @param HCPhys The physical page we is being dereferenced.
1252	*/
1253	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1254	{
1255	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1256	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1257	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1258
1259	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1260	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1261	* 2. write protect all shadowed pages. I.e. implement caching.
1262	*/
1263	/*
1264	* Find the guest address.
1265	*/
1266	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1267	pRam;
1268	pRam = CTXALLSUFF(pRam->pNext))
1269	{
1270	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1271	while (iPage-- > 0)
1272	{
1273	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1274	{
1275	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1276	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1277	pShwPage->cPresent--;
1278	pPool->cPresent--;
1279	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1280	return;
1281	}
1282	}
1283	}
1284
1285	for (;;)
1286	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1287	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1288	pShwPage->cPresent--;
1289	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1290	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1291	}
1292
1293
1294	/**
1295	* Update the tracking of shadowed pages.
1296	*
1297	* @param pVM The VM handle.
1298	* @param pShwPage The shadow page.
1299	* @param u16 The top 16-bit of the pPage->HCPhys.
1300	* @param pPage Pointer to the guest page. this will be modified.
1301	* @param iPTDst The index into the shadow table.
1302	*/
1303	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1304	{
1305	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1306	/*
1307	* We're making certain assumptions about the placement of cRef and idx.
1308	*/
1309	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1310	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1311
1312	/*
1313	* Just deal with the simple first time here.
1314	*/
1315	if (!u16)
1316	{
1317	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1318	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1319	}
1320	else
1321	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1322
1323	/* write back, trying to be clever... */
1324	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1325	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1326	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1327	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1328
1329	/* update statistics. */
1330	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1331	pShwPage->cPresent++;
1332	if (pShwPage->iFirstPresent > iPTDst)
1333	pShwPage->iFirstPresent = iPTDst;
1334	}
1335	#endif /* PGMPOOL_WITH_USER_TRACKING */
1336
1337
1338	/**
1339	* Creates a 4K shadow page for a guest page.
1340	*
1341	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1342	* physical address. The PdeSrc argument only the flags are used. No page structured
1343	* will be mapped in this function.
1344	*
1345	* @param pVM VM handle.
1346	* @param pPteDst Destination page table entry.
1347	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1348	* Can safely assume that only the flags are being used.
1349	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1350	* @param pShwPage Pointer to the shadow page.
1351	* @param iPTDst The index into the shadow table.
1352	*
1353	* @remark Not used for 2/4MB pages!
1354	*/
1355	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1356	{
1357	if (PteSrc.n.u1Present)
1358	{
1359	/*
1360	* Find the ram range.
1361	*/
1362	PPGMPAGE pPage;
1363	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1364	if (VBOX_SUCCESS(rc))
1365	{
1366	/** @todo investiage PWT, PCD and PAT. */
1367	/*
1368	* Make page table entry.
1369	*/
1370	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1371	SHWPTE PteDst;
1372	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1373	{
1374	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1375	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1376	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1377	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1378	else
1379	{
1380	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1381	PteDst.u = 0;
1382	}
1383	/** @todo count these two kinds. */
1384	}
1385	else
1386	{
1387	/*
1388	* If the page or page directory entry is not marked accessed,
1389	* we mark the page not present.
1390	*/
1391	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1392	{
1393	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1394	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1395	PteDst.u = 0;
1396	}
1397	else
1398	/*
1399	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1400	* when the page is modified.
1401	*/
1402	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1403	{
1404	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1405	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1406	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1407	\| PGM_PTFLAGS_TRACK_DIRTY;
1408	}
1409	else
1410	{
1411	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1412	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1413	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1414	}
1415	}
1416
1417	#ifdef PGMPOOL_WITH_USER_TRACKING
1418	/*
1419	* Keep user track up to date.
1420	*/
1421	if (PteDst.n.u1Present)
1422	{
1423	if (!pPteDst->n.u1Present)
1424	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1425	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1426	{
1427	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1428	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1429	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1430	}
1431	}
1432	else if (pPteDst->n.u1Present)
1433	{
1434	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1435	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1436	}
1437	#endif /* PGMPOOL_WITH_USER_TRACKING */
1438
1439	/*
1440	* Update statistics and commit the entry.
1441	*/
1442	if (!PteSrc.n.u1Global)
1443	pShwPage->fSeenNonGlobal = true;
1444	*pPteDst = PteDst;
1445	}
1446	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1447	/** @todo count these. */
1448	}
1449	else
1450	{
1451	/*
1452	* Page not-present.
1453	*/
1454	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1455	#ifdef PGMPOOL_WITH_USER_TRACKING
1456	/* Keep user track up to date. */
1457	if (pPteDst->n.u1Present)
1458	{
1459	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1460	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1461	}
1462	#endif /* PGMPOOL_WITH_USER_TRACKING */
1463	pPteDst->u = 0;
1464	/** @todo count these. */
1465	}
1466	}
1467
1468
1469	/**
1470	* Syncs a guest OS page.
1471	*
1472	* There are no conflicts at this point, neither is there any need for
1473	* page table allocations.
1474	*
1475	* @returns VBox status code.
1476	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1477	* @param pVM VM handle.
1478	* @param PdeSrc Page directory entry of the guest.
1479	* @param GCPtrPage Guest context page address.
1480	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1481	* @param uErr Fault error (X86_TRAP_PF_*).
1482	*/
1483	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1484	{
1485	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1486
1487	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1488	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1489	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1490	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
1491
1492	# if PGM_WITH_NX(PGM_GST_TYPE)
1493	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1494	# endif
1495
1496	/*
1497	* Assert preconditions.
1498	*/
1499	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1500	Assert(PdeSrc.n.u1Present);
1501	Assert(cPages);
1502
1503	/*
1504	* Get the shadow PDE, find the shadow page table in the pool.
1505	*/
1506	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1507	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1508	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1509	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1510	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1511	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); /* no mask; flat index into the 2048 entry array. */
1512	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
1513	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1514	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1515	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1516	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1517	PX86PDPAE pPDDst;
1518	X86PDEPAE PdeDst;
1519	PX86PDPT pPdptDst;
1520
1521	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1522	AssertRCReturn(rc, rc);
1523	Assert(pPDDst && pPdptDst);
1524	PdeDst = pPDDst->a[iPDDst];
1525	# endif
1526	Assert(PdeDst.n.u1Present);
1527	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1528
1529	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1530	/* Fetch the pgm pool shadow descriptor. */
1531	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
1532	Assert(pShwPde);
1533	# endif
1534
1535	/*
1536	* Check that the page is present and that the shadow PDE isn't out of sync.
1537	*/
1538	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1539	const bool fBigPage = PdeSrc.b.u1Size;
1540	# else
1541	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1542	# endif
1543	RTGCPHYS GCPhys;
1544	if (!fBigPage)
1545	{
1546	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1547	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1548	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1549	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1550	# endif
1551	}
1552	else
1553	{
1554	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1555	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1556	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1557	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1558	# endif
1559	}
1560	if ( pShwPage->GCPhys == GCPhys
1561	&& PdeSrc.n.u1Present
1562	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1563	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1564	# if PGM_WITH_NX(PGM_GST_TYPE)
1565	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1566	# endif
1567	)
1568	{
1569	/*
1570	* Check that the PDE is marked accessed already.
1571	* Since we set the accessed bit before getting here on a #PF, this
1572	* check is only meant for dealing with non-#PF'ing paths.
1573	*/
1574	if (PdeSrc.n.u1Accessed)
1575	{
1576	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1577	if (!fBigPage)
1578	{
1579	/*
1580	* 4KB Page - Map the guest page table.
1581	*/
1582	PGSTPT pPTSrc;
1583	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1584	if (VBOX_SUCCESS(rc))
1585	{
1586	# ifdef PGM_SYNC_N_PAGES
1587	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1588	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1589	{
1590	/*
1591	* This code path is currently only taken when the caller is PGMTrap0eHandler
1592	* for non-present pages!
1593	*
1594	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1595	* deal with locality.
1596	*/
1597	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1598	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1599	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1600	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1601	# else
1602	const unsigned offPTSrc = 0;
1603	# endif
1604	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1605	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1606	iPTDst = 0;
1607	else
1608	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1609	for (; iPTDst < iPTDstEnd; iPTDst++)
1610	{
1611	if (!pPTDst->a[iPTDst].n.u1Present)
1612	{
1613	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1614	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1615	NOREF(GCPtrCurPage);
1616	#ifndef IN_RING0
1617	/*
1618	* Assuming kernel code will be marked as supervisor - and not as user level
1619	* and executed using a conforming code selector - And marked as readonly.
1620	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1621	*/
1622	PPGMPAGE pPage;
1623	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1624	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1625	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1626	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1627	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1628	)
1629	#endif /* else: CSAM not active */
1630	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1631	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1632	GCPtrCurPage, PteSrc.n.u1Present,
1633	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1634	PteSrc.n.u1User & PdeSrc.n.u1User,
1635	(uint64_t)PteSrc.u,
1636	(uint64_t)pPTDst->a[iPTDst].u,
1637	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1638	}
1639	}
1640	}
1641	else
1642	# endif /* PGM_SYNC_N_PAGES */
1643	{
1644	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1645	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1646	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1647	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1648	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1649	GCPtrPage, PteSrc.n.u1Present,
1650	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1651	PteSrc.n.u1User & PdeSrc.n.u1User,
1652	(uint64_t)PteSrc.u,
1653	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1654	}
1655	}
1656	else /* MMIO or invalid page: emulated in #PF handler. */
1657	{
1658	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1659	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1660	}
1661	}
1662	else
1663	{
1664	/*
1665	* 4/2MB page - lazy syncing shadow 4K pages.
1666	* (There are many causes of getting here, it's no longer only CSAM.)
1667	*/
1668	/* Calculate the GC physical address of this 4KB shadow page. */
1669	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1670	/* Find ram range. */
1671	PPGMPAGE pPage;
1672	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1673	if (VBOX_SUCCESS(rc))
1674	{
1675	/*
1676	* Make shadow PTE entry.
1677	*/
1678	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1679	SHWPTE PteDst;
1680	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1681	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1682	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1683	{
1684	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1685	PteDst.n.u1Write = 0;
1686	else
1687	PteDst.u = 0;
1688	}
1689	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1690	# ifdef PGMPOOL_WITH_USER_TRACKING
1691	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1692	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1693	# endif
1694	pPTDst->a[iPTDst] = PteDst;
1695
1696
1697	/*
1698	* If the page is not flagged as dirty and is writable, then make it read-only
1699	* at PD level, so we can set the dirty bit when the page is modified.
1700	*
1701	* ASSUMES that page access handlers are implemented on page table entry level.
1702	* Thus we will first catch the dirty access and set PDE.D and restart. If
1703	* there is an access handler, we'll trap again and let it work on the problem.
1704	*/
1705	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1706	* As for invlpg, it simply frees the whole shadow PT.
1707	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1708	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1709	{
1710	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1711	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1712	PdeDst.n.u1Write = 0;
1713	}
1714	else
1715	{
1716	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1717	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1718	}
1719	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1720	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1721	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1722	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1723	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1724	pPDDst->a[iPDDst] = PdeDst;
1725	# endif
1726	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1727	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1728	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1729	}
1730	else
1731	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1732	}
1733	return VINF_SUCCESS;
1734	}
1735	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1736	}
1737	else
1738	{
1739	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1740	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1741	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1742	}
1743
1744	/*
1745	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1746	* Yea, I'm lazy.
1747	*/
1748	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1749	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1750	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1751	# else
1752	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1753	# endif
1754
1755	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1756	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1757	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1758	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1759	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1760	pPDDst->a[iPDDst].u = 0;
1761	# endif
1762	PGM_INVL_GUEST_TLBS();
1763	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1764
1765	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1766	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
1767
1768	# ifdef PGM_SYNC_N_PAGES
1769	/*
1770	* Get the shadow PDE, find the shadow page table in the pool.
1771	*/
1772	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1773	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1774	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1775	# else /* PAE */
1776	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1777	# endif
1778	Assert(PdeDst.n.u1Present);
1779	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1780	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1781
1782	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1783	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1784	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1785	# else
1786	const unsigned offPTSrc = 0;
1787	# endif
1788
1789	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1790	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1791	{
1792	/*
1793	* This code path is currently only taken when the caller is PGMTrap0eHandler
1794	* for non-present pages!
1795	*
1796	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1797	* deal with locality.
1798	*/
1799	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1800	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1801	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1802	iPTDst = 0;
1803	else
1804	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1805	for (; iPTDst < iPTDstEnd; iPTDst++)
1806	{
1807	if (!pPTDst->a[iPTDst].n.u1Present)
1808	{
1809	GSTPTE PteSrc;
1810
1811	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1812
1813	/* Fake the page table entry */
1814	PteSrc.u = GCPtrCurPage;
1815	PteSrc.n.u1Present = 1;
1816	PteSrc.n.u1Dirty = 1;
1817	PteSrc.n.u1Accessed = 1;
1818	PteSrc.n.u1Write = 1;
1819	PteSrc.n.u1User = 1;
1820
1821	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1822
1823	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1824	GCPtrCurPage, PteSrc.n.u1Present,
1825	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1826	PteSrc.n.u1User & PdeSrc.n.u1User,
1827	(uint64_t)PteSrc.u,
1828	(uint64_t)pPTDst->a[iPTDst].u,
1829	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1830	}
1831	}
1832	}
1833	else
1834	# endif /* PGM_SYNC_N_PAGES */
1835	{
1836	GSTPTE PteSrc;
1837	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1838	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1839
1840	/* Fake the page table entry */
1841	PteSrc.u = GCPtrCurPage;
1842	PteSrc.n.u1Present = 1;
1843	PteSrc.n.u1Dirty = 1;
1844	PteSrc.n.u1Accessed = 1;
1845	PteSrc.n.u1Write = 1;
1846	PteSrc.n.u1User = 1;
1847	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1848
1849	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1850	GCPtrPage, PteSrc.n.u1Present,
1851	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1852	PteSrc.n.u1User & PdeSrc.n.u1User,
1853	(uint64_t)PteSrc.u,
1854	(uint64_t)pPTDst->a[iPTDst].u,
1855	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1856	}
1857	return VINF_SUCCESS;
1858
1859	#else
1860	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1861	return VERR_INTERNAL_ERROR;
1862	#endif
1863	}
1864
1865
1866
1867	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1868
1869	/**
1870	* Investigate page fault and handle write protection page faults caused by
1871	* dirty bit tracking.
1872	*
1873	* @returns VBox status code.
1874	* @param pVM VM handle.
1875	* @param uErr Page fault error code.
1876	* @param pPdeDst Shadow page directory entry.
1877	* @param pPdeSrc Guest page directory entry.
1878	* @param GCPtrPage Guest context page address.
1879	*/
1880	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1881	{
1882	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1883	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1884	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1885	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1886	bool fBigPagesSupported = true;
1887	# else
1888	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1889	# endif
1890	# if PGM_WITH_NX(PGM_GST_TYPE)
1891	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1892	# endif
1893	unsigned uPageFaultLevel;
1894	int rc;
1895
1896	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1897	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1898
1899	# if PGM_GST_TYPE == PGM_TYPE_PAE \
1900	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
1901
1902	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1903	PX86PML4E pPml4eSrc;
1904	PX86PDPE pPdpeSrc;
1905
1906	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
1907	Assert(pPml4eSrc);
1908
1909	/*
1910	* Real page fault? (PML4E level)
1911	*/
1912	if ( (uErr & X86_TRAP_PF_RSVD)
1913	\|\| !pPml4eSrc->n.u1Present
1914	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
1915	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1916	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
1917	)
1918	{
1919	uPageFaultLevel = 0;
1920	goto UpperLevelPageFault;
1921	}
1922	Assert(pPdpeSrc);
1923
1924	# else /* PAE */
1925	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1926	# endif
1927
1928	/*
1929	* Real page fault? (PDPE level)
1930	*/
1931	if ( (uErr & X86_TRAP_PF_RSVD)
1932	\|\| !pPdpeSrc->n.u1Present
1933	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1934	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
1935	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
1936	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
1937	# endif
1938	)
1939	{
1940	uPageFaultLevel = 1;
1941	goto UpperLevelPageFault;
1942	}
1943	# endif
1944
1945	/*
1946	* Real page fault? (PDE level)
1947	*/
1948	if ( (uErr & X86_TRAP_PF_RSVD)
1949	\|\| !pPdeSrc->n.u1Present
1950	# if PGM_WITH_NX(PGM_GST_TYPE)
1951	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1952	# endif
1953	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1954	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1955	{
1956	uPageFaultLevel = 2;
1957	goto UpperLevelPageFault;
1958	}
1959
1960	/*
1961	* First check the easy case where the page directory has been marked read-only to track
1962	* the dirty bit of an emulated BIG page
1963	*/
1964	if (pPdeSrc->b.u1Size && fBigPagesSupported)
1965	{
1966	/* Mark guest page directory as accessed */
1967	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1968	pPml4eSrc->n.u1Accessed = 1;
1969	pPdpeSrc->lm.u1Accessed = 1;
1970	# endif
1971	pPdeSrc->b.u1Accessed = 1;
1972
1973	/*
1974	* Only write protection page faults are relevant here.
1975	*/
1976	if (fWriteFault)
1977	{
1978	/* Mark guest page directory as dirty (BIG page only). */
1979	pPdeSrc->b.u1Dirty = 1;
1980
1981	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1982	{
1983	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1984
1985	Assert(pPdeSrc->b.u1Write);
1986
1987	pPdeDst->n.u1Write = 1;
1988	pPdeDst->n.u1Accessed = 1;
1989	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1990	PGM_INVL_BIG_PG(GCPtrPage);
1991	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1992	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1993	}
1994	}
1995	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1996	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1997	}
1998	/* else: 4KB page table */
1999
2000	/*
2001	* Map the guest page table.
2002	*/
2003	PGSTPT pPTSrc;
2004	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2005	if (VBOX_SUCCESS(rc))
2006	{
2007	/*
2008	* Real page fault?
2009	*/
2010	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2011	const GSTPTE PteSrc = *pPteSrc;
2012	if ( !PteSrc.n.u1Present
2013	# if PGM_WITH_NX(PGM_GST_TYPE)
2014	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2015	# endif
2016	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2017	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2018	)
2019	{
2020	# ifdef IN_GC
2021	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
2022	# endif
2023	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2024	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2025
2026	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2027	* See the 2nd case above as well.
2028	*/
2029	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2030	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2031
2032	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2033	return VINF_EM_RAW_GUEST_TRAP;
2034	}
2035	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2036
2037	/*
2038	* Set the accessed bits in the page directory and the page table.
2039	*/
2040	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2041	pPml4eSrc->n.u1Accessed = 1;
2042	pPdpeSrc->lm.u1Accessed = 1;
2043	# endif
2044	pPdeSrc->n.u1Accessed = 1;
2045	pPteSrc->n.u1Accessed = 1;
2046
2047	/*
2048	* Only write protection page faults are relevant here.
2049	*/
2050	if (fWriteFault)
2051	{
2052	/* Write access, so mark guest entry as dirty. */
2053	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
2054	if (!pPteSrc->n.u1Dirty)
2055	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
2056	else
2057	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
2058	# endif
2059
2060	pPteSrc->n.u1Dirty = 1;
2061
2062	if (pPdeDst->n.u1Present)
2063	{
2064	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2065	* Our individual shadow handlers will provide more information and force a fatal exit.
2066	*/
2067	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2068	{
2069	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
2070	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2071	return VINF_SUCCESS;
2072	}
2073
2074	/*
2075	* Map shadow page table.
2076	*/
2077	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2078	if (pShwPage)
2079	{
2080	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2081	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2082	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2083	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2084	{
2085	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
2086	# ifdef VBOX_STRICT
2087	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2088	if (pPage)
2089	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2090	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2091	# endif
2092	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
2093
2094	Assert(pPteSrc->n.u1Write);
2095
2096	pPteDst->n.u1Write = 1;
2097	pPteDst->n.u1Dirty = 1;
2098	pPteDst->n.u1Accessed = 1;
2099	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2100	PGM_INVL_PG(GCPtrPage);
2101
2102	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2103	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2104	}
2105	}
2106	else
2107	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2108	}
2109	}
2110	/** @todo Optimize accessed bit emulation? */
2111	# ifdef VBOX_STRICT
2112	/*
2113	* Sanity check.
2114	*/
2115	else if ( !pPteSrc->n.u1Dirty
2116	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2117	&& pPdeDst->n.u1Present)
2118	{
2119	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2120	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2121	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2122	if ( pPteDst->n.u1Present
2123	&& pPteDst->n.u1Write)
2124	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2125	}
2126	# endif /* VBOX_STRICT */
2127	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2128	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2129	}
2130	AssertRC(rc);
2131	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2132	return rc;
2133
2134
2135	UpperLevelPageFault:
2136	/* Pagefault detected while checking the PML4E, PDPE or PDE.
2137	* Single exit handler to get rid of duplicate code paths.
2138	*/
2139	# ifdef IN_GC
2140	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
2141	# endif
2142	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
2143	LogFlow(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
2144
2145	if (
2146	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2147	pPml4eSrc->n.u1Present &&
2148	# endif
2149	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2150	pPdpeSrc->n.u1Present &&
2151	# endif
2152	pPdeSrc->n.u1Present)
2153	{
2154	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2155	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2156	{
2157	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2158	}
2159	else
2160	{
2161	/*
2162	* Map the guest page table.
2163	*/
2164	PGSTPT pPTSrc;
2165	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2166	if (VBOX_SUCCESS(rc))
2167	{
2168	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2169	const GSTPTE PteSrc = *pPteSrc;
2170	if (pPteSrc->n.u1Present)
2171	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2172	}
2173	AssertRC(rc);
2174	}
2175	}
2176	return VINF_EM_RAW_GUEST_TRAP;
2177	}
2178
2179	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2180
2181
2182	/**
2183	* Sync a shadow page table.
2184	*
2185	* The shadow page table is not present. This includes the case where
2186	* there is a conflict with a mapping.
2187	*
2188	* @returns VBox status code.
2189	* @param pVM VM handle.
2190	* @param iPD Page directory index.
2191	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2192	* Assume this is a temporary mapping.
2193	* @param GCPtrPage GC Pointer of the page that caused the fault
2194	*/
2195	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
2196	{
2197	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2198	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
2199	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
2200
2201	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2202	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2203	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2204	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2205
2206	int rc = VINF_SUCCESS;
2207
2208	/*
2209	* Validate input a little bit.
2210	*/
2211	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
2212	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2213	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2214	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2215	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2216	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* 0 - 2047 */
2217	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT);
2218	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
2219	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2220	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2221	const unsigned iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
2222	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2223	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2224	PX86PDPAE pPDDst;
2225	PX86PDPT pPdptDst;
2226	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2227	if (rc != VINF_SUCCESS)
2228	{
2229	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2230	return rc;
2231	}
2232	Assert(pPDDst);
2233	# endif
2234
2235	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2236	SHWPDE PdeDst = *pPdeDst;
2237
2238	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2239	/* Fetch the pgm pool shadow descriptor. */
2240	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2241	Assert(pShwPde);
2242	# endif
2243
2244	# ifndef PGM_WITHOUT_MAPPINGS
2245	/*
2246	* Check for conflicts.
2247	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2248	* HC: Simply resolve the conflict.
2249	*/
2250	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2251	{
2252	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2253	# ifndef IN_RING3
2254	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
2255	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2256	return VERR_ADDRESS_CONFLICT;
2257	# else
2258	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2259	Assert(pMapping);
2260	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2261	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2262	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2263	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2264	# else
2265	AssertFailed(); /* can't happen for amd64 */
2266	# endif
2267	if (VBOX_FAILURE(rc))
2268	{
2269	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2270	return rc;
2271	}
2272	PdeDst = *pPdeDst;
2273	# endif
2274	}
2275	# else /* PGM_WITHOUT_MAPPINGS */
2276	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2277	# endif /* PGM_WITHOUT_MAPPINGS */
2278	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2279
2280	/*
2281	* Sync page directory entry.
2282	*/
2283	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2284	if (PdeSrc.n.u1Present)
2285	{
2286	/*
2287	* Allocate & map the page table.
2288	*/
2289	PSHWPT pPTDst;
2290	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2291	const bool fPageTable = !PdeSrc.b.u1Size;
2292	# else
2293	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2294	# endif
2295	PPGMPOOLPAGE pShwPage;
2296	RTGCPHYS GCPhys;
2297	if (fPageTable)
2298	{
2299	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2300	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2301	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2302	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2303	# endif
2304	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2305	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2306	# else
2307	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2308	# endif
2309	}
2310	else
2311	{
2312	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2313	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2314	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2315	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2316	# endif
2317	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2318	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2319	# else
2320	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2321	# endif
2322	}
2323	if (rc == VINF_SUCCESS)
2324	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2325	else if (rc == VINF_PGM_CACHED_PAGE)
2326	{
2327	/*
2328	* The PT was cached, just hook it up.
2329	*/
2330	if (fPageTable)
2331	PdeDst.u = pShwPage->Core.Key
2332	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2333	else
2334	{
2335	PdeDst.u = pShwPage->Core.Key
2336	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2337	/* (see explanation and assumptions further down.) */
2338	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2339	{
2340	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2341	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2342	PdeDst.b.u1Write = 0;
2343	}
2344	}
2345	*pPdeDst = PdeDst;
2346	return VINF_SUCCESS;
2347	}
2348	else if (rc == VERR_PGM_POOL_FLUSHED)
2349	return VINF_PGM_SYNC_CR3;
2350	else
2351	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2352	PdeDst.u &= X86_PDE_AVL_MASK;
2353	PdeDst.u \|= pShwPage->Core.Key;
2354
2355	/*
2356	* Page directory has been accessed (this is a fault situation, remember).
2357	*/
2358	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2359	if (fPageTable)
2360	{
2361	/*
2362	* Page table - 4KB.
2363	*
2364	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2365	*/
2366	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2367	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2368	PGSTPT pPTSrc;
2369	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2370	if (VBOX_SUCCESS(rc))
2371	{
2372	/*
2373	* Start by syncing the page directory entry so CSAM's TLB trick works.
2374	*/
2375	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2376	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2377	*pPdeDst = PdeDst;
2378
2379	/*
2380	* Directory/page user or supervisor privilege: (same goes for read/write)
2381	*
2382	* Directory Page Combined
2383	* U/S U/S U/S
2384	* 0 0 0
2385	* 0 1 0
2386	* 1 0 0
2387	* 1 1 1
2388	*
2389	* Simple AND operation. Table listed for completeness.
2390	*
2391	*/
2392	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2393	# ifdef PGM_SYNC_N_PAGES
2394	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2395	unsigned iPTDst = iPTBase;
2396	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2397	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2398	iPTDst = 0;
2399	else
2400	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2401	# else /* !PGM_SYNC_N_PAGES */
2402	unsigned iPTDst = 0;
2403	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2404	# endif /* !PGM_SYNC_N_PAGES */
2405	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2406	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2407	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2408	# else
2409	const unsigned offPTSrc = 0;
2410	# endif
2411	for (; iPTDst < iPTDstEnd; iPTDst++)
2412	{
2413	const unsigned iPTSrc = iPTDst + offPTSrc;
2414	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2415
2416	if (PteSrc.n.u1Present) /* we've already cleared it above */
2417	{
2418	# ifndef IN_RING0
2419	/*
2420	* Assuming kernel code will be marked as supervisor - and not as user level
2421	* and executed using a conforming code selector - And marked as readonly.
2422	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2423	*/
2424	PPGMPAGE pPage;
2425	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2426	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2427	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2428	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2429	)
2430	# endif
2431	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2432	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2433	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2434	PteSrc.n.u1Present,
2435	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2436	PteSrc.n.u1User & PdeSrc.n.u1User,
2437	(uint64_t)PteSrc.u,
2438	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2439	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2440	}
2441	} /* for PTEs */
2442	}
2443	}
2444	else
2445	{
2446	/*
2447	* Big page - 2/4MB.
2448	*
2449	* We'll walk the ram range list in parallel and optimize lookups.
2450	* We will only sync on shadow page table at a time.
2451	*/
2452	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2453
2454	/**
2455	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2456	*/
2457
2458	/*
2459	* Start by syncing the page directory entry.
2460	*/
2461	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2462	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2463
2464	/*
2465	* If the page is not flagged as dirty and is writable, then make it read-only
2466	* at PD level, so we can set the dirty bit when the page is modified.
2467	*
2468	* ASSUMES that page access handlers are implemented on page table entry level.
2469	* Thus we will first catch the dirty access and set PDE.D and restart. If
2470	* there is an access handler, we'll trap again and let it work on the problem.
2471	*/
2472	/** @todo move the above stuff to a section in the PGM documentation. */
2473	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2474	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2475	{
2476	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2477	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2478	PdeDst.b.u1Write = 0;
2479	}
2480	*pPdeDst = PdeDst;
2481
2482	/*
2483	* Fill the shadow page table.
2484	*/
2485	/* Get address and flags from the source PDE. */
2486	SHWPTE PteDstBase;
2487	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2488
2489	/* Loop thru the entries in the shadow PT. */
2490	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2491	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2492	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2493	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2494	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2495	unsigned iPTDst = 0;
2496	while (iPTDst < ELEMENTS(pPTDst->a))
2497	{
2498	/* Advance ram range list. */
2499	while (pRam && GCPhys > pRam->GCPhysLast)
2500	pRam = CTXALLSUFF(pRam->pNext);
2501	if (pRam && GCPhys >= pRam->GCPhys)
2502	{
2503	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2504	do
2505	{
2506	/* Make shadow PTE. */
2507	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2508	SHWPTE PteDst;
2509
2510	/* Make sure the RAM has already been allocated. */
2511	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2512	{
2513	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2514	{
2515	# ifdef IN_RING3
2516	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2517	# else
2518	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2519	# endif
2520	if (rc != VINF_SUCCESS)
2521	return rc;
2522	}
2523	}
2524
2525	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2526	{
2527	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2528	{
2529	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2530	PteDst.n.u1Write = 0;
2531	}
2532	else
2533	PteDst.u = 0;
2534	}
2535	# ifndef IN_RING0
2536	/*
2537	* Assuming kernel code will be marked as supervisor and not as user level and executed
2538	* using a conforming code selector. Don't check for readonly, as that implies the whole
2539	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2540	*/
2541	else if ( !PdeSrc.n.u1User
2542	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2543	PteDst.u = 0;
2544	# endif
2545	else
2546	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2547	# ifdef PGMPOOL_WITH_USER_TRACKING
2548	if (PteDst.n.u1Present)
2549	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2550	# endif
2551	/* commit it */
2552	pPTDst->a[iPTDst] = PteDst;
2553	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2554	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2555	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2556
2557	/* advance */
2558	GCPhys += PAGE_SIZE;
2559	iHCPage++;
2560	iPTDst++;
2561	} while ( iPTDst < ELEMENTS(pPTDst->a)
2562	&& GCPhys <= pRam->GCPhysLast);
2563	}
2564	else if (pRam)
2565	{
2566	Log(("Invalid pages at %VGp\n", GCPhys));
2567	do
2568	{
2569	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2570	GCPhys += PAGE_SIZE;
2571	iPTDst++;
2572	} while ( iPTDst < ELEMENTS(pPTDst->a)
2573	&& GCPhys < pRam->GCPhys);
2574	}
2575	else
2576	{
2577	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2578	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2579	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2580	}
2581	} /* while more PTEs */
2582	} /* 4KB / 4MB */
2583	}
2584	else
2585	AssertRelease(!PdeDst.n.u1Present);
2586
2587	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2588	# ifdef IN_GC
2589	if (VBOX_FAILURE(rc))
2590	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2591	# endif
2592	return rc;
2593
2594	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2595	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2596
2597	int rc = VINF_SUCCESS;
2598
2599	/*
2600	* Validate input a little bit.
2601	*/
2602	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2603	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2604	# else
2605	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2606	# endif
2607	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2608	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2609	SHWPDE PdeDst = *pPdeDst;
2610
2611	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2612	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2613
2614	GSTPDE PdeSrc;
2615	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2616	PdeSrc.n.u1Present = 1;
2617	PdeSrc.n.u1Write = 1;
2618	PdeSrc.n.u1Accessed = 1;
2619	PdeSrc.n.u1User = 1;
2620
2621	/*
2622	* Allocate & map the page table.
2623	*/
2624	PSHWPT pPTDst;
2625	PPGMPOOLPAGE pShwPage;
2626	RTGCPHYS GCPhys;
2627
2628	/* Virtual address = physical address */
2629	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2630	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2631
2632	if ( rc == VINF_SUCCESS
2633	\|\| rc == VINF_PGM_CACHED_PAGE)
2634	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2635	else
2636	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2637
2638	PdeDst.u &= X86_PDE_AVL_MASK;
2639	PdeDst.u \|= pShwPage->Core.Key;
2640	PdeDst.n.u1Present = 1;
2641	PdeDst.n.u1Write = 1;
2642	PdeDst.n.u1User = 1;
2643	*pPdeDst = PdeDst;
2644
2645	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2646	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2647	return rc;
2648
2649	#else
2650	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2651	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2652	return VERR_INTERNAL_ERROR;
2653	#endif
2654	}
2655
2656
2657
2658	/**
2659	* Prefetch a page/set of pages.
2660	*
2661	* Typically used to sync commonly used pages before entering raw mode
2662	* after a CR3 reload.
2663	*
2664	* @returns VBox status code.
2665	* @param pVM VM handle.
2666	* @param GCPtrPage Page to invalidate.
2667	*/
2668	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2669	{
2670	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2671	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2672	/*
2673	* Check that all Guest levels thru the PDE are present, getting the
2674	* PD and PDE in the processes.
2675	*/
2676	int rc = VINF_SUCCESS;
2677	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2678	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2679	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2680	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2681	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2682	unsigned iPDSrc;
2683	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2684	if (!pPDSrc)
2685	return VINF_SUCCESS; /* not present */
2686	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2687	unsigned iPDSrc;
2688	PX86PML4E pPml4eSrc;
2689	X86PDPE PdpeSrc;
2690	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2691	if (!pPDSrc)
2692	return VINF_SUCCESS; /* not present */
2693	# endif
2694	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2695	# else
2696	PGSTPD pPDSrc = NULL;
2697	const unsigned iPDSrc = 0;
2698	GSTPDE PdeSrc;
2699
2700	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2701	PdeSrc.n.u1Present = 1;
2702	PdeSrc.n.u1Write = 1;
2703	PdeSrc.n.u1Accessed = 1;
2704	PdeSrc.n.u1User = 1;
2705	# endif
2706
2707	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2708	{
2709	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2710	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2711	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2712	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2713	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2714	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2715	PX86PDPAE pPDDst;
2716	X86PDEPAE PdeDst;
2717
2718	# if PGM_GST_TYPE == PGM_TYPE_PROT
2719	/* AMD-V nested paging */
2720	X86PML4E Pml4eSrc;
2721	X86PDPE PdpeSrc;
2722	PX86PML4E pPml4eSrc = &Pml4eSrc;
2723
2724	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2725	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2726	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2727	# endif
2728
2729	int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2730	if (rc != VINF_SUCCESS)
2731	{
2732	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2733	return rc;
2734	}
2735	Assert(pPDDst);
2736	PdeDst = pPDDst->a[iPDDst];
2737	# endif
2738	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2739	{
2740	if (!PdeDst.n.u1Present)
2741	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2742	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2743	else
2744	{
2745	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2746	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2747	* makes no sense to prefetch more than one page.
2748	*/
2749	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2750	if (VBOX_SUCCESS(rc))
2751	rc = VINF_SUCCESS;
2752	}
2753	}
2754	}
2755	return rc;
2756	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED
2757	return VINF_SUCCESS; /* ignore */
2758	#endif
2759	}
2760
2761
2762
2763
2764	/**
2765	* Syncs a page during a PGMVerifyAccess() call.
2766	*
2767	* @returns VBox status code (informational included).
2768	* @param GCPtrPage The address of the page to sync.
2769	* @param fPage The effective guest page flags.
2770	* @param uErr The trap error code.
2771	*/
2772	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2773	{
2774	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2775
2776	Assert(!HWACCMIsNestedPagingActive(pVM));
2777	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2778	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2779
2780	# ifndef IN_RING0
2781	if (!(fPage & X86_PTE_US))
2782	{
2783	/*
2784	* Mark this page as safe.
2785	*/
2786	/** @todo not correct for pages that contain both code and data!! */
2787	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2788	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2789	}
2790	# endif
2791	/*
2792	* Get guest PD and index.
2793	*/
2794
2795	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2796	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2797	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2798	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2799	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2800	unsigned iPDSrc;
2801	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2802
2803	if (pPDSrc)
2804	{
2805	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2806	return VINF_EM_RAW_GUEST_TRAP;
2807	}
2808	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2809	unsigned iPDSrc;
2810	PX86PML4E pPml4eSrc;
2811	X86PDPE PdpeSrc;
2812	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2813	if (!pPDSrc)
2814	{
2815	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2816	return VINF_EM_RAW_GUEST_TRAP;
2817	}
2818	# endif
2819	# else
2820	PGSTPD pPDSrc = NULL;
2821	const unsigned iPDSrc = 0;
2822	# endif
2823	int rc = VINF_SUCCESS;
2824
2825	/*
2826	* First check if the shadow pd is present.
2827	*/
2828	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2829	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2830	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2831	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2832	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2833	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2834	PX86PDPAE pPDDst;
2835	PX86PDEPAE pPdeDst;
2836
2837	# if PGM_GST_TYPE == PGM_TYPE_PROT
2838	/* AMD-V nested paging */
2839	X86PML4E Pml4eSrc;
2840	X86PDPE PdpeSrc;
2841	PX86PML4E pPml4eSrc = &Pml4eSrc;
2842
2843	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2844	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2845	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2846	# endif
2847
2848	rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2849	if (rc != VINF_SUCCESS)
2850	{
2851	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2852	return rc;
2853	}
2854	Assert(pPDDst);
2855	pPdeDst = &pPDDst->a[iPDDst];
2856	# endif
2857	if (!pPdeDst->n.u1Present)
2858	{
2859	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2860	AssertRC(rc);
2861	if (rc != VINF_SUCCESS)
2862	return rc;
2863	}
2864
2865	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2866	/* Check for dirty bit fault */
2867	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2868	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2869	Log(("PGMVerifyAccess: success (dirty)\n"));
2870	else
2871	{
2872	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2873	#else
2874	{
2875	GSTPDE PdeSrc;
2876	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2877	PdeSrc.n.u1Present = 1;
2878	PdeSrc.n.u1Write = 1;
2879	PdeSrc.n.u1Accessed = 1;
2880	PdeSrc.n.u1User = 1;
2881
2882	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2883	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2884	if (uErr & X86_TRAP_PF_US)
2885	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2886	else /* supervisor */
2887	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2888
2889	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2890	if (VBOX_SUCCESS(rc))
2891	{
2892	/* Page was successfully synced */
2893	Log2(("PGMVerifyAccess: success (sync)\n"));
2894	rc = VINF_SUCCESS;
2895	}
2896	else
2897	{
2898	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2899	return VINF_EM_RAW_GUEST_TRAP;
2900	}
2901	}
2902	return rc;
2903
2904	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2905
2906	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2907	return VERR_INTERNAL_ERROR;
2908	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2909	}
2910
2911
2912	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2913	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
2914	/**
2915	* Figures out which kind of shadow page this guest PDE warrants.
2916	*
2917	* @returns Shadow page kind.
2918	* @param pPdeSrc The guest PDE in question.
2919	* @param cr4 The current guest cr4 value.
2920	*/
2921	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2922	{
2923	# if PMG_GST_TYPE == PGM_TYPE_AMD64
2924	if (!pPdeSrc->n.u1Size)
2925	# else
2926	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2927	# endif
2928	return BTH_PGMPOOLKIND_PT_FOR_PT;
2929	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2930	//{
2931	// case 0:
2932	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2933	// case X86_PDE4M_RW:
2934	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2935	// case X86_PDE4M_US:
2936	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2937	// case X86_PDE4M_RW \| X86_PDE4M_US:
2938	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2939	# if 0
2940	// case X86_PDE4M_PAE_NX:
2941	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2942	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2943	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2944	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2945	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2946	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2947	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2948	# endif
2949	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2950	//}
2951	}
2952	# endif
2953	#endif
2954
2955	#undef MY_STAM_COUNTER_INC
2956	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2957
2958
2959	/**
2960	* Syncs the paging hierarchy starting at CR3.
2961	*
2962	* @returns VBox status code, no specials.
2963	* @param pVM The virtual machine.
2964	* @param cr0 Guest context CR0 register
2965	* @param cr3 Guest context CR3 register
2966	* @param cr4 Guest context CR4 register
2967	* @param fGlobal Including global page directories or not
2968	*/
2969	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2970	{
2971	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
2972	/** @todo check if this is really necessary */
2973	HWACCMFlushTLB(pVM);
2974	return VINF_SUCCESS;
2975
2976	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
2977	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2978	fGlobal = true; /* Change this CR3 reload to be a global one. */
2979
2980	/*
2981	* Update page access handlers.
2982	* The virtual are always flushed, while the physical are only on demand.
2983	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2984	* have to look into that later because it will have a bad influence on the performance.
2985	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2986	* bird: Yes, but that won't work for aliases.
2987	*/
2988	/** @todo this MUST go away. See #1557. */
2989	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2990	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2991	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2992
2993	# ifdef PGMPOOL_WITH_MONITORING
2994	/*
2995	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2996	* Occationally we will have to clear all the shadow page tables because we wanted
2997	* to monitor a page which was mapped by too many shadowed page tables. This operation
2998	* sometimes refered to as a 'lightweight flush'.
2999	*/
3000	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
3001	pgmPoolMonitorModifiedClearAll(pVM);
3002	else
3003	{
3004	# ifdef IN_RING3
3005	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
3006	pgmPoolClearAll(pVM);
3007	# else
3008	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
3009	return VINF_PGM_SYNC_CR3;
3010	# endif
3011	}
3012	# endif
3013
3014	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3015	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
3016
3017	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3018	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3019	bool fBigPagesSupported = true;
3020	# else
3021	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3022	# endif
3023
3024	/*
3025	* Get page directory addresses.
3026	*/
3027	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3028	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3029	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
3030	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3031	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
3032	# endif
3033	# endif
3034
3035	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3036	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
3037	Assert(pPDSrc);
3038	# ifndef IN_GC
3039	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3040	# endif
3041	# endif
3042
3043	/*
3044	* Iterate the page directory.
3045	*/
3046	PPGMMAPPING pMapping;
3047	unsigned iPdNoMapping;
3048	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3049	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
3050
3051	/* Only check mappings if they are supposed to be put into the shadow page table. */
3052	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3053	{
3054	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
3055	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3056	}
3057	else
3058	{
3059	pMapping = 0;
3060	iPdNoMapping = ~0U;
3061	}
3062	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3063	for (uint64_t iPml4e = 0; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3064	{
3065	PPGMPOOLPAGE pShwPdpt = NULL;
3066	PX86PML4E pPml4eSrc, pPml4eDst;
3067	RTGCPHYS GCPhysPdptSrc;
3068
3069	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3070	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3071
3072	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3073	if (!pPml4eDst->n.u1Present)
3074	continue;
3075	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3076
3077	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3078
3079	/* Anything significant changed? */
3080	if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
3081	\|\| GCPhysPdptSrc != pShwPdpt->GCPhys)
3082	{
3083	/* Free it. */
3084	LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3085	(uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
3086	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
3087	pPml4eDst->u = 0;
3088	continue;
3089	}
3090	/* Force an attribute sync. */
3091	pPml4eDst->n.u1User = pPml4eSrc->n.u1User;
3092	pPml4eDst->n.u1Write = pPml4eSrc->n.u1Write;
3093	pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
3094
3095	# else
3096	{
3097	# endif
3098	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3099	for (uint64_t iPdpte = 0; iPdpte < GST_PDPE_ENTRIES; iPdpte++)
3100	{
3101	unsigned iPDSrc;
3102	# if PGM_GST_TYPE == PGM_TYPE_PAE
3103	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3104	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
3105	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpte << X86_PDPT_SHIFT, &iPDSrc);
3106	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3107	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3108
3109	if (pPDSrc == NULL)
3110	{
3111	/* PDPE not present */
3112	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
3113	{
3114	LogFlow(("SyncCR3: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
3115	/* for each page directory entry */
3116	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
3117	{
3118	if ( pPDEDst[iPD].n.u1Present
3119	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3120	{
3121	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
3122	pPDEDst[iPD].u = 0;
3123	}
3124	}
3125	}
3126	if (!(pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
3127	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 0;
3128	continue;
3129	}
3130	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3131	PPGMPOOLPAGE pShwPde = NULL;
3132	RTGCPHYS GCPhysPdeSrc;
3133	PX86PDPE pPdpeDst;
3134	PX86PML4E pPml4eSrc;
3135	X86PDPE PdpeSrc;
3136	PX86PDPT pPdptDst;
3137	PX86PDPAE pPDDst;
3138	PX86PDEPAE pPDEDst;
3139	RTGCUINTPTR GCPtr = (iPml4e << X86_PML4_SHIFT) \|\| (iPdpte << X86_PDPT_SHIFT);
3140	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3141
3142	int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3143	if (rc != VINF_SUCCESS)
3144	{
3145	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3146	break; /* next PML4E */
3147
3148	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3149	continue; /* next PDPTE */
3150	}
3151	Assert(pPDDst);
3152	pPDEDst = &pPDDst->a[0];
3153	Assert(iPDSrc == 0);
3154
3155	pPdpeDst = &pPdptDst->a[iPdpte];
3156
3157	/* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
3158	if (!pPdpeDst->n.u1Present)
3159	continue; /* next PDPTE */
3160
3161	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3162	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3163
3164	/* Anything significant changed? */
3165	if ( PdpeSrc.n.u1Present != pPdpeDst->n.u1Present
3166	\|\| GCPhysPdeSrc != pShwPde->GCPhys)
3167	{
3168	/* Free it. */
3169	LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3170	((uint64_t)iPml4e << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
3171
3172	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3173	Assert(!(pPdpeDst->u & PGM_PLXFLAGS_MAPPING));
3174	pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpte);
3175	pPdpeDst->u = 0;
3176	continue; /* next guest PDPTE */
3177	}
3178	/* Force an attribute sync. */
3179	pPdpeDst->lm.u1User = PdpeSrc.lm.u1User;
3180	pPdpeDst->lm.u1Write = PdpeSrc.lm.u1Write;
3181	pPdpeDst->lm.u1NoExecute = PdpeSrc.lm.u1NoExecute;
3182	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3183
3184	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3185	{
3186	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3187	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
3188	{
3189	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3190	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3191	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3192	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3193	# endif
3194	register GSTPDE PdeSrc = pPDSrc->a[iPD];
3195	if ( PdeSrc.n.u1Present
3196	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3197	{
3198	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3199	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3200	&& !defined(PGM_WITHOUT_MAPPINGS)
3201
3202	/*
3203	* Check for conflicts with GC mappings.
3204	*/
3205	# if PGM_GST_TYPE == PGM_TYPE_PAE
3206	if (iPD + iPdpte * X86_PG_PAE_ENTRIES == iPdNoMapping)
3207	# else
3208	if (iPD == iPdNoMapping)
3209	# endif
3210	{
3211	if (pVM->pgm.s.fMappingsFixed)
3212	{
3213	/* It's fixed, just skip the mapping. */
3214	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3215	iPD += cPTs - 1;
3216	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3217	pMapping = pMapping->CTXALLSUFF(pNext);
3218	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3219	continue;
3220	}
3221	# ifdef IN_RING3
3222	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3223	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3224	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3225	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3226	# endif
3227	if (VBOX_FAILURE(rc))
3228	return rc;
3229
3230	/*
3231	* Update iPdNoMapping and pMapping.
3232	*/
3233	pMapping = pVM->pgm.s.pMappingsR3;
3234	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3235	pMapping = pMapping->pNextR3;
3236	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3237	# else
3238	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3239	return VINF_PGM_SYNC_CR3;
3240	# endif
3241	}
3242	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3243	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3244	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3245	/*
3246	* Sync page directory entry.
3247	*
3248	* The current approach is to allocated the page table but to set
3249	* the entry to not-present and postpone the page table synching till
3250	* it's actually used.
3251	*/
3252	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3253	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3254	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3255	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3256	# else
3257	const unsigned iPdShw = iPD; NOREF(iPdShw);
3258	# endif
3259	{
3260	SHWPDE PdeDst = *pPDEDst;
3261	if (PdeDst.n.u1Present)
3262	{
3263	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3264	RTGCPHYS GCPhys;
3265	if ( !PdeSrc.b.u1Size
3266	\|\| !fBigPagesSupported)
3267	{
3268	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3269	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3270	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3271	GCPhys \|= i * (PAGE_SIZE / 2);
3272	# endif
3273	}
3274	else
3275	{
3276	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3277	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3278	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3279	GCPhys \|= i * X86_PAGE_2M_SIZE;
3280	# endif
3281	}
3282
3283	if ( pShwPage->GCPhys == GCPhys
3284	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3285	&& ( pShwPage->fCached
3286	\|\| ( !fGlobal
3287	&& ( false
3288	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3289	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3290	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3291	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3292	# else
3293	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3294	# endif
3295	\|\| ( !pShwPage->fSeenNonGlobal
3296	&& (cr4 & X86_CR4_PGE))
3297	# endif
3298	)
3299	)
3300	)
3301	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3302	\|\| ( fBigPagesSupported
3303	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3304	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3305	)
3306	)
3307	{
3308	# ifdef VBOX_WITH_STATISTICS
3309	if ( !fGlobal
3310	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3311	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3312	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3313	# else
3314	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3315	# endif
3316	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
3317	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3318	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
3319	else
3320	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
3321	# endif /* VBOX_WITH_STATISTICS */
3322	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3323	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3324	//# ifdef PGMPOOL_WITH_CACHE
3325	// pgmPoolCacheUsed(pPool, pShwPage);
3326	//# endif
3327	}
3328	else
3329	{
3330	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3331	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
3332	# else
3333	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3334	# endif
3335	pPDEDst->u = 0;
3336	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
3337	}
3338	}
3339	else
3340	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
3341	pPDEDst++;
3342	}
3343	}
3344	# if PGM_GST_TYPE == PGM_TYPE_PAE
3345	else if (iPD + iPdpte * X86_PG_PAE_ENTRIES != iPdNoMapping)
3346	# else
3347	else if (iPD != iPdNoMapping)
3348	# endif
3349	{
3350	/*
3351	* Check if there is any page directory to mark not present here.
3352	*/
3353	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3354	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3355	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3356	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3357	# else
3358	const unsigned iPdShw = iPD; NOREF(iPdShw);
3359	# endif
3360	{
3361	if (pPDEDst->n.u1Present)
3362	{
3363	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3364	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
3365	# else
3366	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3367	# endif
3368	pPDEDst->u = 0;
3369	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
3370	}
3371	pPDEDst++;
3372	}
3373	}
3374	else
3375	{
3376	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3377	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3378	&& !defined(PGM_WITHOUT_MAPPINGS)
3379
3380	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3381
3382	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3383	if (pVM->pgm.s.fMappingsFixed)
3384	{
3385	/* It's fixed, just skip the mapping. */
3386	pMapping = pMapping->CTXALLSUFF(pNext);
3387	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3388	}
3389	else
3390	{
3391	/*
3392	* Check for conflicts for subsequent pagetables
3393	* and advance to the next mapping.
3394	*/
3395	iPdNoMapping = ~0U;
3396	unsigned iPT = cPTs;
3397	while (iPT-- > 1)
3398	{
3399	if ( pPDSrc->a[iPD + iPT].n.u1Present
3400	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3401	{
3402	# ifdef IN_RING3
3403	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3404	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3405	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3406	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3407	# endif
3408	if (VBOX_FAILURE(rc))
3409	return rc;
3410
3411	/*
3412	* Update iPdNoMapping and pMapping.
3413	*/
3414	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
3415	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3416	pMapping = pMapping->CTXALLSUFF(pNext);
3417	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3418	break;
3419	# else
3420	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3421	return VINF_PGM_SYNC_CR3;
3422	# endif
3423	}
3424	}
3425	if (iPdNoMapping == ~0U && pMapping)
3426	{
3427	pMapping = pMapping->CTXALLSUFF(pNext);
3428	if (pMapping)
3429	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3430	}
3431	}
3432
3433	/* advance. */
3434	iPD += cPTs - 1;
3435	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3436	# if PGM_GST_TYPE != PGM_SHW_TYPE
3437	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3438	# endif
3439	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3440	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3441	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3442	}
3443
3444	} /* for iPD */
3445	} /* for each PDPTE (PAE) */
3446	} /* for each page map level 4 entry (amd64) */
3447	return VINF_SUCCESS;
3448
3449	# else /* guest real and protected mode */
3450	return VINF_SUCCESS;
3451	# endif
3452	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
3453	}
3454
3455
3456
3457
3458	#ifdef VBOX_STRICT
3459	#ifdef IN_GC
3460	# undef AssertMsgFailed
3461	# define AssertMsgFailed Log
3462	#endif
3463	#ifdef IN_RING3
3464	# include <VBox/dbgf.h>
3465
3466	/**
3467	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3468	*
3469	* @returns VBox status code (VINF_SUCCESS).
3470	* @param pVM The VM handle.
3471	* @param cr3 The root of the hierarchy.
3472	* @param crr The cr4, only PAE and PSE is currently used.
3473	* @param fLongMode Set if long mode, false if not long mode.
3474	* @param cMaxDepth Number of levels to dump.
3475	* @param pHlp Pointer to the output functions.
3476	*/
3477	__BEGIN_DECLS
3478	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3479	__END_DECLS
3480
3481	#endif
3482
3483	/**
3484	* Checks that the shadow page table is in sync with the guest one.
3485	*
3486	* @returns The number of errors.
3487	* @param pVM The virtual machine.
3488	* @param cr3 Guest context CR3 register
3489	* @param cr4 Guest context CR4 register
3490	* @param GCPtr Where to start. Defaults to 0.
3491	* @param cb How much to check. Defaults to everything.
3492	*/
3493	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3494	{
3495	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
3496	return 0;
3497	#else
3498	unsigned cErrors = 0;
3499
3500	#if PGM_GST_TYPE == PGM_TYPE_PAE
3501	/* @todo currently broken; crashes below somewhere */
3502	AssertFailed();
3503	#endif
3504
3505	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3506	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3507	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3508
3509	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3510	bool fBigPagesSupported = true;
3511	# else
3512	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3513	# endif
3514	PPGM pPGM = &pVM->pgm.s;
3515	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3516	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3517	# ifndef IN_RING0
3518	RTHCPHYS HCPhys; /* general usage. */
3519	# endif
3520	int rc;
3521
3522	/*
3523	* Check that the Guest CR3 and all its mappings are correct.
3524	*/
3525	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3526	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3527	false);
3528	# ifndef IN_RING0
3529	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3530	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDGC, NULL, &HCPhysShw);
3531	# else
3532	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3533	# endif
3534	AssertRCReturn(rc, 1);
3535	HCPhys = NIL_RTHCPHYS;
3536	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3537	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3538	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3539	RTGCPHYS GCPhys;
3540	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3541	AssertRCReturn(rc, 1);
3542	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3543	# endif
3544	#endif /* !IN_RING0 */
3545
3546	/*
3547	* Get and check the Shadow CR3.
3548	*/
3549	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3550	unsigned cPDEs = X86_PG_ENTRIES;
3551	unsigned ulIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3552	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3553	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3554	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3555	# else
3556	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3557	# endif
3558	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3559	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3560	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3561	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3562	# endif
3563	if (cb != ~(RTGCUINTPTR)0)
3564	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3565
3566	/** @todo call the other two PGMAssert() functions. /
3567
3568	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3569	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
3570	# endif
3571
3572	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3573	unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3574
3575	for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3576	{
3577	PPGMPOOLPAGE pShwPdpt = NULL;
3578	PX86PML4E pPml4eSrc, pPml4eDst;
3579	RTGCPHYS GCPhysPdptSrc;
3580
3581	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3582	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3583
3584	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3585	if (!pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e].n.u1Present)
3586	{
3587	GCPtr += UINT64_C(_2M * 512 * 512);
3588	continue;
3589	}
3590
3591	# if PGM_GST_TYPE == PGM_TYPE_PAE
3592	/* not correct to call pgmPoolGetPage */
3593	# endif
3594	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3595	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3596
3597	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3598	{
3599	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3600	GCPtr += UINT64_C(_2M * 512 * 512);
3601	cErrors++;
3602	continue;
3603	}
3604
3605	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3606	{
3607	AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3608	GCPtr += UINT64_C(_2M * 512 * 512);
3609	cErrors++;
3610	continue;
3611	}
3612
3613	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3614	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3615	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3616	{
3617	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3618	GCPtr += UINT64_C(_2M * 512 * 512);
3619	cErrors++;
3620	continue;
3621	}
3622	# else
3623	{
3624	# endif
3625
3626	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3627	/*
3628	* Check the PDPTEs too.
3629	*/
3630	unsigned iPdpte = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3631
3632	for (;iPdpte <= SHW_PDPT_MASK; iPdpte++)
3633	{
3634	unsigned iPDSrc;
3635	PPGMPOOLPAGE pShwPde = NULL;
3636	PX86PDPE pPdpeDst;
3637	RTGCPHYS GCPhysPdeSrc;
3638	# if PGM_GST_TYPE == PGM_TYPE_PAE
3639	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3640	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc);
3641	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3642	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3643	# else
3644	PX86PML4E pPml4eSrc;
3645	X86PDPE PdpeSrc;
3646	PX86PDPT pPdptDst;
3647	PX86PDPAE pPDDst;
3648	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3649
3650	rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3651	if (rc != VINF_SUCCESS)
3652	{
3653	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3654	GCPtr += 512 * _2M;
3655	continue; /* next PDPTE */
3656	}
3657	Assert(pPDDst);
3658	# endif
3659	Assert(iPDSrc == 0);
3660
3661	pPdpeDst = &pPdptDst->a[iPdpte];
3662
3663	if (!pPdpeDst->n.u1Present)
3664	{
3665	GCPtr += 512 * _2M;
3666	continue; /* next PDPTE */
3667	}
3668
3669	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3670	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3671
3672	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3673	{
3674	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3675	GCPtr += 512 * _2M;
3676	cErrors++;
3677	continue;
3678	}
3679
3680	if (GCPhysPdeSrc != pShwPde->GCPhys)
3681	{
3682	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3683	AssertMsgFailed(("Physical address doesn't match! iPml4e %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3684	# else
3685	AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3686	# endif
3687	GCPtr += 512 * _2M;
3688	cErrors++;
3689	continue;
3690	}
3691
3692	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3693	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3694	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3695	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3696	{
3697	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3698	GCPtr += 512 * _2M;
3699	cErrors++;
3700	continue;
3701	}
3702	# endif
3703
3704	# else
3705	{
3706	# endif
3707	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3708	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3709	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3710	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3711	# else
3712	const PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
3713	# endif
3714	# endif
3715	/*
3716	* Iterate the shadow page directory.
3717	*/
3718	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3719	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3720
3721	for (;
3722	iPDDst < cPDEs;
3723	iPDDst++, GCPtr += ulIncrement)
3724	{
3725	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3726	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3727	{
3728	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3729	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3730	{
3731	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3732	cErrors++;
3733	continue;
3734	}
3735	}
3736	else if ( (PdeDst.u & X86_PDE_P)
3737	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3738	)
3739	{
3740	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3741	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3742	if (!pPoolPage)
3743	{
3744	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3745	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3746	cErrors++;
3747	continue;
3748	}
3749	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3750
3751	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3752	{
3753	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3754	GCPtr, (uint64_t)PdeDst.u));
3755	cErrors++;
3756	}
3757
3758	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3759	{
3760	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3761	GCPtr, (uint64_t)PdeDst.u));
3762	cErrors++;
3763	}
3764
3765	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3766	if (!PdeSrc.n.u1Present)
3767	{
3768	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3769	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3770	cErrors++;
3771	continue;
3772	}
3773
3774	if ( !PdeSrc.b.u1Size
3775	\|\| !fBigPagesSupported)
3776	{
3777	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3778	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3779	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3780	# endif
3781	}
3782	else
3783	{
3784	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3785	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3786	{
3787	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3788	GCPtr, (uint64_t)PdeSrc.u));
3789	cErrors++;
3790	continue;
3791	}
3792	# endif
3793	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3794	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3795	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3796	# endif
3797	}
3798
3799	if ( pPoolPage->enmKind
3800	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3801	{
3802	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3803	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3804	cErrors++;
3805	}
3806
3807	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3808	if (!pPhysPage)
3809	{
3810	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3811	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3812	cErrors++;
3813	continue;
3814	}
3815
3816	if (GCPhysGst != pPoolPage->GCPhys)
3817	{
3818	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3819	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3820	cErrors++;
3821	continue;
3822	}
3823
3824	if ( !PdeSrc.b.u1Size
3825	\|\| !fBigPagesSupported)
3826	{
3827	/*
3828	* Page Table.
3829	*/
3830	const GSTPT *pPTSrc;
3831	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3832	if (VBOX_FAILURE(rc))
3833	{
3834	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3835	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3836	cErrors++;
3837	continue;
3838	}
3839	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3840	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3841	{
3842	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3843	// (This problem will go away when/if we shadow multiple CR3s.)
3844	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3845	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3846	cErrors++;
3847	continue;
3848	}
3849	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3850	{
3851	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3852	GCPtr, (uint64_t)PdeDst.u));
3853	cErrors++;
3854	continue;
3855	}
3856
3857	/* iterate the page table. */
3858	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3859	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3860	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3861	# else
3862	const unsigned offPTSrc = 0;
3863	# endif
3864	for (unsigned iPT = 0, off = 0;
3865	iPT < ELEMENTS(pPTDst->a);
3866	iPT++, off += PAGE_SIZE)
3867	{
3868	const SHWPTE PteDst = pPTDst->a[iPT];
3869
3870	/* skip not-present entries. */
3871	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3872	continue;
3873	Assert(PteDst.n.u1Present);
3874
3875	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3876	if (!PteSrc.n.u1Present)
3877	{
3878	# ifdef IN_RING3
3879	PGMAssertHandlerAndFlagsInSync(pVM);
3880	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3881	# endif
3882	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3883	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3884	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3885	cErrors++;
3886	continue;
3887	}
3888
3889	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3890	# if 1 /** @todo sync accessed bit properly... */
3891	fIgnoreFlags \|= X86_PTE_A;
3892	# endif
3893
3894	/* match the physical addresses */
3895	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3896	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3897
3898	# ifdef IN_RING3
3899	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3900	if (VBOX_FAILURE(rc))
3901	{
3902	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3903	{
3904	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3905	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3906	cErrors++;
3907	continue;
3908	}
3909	}
3910	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3911	{
3912	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3913	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3914	cErrors++;
3915	continue;
3916	}
3917	# endif
3918
3919	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3920	if (!pPhysPage)
3921	{
3922	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3923	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3924	{
3925	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3926	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3927	cErrors++;
3928	continue;
3929	}
3930	# endif
3931	if (PteDst.n.u1Write)
3932	{
3933	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3934	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3935	cErrors++;
3936	}
3937	fIgnoreFlags \|= X86_PTE_RW;
3938	}
3939	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3940	{
3941	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3942	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3943	cErrors++;
3944	continue;
3945	}
3946
3947	/* flags */
3948	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3949	{
3950	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3951	{
3952	if (PteDst.n.u1Write)
3953	{
3954	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3955	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3956	cErrors++;
3957	continue;
3958	}
3959	fIgnoreFlags \|= X86_PTE_RW;
3960	}
3961	else
3962	{
3963	if (PteDst.n.u1Present)
3964	{
3965	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3966	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3967	cErrors++;
3968	continue;
3969	}
3970	fIgnoreFlags \|= X86_PTE_P;
3971	}
3972	}
3973	else
3974	{
3975	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3976	{
3977	if (PteDst.n.u1Write)
3978	{
3979	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3980	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3981	cErrors++;
3982	continue;
3983	}
3984	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3985	{
3986	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3987	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3988	cErrors++;
3989	continue;
3990	}
3991	if (PteDst.n.u1Dirty)
3992	{
3993	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3994	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3995	cErrors++;
3996	}
3997	# if 0 /** @todo sync access bit properly... */
3998	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3999	{
4000	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4001	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4002	cErrors++;
4003	}
4004	fIgnoreFlags \|= X86_PTE_RW;
4005	# else
4006	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4007	# endif
4008	}
4009	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4010	{
4011	/* access bit emulation (not implemented). */
4012	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4013	{
4014	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4015	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4016	cErrors++;
4017	continue;
4018	}
4019	if (!PteDst.n.u1Accessed)
4020	{
4021	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4022	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4023	cErrors++;
4024	}
4025	fIgnoreFlags \|= X86_PTE_P;
4026	}
4027	# ifdef DEBUG_sandervl
4028	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4029	# endif
4030	}
4031
4032	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4033	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4034	)
4035	{
4036	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4037	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4038	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4039	cErrors++;
4040	continue;
4041	}
4042	} /* foreach PTE */
4043	}
4044	else
4045	{
4046	/*
4047	* Big Page.
4048	*/
4049	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4050	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4051	{
4052	if (PdeDst.n.u1Write)
4053	{
4054	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4055	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4056	cErrors++;
4057	continue;
4058	}
4059	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4060	{
4061	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4062	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4063	cErrors++;
4064	continue;
4065	}
4066	# if 0 /** @todo sync access bit properly... */
4067	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4068	{
4069	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4070	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4071	cErrors++;
4072	}
4073	fIgnoreFlags \|= X86_PTE_RW;
4074	# else
4075	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4076	# endif
4077	}
4078	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4079	{
4080	/* access bit emulation (not implemented). */
4081	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4082	{
4083	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4084	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4085	cErrors++;
4086	continue;
4087	}
4088	if (!PdeDst.n.u1Accessed)
4089	{
4090	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4091	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4092	cErrors++;
4093	}
4094	fIgnoreFlags \|= X86_PTE_P;
4095	}
4096
4097	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4098	{
4099	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4100	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4101	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4102	cErrors++;
4103	}
4104
4105	/* iterate the page table. */
4106	for (unsigned iPT = 0, off = 0;
4107	iPT < ELEMENTS(pPTDst->a);
4108	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4109	{
4110	const SHWPTE PteDst = pPTDst->a[iPT];
4111
4112	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4113	{
4114	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4115	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4116	cErrors++;
4117	}
4118
4119	/* skip not-present entries. */
4120	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4121	continue;
4122
4123	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4124
4125	/* match the physical addresses */
4126	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4127
4128	# ifdef IN_RING3
4129	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4130	if (VBOX_FAILURE(rc))
4131	{
4132	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4133	{
4134	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4135	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4136	cErrors++;
4137	}
4138	}
4139	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4140	{
4141	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4142	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4143	cErrors++;
4144	continue;
4145	}
4146	# endif
4147	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4148	if (!pPhysPage)
4149	{
4150	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4151	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4152	{
4153	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4154	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4155	cErrors++;
4156	continue;
4157	}
4158	# endif
4159	if (PteDst.n.u1Write)
4160	{
4161	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4162	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4163	cErrors++;
4164	}
4165	fIgnoreFlags \|= X86_PTE_RW;
4166	}
4167	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4168	{
4169	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4170	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4171	cErrors++;
4172	continue;
4173	}
4174
4175	/* flags */
4176	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4177	{
4178	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4179	{
4180	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4181	{
4182	if (PteDst.n.u1Write)
4183	{
4184	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4185	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4186	cErrors++;
4187	continue;
4188	}
4189	fIgnoreFlags \|= X86_PTE_RW;
4190	}
4191	}
4192	else
4193	{
4194	if (PteDst.n.u1Present)
4195	{
4196	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4197	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4198	cErrors++;
4199	continue;
4200	}
4201	fIgnoreFlags \|= X86_PTE_P;
4202	}
4203	}
4204
4205	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4206	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4207	)
4208	{
4209	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4210	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4211	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4212	cErrors++;
4213	continue;
4214	}
4215	} /* for each PTE */
4216	}
4217	}
4218	/* not present */
4219
4220	} /* for each PDE */
4221
4222	} /* for each PDPTE */
4223
4224	} /* for each PML4E */
4225
4226	# ifdef DEBUG
4227	if (cErrors)
4228	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4229	# endif
4230
4231	#endif
4232	return cErrors;
4233
4234	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
4235	}
4236	#endif /* VBOX_STRICT */
4237

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 9966

Download in other formats: