VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 18646

Last change on this file since 18646 was 17586, checked in by vboxsync, 16 years ago

Removed all dead non-VBOX_WITH_PGMPOOL_PAGING_ONLY code.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 18.5 KB
Line 
1/* $Id: PGMAllGst.h 17586 2009-03-09 15:28:25Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Guest Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Internal Functions *
25*******************************************************************************/
26__BEGIN_DECLS
27PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
28PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
29PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE);
30PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
31__END_DECLS
32
33
34
35/**
36 * Gets effective Guest OS page information.
37 *
38 * When GCPtr is in a big page, the function will return as if it was a normal
39 * 4KB page. If the need for distinguishing between big and normal page becomes
40 * necessary at a later point, a PGMGstGetPage Ex() will be created for that
41 * purpose.
42 *
43 * @returns VBox status.
44 * @param pVM VM Handle.
45 * @param GCPtr Guest Context virtual address of the page. Page aligned!
46 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
47 * @param pGCPhys Where to store the GC physical address of the page.
48 * This is page aligned. The fact that the
49 */
50PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
51{
52#if PGM_GST_TYPE == PGM_TYPE_REAL \
53 || PGM_GST_TYPE == PGM_TYPE_PROT
54 /*
55 * Fake it.
56 */
57 if (pfFlags)
58 *pfFlags = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
59 if (pGCPhys)
60 *pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
61 return VINF_SUCCESS;
62
63#elif PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
64
65 /*
66 * Get the PDE.
67 */
68# if PGM_GST_TYPE == PGM_TYPE_32BIT
69 X86PDE Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
70
71#elif PGM_GST_TYPE == PGM_TYPE_PAE
72 /* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present.
73 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx). */
74 X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
75 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
76
77#elif PGM_GST_TYPE == PGM_TYPE_AMD64
78 PX86PML4E pPml4e;
79 X86PDPE Pdpe;
80 X86PDEPAE Pde = pgmGstGetLongModePDEEx(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
81 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
82
83 Assert(pPml4e);
84 if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
85 return VERR_PAGE_TABLE_NOT_PRESENT;
86
87 /* Merge accessed, write, user and no-execute bits into the PDE. */
88 Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
89 Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
90 Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
91 Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
92# endif
93
94 /*
95 * Lookup the page.
96 */
97 if (!Pde.n.u1Present)
98 return VERR_PAGE_TABLE_NOT_PRESENT;
99
100 if ( !Pde.b.u1Size
101# if PGM_GST_TYPE != PGM_TYPE_AMD64
102 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
103# endif
104 )
105 {
106 PGSTPT pPT;
107 int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
108 if (RT_FAILURE(rc))
109 return rc;
110
111 /*
112 * Get PT entry and check presence.
113 */
114 const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
115 if (!Pte.n.u1Present)
116 return VERR_PAGE_NOT_PRESENT;
117
118 /*
119 * Store the result.
120 * RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
121 * where the PDPE is simplified.
122 */
123 if (pfFlags)
124 {
125 *pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
126 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
127# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
128 /* The NX bit is determined by a bitwise OR between the PT and PD */
129 if (fNoExecuteBitValid)
130 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
131# endif
132 }
133 if (pGCPhys)
134 *pGCPhys = Pte.u & GST_PTE_PG_MASK;
135 }
136 else
137 {
138 /*
139 * Map big to 4k PTE and store the result
140 */
141 if (pfFlags)
142 {
143 *pfFlags = (Pde.u & ~(GST_PTE_PG_MASK | X86_PTE_PAT))
144 | ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
145# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
146 /* The NX bit is determined by a bitwise OR between the PT and PD */
147 if (fNoExecuteBitValid)
148 *pfFlags |= (Pde.u & X86_PTE_PAE_NX);
149# endif
150 }
151 if (pGCPhys)
152 *pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) | (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
153 }
154 return VINF_SUCCESS;
155#else
156# error "shouldn't be here!"
157 /* something else... */
158 return VERR_NOT_SUPPORTED;
159#endif
160}
161
162
163/**
164 * Modify page flags for a range of pages in the guest's tables
165 *
166 * The existing flags are ANDed with the fMask and ORed with the fFlags.
167 *
168 * @returns VBox status code.
169 * @param pVM VM handle.
170 * @param GCPtr Virtual address of the first page in the range. Page aligned!
171 * @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
172 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
173 * @param fMask The AND mask - page flags X86_PTE_*.
174 */
175PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
176{
177#if PGM_GST_TYPE == PGM_TYPE_32BIT \
178 || PGM_GST_TYPE == PGM_TYPE_PAE \
179 || PGM_GST_TYPE == PGM_TYPE_AMD64
180
181 for (;;)
182 {
183 /*
184 * Get the PD entry.
185 */
186# if PGM_GST_TYPE == PGM_TYPE_32BIT
187 PX86PDE pPde = pgmGstGet32bitPDEPtr(&pVM->pgm.s, GCPtr);
188
189# elif PGM_GST_TYPE == PGM_TYPE_PAE
190 /* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
191 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
192 */
193 PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
194 Assert(pPde);
195 if (!pPde)
196 return VERR_PAGE_TABLE_NOT_PRESENT;
197# elif PGM_GST_TYPE == PGM_TYPE_AMD64
198 /** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
199 PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
200 Assert(pPde);
201 if (!pPde)
202 return VERR_PAGE_TABLE_NOT_PRESENT;
203# endif
204 GSTPDE Pde = *pPde;
205 Assert(Pde.n.u1Present);
206 if (!Pde.n.u1Present)
207 return VERR_PAGE_TABLE_NOT_PRESENT;
208
209 if ( !Pde.b.u1Size
210# if PGM_GST_TYPE != PGM_TYPE_AMD64
211 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
212# endif
213 )
214 {
215 /*
216 * 4KB Page table
217 *
218 * Walk page tables and pages till we're done.
219 */
220 PGSTPT pPT;
221 int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
222 if (RT_FAILURE(rc))
223 return rc;
224
225 unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
226 while (iPTE < RT_ELEMENTS(pPT->a))
227 {
228 GSTPTE Pte = pPT->a[iPTE];
229 Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK))
230 | (fFlags & ~GST_PTE_PG_MASK);
231 pPT->a[iPTE] = Pte;
232
233 /* next page */
234 cb -= PAGE_SIZE;
235 if (!cb)
236 return VINF_SUCCESS;
237 GCPtr += PAGE_SIZE;
238 iPTE++;
239 }
240 }
241 else
242 {
243 /*
244 * 4MB Page table
245 */
246# if PGM_GST_TYPE == PGM_TYPE_32BIT
247 Pde.u = (Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PG_HIGH_MASK | X86_PDE4M_PS))
248# else
249 Pde.u = (Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PS))
250# endif
251 | (fFlags & ~GST_PTE_PG_MASK)
252 | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
253 *pPde = Pde;
254
255 /* advance */
256 const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
257 if (cbDone >= cb)
258 return VINF_SUCCESS;
259 cb -= cbDone;
260 GCPtr += cbDone;
261 }
262 }
263
264#else
265 /* real / protected mode: ignore. */
266 return VINF_SUCCESS;
267#endif
268}
269
270
271/**
272 * Retrieve guest PDE information
273 *
274 * @returns VBox status code.
275 * @param pVM The virtual machine.
276 * @param GCPtr Guest context pointer
277 * @param pPDE Pointer to guest PDE structure
278 */
279PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE)
280{
281#if PGM_GST_TYPE == PGM_TYPE_32BIT \
282 || PGM_GST_TYPE == PGM_TYPE_PAE \
283 || PGM_GST_TYPE == PGM_TYPE_AMD64
284
285# if PGM_GST_TYPE == PGM_TYPE_32BIT
286 X86PDE Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
287# elif PGM_GST_TYPE == PGM_TYPE_PAE
288 X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
289# elif PGM_GST_TYPE == PGM_TYPE_AMD64
290 X86PDEPAE Pde = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
291# endif
292
293 pPDE->u = (X86PGPAEUINT)Pde.u;
294 return VINF_SUCCESS;
295#else
296 AssertFailed();
297 return VERR_NOT_IMPLEMENTED;
298#endif
299}
300
301
302#if PGM_GST_TYPE == PGM_TYPE_32BIT \
303 || PGM_GST_TYPE == PGM_TYPE_PAE \
304 || PGM_GST_TYPE == PGM_TYPE_AMD64
305/**
306 * Updates one virtual handler range.
307 *
308 * @returns 0
309 * @param pNode Pointer to a PGMVIRTHANDLER.
310 * @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
311 */
312static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
313{
314 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
315 PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
316 Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
317
318#if PGM_GST_TYPE == PGM_TYPE_32BIT
319 PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pState->pVM->pgm.s);
320#endif
321
322 RTGCPTR GCPtr = pCur->Core.Key;
323#if PGM_GST_MODE != PGM_MODE_AMD64
324 /* skip all stuff above 4GB if not AMD64 mode. */
325 if (GCPtr >= _4GB)
326 return 0;
327#endif
328
329 unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
330 unsigned iPage = 0;
331 while (iPage < pCur->cPages)
332 {
333#if PGM_GST_TYPE == PGM_TYPE_32BIT
334 X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
335#elif PGM_GST_TYPE == PGM_TYPE_PAE
336 X86PDEPAE Pde = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
337#elif PGM_GST_TYPE == PGM_TYPE_AMD64
338 X86PDEPAE Pde = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
339#endif
340 if (Pde.n.u1Present)
341 {
342 if ( !Pde.b.u1Size
343# if PGM_GST_TYPE != PGM_TYPE_AMD64
344 || !(pState->cr4 & X86_CR4_PSE)
345# endif
346 )
347 {
348 /*
349 * Normal page table.
350 */
351 PGSTPT pPT;
352 int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
353 if (RT_SUCCESS(rc))
354 {
355 for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
356 iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
357 iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
358 {
359 GSTPTE Pte = pPT->a[iPTE];
360 RTGCPHYS GCPhysNew;
361 if (Pte.n.u1Present)
362 GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
363 else
364 GCPhysNew = NIL_RTGCPHYS;
365 if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
366 {
367 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
368 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
369#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
370 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
371 ("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
372 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
373 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
374#endif
375 pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
376 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
377 }
378 }
379 }
380 else
381 {
382 /* not-present. */
383 offPage = 0;
384 AssertRC(rc);
385 for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
386 iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
387 iPTE++, iPage++, GCPtr += PAGE_SIZE)
388 {
389 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
390 {
391 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
392#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
393 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
394 ("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
395 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
396 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
397#endif
398 pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
399 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
400 }
401 }
402 }
403 }
404 else
405 {
406 /*
407 * 2/4MB page.
408 */
409 RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
410 for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
411 i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
412 i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
413 {
414 RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
415 if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
416 {
417 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
418 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
419#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
420 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
421 ("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
422 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
423 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
424#endif
425 pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
426 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
427 }
428 }
429 } /* pde type */
430 }
431 else
432 {
433 /* not-present. */
434 for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
435 cPages && iPage < pCur->cPages;
436 iPage++, GCPtr += PAGE_SIZE)
437 {
438 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
439 {
440 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
441 pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
442 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
443 }
444 }
445 offPage = 0;
446 }
447 } /* for pages in virtual mapping. */
448
449 return 0;
450}
451#endif /* 32BIT, PAE and AMD64 */
452
453
454/**
455 * Updates the virtual page access handlers.
456 *
457 * @returns true if bits were flushed.
458 * @returns false if bits weren't flushed.
459 * @param pVM VM handle.
460 * @param pPDSrc The page directory.
461 * @param cr4 The cr4 register value.
462 */
463PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
464{
465#if PGM_GST_TYPE == PGM_TYPE_32BIT \
466 || PGM_GST_TYPE == PGM_TYPE_PAE \
467 || PGM_GST_TYPE == PGM_TYPE_AMD64
468
469 /** @todo
470 * In theory this is not sufficient: the guest can change a single page in a range with invlpg
471 */
472
473 /*
474 * Resolve any virtual address based access handlers to GC physical addresses.
475 * This should be fairly quick.
476 */
477 PGMHVUSTATE State;
478
479 pgmLock(pVM);
480 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
481 State.pVM = pVM;
482 State.fTodo = pVM->pgm.s.fSyncFlags;
483 State.cr4 = cr4;
484 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
485 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
486
487
488 /*
489 * Set / reset bits?
490 */
491 if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
492 {
493 STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
494 Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
495 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
496 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
497 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
498 }
499 pgmUnlock(pVM);
500
501 return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
502
503#else /* real / protected */
504 return false;
505#endif
506}
507
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette