PGMAllGst.h@ 92561

Last change on this file since 92561 was 92459, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Comment nit.
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1	/* $Id: PGMAllGst.h 92459 2021-11-16 13:21:57Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Internal Functions *
21	*********************************************************************************************************************************/
22	RT_C_DECLS_BEGIN
23	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
24	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
25	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
26	DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PGSTPTWALK pGstWalk);
27	#endif
28	PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
29	PGM_GST_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
30
31	#ifdef IN_RING3 /* r3 only for now. */
32	PGM_GST_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
33	PGM_GST_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
34	PGM_GST_DECL(int, Exit)(PVMCPUCC pVCpu);
35	#endif
36	RT_C_DECLS_END
37
38
39	/**
40	* Enters the guest mode.
41	*
42	* @returns VBox status code.
43	* @param pVCpu The cross context virtual CPU structure.
44	* @param GCPhysCR3 The physical address from the CR3 register.
45	*/
46	PGM_GST_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
47	{
48	/*
49	* Map and monitor CR3
50	*/
51	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
52	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
53	AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
54	return g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3, false /* fPdpesMapped */);
55	}
56
57
58	/**
59	* Exits the guest mode.
60	*
61	* @returns VBox status code.
62	* @param pVCpu The cross context virtual CPU structure.
63	*/
64	PGM_GST_DECL(int, Exit)(PVMCPUCC pVCpu)
65	{
66	uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
67	AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
68	AssertReturn(g_aPgmBothModeData[idxBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
69	return g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
70	}
71
72
73	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
74	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
75	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
76
77
78	DECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel)
79	{
80	NOREF(iLevel); NOREF(pVCpu);
81	pWalk->fNotPresent = true;
82	pWalk->uLevel = (uint8_t)iLevel;
83	return VERR_PAGE_TABLE_NOT_PRESENT;
84	}
85
86	DECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel, int rc)
87	{
88	AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
89	pWalk->fBadPhysAddr = true;
90	pWalk->uLevel = (uint8_t)iLevel;
91	return VERR_PAGE_TABLE_NOT_PRESENT;
92	}
93
94	DECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, int iLevel)
95	{
96	NOREF(pVCpu);
97	pWalk->fRsvdError = true;
98	pWalk->uLevel = (uint8_t)iLevel;
99	return VERR_PAGE_TABLE_NOT_PRESENT;
100	}
101
102
103	/**
104	* Performs a guest page table walk.
105	*
106	* @returns VBox status code.
107	* @retval VINF_SUCCESS on success.
108	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
109	*
110	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
111	* @param GCPtr The guest virtual address to walk by.
112	* @param pWalk The common page walk information.
113	* @param pGstWalk The guest mode specific page walk information.
114	*
115	* @warning Callers must initialize @a pWalk and @a pGstWalk before calling this
116	* function.
117	*/
118	DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PGSTPTWALK pGstWalk)
119	{
120	int rc;
121
122	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
123	/** @def PGM_GST_SLAT_WALK
124	* Macro to perform guest second-level address translation (EPT or Nested).
125	*
126	* @param a_pVCpu The cross context virtual CPU structure of the calling
127	* EMT.
128	* @param a_GCPtrNested The nested-guest linear address that caused the
129	* second-level translation.
130	* @param a_GCPhysNested The nested-guest physical address to translate.
131	* @param a_GCPhysOut Where to store the guest-physical address (result).
132	*/
133	# define PGM_GST_SLAT_WALK(a_pVCpu, a_GCPtrNested, a_GCPhysNested, a_GCPhysOut, a_pWalk) \
134	do { \
135	if ((a_pVCpu)->pgm.s.enmGuestSlatMode != PGMSLAT_DIRECT) \
136	{ \
137	PGMPTWALK SlatWalk; \
138	PGMPTWALKGST SlatGstWalk; \
139	int const rcX = pgmGstSlatWalk(a_pVCpu, a_GCPhysNested, true /* fIsLinearAddrValid */, a_GCPtrNested, &SlatWalk, \
140	&SlatGstWalk); \
141	if (RT_SUCCESS(rcX)) \
142	(a_GCPhysOut) = SlatWalk.GCPhys; \
143	else \
144	{ \
145	*(a_pWalk) = SlatWalk; \
146	return rcX; \
147	} \
148	} \
149	} while (0)
150	#endif
151
152	/*
153	* Init the walking structures.
154	*/
155	RT_ZERO(*pWalk);
156	RT_ZERO(*pGstWalk);
157	pWalk->GCPtr = GCPtr;
158
159	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
160	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
161	/*
162	* Boundary check for PAE and 32-bit (prevents trouble further down).
163	*/
164	if (RT_UNLIKELY(GCPtr >= _4G))
165	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
166	# endif
167
168	uint64_t fEffective;
169	{
170	# if PGM_GST_TYPE == PGM_TYPE_AMD64
171	/*
172	* The PML4 table.
173	*/
174	rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pGstWalk->pPml4);
175	if (RT_SUCCESS(rc)) { /* probable */ }
176	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
177
178	PX86PML4E pPml4e;
179	pGstWalk->pPml4e = pPml4e = &pGstWalk->pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
180	X86PML4E Pml4e;
181	pGstWalk->Pml4e.u = Pml4e.u = pPml4e->u;
182
183	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
184	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
185
186	if (RT_LIKELY(GST_IS_PML4E_VALID(pVCpu, Pml4e))) { /* likely */ }
187	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
188
189	pWalk->fEffective = fEffective = Pml4e.u & ( X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_PWT
190	\| X86_PML4E_PCD \| X86_PML4E_A \| X86_PML4E_NX);
191
192	/*
193	* The PDPT.
194	*/
195	RTGCPHYS GCPhysPdpt = Pml4e.u & X86_PML4E_PG_MASK;
196	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
197	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPdpt, GCPhysPdpt, pWalk);
198	#endif
199	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPdpt, &pGstWalk->pPdpt);
200	if (RT_SUCCESS(rc)) { /* probable */ }
201	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
202
203	# elif PGM_GST_TYPE == PGM_TYPE_PAE
204	rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pGstWalk->pPdpt);
205	if (RT_SUCCESS(rc)) { /* probable */ }
206	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
207	#endif
208	}
209	{
210	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
211	PX86PDPE pPdpe;
212	pGstWalk->pPdpe = pPdpe = &pGstWalk->pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
213	X86PDPE Pdpe;
214	pGstWalk->Pdpe.u = Pdpe.u = pPdpe->u;
215
216	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pdpe)) { /* probable */ }
217	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
218
219	if (RT_LIKELY(GST_IS_PDPE_VALID(pVCpu, Pdpe))) { /* likely */ }
220	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
221
222	# if PGM_GST_TYPE == PGM_TYPE_AMD64
223	pWalk->fEffective = fEffective &= (Pdpe.u & ( X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US
224	\| X86_PDPE_PWT \| X86_PDPE_PCD \| X86_PDPE_A))
225	\| (Pdpe.u & X86_PDPE_LM_NX);
226	# else
227	/* NX in the legacy-mode PAE PDPE is reserved. The valid check above ensures the NX bit is not set. */
228	pWalk->fEffective = fEffective = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A
229	\| (Pdpe.u & (X86_PDPE_PWT \| X86_PDPE_PCD));
230	# endif
231
232	/*
233	* The PD.
234	*/
235	RTGCPHYS GCPhysPd = Pdpe.u & X86_PDPE_PG_MASK;
236	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
237	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPd, GCPhysPd, pWalk);
238	# endif
239	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPd, &pGstWalk->pPd);
240	if (RT_SUCCESS(rc)) { /* probable */ }
241	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
242
243	# elif PGM_GST_TYPE == PGM_TYPE_32BIT
244	rc = pgmGstGet32bitPDPtrEx(pVCpu, &pGstWalk->pPd);
245	if (RT_SUCCESS(rc)) { /* probable */ }
246	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
247	# endif
248	}
249	{
250	PGSTPDE pPde;
251	pGstWalk->pPde = pPde = &pGstWalk->pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
252	GSTPDE Pde;
253	pGstWalk->Pde.u = Pde.u = pPde->u;
254	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
255	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
256	if ((Pde.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
257	{
258	if (RT_LIKELY(GST_IS_BIG_PDE_VALID(pVCpu, Pde))) { /* likely */ }
259	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
260
261	/*
262	* We're done.
263	*/
264	# if PGM_GST_TYPE == PGM_TYPE_32BIT
265	fEffective = Pde.u & (X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PWT \| X86_PDE4M_PCD \| X86_PDE4M_A);
266	# else
267	fEffective &= (Pde.u & (X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PWT \| X86_PDE4M_PCD \| X86_PDE4M_A))
268	\| (Pde.u & X86_PDE2M_PAE_NX);
269	# endif
270	fEffective \|= Pde.u & (X86_PDE4M_D \| X86_PDE4M_G);
271	fEffective \|= (Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT;
272	pWalk->fEffective = fEffective;
273	Assert(GST_IS_NX_ACTIVE(pVCpu) \|\| !(fEffective & PGM_PTATTRS_NX_MASK));
274	Assert(fEffective & PGM_PTATTRS_R_MASK);
275
276	pWalk->fBigPage = true;
277	pWalk->fSucceeded = true;
278	RTGCPHYS GCPhysPde = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
279	\| (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
280	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
281	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPde, GCPhysPde, pWalk);
282	# endif
283	pWalk->GCPhys = GCPhysPde;
284	PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
285	return VINF_SUCCESS;
286	}
287
288	if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
289	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
290	# if PGM_GST_TYPE == PGM_TYPE_32BIT
291	pWalk->fEffective = fEffective = Pde.u & ( X86_PDE_P \| X86_PDE_RW \| X86_PDE_US
292	\| X86_PDE_PWT \| X86_PDE_PCD \| X86_PDE_A);
293	# else
294	pWalk->fEffective = fEffective &= (Pde.u & ( X86_PDE_P \| X86_PDE_RW \| X86_PDE_US
295	\| X86_PDE_PWT \| X86_PDE_PCD \| X86_PDE_A))
296	\| (Pde.u & X86_PDE_PAE_NX);
297	# endif
298
299	/*
300	* The PT.
301	*/
302	RTGCPHYS GCPhysPt = GST_GET_PDE_GCPHYS(Pde);
303	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
304	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPt, GCPhysPt, pWalk);
305	# endif
306	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pGstWalk->pPt);
307	if (RT_SUCCESS(rc)) { /* probable */ }
308	else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
309	}
310	{
311	PGSTPTE pPte;
312	pGstWalk->pPte = pPte = &pGstWalk->pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
313	GSTPTE Pte;
314	pGstWalk->Pte.u = Pte.u = pPte->u;
315
316	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
317	else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
318
319	if (RT_LIKELY(GST_IS_PTE_VALID(pVCpu, Pte))) { /* likely */ }
320	else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
321
322	/*
323	* We're done.
324	*/
325	# if PGM_GST_TYPE == PGM_TYPE_32BIT
326	fEffective &= Pte.u & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A);
327	# else
328	fEffective &= (Pte.u & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_A))
329	\| (Pte.u & X86_PTE_PAE_NX);
330	# endif
331	fEffective \|= Pte.u & (X86_PTE_D \| X86_PTE_PAT \| X86_PTE_G);
332	pWalk->fEffective = fEffective;
333	Assert(GST_IS_NX_ACTIVE(pVCpu) \|\| !(fEffective & PGM_PTATTRS_NX_MASK));
334	Assert(fEffective & PGM_PTATTRS_R_MASK);
335
336	pWalk->fSucceeded = true;
337	RTGCPHYS GCPhysPte = GST_GET_PTE_GCPHYS(Pte)
338	\| (GCPtr & PAGE_OFFSET_MASK);
339	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
340	PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPte, GCPhysPte, pWalk);
341	# endif
342	pWalk->GCPhys = GCPhysPte;
343	return VINF_SUCCESS;
344	}
345	}
346
347	#endif /* 32BIT, PAE, AMD64 */
348
349	/**
350	* Gets effective Guest OS page information.
351	*
352	* When GCPtr is in a big page, the function will return as if it was a normal
353	* 4KB page. If the need for distinguishing between big and normal page becomes
354	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
355	* purpose.
356	*
357	* @returns VBox status code.
358	* @param pVCpu The cross context virtual CPU structure.
359	* @param GCPtr Guest Context virtual address of the page.
360	* @param pWalk Where to store the page walk info.
361	*/
362	PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk)
363	{
364	#if PGM_GST_TYPE == PGM_TYPE_REAL \
365	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
366	/*
367	* Fake it.
368	*/
369	RT_ZERO(*pWalk);
370	pWalk->fSucceeded = true;
371	pWalk->GCPtr = GCPtr;
372	pWalk->GCPhys = GCPtr & PAGE_BASE_GC_MASK;
373	pWalk->fEffective = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
374	pWalk->GCPhys = GCPtr & PAGE_BASE_GC_MASK;
375	NOREF(pVCpu);
376	return VINF_SUCCESS;
377
378	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
379	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
380	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
381
382	PGMPTWALK Walk;
383	GSTPTWALK GstWalk;
384	RT_ZERO(Walk);
385	RT_ZERO(GstWalk);
386	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk, &GstWalk);
387	if (RT_FAILURE(rc))
388	return rc;
389
390	uint64_t fFlags;
391	if (!Walk.fBigPage)
392	fFlags = (GstWalk.Pte.u & ~(GST_PTE_PG_MASK \| X86_PTE_RW \| X86_PTE_US)) /* NX not needed */
393	\| (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK))
394	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
395	\| (Walk.fEffective & PGM_PTATTRS_NX_MASK)
396	# endif
397	;
398	else
399	{
400	fFlags = (GstWalk.Pde.u & ~(GST_PTE_PG_MASK \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PS)) /* NX not needed */
401	\| (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK \| PGM_PTATTRS_PAT_MASK))
402	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
403	\| (Walk.fEffective & PGM_PTATTRS_NX_MASK)
404	# endif
405	;
406	}
407
408	pWalk->fSucceeded = true;
409	pWalk->GCPtr = GCPtr;
410	pWalk->GCPhys = Walk.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
411	pWalk->fEffective = fFlags;
412	return VINF_SUCCESS;
413
414	#else
415	# error "shouldn't be here!"
416	/* something else... */
417	return VERR_NOT_SUPPORTED;
418	#endif
419	}
420
421
422	/**
423	* Modify page flags for a range of pages in the guest's tables
424	*
425	* The existing flags are ANDed with the fMask and ORed with the fFlags.
426	*
427	* @returns VBox status code.
428	* @param pVCpu The cross context virtual CPU structure.
429	* @param GCPtr Virtual address of the first page in the range. Page aligned!
430	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
431	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
432	* @param fMask The AND mask - page flags X86_PTE_*.
433	*/
434	PGM_GST_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
435	{
436	Assert((cb & PAGE_OFFSET_MASK) == 0); RT_NOREF_PV(cb);
437
438	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
439	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
440	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
441	for (;;)
442	{
443	PGMPTWALK Walk;
444	GSTPTWALK GstWalk;
445	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk, &GstWalk);
446	if (RT_FAILURE(rc))
447	return rc;
448
449	if (!Walk.fBigPage)
450	{
451	/*
452	* 4KB Page table, process
453	*
454	* Walk pages till we're done.
455	*/
456	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
457	while (iPTE < RT_ELEMENTS(GstWalk.pPt->a))
458	{
459	GSTPTE Pte = GstWalk.pPt->a[iPTE];
460	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
461	\| (fFlags & ~GST_PTE_PG_MASK);
462	GstWalk.pPt->a[iPTE] = Pte;
463
464	/* next page */
465	cb -= PAGE_SIZE;
466	if (!cb)
467	return VINF_SUCCESS;
468	GCPtr += PAGE_SIZE;
469	iPTE++;
470	}
471	}
472	else
473	{
474	/*
475	* 2/4MB Page table
476	*/
477	GSTPDE PdeNew;
478	# if PGM_GST_TYPE == PGM_TYPE_32BIT
479	PdeNew.u = (GstWalk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
480	# else
481	PdeNew.u = (GstWalk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
482	# endif
483	\| (fFlags & ~GST_PTE_PG_MASK)
484	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
485	*GstWalk.pPde = PdeNew;
486
487	/* advance */
488	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
489	if (cbDone >= cb)
490	return VINF_SUCCESS;
491	cb -= cbDone;
492	GCPtr += cbDone;
493	}
494	}
495
496	#else
497	/* real / protected mode: ignore. */
498	NOREF(pVCpu); NOREF(GCPtr); NOREF(fFlags); NOREF(fMask);
499	return VINF_SUCCESS;
500	#endif
501	}
502
503
504	#ifdef IN_RING3
505	/**
506	* Relocate any GC pointers related to guest mode paging.
507	*
508	* @returns VBox status code.
509	* @param pVCpu The cross context virtual CPU structure.
510	* @param offDelta The relocation offset.
511	*/
512	PGM_GST_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta)
513	{
514	RT_NOREF(pVCpu, offDelta);
515	return VINF_SUCCESS;
516	}
517	#endif

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 92561

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