PGMAllGst.h@ 12967

Last change on this file since 12967 was 12932, checked in by vboxsync, 16 years ago
Paging updates in preparation for EPT.
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1	/* $Id: PGMAllGst.h 12932 2008-10-02 11:48:49Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48	#undef GST_PDPE_PG_MASK
49	#undef GST_GET_PDE_BIG_PG_GCPHYS
50
51	#if PGM_GST_TYPE == PGM_TYPE_REAL \
52	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
53	# define GSTPT SHWPT
54	# define PGSTPT PSHWPT
55	# define GSTPTE SHWPTE
56	# define PGSTPTE PSHWPTE
57	# define GSTPD SHWPD
58	# define PGSTPD PSHWPD
59	# define GSTPDE SHWPDE
60	# define PGSTPDE PSHWPDE
61	# define GST_PTE_PG_MASK SHW_PTE_PG_MASK
62	#elif PGM_GST_TYPE == PGM_TYPE_32BIT
63	# define GSTPT X86PT
64	# define PGSTPT PX86PT
65	# define GSTPTE X86PTE
66	# define PGSTPTE PX86PTE
67	# define GSTPD X86PD
68	# define PGSTPD PX86PD
69	# define GSTPDE X86PDE
70	# define PGSTPDE PX86PDE
71	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
72	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
73	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
74	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
75	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
76	# define GST_PD_SHIFT X86_PD_SHIFT
77	# define GST_PD_MASK X86_PD_MASK
78	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
79	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
80	# define GST_PT_SHIFT X86_PT_SHIFT
81	# define GST_PT_MASK X86_PT_MASK
82	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
83	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
84	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
85	# define GSTPT X86PTPAE
86	# define PGSTPT PX86PTPAE
87	# define GSTPTE X86PTEPAE
88	# define PGSTPTE PX86PTEPAE
89	# define GSTPD X86PDPAE
90	# define PGSTPD PX86PDPAE
91	# define GSTPDE X86PDEPAE
92	# define PGSTPDE PX86PDEPAE
93	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
94	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
95	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
96	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
97	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) (PdeGst.u & GST_PDE_BIG_PG_MASK)
98	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
99	# define GST_PD_MASK X86_PD_PAE_MASK
100	# if PGM_GST_TYPE == PGM_TYPE_PAE
101	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
102	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
103	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
104	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
105	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
106	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
107	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
108	# else
109	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
110	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
111	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
112	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
113	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
114	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
115	# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
116	# endif
117	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
118	# define GST_PT_MASK X86_PT_PAE_MASK
119	#endif
120
121
122	/*******************************************************************************
123	* Internal Functions *
124	*******************************************************************************/
125	__BEGIN_DECLS
126	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
127	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
128	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
129	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
130	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
131	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
132	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
133	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
134	#ifndef IN_RING3
135	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
136	# if PGM_GST_TYPE == PGM_TYPE_PAE \
137	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
138	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
139	# endif
140	#endif
141	__END_DECLS
142
143
144
145	/**
146	* Gets effective Guest OS page information.
147	*
148	* When GCPtr is in a big page, the function will return as if it was a normal
149	* 4KB page. If the need for distinguishing between big and normal page becomes
150	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
151	* purpose.
152	*
153	* @returns VBox status.
154	* @param pVM VM Handle.
155	* @param GCPtr Guest Context virtual address of the page. Page aligned!
156	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
157	* @param pGCPhys Where to store the GC physical address of the page.
158	* This is page aligned. The fact that the
159	*/
160	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
161	{
162	#if PGM_GST_TYPE == PGM_TYPE_REAL \
163	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
164	/*
165	* Fake it.
166	*/
167	if (pfFlags)
168	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
169	if (pGCPhys)
170	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
171	return VINF_SUCCESS;
172
173	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
174
175	/*
176	* Get the PDE.
177	*/
178	# if PGM_GST_TYPE == PGM_TYPE_32BIT
179	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
180	#elif PGM_GST_TYPE == PGM_TYPE_PAE
181	X86PDEPAE Pde;
182	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
183
184	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
185	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
186	*/
187	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
188	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
189	PX86PML4E pPml4e;
190	X86PDPE Pdpe;
191	X86PDEPAE Pde;
192	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
193
194	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
195	Assert(pPml4e);
196	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
197	return VERR_PAGE_TABLE_NOT_PRESENT;
198
199	/* Merge accessed, write, user and no-execute bits into the PDE. */
200	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
201	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
202	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
203	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
204	# endif
205
206	/*
207	* Lookup the page.
208	*/
209	if (!Pde.n.u1Present)
210	return VERR_PAGE_TABLE_NOT_PRESENT;
211
212	if ( !Pde.b.u1Size
213	# if PGM_GST_TYPE != PGM_TYPE_AMD64
214	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
215	# endif
216	)
217	{
218	PGSTPT pPT;
219	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
220	if (VBOX_FAILURE(rc))
221	return rc;
222
223	/*
224	* Get PT entry and check presence.
225	*/
226	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
227	if (!Pte.n.u1Present)
228	return VERR_PAGE_NOT_PRESENT;
229
230	/*
231	* Store the result.
232	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
233	* where the PDPE is simplified.
234	*/
235	if (pfFlags)
236	{
237	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
238	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
239	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
240	/* The NX bit is determined by a bitwise OR between the PT and PD */
241	if (fNoExecuteBitValid)
242	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
243	# endif
244	}
245	if (pGCPhys)
246	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
247	}
248	else
249	{
250	/*
251	* Map big to 4k PTE and store the result
252	*/
253	if (pfFlags)
254	{
255	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
256	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
257	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
258	/* The NX bit is determined by a bitwise OR between the PT and PD */
259	if (fNoExecuteBitValid)
260	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
261	# endif
262	}
263	if (pGCPhys)
264	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
265	}
266	return VINF_SUCCESS;
267	#else
268	# error "shouldn't be here!"
269	/* something else... */
270	return VERR_NOT_SUPPORTED;
271	#endif
272	}
273
274
275	/**
276	* Modify page flags for a range of pages in the guest's tables
277	*
278	* The existing flags are ANDed with the fMask and ORed with the fFlags.
279	*
280	* @returns VBox status code.
281	* @param pVM VM handle.
282	* @param GCPtr Virtual address of the first page in the range. Page aligned!
283	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
284	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
285	* @param fMask The AND mask - page flags X86_PTE_*.
286	*/
287	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
288	{
289	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
290	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
291	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
292
293	for (;;)
294	{
295	/*
296	* Get the PD entry.
297	*/
298	# if PGM_GST_TYPE == PGM_TYPE_32BIT
299	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
300	# elif PGM_GST_TYPE == PGM_TYPE_PAE
301	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
302	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
303	*/
304	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
305	Assert(pPde);
306	if (!pPde)
307	return VERR_PAGE_TABLE_NOT_PRESENT;
308	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
309	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
310	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
311	Assert(pPde);
312	if (!pPde)
313	return VERR_PAGE_TABLE_NOT_PRESENT;
314	# endif
315	GSTPDE Pde = *pPde;
316	Assert(Pde.n.u1Present);
317	if (!Pde.n.u1Present)
318	return VERR_PAGE_TABLE_NOT_PRESENT;
319
320	if ( !Pde.b.u1Size
321	# if PGM_GST_TYPE != PGM_TYPE_AMD64
322	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
323	# endif
324	)
325	{
326	/*
327	* 4KB Page table
328	*
329	* Walk page tables and pages till we're done.
330	*/
331	PGSTPT pPT;
332	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
333	if (VBOX_FAILURE(rc))
334	return rc;
335
336	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
337	while (iPTE < RT_ELEMENTS(pPT->a))
338	{
339	GSTPTE Pte = pPT->a[iPTE];
340	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
341	\| (fFlags & ~GST_PTE_PG_MASK);
342	pPT->a[iPTE] = Pte;
343
344	/* next page */
345	cb -= PAGE_SIZE;
346	if (!cb)
347	return VINF_SUCCESS;
348	GCPtr += PAGE_SIZE;
349	iPTE++;
350	}
351	}
352	else
353	{
354	/*
355	* 4MB Page table
356	*/
357	# if PGM_GST_TYPE == PGM_TYPE_32BIT
358	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
359	# else
360	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
361	# endif
362	\| (fFlags & ~GST_PTE_PG_MASK)
363	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
364	*pPde = Pde;
365
366	/* advance */
367	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
368	if (cbDone >= cb)
369	return VINF_SUCCESS;
370	cb -= cbDone;
371	GCPtr += cbDone;
372	}
373	}
374
375	#else
376	/* real / protected mode: ignore. */
377	return VINF_SUCCESS;
378	#endif
379	}
380
381
382	/**
383	* Retrieve guest PDE information
384	*
385	* @returns VBox status code.
386	* @param pVM The virtual machine.
387	* @param GCPtr Guest context pointer
388	* @param pPDE Pointer to guest PDE structure
389	*/
390	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
391	{
392	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
393	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
394	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
395
396	# if PGM_GST_TYPE == PGM_TYPE_32BIT
397	X86PDE Pde;
398	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
399	# elif PGM_GST_TYPE == PGM_TYPE_PAE
400	X86PDEPAE Pde;
401	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
402	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
403	X86PDEPAE Pde;
404	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
405	# endif
406
407	pPDE->u = (X86PGPAEUINT)Pde.u;
408	return VINF_SUCCESS;
409	#else
410	AssertFailed();
411	return VERR_NOT_IMPLEMENTED;
412	#endif
413	}
414
415
416
417	/**
418	* Maps the CR3 into HMA in GC and locate it in HC.
419	*
420	* Note that a MapCR3 call is usually not followed by an UnmapCR3 call; whenever
421	* CR3 is updated we simply call MapCR3 again.
422	*
423	* @returns VBox status, no specials.
424	* @param pVM VM handle.
425	* @param GCPhysCR3 The physical address in the CR3 register.
426	*/
427	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
428	{
429	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
430	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
431	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
432
433	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
434
435	/*
436	* Map the page CR3 points at.
437	*/
438	RTHCPHYS HCPhysGuestCR3;
439	RTHCPTR HCPtrGuestCR3;
440	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
441	if (VBOX_SUCCESS(rc))
442	{
443	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
444	if (VBOX_SUCCESS(rc))
445	{
446	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
447	# if PGM_GST_TYPE == PGM_TYPE_32BIT
448	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
449	pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
450
451	# elif PGM_GST_TYPE == PGM_TYPE_PAE
452	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
453	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
454	pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
455	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
456
457	/*
458	* Map the 4 PDs too.
459	*/
460	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
461	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
462	{
463	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
464	{
465	RTHCPTR HCPtr;
466	RTHCPHYS HCPhys;
467	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
468	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
469	if (VBOX_SUCCESS(rc2))
470	{
471	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
472	AssertRCReturn(rc, rc);
473	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
474	pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
475	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
476	PGM_INVL_PG(GCPtr);
477	continue;
478	}
479	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
480	}
481
482	pVM->pgm.s.apGstPaePDsHC[i] = 0;
483	pVM->pgm.s.apGstPaePDsGC[i] = 0;
484	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
485	PGM_INVL_PG(GCPtr);
486	}
487	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
488	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
489
490	pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
491
492	if (!HWACCMIsNestedPagingActive(pVM))
493	{
494	if (pVM->pgm.s.pHCShwAmd64CR3)
495	{
496	/* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
497	if (pVM->pgm.s.pHCShwAmd64CR3->enmKind != PGMPOOLKIND_FREE)
498	pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
499	pVM->pgm.s.pHCShwAmd64CR3 = 0;
500	pVM->pgm.s.pHCPaePML4 = 0;
501	pVM->pgm.s.HCPhysPaePML4 = 0;
502	}
503
504	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
505	try_again:
506	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pHCShwAmd64CR3);
507	if (rc == VERR_PGM_POOL_FLUSHED)
508	{
509	Log(("MapCR3: Flush pool and try again\n"));
510	Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
511	rc = pgmPoolSyncCR3(pVM);
512	AssertRC(rc);
513	goto try_again;
514	}
515	pVM->pgm.s.pHCPaePML4 = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTXSUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
516	pVM->pgm.s.HCPhysPaePML4 = pVM->pgm.s.pHCShwAmd64CR3->Core.Key;
517	}
518	# endif
519	}
520	else
521	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
522	}
523	else
524	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
525
526	#else /* prot/real stub */
527	int rc = VINF_SUCCESS;
528	#endif
529	return rc;
530	}
531
532
533	/**
534	* Unmaps the CR3.
535	*
536	* @returns VBox status, no specials.
537	* @param pVM VM handle.
538	*/
539	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
540	{
541	LogFlow(("UnmapCR3\n"));
542
543	int rc = VINF_SUCCESS;
544
545	#if PGM_GST_TYPE == PGM_TYPE_32BIT
546	pVM->pgm.s.pGuestPDHC = 0;
547	pVM->pgm.s.pGuestPDGC = 0;
548
549	#elif PGM_GST_TYPE == PGM_TYPE_PAE
550	pVM->pgm.s.pGstPaePDPTHC = 0;
551	pVM->pgm.s.pGstPaePDPTGC = 0;
552	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
553	{
554	pVM->pgm.s.apGstPaePDsHC[i] = 0;
555	pVM->pgm.s.apGstPaePDsGC[i] = 0;
556	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
557	}
558
559	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
560	pVM->pgm.s.pGstPaePML4HC = 0;
561	if (!HWACCMIsNestedPagingActive(pVM))
562	{
563	pVM->pgm.s.pHCPaePML4 = 0;
564	if (pVM->pgm.s.pHCShwAmd64CR3)
565	{
566	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
567	pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
568	pVM->pgm.s.pHCShwAmd64CR3 = NULL;
569	}
570	}
571
572	#else /* prot/real mode stub */
573	/* nothing to do */
574	#endif
575	return rc;
576	}
577
578
579	#undef LOG_GROUP
580	#define LOG_GROUP LOG_GROUP_PGM_POOL
581
582	/**
583	* Registers physical page monitors for the necessary paging
584	* structures to detect conflicts with our guest mappings.
585	*
586	* This is always called after mapping CR3.
587	* This is never called with fixed mappings.
588	*
589	* @returns VBox status, no specials.
590	* @param pVM VM handle.
591	* @param GCPhysCR3 The physical address in the CR3 register.
592	*/
593	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
594	{
595	Assert(!pVM->pgm.s.fMappingsFixed);
596	int rc = VINF_SUCCESS;
597
598	/*
599	* Register/Modify write phys handler for guest's CR3 if it changed.
600	*/
601	#if PGM_GST_TYPE == PGM_TYPE_32BIT
602
603	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
604	{
605	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
606	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
607	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
608	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
609	else
610	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
611	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
612	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
613	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
614	pVM->pgm.s.pszR3GstWriteHandlerCR3);
615	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
616	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
617	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
618	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
619	? PGMPOOL_IDX_PAE_PD
620	: PGMPOOL_IDX_PD,
621	GCPhysCR3);
622	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
623	if (VBOX_FAILURE(rc))
624	{
625	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
626	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
627	return rc;
628	}
629	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
630	}
631
632	#elif PGM_GST_TYPE == PGM_TYPE_PAE
633	/* Monitor the PDPT page */
634	/*
635	* Register/Modify write phys handler for guest's CR3 if it changed.
636	*/
637	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
638	AssertFailed();
639	# endif
640	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
641	{
642	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
643	if (VBOX_FAILURE(rc))
644	{
645	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
646	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
647	return rc;
648	}
649	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
650	}
651	/*
652	* Do the 4 PDs.
653	*/
654	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
655	{
656	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
657	{
658	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
659	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
660	{
661	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
662
663	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
664	}
665
666	if (VBOX_FAILURE(rc))
667	{
668	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
669	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
670	return rc;
671	}
672	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
673	}
674	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
675	{
676	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
677	AssertRC(rc);
678	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
679	}
680	}
681
682	#else
683	/* prot/real/amd64 mode stub */
684
685	#endif
686	return rc;
687	}
688
689	/**
690	* Deregisters any physical page monitors installed by MonitorCR3.
691	*
692	* @returns VBox status code, no specials.
693	* @param pVM The VM handle.
694	*/
695	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
696	{
697	int rc = VINF_SUCCESS;
698
699	/*
700	* Deregister the access handlers.
701	*
702	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
703	* before we enter GC again.
704	*/
705	#if PGM_GST_TYPE == PGM_TYPE_32BIT
706	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
707	{
708	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
709	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
710	AssertRCReturn(rc, rc);
711	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
712	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
713	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
714	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
715	? PGMPOOL_IDX_PAE_PD
716	: PGMPOOL_IDX_PD);
717	AssertRCReturn(rc, rc);
718	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
719	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
720	}
721
722	#elif PGM_GST_TYPE == PGM_TYPE_PAE
723	/* The PDPT page */
724	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
725	AssertFailed();
726	# endif
727
728	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
729	{
730	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
731	AssertRC(rc);
732	}
733
734	/* The 4 PDs. */
735	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
736	{
737	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
738	{
739	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
740	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
741	AssertRC(rc2);
742	if (VBOX_FAILURE(rc2))
743	rc = rc2;
744	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
745	}
746	}
747	#else
748	/* prot/real/amd64 mode stub */
749	#endif
750	return rc;
751
752	}
753
754	#undef LOG_GROUP
755	#define LOG_GROUP LOG_GROUP_PGM
756
757
758	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
759	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
760	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
761	/**
762	* Updates one virtual handler range.
763	*
764	* @returns 0
765	* @param pNode Pointer to a PGMVIRTHANDLER.
766	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
767	*/
768	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
769	{
770	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
771	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
772	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
773
774	#if PGM_GST_TYPE == PGM_TYPE_32BIT
775	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
776	#endif
777
778	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
779	#if PGM_GST_MODE != PGM_MODE_AMD64
780	/* skip all stuff above 4GB if not AMD64 mode. */
781	if (GCPtr >= _4GB)
782	return 0;
783	#endif
784
785	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
786	unsigned iPage = 0;
787	while (iPage < pCur->cPages)
788	{
789	#if PGM_GST_TYPE == PGM_TYPE_32BIT
790	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
791	#elif PGM_GST_TYPE == PGM_TYPE_PAE
792	X86PDEPAE Pde;
793	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
794	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
795	X86PDEPAE Pde;
796	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
797	#endif
798	if (Pde.n.u1Present)
799	{
800	if ( !Pde.b.u1Size
801	# if PGM_GST_TYPE != PGM_TYPE_AMD64
802	\|\| !(pState->cr4 & X86_CR4_PSE)
803	# endif
804	)
805	{
806	/*
807	* Normal page table.
808	*/
809	PGSTPT pPT;
810	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
811	if (VBOX_SUCCESS(rc))
812	{
813	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
814	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
815	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
816	{
817	GSTPTE Pte = pPT->a[iPTE];
818	RTGCPHYS GCPhysNew;
819	if (Pte.n.u1Present)
820	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
821	else
822	GCPhysNew = NIL_RTGCPHYS;
823	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
824	{
825	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
826	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
827	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
828	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
829	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
830	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
831	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
832	#endif
833	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
834	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
835	}
836	}
837	}
838	else
839	{
840	/* not-present. */
841	offPage = 0;
842	AssertRC(rc);
843	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
844	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
845	iPTE++, iPage++, GCPtr += PAGE_SIZE)
846	{
847	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
848	{
849	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
850	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
851	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
852	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
853	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
854	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
855	#endif
856	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
857	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
858	}
859	}
860	}
861	}
862	else
863	{
864	/*
865	* 2/4MB page.
866	*/
867	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
868	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
869	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
870	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
871	{
872	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
873	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
874	{
875	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
876	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
877	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
878	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
879	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
880	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
881	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
882	#endif
883	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
884	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
885	}
886	}
887	} /* pde type */
888	}
889	else
890	{
891	/* not-present. */
892	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
893	cPages && iPage < pCur->cPages;
894	iPage++, GCPtr += PAGE_SIZE)
895	{
896	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
897	{
898	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
899	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
900	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
901	}
902	}
903	offPage = 0;
904	}
905	} /* for pages in virtual mapping. */
906
907	return 0;
908	}
909	#endif /* 32BIT, PAE and AMD64 */
910
911
912	/**
913	* Updates the virtual page access handlers.
914	*
915	* @returns true if bits were flushed.
916	* @returns false if bits weren't flushed.
917	* @param pVM VM handle.
918	* @param pPDSrc The page directory.
919	* @param cr4 The cr4 register value.
920	*/
921	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
922	{
923	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
924	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
925	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
926
927	/** @todo
928	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
929	*/
930
931	/*
932	* Resolve any virtual address based access handlers to GC physical addresses.
933	* This should be fairly quick.
934	*/
935	PGMHVUSTATE State;
936
937	pgmLock(pVM);
938	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
939	State.pVM = pVM;
940	State.fTodo = pVM->pgm.s.fSyncFlags;
941	State.cr4 = cr4;
942	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
943	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
944
945
946	/*
947	* Set / reset bits?
948	*/
949	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
950	{
951	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
952	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
953	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
954	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
955	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
956	}
957	pgmUnlock(pVM);
958
959	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
960
961	#else /* real / protected */
962	return false;
963	#endif
964	}
965
966
967	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
968
969	/**
970	* Write access handler for the Guest CR3 page in 32-bit mode.
971	*
972	* This will try interpret the instruction, if failure fail back to the recompiler.
973	* Check if the changed PDEs are marked present and conflicts with our
974	* mappings. If conflict, we'll switch to the host context and resolve it there
975	*
976	* @returns VBox status code (appropritate for trap handling and GC return).
977	* @param pVM VM Handle.
978	* @param uErrorCode CPU Error code.
979	* @param pRegFrame Trap register frame.
980	* @param pvFault The fault address (cr2).
981	* @param GCPhysFault The GC physical address corresponding to pvFault.
982	* @param pvUser User argument.
983	*/
984	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
985	{
986	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
987
988	/*
989	* Try interpret the instruction.
990	*/
991	uint32_t cb;
992	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
993	if (VBOX_SUCCESS(rc) && cb)
994	{
995	/*
996	* Check if the modified PDEs are present and mappings.
997	*/
998	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
999	const unsigned iPD1 = offPD / sizeof(X86PDE);
1000	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
1001
1002	Assert(cb > 0 && cb <= 8);
1003	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
1004	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
1005
1006	#ifdef DEBUG
1007	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
1008	if (iPD1 != iPD2)
1009	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
1010	#endif
1011
1012	if (!pVM->pgm.s.fMappingsFixed)
1013	{
1014	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
1015	if ( ( pPDSrc->a[iPD1].n.u1Present
1016	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
1017	\|\| ( iPD1 != iPD2
1018	&& pPDSrc->a[iPD2].n.u1Present
1019	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
1020	)
1021	{
1022	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1023	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1024	if (rc == VINF_SUCCESS)
1025	rc = VINF_PGM_SYNC_CR3;
1026	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
1027	return rc;
1028	}
1029	}
1030
1031	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1032	}
1033	else
1034	{
1035	Assert(VBOX_FAILURE(rc));
1036	if (rc == VERR_EM_INTERPRETER)
1037	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1038	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1039	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1040	}
1041	return rc;
1042	}
1043
1044	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
1045
1046
1047	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
1048
1049	/**
1050	* Write access handler for the Guest CR3 page in PAE mode.
1051	*
1052	* This will try interpret the instruction, if failure fail back to the recompiler.
1053	* Check if the changed PDEs are marked present and conflicts with our
1054	* mappings. If conflict, we'll switch to the host context and resolve it there
1055	*
1056	* @returns VBox status code (appropritate for trap handling and GC return).
1057	* @param pVM VM Handle.
1058	* @param uErrorCode CPU Error code.
1059	* @param pRegFrame Trap register frame.
1060	* @param pvFault The fault address (cr2).
1061	* @param GCPhysFault The GC physical address corresponding to pvFault.
1062	* @param pvUser User argument.
1063	*/
1064	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1065	{
1066	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1067
1068	/*
1069	* Try interpret the instruction.
1070	*/
1071	uint32_t cb;
1072	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1073	if (VBOX_SUCCESS(rc) && cb)
1074	{
1075	/*
1076	* Check if any of the PDs have changed.
1077	* We'll simply check all of them instead of figuring out which one/two to check.
1078	*/
1079	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1080	{
1081	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1082	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1083	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1084	{
1085	/*
1086	* The PDPE has changed.
1087	* We will schedule a monitoring update for the next TLB Flush,
1088	* InvalidatePage or SyncCR3.
1089	*
1090	* This isn't perfect, because a lazy page sync might be dealing with an half
1091	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1092	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1093	* executing.
1094	*/
1095	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1096	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1097	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1098	}
1099	}
1100
1101	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1102	}
1103	else
1104	{
1105	Assert(VBOX_FAILURE(rc));
1106	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1107	if (rc == VERR_EM_INTERPRETER)
1108	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1109	}
1110	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1111	return rc;
1112	}
1113
1114
1115	/**
1116	* Write access handler for the Guest PDs in PAE mode.
1117	*
1118	* This will try interpret the instruction, if failure fail back to the recompiler.
1119	* Check if the changed PDEs are marked present and conflicts with our
1120	* mappings. If conflict, we'll switch to the host context and resolve it there
1121	*
1122	* @returns VBox status code (appropritate for trap handling and GC return).
1123	* @param pVM VM Handle.
1124	* @param uErrorCode CPU Error code.
1125	* @param pRegFrame Trap register frame.
1126	* @param pvFault The fault address (cr2).
1127	* @param GCPhysFault The GC physical address corresponding to pvFault.
1128	* @param pvUser User argument.
1129	*/
1130	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1131	{
1132	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1133
1134	/*
1135	* Try interpret the instruction.
1136	*/
1137	uint32_t cb;
1138	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1139	if (VBOX_SUCCESS(rc) && cb)
1140	{
1141	/*
1142	* Figure out which of the 4 PDs this is.
1143	*/
1144	RTGCUINTPTR i;
1145	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1146	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1147	{
1148	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1149	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1150	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1151	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1152
1153	Assert(cb > 0 && cb <= 8);
1154	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1155	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1156
1157	#ifdef DEBUG
1158	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1159	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1160	if (iPD1 != iPD2)
1161	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1162	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1163	#endif
1164
1165	if (!pVM->pgm.s.fMappingsFixed)
1166	{
1167	if ( ( pPDSrc->a[iPD1].n.u1Present
1168	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1169	\|\| ( iPD1 != iPD2
1170	&& pPDSrc->a[iPD2].n.u1Present
1171	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1172	)
1173	{
1174	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1175	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1176	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1177	return VINF_PGM_SYNC_CR3;
1178	}
1179	}
1180	break; /* ASSUMES no duplicate entries... */
1181	}
1182	Assert(i < 4);
1183
1184	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1185	}
1186	else
1187	{
1188	Assert(VBOX_FAILURE(rc));
1189	if (rc == VERR_EM_INTERPRETER)
1190	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1191	else
1192	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1193	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1194	}
1195	return rc;
1196	}
1197
1198	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1199

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 12967

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