PGMAllGst.h@ 13796

Last change on this file since 13796 was 13582, checked in by vboxsync, 16 years ago
Invalidate the current pml4 phys pointer properly when changing cr3.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 45.1 KB

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1	/* $Id: PGMAllGst.h 13582 2008-10-27 14:46:35Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48	#undef GST_PDPE_PG_MASK
49	#undef GST_GET_PDE_BIG_PG_GCPHYS
50
51	#if PGM_GST_TYPE == PGM_TYPE_REAL \
52	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
53	# define GSTPT SHWPT
54	# define PGSTPT PSHWPT
55	# define GSTPTE SHWPTE
56	# define PGSTPTE PSHWPTE
57	# define GSTPD SHWPD
58	# define PGSTPD PSHWPD
59	# define GSTPDE SHWPDE
60	# define PGSTPDE PSHWPDE
61	# define GST_PTE_PG_MASK SHW_PTE_PG_MASK
62
63	#elif PGM_GST_TYPE == PGM_TYPE_32BIT
64	# define GSTPT X86PT
65	# define PGSTPT PX86PT
66	# define GSTPTE X86PTE
67	# define PGSTPTE PX86PTE
68	# define GSTPD X86PD
69	# define PGSTPD PX86PD
70	# define GSTPDE X86PDE
71	# define PGSTPDE PX86PDE
72	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
73	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
74	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
75	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
76	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
77	# define GST_PD_SHIFT X86_PD_SHIFT
78	# define GST_PD_MASK X86_PD_MASK
79	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
80	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
81	# define GST_PT_SHIFT X86_PT_SHIFT
82	# define GST_PT_MASK X86_PT_MASK
83	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
84
85	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
86	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
87	# define GSTPT X86PTPAE
88	# define PGSTPT PX86PTPAE
89	# define GSTPTE X86PTEPAE
90	# define PGSTPTE PX86PTEPAE
91	# define GSTPD X86PDPAE
92	# define PGSTPD PX86PDPAE
93	# define GSTPDE X86PDEPAE
94	# define PGSTPDE PX86PDEPAE
95	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
96	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
97	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
98	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
99	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) (PdeGst.u & GST_PDE_BIG_PG_MASK)
100	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
101	# define GST_PD_MASK X86_PD_PAE_MASK
102	# if PGM_GST_TYPE == PGM_TYPE_PAE
103	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
104	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
105	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
106	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
107	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
108	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
109	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
110	# else
111	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
112	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
113	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
114	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
115	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
116	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
117	# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
118	# endif
119	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
120	# define GST_PT_MASK X86_PT_PAE_MASK
121	#endif
122
123
124	/*******************************************************************************
125	* Internal Functions *
126	*******************************************************************************/
127	__BEGIN_DECLS
128	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
129	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
130	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
131	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
132	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
133	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
134	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
135	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
136	#ifndef IN_RING3
137	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
138	# if PGM_GST_TYPE == PGM_TYPE_PAE \
139	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
140	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
141	# endif
142	#endif
143	__END_DECLS
144
145
146
147	/**
148	* Gets effective Guest OS page information.
149	*
150	* When GCPtr is in a big page, the function will return as if it was a normal
151	* 4KB page. If the need for distinguishing between big and normal page becomes
152	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
153	* purpose.
154	*
155	* @returns VBox status.
156	* @param pVM VM Handle.
157	* @param GCPtr Guest Context virtual address of the page. Page aligned!
158	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
159	* @param pGCPhys Where to store the GC physical address of the page.
160	* This is page aligned. The fact that the
161	*/
162	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
163	{
164	#if PGM_GST_TYPE == PGM_TYPE_REAL \
165	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
166	/*
167	* Fake it.
168	*/
169	if (pfFlags)
170	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
171	if (pGCPhys)
172	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
173	return VINF_SUCCESS;
174
175	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
176
177	/*
178	* Get the PDE.
179	*/
180	# if PGM_GST_TYPE == PGM_TYPE_32BIT
181	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
182	#elif PGM_GST_TYPE == PGM_TYPE_PAE
183	X86PDEPAE Pde;
184	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
185
186	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
187	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
188	*/
189	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
190	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
191	PX86PML4E pPml4e;
192	X86PDPE Pdpe;
193	X86PDEPAE Pde;
194	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
195
196	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
197	Assert(pPml4e);
198	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
199	return VERR_PAGE_TABLE_NOT_PRESENT;
200
201	/* Merge accessed, write, user and no-execute bits into the PDE. */
202	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
203	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
204	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
205	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
206	# endif
207
208	/*
209	* Lookup the page.
210	*/
211	if (!Pde.n.u1Present)
212	return VERR_PAGE_TABLE_NOT_PRESENT;
213
214	if ( !Pde.b.u1Size
215	# if PGM_GST_TYPE != PGM_TYPE_AMD64
216	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
217	# endif
218	)
219	{
220	PGSTPT pPT;
221	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
222	if (VBOX_FAILURE(rc))
223	return rc;
224
225	/*
226	* Get PT entry and check presence.
227	*/
228	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
229	if (!Pte.n.u1Present)
230	return VERR_PAGE_NOT_PRESENT;
231
232	/*
233	* Store the result.
234	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
235	* where the PDPE is simplified.
236	*/
237	if (pfFlags)
238	{
239	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
240	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
241	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
242	/* The NX bit is determined by a bitwise OR between the PT and PD */
243	if (fNoExecuteBitValid)
244	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
245	# endif
246	}
247	if (pGCPhys)
248	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
249	}
250	else
251	{
252	/*
253	* Map big to 4k PTE and store the result
254	*/
255	if (pfFlags)
256	{
257	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
258	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
259	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
260	/* The NX bit is determined by a bitwise OR between the PT and PD */
261	if (fNoExecuteBitValid)
262	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
263	# endif
264	}
265	if (pGCPhys)
266	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
267	}
268	return VINF_SUCCESS;
269	#else
270	# error "shouldn't be here!"
271	/* something else... */
272	return VERR_NOT_SUPPORTED;
273	#endif
274	}
275
276
277	/**
278	* Modify page flags for a range of pages in the guest's tables
279	*
280	* The existing flags are ANDed with the fMask and ORed with the fFlags.
281	*
282	* @returns VBox status code.
283	* @param pVM VM handle.
284	* @param GCPtr Virtual address of the first page in the range. Page aligned!
285	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
286	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
287	* @param fMask The AND mask - page flags X86_PTE_*.
288	*/
289	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
290	{
291	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
292	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
293	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
294
295	for (;;)
296	{
297	/*
298	* Get the PD entry.
299	*/
300	# if PGM_GST_TYPE == PGM_TYPE_32BIT
301	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
302	# elif PGM_GST_TYPE == PGM_TYPE_PAE
303	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
304	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
305	*/
306	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
307	Assert(pPde);
308	if (!pPde)
309	return VERR_PAGE_TABLE_NOT_PRESENT;
310	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
311	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
312	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
313	Assert(pPde);
314	if (!pPde)
315	return VERR_PAGE_TABLE_NOT_PRESENT;
316	# endif
317	GSTPDE Pde = *pPde;
318	Assert(Pde.n.u1Present);
319	if (!Pde.n.u1Present)
320	return VERR_PAGE_TABLE_NOT_PRESENT;
321
322	if ( !Pde.b.u1Size
323	# if PGM_GST_TYPE != PGM_TYPE_AMD64
324	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
325	# endif
326	)
327	{
328	/*
329	* 4KB Page table
330	*
331	* Walk page tables and pages till we're done.
332	*/
333	PGSTPT pPT;
334	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
335	if (VBOX_FAILURE(rc))
336	return rc;
337
338	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
339	while (iPTE < RT_ELEMENTS(pPT->a))
340	{
341	GSTPTE Pte = pPT->a[iPTE];
342	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
343	\| (fFlags & ~GST_PTE_PG_MASK);
344	pPT->a[iPTE] = Pte;
345
346	/* next page */
347	cb -= PAGE_SIZE;
348	if (!cb)
349	return VINF_SUCCESS;
350	GCPtr += PAGE_SIZE;
351	iPTE++;
352	}
353	}
354	else
355	{
356	/*
357	* 4MB Page table
358	*/
359	# if PGM_GST_TYPE == PGM_TYPE_32BIT
360	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
361	# else
362	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
363	# endif
364	\| (fFlags & ~GST_PTE_PG_MASK)
365	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
366	*pPde = Pde;
367
368	/* advance */
369	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
370	if (cbDone >= cb)
371	return VINF_SUCCESS;
372	cb -= cbDone;
373	GCPtr += cbDone;
374	}
375	}
376
377	#else
378	/* real / protected mode: ignore. */
379	return VINF_SUCCESS;
380	#endif
381	}
382
383
384	/**
385	* Retrieve guest PDE information
386	*
387	* @returns VBox status code.
388	* @param pVM The virtual machine.
389	* @param GCPtr Guest context pointer
390	* @param pPDE Pointer to guest PDE structure
391	*/
392	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
393	{
394	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
395	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
396	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
397
398	# if PGM_GST_TYPE == PGM_TYPE_32BIT
399	X86PDE Pde;
400	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
401	# elif PGM_GST_TYPE == PGM_TYPE_PAE
402	X86PDEPAE Pde;
403	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
404	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
405	X86PDEPAE Pde;
406	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
407	# endif
408
409	pPDE->u = (X86PGPAEUINT)Pde.u;
410	return VINF_SUCCESS;
411	#else
412	AssertFailed();
413	return VERR_NOT_IMPLEMENTED;
414	#endif
415	}
416
417
418
419	/**
420	* Maps the CR3 into HMA in GC and locate it in HC.
421	*
422	* Note that a MapCR3 call is usually not followed by an UnmapCR3 call; whenever
423	* CR3 is updated we simply call MapCR3 again.
424	*
425	* @returns VBox status, no specials.
426	* @param pVM VM handle.
427	* @param GCPhysCR3 The physical address in the CR3 register.
428	*/
429	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
430	{
431	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
432	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
433	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
434
435	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
436
437	/*
438	* Map the page CR3 points at.
439	*/
440	RTHCPHYS HCPhysGuestCR3;
441	RTHCPTR HCPtrGuestCR3;
442	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
443	if (VBOX_SUCCESS(rc))
444	{
445	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
446	if (VBOX_SUCCESS(rc))
447	{
448	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
449	# if PGM_GST_TYPE == PGM_TYPE_32BIT
450	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
451	pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
452
453	# elif PGM_GST_TYPE == PGM_TYPE_PAE
454	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
455	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
456	pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
457	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
458
459	/*
460	* Map the 4 PDs too.
461	*/
462	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
463	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
464	{
465	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
466	{
467	RTHCPTR HCPtr;
468	RTHCPHYS HCPhys;
469	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
470	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
471	if (VBOX_SUCCESS(rc2))
472	{
473	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
474	AssertRCReturn(rc, rc);
475	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
476	pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
477	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
478	PGM_INVL_PG(GCPtr);
479	continue;
480	}
481	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
482	}
483
484	pVM->pgm.s.apGstPaePDsHC[i] = 0;
485	pVM->pgm.s.apGstPaePDsGC[i] = 0;
486	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
487	PGM_INVL_PG(GCPtr);
488	}
489	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
490	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
491
492	pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
493
494	if (!HWACCMIsNestedPagingActive(pVM))
495	{
496	if (pVM->pgm.s.pHCShwAmd64CR3)
497	{
498	/* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
499	if (pVM->pgm.s.pHCShwAmd64CR3->enmKind != PGMPOOLKIND_FREE)
500	pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
501	pVM->pgm.s.pHCShwAmd64CR3 = 0;
502	pVM->pgm.s.pHCPaePML4 = 0;
503	pVM->pgm.s.HCPhysPaePML4 = 0;
504	}
505
506	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
507	l_try_again:
508	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pHCShwAmd64CR3);
509	if (rc == VERR_PGM_POOL_FLUSHED)
510	{
511	Log(("MapCR3: Flush pool and try again\n"));
512	Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
513	rc = pgmPoolSyncCR3(pVM);
514	AssertRC(rc);
515	goto l_try_again;
516	}
517	pVM->pgm.s.pHCPaePML4 = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.pHCShwAmd64CR3);
518	pVM->pgm.s.HCPhysPaePML4 = pVM->pgm.s.pHCShwAmd64CR3->Core.Key;
519	}
520	# endif
521	}
522	else
523	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
524	}
525	else
526	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
527
528	#else /* prot/real stub */
529	int rc = VINF_SUCCESS;
530	#endif
531	return rc;
532	}
533
534
535	/**
536	* Unmaps the CR3.
537	*
538	* @returns VBox status, no specials.
539	* @param pVM VM handle.
540	*/
541	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
542	{
543	LogFlow(("UnmapCR3\n"));
544
545	int rc = VINF_SUCCESS;
546
547	#if PGM_GST_TYPE == PGM_TYPE_32BIT
548	pVM->pgm.s.pGuestPDHC = 0;
549	pVM->pgm.s.pGuestPDGC = 0;
550
551	#elif PGM_GST_TYPE == PGM_TYPE_PAE
552	pVM->pgm.s.pGstPaePDPTHC = 0;
553	pVM->pgm.s.pGstPaePDPTGC = 0;
554	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
555	{
556	pVM->pgm.s.apGstPaePDsHC[i] = 0;
557	pVM->pgm.s.apGstPaePDsGC[i] = 0;
558	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
559	}
560
561	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
562	pVM->pgm.s.pGstPaePML4HC = 0;
563	if (!HWACCMIsNestedPagingActive(pVM))
564	{
565	pVM->pgm.s.pHCPaePML4 = 0;
566	pVM->pgm.s.HCPhysPaePML4 = 0;
567	if (pVM->pgm.s.pHCShwAmd64CR3)
568	{
569	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
570	pgmPoolFreeByPage(pPool, pVM->pgm.s.pHCShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pHCShwAmd64CR3->GCPhys >> PAGE_SHIFT);
571	pVM->pgm.s.pHCShwAmd64CR3 = 0;
572	}
573	}
574
575	#else /* prot/real mode stub */
576	/* nothing to do */
577	#endif
578	return rc;
579	}
580
581
582	#undef LOG_GROUP
583	#define LOG_GROUP LOG_GROUP_PGM_POOL
584
585	/**
586	* Registers physical page monitors for the necessary paging
587	* structures to detect conflicts with our guest mappings.
588	*
589	* This is always called after mapping CR3.
590	* This is never called with fixed mappings.
591	*
592	* @returns VBox status, no specials.
593	* @param pVM VM handle.
594	* @param GCPhysCR3 The physical address in the CR3 register.
595	*/
596	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
597	{
598	Assert(!pVM->pgm.s.fMappingsFixed);
599	int rc = VINF_SUCCESS;
600
601	/*
602	* Register/Modify write phys handler for guest's CR3 if it changed.
603	*/
604	#if PGM_GST_TYPE == PGM_TYPE_32BIT
605
606	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
607	{
608	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
609	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
610	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
611	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
612	else
613	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
614	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
615	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
616	pVM->pgm.s.pfnRCGstWriteHandlerCR3, 0,
617	pVM->pgm.s.pszR3GstWriteHandlerCR3);
618	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
619	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
620	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
621	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
622	? PGMPOOL_IDX_PAE_PD
623	: PGMPOOL_IDX_PD,
624	GCPhysCR3);
625	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
626	if (VBOX_FAILURE(rc))
627	{
628	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
629	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
630	return rc;
631	}
632	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
633	}
634
635	#elif PGM_GST_TYPE == PGM_TYPE_PAE
636	/* Monitor the PDPT page */
637	/*
638	* Register/Modify write phys handler for guest's CR3 if it changed.
639	*/
640	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
641	AssertFailed();
642	# endif
643	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
644	{
645	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
646	if (VBOX_FAILURE(rc))
647	{
648	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
649	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
650	return rc;
651	}
652	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
653	}
654
655	/*
656	* Do the 4 PDs.
657	*/
658	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
659	{
660	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
661	{
662	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
663	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
664	{
665	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
666
667	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
668	}
669
670	if (VBOX_FAILURE(rc))
671	{
672	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
673	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
674	return rc;
675	}
676	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
677	}
678	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
679	{
680	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
681	AssertRC(rc);
682	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
683	}
684	}
685
686	#else
687	/* prot/real/amd64 mode stub */
688
689	#endif
690	return rc;
691	}
692
693	/**
694	* Deregisters any physical page monitors installed by MonitorCR3.
695	*
696	* @returns VBox status code, no specials.
697	* @param pVM The VM handle.
698	*/
699	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
700	{
701	int rc = VINF_SUCCESS;
702
703	/*
704	* Deregister the access handlers.
705	*
706	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
707	* before we enter GC again.
708	*/
709	#if PGM_GST_TYPE == PGM_TYPE_32BIT
710	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
711	{
712	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
713	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
714	AssertRCReturn(rc, rc);
715	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
716	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
717	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
718	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
719	? PGMPOOL_IDX_PAE_PD
720	: PGMPOOL_IDX_PD);
721	AssertRCReturn(rc, rc);
722	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
723	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
724	}
725
726	#elif PGM_GST_TYPE == PGM_TYPE_PAE
727	/* The PDPT page */
728	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
729	AssertFailed();
730	# endif
731
732	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
733	{
734	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT);
735	AssertRC(rc);
736	}
737
738	/* The 4 PDs. */
739	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
740	{
741	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
742	{
743	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
744	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
745	AssertRC(rc2);
746	if (VBOX_FAILURE(rc2))
747	rc = rc2;
748	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
749	}
750	}
751	#else
752	/* prot/real/amd64 mode stub */
753	#endif
754	return rc;
755
756	}
757
758	#undef LOG_GROUP
759	#define LOG_GROUP LOG_GROUP_PGM
760
761
762	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
763	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
764	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
765	/**
766	* Updates one virtual handler range.
767	*
768	* @returns 0
769	* @param pNode Pointer to a PGMVIRTHANDLER.
770	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
771	*/
772	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
773	{
774	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
775	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
776	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
777
778	#if PGM_GST_TYPE == PGM_TYPE_32BIT
779	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
780	#endif
781
782	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->Core.Key;
783	#if PGM_GST_MODE != PGM_MODE_AMD64
784	/* skip all stuff above 4GB if not AMD64 mode. */
785	if (GCPtr >= _4GB)
786	return 0;
787	#endif
788
789	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
790	unsigned iPage = 0;
791	while (iPage < pCur->cPages)
792	{
793	#if PGM_GST_TYPE == PGM_TYPE_32BIT
794	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
795	#elif PGM_GST_TYPE == PGM_TYPE_PAE
796	X86PDEPAE Pde;
797	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
798	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
799	X86PDEPAE Pde;
800	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
801	#endif
802	if (Pde.n.u1Present)
803	{
804	if ( !Pde.b.u1Size
805	# if PGM_GST_TYPE != PGM_TYPE_AMD64
806	\|\| !(pState->cr4 & X86_CR4_PSE)
807	# endif
808	)
809	{
810	/*
811	* Normal page table.
812	*/
813	PGSTPT pPT;
814	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
815	if (VBOX_SUCCESS(rc))
816	{
817	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
818	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
819	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
820	{
821	GSTPTE Pte = pPT->a[iPTE];
822	RTGCPHYS GCPhysNew;
823	if (Pte.n.u1Present)
824	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
825	else
826	GCPhysNew = NIL_RTGCPHYS;
827	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
828	{
829	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
830	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
831	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
832	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
833	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
834	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
835	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
836	#endif
837	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
838	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
839	}
840	}
841	}
842	else
843	{
844	/* not-present. */
845	offPage = 0;
846	AssertRC(rc);
847	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
848	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
849	iPTE++, iPage++, GCPtr += PAGE_SIZE)
850	{
851	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
852	{
853	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
854	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
855	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
856	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
857	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
858	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
859	#endif
860	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
861	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
862	}
863	}
864	}
865	}
866	else
867	{
868	/*
869	* 2/4MB page.
870	*/
871	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
872	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
873	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
874	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
875	{
876	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
877	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
878	{
879	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
880	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
881	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
882	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
883	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
884	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
885	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
886	#endif
887	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
888	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
889	}
890	}
891	} /* pde type */
892	}
893	else
894	{
895	/* not-present. */
896	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
897	cPages && iPage < pCur->cPages;
898	iPage++, GCPtr += PAGE_SIZE)
899	{
900	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
901	{
902	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
903	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
904	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
905	}
906	}
907	offPage = 0;
908	}
909	} /* for pages in virtual mapping. */
910
911	return 0;
912	}
913	#endif /* 32BIT, PAE and AMD64 */
914
915
916	/**
917	* Updates the virtual page access handlers.
918	*
919	* @returns true if bits were flushed.
920	* @returns false if bits weren't flushed.
921	* @param pVM VM handle.
922	* @param pPDSrc The page directory.
923	* @param cr4 The cr4 register value.
924	*/
925	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
926	{
927	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
928	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
929	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
930
931	/** @todo
932	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
933	*/
934
935	/*
936	* Resolve any virtual address based access handlers to GC physical addresses.
937	* This should be fairly quick.
938	*/
939	PGMHVUSTATE State;
940
941	pgmLock(pVM);
942	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
943	State.pVM = pVM;
944	State.fTodo = pVM->pgm.s.fSyncFlags;
945	State.cr4 = cr4;
946	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
947	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
948
949
950	/*
951	* Set / reset bits?
952	*/
953	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
954	{
955	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
956	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
957	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
958	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
959	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
960	}
961	pgmUnlock(pVM);
962
963	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
964
965	#else /* real / protected */
966	return false;
967	#endif
968	}
969
970
971	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
972
973	/**
974	* Write access handler for the Guest CR3 page in 32-bit mode.
975	*
976	* This will try interpret the instruction, if failure fail back to the recompiler.
977	* Check if the changed PDEs are marked present and conflicts with our
978	* mappings. If conflict, we'll switch to the host context and resolve it there
979	*
980	* @returns VBox status code (appropritate for trap handling and GC return).
981	* @param pVM VM Handle.
982	* @param uErrorCode CPU Error code.
983	* @param pRegFrame Trap register frame.
984	* @param pvFault The fault address (cr2).
985	* @param GCPhysFault The GC physical address corresponding to pvFault.
986	* @param pvUser User argument.
987	*/
988	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
989	{
990	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
991
992	/*
993	* Try interpret the instruction.
994	*/
995	uint32_t cb;
996	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
997	if (VBOX_SUCCESS(rc) && cb)
998	{
999	/*
1000	* Check if the modified PDEs are present and mappings.
1001	*/
1002	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1003	const unsigned iPD1 = offPD / sizeof(X86PDE);
1004	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
1005
1006	Assert(cb > 0 && cb <= 8);
1007	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
1008	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
1009
1010	#ifdef DEBUG
1011	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
1012	if (iPD1 != iPD2)
1013	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
1014	#endif
1015
1016	if (!pVM->pgm.s.fMappingsFixed)
1017	{
1018	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
1019	if ( ( pPDSrc->a[iPD1].n.u1Present
1020	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
1021	\|\| ( iPD1 != iPD2
1022	&& pPDSrc->a[iPD2].n.u1Present
1023	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
1024	)
1025	{
1026	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1027	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1028	if (rc == VINF_SUCCESS)
1029	rc = VINF_PGM_SYNC_CR3;
1030	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
1031	return rc;
1032	}
1033	}
1034
1035	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1036	}
1037	else
1038	{
1039	Assert(VBOX_FAILURE(rc));
1040	if (rc == VERR_EM_INTERPRETER)
1041	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1042	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1043	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1044	}
1045	return rc;
1046	}
1047
1048	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
1049	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
1050
1051	/**
1052	* Write access handler for the Guest CR3 page in PAE mode.
1053	*
1054	* This will try interpret the instruction, if failure fail back to the recompiler.
1055	* Check if the changed PDEs are marked present and conflicts with our
1056	* mappings. If conflict, we'll switch to the host context and resolve it there
1057	*
1058	* @returns VBox status code (appropritate for trap handling and GC return).
1059	* @param pVM VM Handle.
1060	* @param uErrorCode CPU Error code.
1061	* @param pRegFrame Trap register frame.
1062	* @param pvFault The fault address (cr2).
1063	* @param GCPhysFault The GC physical address corresponding to pvFault.
1064	* @param pvUser User argument.
1065	*/
1066	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1067	{
1068	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1069
1070	/*
1071	* Try interpret the instruction.
1072	*/
1073	uint32_t cb;
1074	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1075	if (VBOX_SUCCESS(rc) && cb)
1076	{
1077	/*
1078	* Check if any of the PDs have changed.
1079	* We'll simply check all of them instead of figuring out which one/two to check.
1080	*/
1081	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1082	{
1083	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1084	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1085	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1086	{
1087	/*
1088	* The PDPE has changed.
1089	* We will schedule a monitoring update for the next TLB Flush,
1090	* InvalidatePage or SyncCR3.
1091	*
1092	* This isn't perfect, because a lazy page sync might be dealing with an half
1093	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1094	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1095	* executing.
1096	*/
1097	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1098	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1099	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1100	}
1101	}
1102
1103	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1104	}
1105	else
1106	{
1107	Assert(VBOX_FAILURE(rc));
1108	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1109	if (rc == VERR_EM_INTERPRETER)
1110	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1111	}
1112	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1113	return rc;
1114	}
1115
1116
1117	/**
1118	* Write access handler for the Guest PDs in PAE mode.
1119	*
1120	* This will try interpret the instruction, if failure fail back to the recompiler.
1121	* Check if the changed PDEs are marked present and conflicts with our
1122	* mappings. If conflict, we'll switch to the host context and resolve it there
1123	*
1124	* @returns VBox status code (appropritate for trap handling and GC return).
1125	* @param pVM VM Handle.
1126	* @param uErrorCode CPU Error code.
1127	* @param pRegFrame Trap register frame.
1128	* @param pvFault The fault address (cr2).
1129	* @param GCPhysFault The GC physical address corresponding to pvFault.
1130	* @param pvUser User argument.
1131	*/
1132	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1133	{
1134	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1135
1136	/*
1137	* Try interpret the instruction.
1138	*/
1139	uint32_t cb;
1140	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1141	if (VBOX_SUCCESS(rc) && cb)
1142	{
1143	/*
1144	* Figure out which of the 4 PDs this is.
1145	*/
1146	RTGCUINTPTR i;
1147	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1148	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1149	{
1150	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1151	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1152	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1153	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1154
1155	Assert(cb > 0 && cb <= 8);
1156	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1157	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1158
1159	#ifdef DEBUG
1160	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1161	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1162	if (iPD1 != iPD2)
1163	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1164	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1165	#endif
1166
1167	if (!pVM->pgm.s.fMappingsFixed)
1168	{
1169	if ( ( pPDSrc->a[iPD1].n.u1Present
1170	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1171	\|\| ( iPD1 != iPD2
1172	&& pPDSrc->a[iPD2].n.u1Present
1173	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1174	)
1175	{
1176	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1177	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1178	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1179	return VINF_PGM_SYNC_CR3;
1180	}
1181	}
1182	break; /* ASSUMES no duplicate entries... */
1183	}
1184	Assert(i < 4);
1185
1186	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1187	}
1188	else
1189	{
1190	Assert(VBOX_FAILURE(rc));
1191	if (rc == VERR_EM_INTERPRETER)
1192	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1193	else
1194	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1195	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1196	}
1197	return rc;
1198	}
1199
1200	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1201

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 13796

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