PGMAllGst.h@ 14141

Last change on this file since 14141 was 14141, checked in by vboxsync, 16 years ago
PGM: More union returns.
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1	/* $Id: PGMAllGst.h 14141 2008-11-12 19:12:30Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48	#undef GST_PDPE_PG_MASK
49	#undef GST_GET_PDE_BIG_PG_GCPHYS
50
51	#if PGM_GST_TYPE == PGM_TYPE_REAL \
52	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
53	# define GSTPT SHWPT
54	# define PGSTPT PSHWPT
55	# define GSTPTE SHWPTE
56	# define PGSTPTE PSHWPTE
57	# define GSTPD SHWPD
58	# define PGSTPD PSHWPD
59	# define GSTPDE SHWPDE
60	# define PGSTPDE PSHWPDE
61	# define GST_PTE_PG_MASK SHW_PTE_PG_MASK
62
63	#elif PGM_GST_TYPE == PGM_TYPE_32BIT
64	# define GSTPT X86PT
65	# define PGSTPT PX86PT
66	# define GSTPTE X86PTE
67	# define PGSTPTE PX86PTE
68	# define GSTPD X86PD
69	# define PGSTPD PX86PD
70	# define GSTPDE X86PDE
71	# define PGSTPDE PX86PDE
72	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
73	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
74	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
75	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
76	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
77	# define GST_PD_SHIFT X86_PD_SHIFT
78	# define GST_PD_MASK X86_PD_MASK
79	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
80	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
81	# define GST_PT_SHIFT X86_PT_SHIFT
82	# define GST_PT_MASK X86_PT_MASK
83	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
84
85	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
86	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
87	# define GSTPT X86PTPAE
88	# define PGSTPT PX86PTPAE
89	# define GSTPTE X86PTEPAE
90	# define PGSTPTE PX86PTEPAE
91	# define GSTPD X86PDPAE
92	# define PGSTPD PX86PDPAE
93	# define GSTPDE X86PDEPAE
94	# define PGSTPDE PX86PDEPAE
95	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
96	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
97	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
98	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
99	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) (PdeGst.u & GST_PDE_BIG_PG_MASK)
100	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
101	# define GST_PD_MASK X86_PD_PAE_MASK
102	# if PGM_GST_TYPE == PGM_TYPE_PAE
103	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
104	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
105	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
106	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
107	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
108	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
109	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
110	# else
111	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
112	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
113	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
114	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
115	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
116	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
117	# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
118	# endif
119	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
120	# define GST_PT_MASK X86_PT_PAE_MASK
121	#endif
122
123
124	/*******************************************************************************
125	* Internal Functions *
126	*******************************************************************************/
127	__BEGIN_DECLS
128	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
129	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
130	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE);
131	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
132	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
133	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
134	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
135	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
136	#ifndef IN_RING3
137	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
138	# if PGM_GST_TYPE == PGM_TYPE_PAE \
139	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
140	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
141	# endif
142	#endif
143	__END_DECLS
144
145
146
147	/**
148	* Gets effective Guest OS page information.
149	*
150	* When GCPtr is in a big page, the function will return as if it was a normal
151	* 4KB page. If the need for distinguishing between big and normal page becomes
152	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
153	* purpose.
154	*
155	* @returns VBox status.
156	* @param pVM VM Handle.
157	* @param GCPtr Guest Context virtual address of the page. Page aligned!
158	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
159	* @param pGCPhys Where to store the GC physical address of the page.
160	* This is page aligned. The fact that the
161	*/
162	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
163	{
164	#if PGM_GST_TYPE == PGM_TYPE_REAL \
165	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
166	/*
167	* Fake it.
168	*/
169	if (pfFlags)
170	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
171	if (pGCPhys)
172	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
173	return VINF_SUCCESS;
174
175	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
176
177	/*
178	* Get the PDE.
179	*/
180	# if PGM_GST_TYPE == PGM_TYPE_32BIT
181	X86PDE Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
182
183	#elif PGM_GST_TYPE == PGM_TYPE_PAE
184	X86PDEPAE Pde;
185	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
186
187	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
188	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
189	*/
190	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
191
192	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
193	PX86PML4E pPml4e;
194	X86PDPE Pdpe;
195	X86PDEPAE Pde;
196	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
197
198	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
199	Assert(pPml4e);
200	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
201	return VERR_PAGE_TABLE_NOT_PRESENT;
202
203	/* Merge accessed, write, user and no-execute bits into the PDE. */
204	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
205	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
206	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
207	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
208	# endif
209
210	/*
211	* Lookup the page.
212	*/
213	if (!Pde.n.u1Present)
214	return VERR_PAGE_TABLE_NOT_PRESENT;
215
216	if ( !Pde.b.u1Size
217	# if PGM_GST_TYPE != PGM_TYPE_AMD64
218	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
219	# endif
220	)
221	{
222	PGSTPT pPT;
223	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
224	if (RT_FAILURE(rc))
225	return rc;
226
227	/*
228	* Get PT entry and check presence.
229	*/
230	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
231	if (!Pte.n.u1Present)
232	return VERR_PAGE_NOT_PRESENT;
233
234	/*
235	* Store the result.
236	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
237	* where the PDPE is simplified.
238	*/
239	if (pfFlags)
240	{
241	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
242	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
243	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
244	/* The NX bit is determined by a bitwise OR between the PT and PD */
245	if (fNoExecuteBitValid)
246	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
247	# endif
248	}
249	if (pGCPhys)
250	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
251	}
252	else
253	{
254	/*
255	* Map big to 4k PTE and store the result
256	*/
257	if (pfFlags)
258	{
259	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
260	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
261	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
262	/* The NX bit is determined by a bitwise OR between the PT and PD */
263	if (fNoExecuteBitValid)
264	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
265	# endif
266	}
267	if (pGCPhys)
268	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
269	}
270	return VINF_SUCCESS;
271	#else
272	# error "shouldn't be here!"
273	/* something else... */
274	return VERR_NOT_SUPPORTED;
275	#endif
276	}
277
278
279	/**
280	* Modify page flags for a range of pages in the guest's tables
281	*
282	* The existing flags are ANDed with the fMask and ORed with the fFlags.
283	*
284	* @returns VBox status code.
285	* @param pVM VM handle.
286	* @param GCPtr Virtual address of the first page in the range. Page aligned!
287	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
288	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
289	* @param fMask The AND mask - page flags X86_PTE_*.
290	*/
291	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
292	{
293	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
294	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
295	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
296
297	for (;;)
298	{
299	/*
300	* Get the PD entry.
301	*/
302	# if PGM_GST_TYPE == PGM_TYPE_32BIT
303	PX86PDE pPde = pgmGstGet32bitPDEPtr(&pVM->pgm.s, GCPtr);
304
305	# elif PGM_GST_TYPE == PGM_TYPE_PAE
306	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
307	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
308	*/
309	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
310	Assert(pPde);
311	if (!pPde)
312	return VERR_PAGE_TABLE_NOT_PRESENT;
313	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
314	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
315	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
316	Assert(pPde);
317	if (!pPde)
318	return VERR_PAGE_TABLE_NOT_PRESENT;
319	# endif
320	GSTPDE Pde = *pPde;
321	Assert(Pde.n.u1Present);
322	if (!Pde.n.u1Present)
323	return VERR_PAGE_TABLE_NOT_PRESENT;
324
325	if ( !Pde.b.u1Size
326	# if PGM_GST_TYPE != PGM_TYPE_AMD64
327	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
328	# endif
329	)
330	{
331	/*
332	* 4KB Page table
333	*
334	* Walk page tables and pages till we're done.
335	*/
336	PGSTPT pPT;
337	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
338	if (RT_FAILURE(rc))
339	return rc;
340
341	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
342	while (iPTE < RT_ELEMENTS(pPT->a))
343	{
344	GSTPTE Pte = pPT->a[iPTE];
345	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
346	\| (fFlags & ~GST_PTE_PG_MASK);
347	pPT->a[iPTE] = Pte;
348
349	/* next page */
350	cb -= PAGE_SIZE;
351	if (!cb)
352	return VINF_SUCCESS;
353	GCPtr += PAGE_SIZE;
354	iPTE++;
355	}
356	}
357	else
358	{
359	/*
360	* 4MB Page table
361	*/
362	# if PGM_GST_TYPE == PGM_TYPE_32BIT
363	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
364	# else
365	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
366	# endif
367	\| (fFlags & ~GST_PTE_PG_MASK)
368	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
369	*pPde = Pde;
370
371	/* advance */
372	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
373	if (cbDone >= cb)
374	return VINF_SUCCESS;
375	cb -= cbDone;
376	GCPtr += cbDone;
377	}
378	}
379
380	#else
381	/* real / protected mode: ignore. */
382	return VINF_SUCCESS;
383	#endif
384	}
385
386
387	/**
388	* Retrieve guest PDE information
389	*
390	* @returns VBox status code.
391	* @param pVM The virtual machine.
392	* @param GCPtr Guest context pointer
393	* @param pPDE Pointer to guest PDE structure
394	*/
395	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE)
396	{
397	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
398	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
399	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
400
401	# if PGM_GST_TYPE == PGM_TYPE_32BIT
402	X86PDE Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
403	# elif PGM_GST_TYPE == PGM_TYPE_PAE
404	X86PDEPAE Pde;
405	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
406	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
407	X86PDEPAE Pde;
408	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
409	# endif
410
411	pPDE->u = (X86PGPAEUINT)Pde.u;
412	return VINF_SUCCESS;
413	#else
414	AssertFailed();
415	return VERR_NOT_IMPLEMENTED;
416	#endif
417	}
418
419
420
421	/**
422	* Maps the CR3 into HMA in GC and locate it in HC.
423	*
424	* Note that a MapCR3 call is usually not followed by an UnmapCR3 call; whenever
425	* CR3 is updated we simply call MapCR3 again.
426	*
427	* @returns VBox status, no specials.
428	* @param pVM VM handle.
429	* @param GCPhysCR3 The physical address in the CR3 register.
430	*/
431	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
432	{
433	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
434	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
435	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
436
437	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
438
439	/*
440	* Map the page CR3 points at.
441	*/
442	RTHCPHYS HCPhysGuestCR3;
443	RTHCPTR HCPtrGuestCR3;
444	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
445	if (RT_SUCCESS(rc))
446	{
447	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
448	if (RT_SUCCESS(rc))
449	{
450	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
451	# if PGM_GST_TYPE == PGM_TYPE_32BIT
452	pVM->pgm.s.pGuestPDR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
453	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
454	pVM->pgm.s.pGuestPDR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
455	# endif
456	pVM->pgm.s.pGuestPDRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
457
458	# elif PGM_GST_TYPE == PGM_TYPE_PAE
459	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
460	pVM->pgm.s.pGstPaePDPTR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
461	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
462	pVM->pgm.s.pGstPaePDPTR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
463	# endif
464	pVM->pgm.s.pGstPaePDPTRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
465	Log(("Cached mapping %RGv\n", pVM->pgm.s.pGstPaePDPTRC));
466
467	/*
468	* Map the 4 PDs too.
469	*/
470	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
471	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
472	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
473	{
474	if (pGuestPDPT->a[i].n.u1Present)
475	{
476	RTHCPTR HCPtr;
477	RTHCPHYS HCPhys;
478	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
479	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
480	if (RT_SUCCESS(rc2))
481	{
482	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
483	AssertRCReturn(rc, rc);
484
485	pVM->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
486	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
487	pVM->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
488	# endif
489	pVM->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
490	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
491	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
492	continue;
493	}
494	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
495	}
496
497	pVM->pgm.s.apGstPaePDsR3[i] = 0;
498	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
499	pVM->pgm.s.apGstPaePDsR0[i] = 0;
500	# endif
501	pVM->pgm.s.apGstPaePDsRC[i] = 0;
502	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
503	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
504	}
505
506	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
507	pVM->pgm.s.pGstAmd64PML4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
508	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
509	pVM->pgm.s.pGstAmd64PML4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
510	# endif
511	if (!HWACCMIsNestedPagingActive(pVM))
512	{
513	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
514	if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3))
515	{
516	/* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
517	if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->enmKind != PGMPOOLKIND_FREE)
518	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->GCPhys >> PAGE_SHIFT);
519	pVM->pgm.s.CTX_SUFF(pShwAmd64CR3) = 0;
520	pVM->pgm.s.pShwPaePml4R3 = 0;
521	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
522	pVM->pgm.s.pShwPaePml4R0 = 0;
523	# endif
524	pVM->pgm.s.HCPhysPaePML4 = 0;
525	}
526
527	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
528	l_try_again:
529	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
530	if (rc == VERR_PGM_POOL_FLUSHED)
531	{
532	Log(("MapCR3: Flush pool and try again\n"));
533	Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
534	rc = pgmPoolSyncCR3(pVM);
535	AssertRC(rc);
536	goto l_try_again;
537	}
538	# ifdef IN_RING0
539	pVM->pgm.s.pShwAmd64CR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
540	# else
541	pVM->pgm.s.pShwAmd64CR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
542	# endif
543	pVM->pgm.s.pShwPaePml4R3 = (R3PTRTYPE(PX86PML4))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
544	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
545	pVM->pgm.s.pShwPaePml4R0 = (R0PTRTYPE(PX86PML4))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
546	# endif
547	pVM->pgm.s.HCPhysPaePML4 = pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->Core.Key;
548	}
549	# endif
550	}
551	else
552	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
553	}
554	else
555	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
556
557	#else /* prot/real stub */
558	int rc = VINF_SUCCESS;
559	#endif
560	return rc;
561	}
562
563
564	/**
565	* Unmaps the CR3.
566	*
567	* @returns VBox status, no specials.
568	* @param pVM VM handle.
569	*/
570	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
571	{
572	LogFlow(("UnmapCR3\n"));
573
574	int rc = VINF_SUCCESS;
575
576	#if PGM_GST_TYPE == PGM_TYPE_32BIT
577	pVM->pgm.s.pGuestPDR3 = 0;
578	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
579	pVM->pgm.s.pGuestPDR0 = 0;
580	#endif
581	pVM->pgm.s.pGuestPDRC = 0;
582
583	#elif PGM_GST_TYPE == PGM_TYPE_PAE
584	pVM->pgm.s.pGstPaePDPTR3 = 0;
585	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
586	pVM->pgm.s.pGstPaePDPTR0 = 0;
587	# endif
588	pVM->pgm.s.pGstPaePDPTRC = 0;
589	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
590	{
591	pVM->pgm.s.apGstPaePDsR3[i] = 0;
592	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
593	pVM->pgm.s.apGstPaePDsR0[i] = 0;
594	# endif
595	pVM->pgm.s.apGstPaePDsRC[i] = 0;
596	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
597	}
598
599	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
600	pVM->pgm.s.pGstAmd64PML4R3 = 0;
601	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
602	pVM->pgm.s.pGstAmd64PML4R0 = 0;
603	# endif
604	if (!HWACCMIsNestedPagingActive(pVM))
605	{
606	pVM->pgm.s.pShwPaePml4R3 = 0;
607	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
608	pVM->pgm.s.pShwPaePml4R0 = 0;
609	# endif
610	pVM->pgm.s.HCPhysPaePML4 = 0;
611	if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3))
612	{
613	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
614	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->GCPhys >> PAGE_SHIFT);
615	pVM->pgm.s.pShwAmd64CR3R3 = 0;
616	pVM->pgm.s.pShwAmd64CR3R0 = 0;
617	}
618	}
619
620	#else /* prot/real mode stub */
621	/* nothing to do */
622	#endif
623	return rc;
624	}
625
626
627	#undef LOG_GROUP
628	#define LOG_GROUP LOG_GROUP_PGM_POOL
629
630	/**
631	* Registers physical page monitors for the necessary paging
632	* structures to detect conflicts with our guest mappings.
633	*
634	* This is always called after mapping CR3.
635	* This is never called with fixed mappings.
636	*
637	* @returns VBox status, no specials.
638	* @param pVM VM handle.
639	* @param GCPhysCR3 The physical address in the CR3 register.
640	*/
641	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
642	{
643	Assert(!pVM->pgm.s.fMappingsFixed);
644	int rc = VINF_SUCCESS;
645
646	/*
647	* Register/Modify write phys handler for guest's CR3 if it changed.
648	*/
649	#if PGM_GST_TYPE == PGM_TYPE_32BIT
650
651	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
652	{
653	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
654	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
655	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
656	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
657	else
658	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
659	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
660	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
661	pVM->pgm.s.pfnRCGstWriteHandlerCR3, 0,
662	pVM->pgm.s.pszR3GstWriteHandlerCR3);
663	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
664	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
665	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
666	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
667	? PGMPOOL_IDX_PAE_PD
668	: PGMPOOL_IDX_PD,
669	GCPhysCR3);
670	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
671	if (RT_FAILURE(rc))
672	{
673	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
674	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
675	return rc;
676	}
677	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
678	}
679
680	#elif PGM_GST_TYPE == PGM_TYPE_PAE
681	/* Monitor the PDPT page */
682	/*
683	* Register/Modify write phys handler for guest's CR3 if it changed.
684	*/
685	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
686	AssertFailed();
687	# endif
688	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
689	{
690	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
691	if (RT_FAILURE(rc))
692	{
693	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
694	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
695	return rc;
696	}
697	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
698	}
699
700	/*
701	* Do the 4 PDs.
702	*/
703	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
704	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
705	{
706	if (pGuestPDPT->a[i].n.u1Present)
707	{
708	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
709	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
710	{
711	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
712
713	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
714	}
715
716	if (RT_FAILURE(rc))
717	{
718	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
719	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
720	return rc;
721	}
722	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
723	}
724	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
725	{
726	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
727	AssertRC(rc);
728	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
729	}
730	}
731
732	#else
733	/* prot/real/amd64 mode stub */
734
735	#endif
736	return rc;
737	}
738
739	/**
740	* Deregisters any physical page monitors installed by MonitorCR3.
741	*
742	* @returns VBox status code, no specials.
743	* @param pVM The VM handle.
744	*/
745	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
746	{
747	int rc = VINF_SUCCESS;
748
749	/*
750	* Deregister the access handlers.
751	*
752	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
753	* before we enter GC again.
754	*/
755	#if PGM_GST_TYPE == PGM_TYPE_32BIT
756	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
757	{
758	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
759	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
760	AssertRCReturn(rc, rc);
761	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
762	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
763	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
764	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
765	? PGMPOOL_IDX_PAE_PD
766	: PGMPOOL_IDX_PD);
767	AssertRCReturn(rc, rc);
768	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
769	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
770	}
771
772	#elif PGM_GST_TYPE == PGM_TYPE_PAE
773	/* The PDPT page */
774	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
775	AssertFailed();
776	# endif
777
778	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
779	{
780	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT);
781	AssertRC(rc);
782	}
783
784	/* The 4 PDs. */
785	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
786	{
787	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
788	{
789	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
790	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
791	AssertRC(rc2);
792	if (RT_FAILURE(rc2))
793	rc = rc2;
794	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
795	}
796	}
797	#else
798	/* prot/real/amd64 mode stub */
799	#endif
800	return rc;
801
802	}
803
804	#undef LOG_GROUP
805	#define LOG_GROUP LOG_GROUP_PGM
806
807
808	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
809	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
810	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
811	/**
812	* Updates one virtual handler range.
813	*
814	* @returns 0
815	* @param pNode Pointer to a PGMVIRTHANDLER.
816	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
817	*/
818	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
819	{
820	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
821	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
822	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
823
824	#if PGM_GST_TYPE == PGM_TYPE_32BIT
825	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pState->pVM->pgm.s);
826	#endif
827
828	RTGCPTR GCPtr = pCur->Core.Key;
829	#if PGM_GST_MODE != PGM_MODE_AMD64
830	/* skip all stuff above 4GB if not AMD64 mode. */
831	if (GCPtr >= _4GB)
832	return 0;
833	#endif
834
835	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
836	unsigned iPage = 0;
837	while (iPage < pCur->cPages)
838	{
839	#if PGM_GST_TYPE == PGM_TYPE_32BIT
840	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
841	#elif PGM_GST_TYPE == PGM_TYPE_PAE
842	X86PDEPAE Pde;
843	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
844	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
845	X86PDEPAE Pde;
846	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
847	#endif
848	if (Pde.n.u1Present)
849	{
850	if ( !Pde.b.u1Size
851	# if PGM_GST_TYPE != PGM_TYPE_AMD64
852	\|\| !(pState->cr4 & X86_CR4_PSE)
853	# endif
854	)
855	{
856	/*
857	* Normal page table.
858	*/
859	PGSTPT pPT;
860	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
861	if (RT_SUCCESS(rc))
862	{
863	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
864	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
865	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
866	{
867	GSTPTE Pte = pPT->a[iPTE];
868	RTGCPHYS GCPhysNew;
869	if (Pte.n.u1Present)
870	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
871	else
872	GCPhysNew = NIL_RTGCPHYS;
873	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
874	{
875	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
876	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
877	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
878	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
879	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
880	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
881	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
882	#endif
883	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
884	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
885	}
886	}
887	}
888	else
889	{
890	/* not-present. */
891	offPage = 0;
892	AssertRC(rc);
893	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
894	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
895	iPTE++, iPage++, GCPtr += PAGE_SIZE)
896	{
897	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
898	{
899	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
900	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
901	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
902	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
903	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
904	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
905	#endif
906	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
907	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
908	}
909	}
910	}
911	}
912	else
913	{
914	/*
915	* 2/4MB page.
916	*/
917	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
918	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
919	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
920	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
921	{
922	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
923	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
924	{
925	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
926	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
927	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
928	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
929	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
930	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
931	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
932	#endif
933	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
934	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
935	}
936	}
937	} /* pde type */
938	}
939	else
940	{
941	/* not-present. */
942	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
943	cPages && iPage < pCur->cPages;
944	iPage++, GCPtr += PAGE_SIZE)
945	{
946	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
947	{
948	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
949	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
950	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
951	}
952	}
953	offPage = 0;
954	}
955	} /* for pages in virtual mapping. */
956
957	return 0;
958	}
959	#endif /* 32BIT, PAE and AMD64 */
960
961
962	/**
963	* Updates the virtual page access handlers.
964	*
965	* @returns true if bits were flushed.
966	* @returns false if bits weren't flushed.
967	* @param pVM VM handle.
968	* @param pPDSrc The page directory.
969	* @param cr4 The cr4 register value.
970	*/
971	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
972	{
973	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
974	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
975	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
976
977	/** @todo
978	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
979	*/
980
981	/*
982	* Resolve any virtual address based access handlers to GC physical addresses.
983	* This should be fairly quick.
984	*/
985	PGMHVUSTATE State;
986
987	pgmLock(pVM);
988	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
989	State.pVM = pVM;
990	State.fTodo = pVM->pgm.s.fSyncFlags;
991	State.cr4 = cr4;
992	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
993	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
994
995
996	/*
997	* Set / reset bits?
998	*/
999	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
1000	{
1001	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
1002	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
1003	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
1004	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
1005	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
1006	}
1007	pgmUnlock(pVM);
1008
1009	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
1010
1011	#else /* real / protected */
1012	return false;
1013	#endif
1014	}
1015
1016
1017	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
1018
1019	/**
1020	* Write access handler for the Guest CR3 page in 32-bit mode.
1021	*
1022	* This will try interpret the instruction, if failure fail back to the recompiler.
1023	* Check if the changed PDEs are marked present and conflicts with our
1024	* mappings. If conflict, we'll switch to the host context and resolve it there
1025	*
1026	* @returns VBox status code (appropritate for trap handling and GC return).
1027	* @param pVM VM Handle.
1028	* @param uErrorCode CPU Error code.
1029	* @param pRegFrame Trap register frame.
1030	* @param pvFault The fault address (cr2).
1031	* @param GCPhysFault The GC physical address corresponding to pvFault.
1032	* @param pvUser User argument.
1033	*/
1034	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1035	{
1036	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1037
1038	/*
1039	* Try interpret the instruction.
1040	*/
1041	uint32_t cb;
1042	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1043	if (RT_SUCCESS(rc) && cb)
1044	{
1045	/*
1046	* Check if the modified PDEs are present and mappings.
1047	*/
1048	const RTGCPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1049	const unsigned iPD1 = offPD / sizeof(X86PDE);
1050	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
1051
1052	Assert(cb > 0 && cb <= 8);
1053	Assert(iPD1 < X86_PG_ENTRIES);
1054	Assert(iPD2 < X86_PG_ENTRIES);
1055
1056	#ifdef DEBUG
1057	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%x\n", iPD1, iPD1 << X86_PD_SHIFT));
1058	if (iPD1 != iPD2)
1059	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%x\n", iPD2, iPD2 << X86_PD_SHIFT));
1060	#endif
1061
1062	if (!pVM->pgm.s.fMappingsFixed)
1063	{
1064	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
1065	if ( ( pPDSrc->a[iPD1].n.u1Present
1066	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
1067	\|\| ( iPD1 != iPD2
1068	&& pPDSrc->a[iPD2].n.u1Present
1069	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
1070	)
1071	{
1072	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1073	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1074	if (rc == VINF_SUCCESS)
1075	rc = VINF_PGM_SYNC_CR3;
1076	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
1077	return rc;
1078	}
1079	}
1080
1081	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1082	}
1083	else
1084	{
1085	Assert(RT_FAILURE(rc));
1086	if (rc == VERR_EM_INTERPRETER)
1087	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1088	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1089	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1090	}
1091	return rc;
1092	}
1093
1094	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
1095	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
1096
1097	/**
1098	* Write access handler for the Guest CR3 page in PAE mode.
1099	*
1100	* This will try interpret the instruction, if failure fail back to the recompiler.
1101	* Check if the changed PDEs are marked present and conflicts with our
1102	* mappings. If conflict, we'll switch to the host context and resolve it there
1103	*
1104	* @returns VBox status code (appropritate for trap handling and GC return).
1105	* @param pVM VM Handle.
1106	* @param uErrorCode CPU Error code.
1107	* @param pRegFrame Trap register frame.
1108	* @param pvFault The fault address (cr2).
1109	* @param GCPhysFault The GC physical address corresponding to pvFault.
1110	* @param pvUser User argument.
1111	*/
1112	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1113	{
1114	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1115
1116	/*
1117	* Try interpret the instruction.
1118	*/
1119	uint32_t cb;
1120	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1121	if (RT_SUCCESS(rc) && cb)
1122	{
1123	/*
1124	* Check if any of the PDs have changed.
1125	* We'll simply check all of them instead of figuring out which one/two to check.
1126	*/
1127	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
1128	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1129	{
1130	if ( pGuestPDPT->a[i].n.u1Present
1131	&& (pGuestPDPT->a[i].u & X86_PDPE_PG_MASK)
1132	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1133	{
1134	/*
1135	* The PDPE has changed.
1136	* We will schedule a monitoring update for the next TLB Flush,
1137	* InvalidatePage or SyncCR3.
1138	*
1139	* This isn't perfect, because a lazy page sync might be dealing with an half
1140	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1141	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1142	* executing.
1143	*/
1144	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1145	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%RGp\n",
1146	i, pGuestPDPT->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1147	}
1148	}
1149
1150	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1151	}
1152	else
1153	{
1154	Assert(RT_FAILURE(rc));
1155	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1156	if (rc == VERR_EM_INTERPRETER)
1157	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1158	}
1159	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1160	return rc;
1161	}
1162
1163
1164	/**
1165	* Write access handler for the Guest PDs in PAE mode.
1166	*
1167	* This will try interpret the instruction, if failure fail back to the recompiler.
1168	* Check if the changed PDEs are marked present and conflicts with our
1169	* mappings. If conflict, we'll switch to the host context and resolve it there
1170	*
1171	* @returns VBox status code (appropritate for trap handling and GC return).
1172	* @param pVM VM Handle.
1173	* @param uErrorCode CPU Error code.
1174	* @param pRegFrame Trap register frame.
1175	* @param pvFault The fault address (cr2).
1176	* @param GCPhysFault The GC physical address corresponding to pvFault.
1177	* @param pvUser User argument.
1178	*/
1179	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1180	{
1181	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1182
1183	/*
1184	* Try interpret the instruction.
1185	*/
1186	uint32_t cb;
1187	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1188	if (RT_SUCCESS(rc) && cb)
1189	{
1190	/*
1191	* Figure out which of the 4 PDs this is.
1192	*/
1193	RTGCPTR i;
1194	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
1195	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1196	if (pGuestPDPT->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1197	{
1198	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1199	const RTGCPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1200	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1201	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1202
1203	Assert(cb > 0 && cb <= 8);
1204	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1205	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1206
1207	# ifdef LOG_ENABLED
1208	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%x)\n",
1209	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1210	if (iPD1 != iPD2)
1211	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%x)\n",
1212	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1213	# endif
1214
1215	if (!pVM->pgm.s.fMappingsFixed)
1216	{
1217	if ( ( pPDSrc->a[iPD1].n.u1Present
1218	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1219	\|\| ( iPD1 != iPD2
1220	&& pPDSrc->a[iPD2].n.u1Present
1221	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1222	)
1223	{
1224	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1225	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1226	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1227	return VINF_PGM_SYNC_CR3;
1228	}
1229	}
1230	break; /* ASSUMES no duplicate entries... */
1231	}
1232	Assert(i < 4);
1233
1234	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1235	}
1236	else
1237	{
1238	Assert(RT_FAILURE(rc));
1239	if (rc == VERR_EM_INTERPRETER)
1240	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1241	else
1242	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1243	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1244	}
1245	return rc;
1246	}
1247
1248	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1249

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 14141

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