PGMAllGst.h@ 14153

Last change on this file since 14153 was 14153, checked in by vboxsync, 16 years ago
PGM: pGstPaePDPT -> pGstPaePdpt
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 46.6 KB

Line
1	/* $Id: PGMAllGst.h 14153 2008-11-12 23:30:34Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48	#undef GST_PDPE_PG_MASK
49	#undef GST_GET_PDE_BIG_PG_GCPHYS
50
51	#if PGM_GST_TYPE == PGM_TYPE_REAL \
52	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
53	# define GSTPT SHWPT
54	# define PGSTPT PSHWPT
55	# define GSTPTE SHWPTE
56	# define PGSTPTE PSHWPTE
57	# define GSTPD SHWPD
58	# define PGSTPD PSHWPD
59	# define GSTPDE SHWPDE
60	# define PGSTPDE PSHWPDE
61	# define GST_PTE_PG_MASK SHW_PTE_PG_MASK
62
63	#elif PGM_GST_TYPE == PGM_TYPE_32BIT
64	# define GSTPT X86PT
65	# define PGSTPT PX86PT
66	# define GSTPTE X86PTE
67	# define PGSTPTE PX86PTE
68	# define GSTPD X86PD
69	# define PGSTPD PX86PD
70	# define GSTPDE X86PDE
71	# define PGSTPDE PX86PDE
72	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
73	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
74	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
75	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
76	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
77	# define GST_PD_SHIFT X86_PD_SHIFT
78	# define GST_PD_MASK X86_PD_MASK
79	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
80	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
81	# define GST_PT_SHIFT X86_PT_SHIFT
82	# define GST_PT_MASK X86_PT_MASK
83	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
84
85	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
86	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
87	# define GSTPT X86PTPAE
88	# define PGSTPT PX86PTPAE
89	# define GSTPTE X86PTEPAE
90	# define PGSTPTE PX86PTEPAE
91	# define GSTPD X86PDPAE
92	# define PGSTPD PX86PDPAE
93	# define GSTPDE X86PDEPAE
94	# define PGSTPDE PX86PDEPAE
95	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
96	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
97	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
98	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
99	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) (PdeGst.u & GST_PDE_BIG_PG_MASK)
100	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
101	# define GST_PD_MASK X86_PD_PAE_MASK
102	# if PGM_GST_TYPE == PGM_TYPE_PAE
103	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
104	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
105	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
106	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
107	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
108	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
109	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
110	# else
111	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
112	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
113	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
114	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
115	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
116	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
117	# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
118	# endif
119	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
120	# define GST_PT_MASK X86_PT_PAE_MASK
121	#endif
122
123
124	/*******************************************************************************
125	* Internal Functions *
126	*******************************************************************************/
127	__BEGIN_DECLS
128	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
129	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
130	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE);
131	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
132	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
133	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
134	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
135	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
136	#ifndef IN_RING3
137	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
138	# if PGM_GST_TYPE == PGM_TYPE_PAE \
139	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
140	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
141	# endif
142	#endif
143	__END_DECLS
144
145
146
147	/**
148	* Gets effective Guest OS page information.
149	*
150	* When GCPtr is in a big page, the function will return as if it was a normal
151	* 4KB page. If the need for distinguishing between big and normal page becomes
152	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
153	* purpose.
154	*
155	* @returns VBox status.
156	* @param pVM VM Handle.
157	* @param GCPtr Guest Context virtual address of the page. Page aligned!
158	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
159	* @param pGCPhys Where to store the GC physical address of the page.
160	* This is page aligned. The fact that the
161	*/
162	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
163	{
164	#if PGM_GST_TYPE == PGM_TYPE_REAL \
165	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
166	/*
167	* Fake it.
168	*/
169	if (pfFlags)
170	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
171	if (pGCPhys)
172	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
173	return VINF_SUCCESS;
174
175	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
176
177	/*
178	* Get the PDE.
179	*/
180	# if PGM_GST_TYPE == PGM_TYPE_32BIT
181	X86PDE Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
182
183	#elif PGM_GST_TYPE == PGM_TYPE_PAE
184	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present.
185	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx). */
186	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
187	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
188
189	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
190	PX86PML4E pPml4e;
191	X86PDPE Pdpe;
192	X86PDEPAE Pde = pgmGstGetLongModePDEEx(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
193	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
194
195	Assert(pPml4e);
196	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
197	return VERR_PAGE_TABLE_NOT_PRESENT;
198
199	/* Merge accessed, write, user and no-execute bits into the PDE. */
200	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
201	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
202	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
203	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
204	# endif
205
206	/*
207	* Lookup the page.
208	*/
209	if (!Pde.n.u1Present)
210	return VERR_PAGE_TABLE_NOT_PRESENT;
211
212	if ( !Pde.b.u1Size
213	# if PGM_GST_TYPE != PGM_TYPE_AMD64
214	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
215	# endif
216	)
217	{
218	PGSTPT pPT;
219	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
220	if (RT_FAILURE(rc))
221	return rc;
222
223	/*
224	* Get PT entry and check presence.
225	*/
226	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
227	if (!Pte.n.u1Present)
228	return VERR_PAGE_NOT_PRESENT;
229
230	/*
231	* Store the result.
232	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
233	* where the PDPE is simplified.
234	*/
235	if (pfFlags)
236	{
237	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
238	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
239	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
240	/* The NX bit is determined by a bitwise OR between the PT and PD */
241	if (fNoExecuteBitValid)
242	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
243	# endif
244	}
245	if (pGCPhys)
246	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
247	}
248	else
249	{
250	/*
251	* Map big to 4k PTE and store the result
252	*/
253	if (pfFlags)
254	{
255	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
256	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
257	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
258	/* The NX bit is determined by a bitwise OR between the PT and PD */
259	if (fNoExecuteBitValid)
260	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
261	# endif
262	}
263	if (pGCPhys)
264	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
265	}
266	return VINF_SUCCESS;
267	#else
268	# error "shouldn't be here!"
269	/* something else... */
270	return VERR_NOT_SUPPORTED;
271	#endif
272	}
273
274
275	/**
276	* Modify page flags for a range of pages in the guest's tables
277	*
278	* The existing flags are ANDed with the fMask and ORed with the fFlags.
279	*
280	* @returns VBox status code.
281	* @param pVM VM handle.
282	* @param GCPtr Virtual address of the first page in the range. Page aligned!
283	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
284	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
285	* @param fMask The AND mask - page flags X86_PTE_*.
286	*/
287	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
288	{
289	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
290	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
291	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
292
293	for (;;)
294	{
295	/*
296	* Get the PD entry.
297	*/
298	# if PGM_GST_TYPE == PGM_TYPE_32BIT
299	PX86PDE pPde = pgmGstGet32bitPDEPtr(&pVM->pgm.s, GCPtr);
300
301	# elif PGM_GST_TYPE == PGM_TYPE_PAE
302	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
303	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
304	*/
305	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
306	Assert(pPde);
307	if (!pPde)
308	return VERR_PAGE_TABLE_NOT_PRESENT;
309	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
310	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
311	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
312	Assert(pPde);
313	if (!pPde)
314	return VERR_PAGE_TABLE_NOT_PRESENT;
315	# endif
316	GSTPDE Pde = *pPde;
317	Assert(Pde.n.u1Present);
318	if (!Pde.n.u1Present)
319	return VERR_PAGE_TABLE_NOT_PRESENT;
320
321	if ( !Pde.b.u1Size
322	# if PGM_GST_TYPE != PGM_TYPE_AMD64
323	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
324	# endif
325	)
326	{
327	/*
328	* 4KB Page table
329	*
330	* Walk page tables and pages till we're done.
331	*/
332	PGSTPT pPT;
333	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
334	if (RT_FAILURE(rc))
335	return rc;
336
337	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
338	while (iPTE < RT_ELEMENTS(pPT->a))
339	{
340	GSTPTE Pte = pPT->a[iPTE];
341	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
342	\| (fFlags & ~GST_PTE_PG_MASK);
343	pPT->a[iPTE] = Pte;
344
345	/* next page */
346	cb -= PAGE_SIZE;
347	if (!cb)
348	return VINF_SUCCESS;
349	GCPtr += PAGE_SIZE;
350	iPTE++;
351	}
352	}
353	else
354	{
355	/*
356	* 4MB Page table
357	*/
358	# if PGM_GST_TYPE == PGM_TYPE_32BIT
359	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
360	# else
361	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
362	# endif
363	\| (fFlags & ~GST_PTE_PG_MASK)
364	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
365	*pPde = Pde;
366
367	/* advance */
368	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
369	if (cbDone >= cb)
370	return VINF_SUCCESS;
371	cb -= cbDone;
372	GCPtr += cbDone;
373	}
374	}
375
376	#else
377	/* real / protected mode: ignore. */
378	return VINF_SUCCESS;
379	#endif
380	}
381
382
383	/**
384	* Retrieve guest PDE information
385	*
386	* @returns VBox status code.
387	* @param pVM The virtual machine.
388	* @param GCPtr Guest context pointer
389	* @param pPDE Pointer to guest PDE structure
390	*/
391	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE)
392	{
393	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
394	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
395	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
396
397	# if PGM_GST_TYPE == PGM_TYPE_32BIT
398	X86PDE Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
399	# elif PGM_GST_TYPE == PGM_TYPE_PAE
400	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
401	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
402	X86PDEPAE Pde = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
403	# endif
404
405	pPDE->u = (X86PGPAEUINT)Pde.u;
406	return VINF_SUCCESS;
407	#else
408	AssertFailed();
409	return VERR_NOT_IMPLEMENTED;
410	#endif
411	}
412
413
414
415	/**
416	* Maps the CR3 into HMA in GC and locate it in HC.
417	*
418	* Note that a MapCR3 call is usually not followed by an UnmapCR3 call; whenever
419	* CR3 is updated we simply call MapCR3 again.
420	*
421	* @returns VBox status, no specials.
422	* @param pVM VM handle.
423	* @param GCPhysCR3 The physical address in the CR3 register.
424	*/
425	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
426	{
427	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
428	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
429	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
430
431	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
432
433	/*
434	* Map the page CR3 points at.
435	*/
436	RTHCPHYS HCPhysGuestCR3;
437	RTHCPTR HCPtrGuestCR3;
438	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
439	if (RT_SUCCESS(rc))
440	{
441	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
442	if (RT_SUCCESS(rc))
443	{
444	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
445	# if PGM_GST_TYPE == PGM_TYPE_32BIT
446	pVM->pgm.s.pGuestPDR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
447	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
448	pVM->pgm.s.pGuestPDR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
449	# endif
450	pVM->pgm.s.pGuestPDRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
451
452	# elif PGM_GST_TYPE == PGM_TYPE_PAE
453	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
454	pVM->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
455	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
456	pVM->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
457	# endif
458	pVM->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
459	Log(("Cached mapping %RGv\n", pVM->pgm.s.pGstPaePdptRC));
460
461	/*
462	* Map the 4 PDs too.
463	*/
464	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
465	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
466	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
467	{
468	if (pGuestPDPT->a[i].n.u1Present)
469	{
470	RTHCPTR HCPtr;
471	RTHCPHYS HCPhys;
472	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
473	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
474	if (RT_SUCCESS(rc2))
475	{
476	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
477	AssertRCReturn(rc, rc);
478
479	pVM->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
480	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
481	pVM->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
482	# endif
483	pVM->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
484	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
485	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
486	continue;
487	}
488	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
489	}
490
491	pVM->pgm.s.apGstPaePDsR3[i] = 0;
492	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
493	pVM->pgm.s.apGstPaePDsR0[i] = 0;
494	# endif
495	pVM->pgm.s.apGstPaePDsRC[i] = 0;
496	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
497	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
498	}
499
500	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
501	pVM->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
502	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
503	pVM->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
504	# endif
505	if (!HWACCMIsNestedPagingActive(pVM))
506	{
507	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
508	if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3))
509	{
510	/* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
511	if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->enmKind != PGMPOOLKIND_FREE)
512	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->GCPhys >> PAGE_SHIFT);
513	pVM->pgm.s.CTX_SUFF(pShwAmd64CR3) = 0;
514	pVM->pgm.s.pShwPaePml4R3 = 0;
515	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
516	pVM->pgm.s.pShwPaePml4R0 = 0;
517	# endif
518	pVM->pgm.s.HCPhysShwPaePml4 = 0;
519	}
520
521	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
522	l_try_again:
523	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
524	if (rc == VERR_PGM_POOL_FLUSHED)
525	{
526	Log(("MapCR3: Flush pool and try again\n"));
527	Assert(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL);
528	rc = pgmPoolSyncCR3(pVM);
529	AssertRC(rc);
530	goto l_try_again;
531	}
532	# ifdef IN_RING0
533	pVM->pgm.s.pShwAmd64CR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
534	# else
535	pVM->pgm.s.pShwAmd64CR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
536	# endif
537	pVM->pgm.s.pShwPaePml4R3 = (R3PTRTYPE(PX86PML4))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
538	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
539	pVM->pgm.s.pShwPaePml4R0 = (R0PTRTYPE(PX86PML4))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwAmd64CR3));
540	# endif
541	pVM->pgm.s.HCPhysShwPaePml4 = pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->Core.Key;
542	}
543	# endif
544	}
545	else
546	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
547	}
548	else
549	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
550
551	#else /* prot/real stub */
552	int rc = VINF_SUCCESS;
553	#endif
554	return rc;
555	}
556
557
558	/**
559	* Unmaps the CR3.
560	*
561	* @returns VBox status, no specials.
562	* @param pVM VM handle.
563	*/
564	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
565	{
566	LogFlow(("UnmapCR3\n"));
567
568	int rc = VINF_SUCCESS;
569
570	#if PGM_GST_TYPE == PGM_TYPE_32BIT
571	pVM->pgm.s.pGuestPDR3 = 0;
572	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
573	pVM->pgm.s.pGuestPDR0 = 0;
574	#endif
575	pVM->pgm.s.pGuestPDRC = 0;
576
577	#elif PGM_GST_TYPE == PGM_TYPE_PAE
578	pVM->pgm.s.pGstPaePdptR3 = 0;
579	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
580	pVM->pgm.s.pGstPaePdptR0 = 0;
581	# endif
582	pVM->pgm.s.pGstPaePdptRC = 0;
583	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
584	{
585	pVM->pgm.s.apGstPaePDsR3[i] = 0;
586	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
587	pVM->pgm.s.apGstPaePDsR0[i] = 0;
588	# endif
589	pVM->pgm.s.apGstPaePDsRC[i] = 0;
590	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
591	}
592
593	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
594	pVM->pgm.s.pGstAmd64Pml4R3 = 0;
595	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
596	pVM->pgm.s.pGstAmd64Pml4R0 = 0;
597	# endif
598	if (!HWACCMIsNestedPagingActive(pVM))
599	{
600	pVM->pgm.s.pShwPaePml4R3 = 0;
601	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
602	pVM->pgm.s.pShwPaePml4R0 = 0;
603	# endif
604	pVM->pgm.s.HCPhysShwPaePml4 = 0;
605	if (pVM->pgm.s.CTX_SUFF(pShwAmd64CR3))
606	{
607	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
608	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->GCPhys >> PAGE_SHIFT);
609	pVM->pgm.s.pShwAmd64CR3R3 = 0;
610	pVM->pgm.s.pShwAmd64CR3R0 = 0;
611	}
612	}
613
614	#else /* prot/real mode stub */
615	/* nothing to do */
616	#endif
617	return rc;
618	}
619
620
621	#undef LOG_GROUP
622	#define LOG_GROUP LOG_GROUP_PGM_POOL
623
624	/**
625	* Registers physical page monitors for the necessary paging
626	* structures to detect conflicts with our guest mappings.
627	*
628	* This is always called after mapping CR3.
629	* This is never called with fixed mappings.
630	*
631	* @returns VBox status, no specials.
632	* @param pVM VM handle.
633	* @param GCPhysCR3 The physical address in the CR3 register.
634	*/
635	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
636	{
637	Assert(!pVM->pgm.s.fMappingsFixed);
638	int rc = VINF_SUCCESS;
639
640	/*
641	* Register/Modify write phys handler for guest's CR3 if it changed.
642	*/
643	#if PGM_GST_TYPE == PGM_TYPE_32BIT
644
645	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
646	{
647	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
648	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
649	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
650	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
651	else
652	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
653	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
654	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
655	pVM->pgm.s.pfnRCGstWriteHandlerCR3, 0,
656	pVM->pgm.s.pszR3GstWriteHandlerCR3);
657	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
658	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
659	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
660	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
661	? PGMPOOL_IDX_PAE_PD
662	: PGMPOOL_IDX_PD,
663	GCPhysCR3);
664	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
665	if (RT_FAILURE(rc))
666	{
667	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
668	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
669	return rc;
670	}
671	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
672	}
673
674	#elif PGM_GST_TYPE == PGM_TYPE_PAE
675	/* Monitor the PDPT page */
676	/*
677	* Register/Modify write phys handler for guest's CR3 if it changed.
678	*/
679	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
680	AssertFailed();
681	# endif
682	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
683	{
684	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
685	if (RT_FAILURE(rc))
686	{
687	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
688	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
689	return rc;
690	}
691	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
692	}
693
694	/*
695	* Do the 4 PDs.
696	*/
697	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
698	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
699	{
700	if (pGuestPDPT->a[i].n.u1Present)
701	{
702	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
703	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
704	{
705	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
706
707	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
708	}
709
710	if (RT_FAILURE(rc))
711	{
712	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
713	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
714	return rc;
715	}
716	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
717	}
718	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
719	{
720	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
721	AssertRC(rc);
722	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
723	}
724	}
725
726	#else
727	/* prot/real/amd64 mode stub */
728
729	#endif
730	return rc;
731	}
732
733	/**
734	* Deregisters any physical page monitors installed by MonitorCR3.
735	*
736	* @returns VBox status code, no specials.
737	* @param pVM The VM handle.
738	*/
739	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
740	{
741	int rc = VINF_SUCCESS;
742
743	/*
744	* Deregister the access handlers.
745	*
746	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
747	* before we enter GC again.
748	*/
749	#if PGM_GST_TYPE == PGM_TYPE_32BIT
750	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
751	{
752	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
753	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
754	AssertRCReturn(rc, rc);
755	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
756	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
757	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
758	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
759	? PGMPOOL_IDX_PAE_PD
760	: PGMPOOL_IDX_PD);
761	AssertRCReturn(rc, rc);
762	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
763	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
764	}
765
766	#elif PGM_GST_TYPE == PGM_TYPE_PAE
767	/* The PDPT page */
768	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
769	AssertFailed();
770	# endif
771
772	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
773	{
774	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT);
775	AssertRC(rc);
776	}
777
778	/* The 4 PDs. */
779	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
780	{
781	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
782	{
783	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
784	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
785	AssertRC(rc2);
786	if (RT_FAILURE(rc2))
787	rc = rc2;
788	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
789	}
790	}
791	#else
792	/* prot/real/amd64 mode stub */
793	#endif
794	return rc;
795
796	}
797
798	#undef LOG_GROUP
799	#define LOG_GROUP LOG_GROUP_PGM
800
801
802	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
803	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
804	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
805	/**
806	* Updates one virtual handler range.
807	*
808	* @returns 0
809	* @param pNode Pointer to a PGMVIRTHANDLER.
810	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
811	*/
812	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
813	{
814	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
815	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
816	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
817
818	#if PGM_GST_TYPE == PGM_TYPE_32BIT
819	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pState->pVM->pgm.s);
820	#endif
821
822	RTGCPTR GCPtr = pCur->Core.Key;
823	#if PGM_GST_MODE != PGM_MODE_AMD64
824	/* skip all stuff above 4GB if not AMD64 mode. */
825	if (GCPtr >= _4GB)
826	return 0;
827	#endif
828
829	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
830	unsigned iPage = 0;
831	while (iPage < pCur->cPages)
832	{
833	#if PGM_GST_TYPE == PGM_TYPE_32BIT
834	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
835	#elif PGM_GST_TYPE == PGM_TYPE_PAE
836	X86PDEPAE Pde = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
837	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
838	X86PDEPAE Pde = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
839	#endif
840	if (Pde.n.u1Present)
841	{
842	if ( !Pde.b.u1Size
843	# if PGM_GST_TYPE != PGM_TYPE_AMD64
844	\|\| !(pState->cr4 & X86_CR4_PSE)
845	# endif
846	)
847	{
848	/*
849	* Normal page table.
850	*/
851	PGSTPT pPT;
852	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
853	if (RT_SUCCESS(rc))
854	{
855	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
856	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
857	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
858	{
859	GSTPTE Pte = pPT->a[iPTE];
860	RTGCPHYS GCPhysNew;
861	if (Pte.n.u1Present)
862	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
863	else
864	GCPhysNew = NIL_RTGCPHYS;
865	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
866	{
867	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
868	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
869	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
870	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
871	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
872	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
873	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
874	#endif
875	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
876	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
877	}
878	}
879	}
880	else
881	{
882	/* not-present. */
883	offPage = 0;
884	AssertRC(rc);
885	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
886	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
887	iPTE++, iPage++, GCPtr += PAGE_SIZE)
888	{
889	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
890	{
891	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
892	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
893	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
894	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
895	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
896	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
897	#endif
898	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
899	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
900	}
901	}
902	}
903	}
904	else
905	{
906	/*
907	* 2/4MB page.
908	*/
909	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
910	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
911	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
912	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
913	{
914	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
915	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
916	{
917	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
918	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
919	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
920	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
921	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
922	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
923	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
924	#endif
925	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
926	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
927	}
928	}
929	} /* pde type */
930	}
931	else
932	{
933	/* not-present. */
934	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
935	cPages && iPage < pCur->cPages;
936	iPage++, GCPtr += PAGE_SIZE)
937	{
938	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
939	{
940	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
941	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
942	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
943	}
944	}
945	offPage = 0;
946	}
947	} /* for pages in virtual mapping. */
948
949	return 0;
950	}
951	#endif /* 32BIT, PAE and AMD64 */
952
953
954	/**
955	* Updates the virtual page access handlers.
956	*
957	* @returns true if bits were flushed.
958	* @returns false if bits weren't flushed.
959	* @param pVM VM handle.
960	* @param pPDSrc The page directory.
961	* @param cr4 The cr4 register value.
962	*/
963	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
964	{
965	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
966	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
967	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
968
969	/** @todo
970	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
971	*/
972
973	/*
974	* Resolve any virtual address based access handlers to GC physical addresses.
975	* This should be fairly quick.
976	*/
977	PGMHVUSTATE State;
978
979	pgmLock(pVM);
980	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
981	State.pVM = pVM;
982	State.fTodo = pVM->pgm.s.fSyncFlags;
983	State.cr4 = cr4;
984	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
985	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
986
987
988	/*
989	* Set / reset bits?
990	*/
991	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
992	{
993	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
994	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
995	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
996	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
997	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
998	}
999	pgmUnlock(pVM);
1000
1001	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
1002
1003	#else /* real / protected */
1004	return false;
1005	#endif
1006	}
1007
1008
1009	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
1010
1011	/**
1012	* Write access handler for the Guest CR3 page in 32-bit mode.
1013	*
1014	* This will try interpret the instruction, if failure fail back to the recompiler.
1015	* Check if the changed PDEs are marked present and conflicts with our
1016	* mappings. If conflict, we'll switch to the host context and resolve it there
1017	*
1018	* @returns VBox status code (appropritate for trap handling and GC return).
1019	* @param pVM VM Handle.
1020	* @param uErrorCode CPU Error code.
1021	* @param pRegFrame Trap register frame.
1022	* @param pvFault The fault address (cr2).
1023	* @param GCPhysFault The GC physical address corresponding to pvFault.
1024	* @param pvUser User argument.
1025	*/
1026	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1027	{
1028	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1029
1030	/*
1031	* Try interpret the instruction.
1032	*/
1033	uint32_t cb;
1034	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1035	if (RT_SUCCESS(rc) && cb)
1036	{
1037	/*
1038	* Check if the modified PDEs are present and mappings.
1039	*/
1040	const RTGCPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1041	const unsigned iPD1 = offPD / sizeof(X86PDE);
1042	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
1043
1044	Assert(cb > 0 && cb <= 8);
1045	Assert(iPD1 < X86_PG_ENTRIES);
1046	Assert(iPD2 < X86_PG_ENTRIES);
1047
1048	#ifdef DEBUG
1049	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%x\n", iPD1, iPD1 << X86_PD_SHIFT));
1050	if (iPD1 != iPD2)
1051	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%x\n", iPD2, iPD2 << X86_PD_SHIFT));
1052	#endif
1053
1054	if (!pVM->pgm.s.fMappingsFixed)
1055	{
1056	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
1057	if ( ( pPDSrc->a[iPD1].n.u1Present
1058	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
1059	\|\| ( iPD1 != iPD2
1060	&& pPDSrc->a[iPD2].n.u1Present
1061	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
1062	)
1063	{
1064	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1065	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1066	if (rc == VINF_SUCCESS)
1067	rc = VINF_PGM_SYNC_CR3;
1068	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
1069	return rc;
1070	}
1071	}
1072
1073	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1074	}
1075	else
1076	{
1077	Assert(RT_FAILURE(rc));
1078	if (rc == VERR_EM_INTERPRETER)
1079	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1080	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1081	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1082	}
1083	return rc;
1084	}
1085
1086	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
1087	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
1088
1089	/**
1090	* Write access handler for the Guest CR3 page in PAE mode.
1091	*
1092	* This will try interpret the instruction, if failure fail back to the recompiler.
1093	* Check if the changed PDEs are marked present and conflicts with our
1094	* mappings. If conflict, we'll switch to the host context and resolve it there
1095	*
1096	* @returns VBox status code (appropritate for trap handling and GC return).
1097	* @param pVM VM Handle.
1098	* @param uErrorCode CPU Error code.
1099	* @param pRegFrame Trap register frame.
1100	* @param pvFault The fault address (cr2).
1101	* @param GCPhysFault The GC physical address corresponding to pvFault.
1102	* @param pvUser User argument.
1103	*/
1104	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1105	{
1106	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1107
1108	/*
1109	* Try interpret the instruction.
1110	*/
1111	uint32_t cb;
1112	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1113	if (RT_SUCCESS(rc) && cb)
1114	{
1115	/*
1116	* Check if any of the PDs have changed.
1117	* We'll simply check all of them instead of figuring out which one/two to check.
1118	*/
1119	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
1120	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1121	{
1122	if ( pGuestPDPT->a[i].n.u1Present
1123	&& (pGuestPDPT->a[i].u & X86_PDPE_PG_MASK)
1124	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1125	{
1126	/*
1127	* The PDPE has changed.
1128	* We will schedule a monitoring update for the next TLB Flush,
1129	* InvalidatePage or SyncCR3.
1130	*
1131	* This isn't perfect, because a lazy page sync might be dealing with an half
1132	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1133	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1134	* executing.
1135	*/
1136	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1137	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%RGp\n",
1138	i, pGuestPDPT->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1139	}
1140	}
1141
1142	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1143	}
1144	else
1145	{
1146	Assert(RT_FAILURE(rc));
1147	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1148	if (rc == VERR_EM_INTERPRETER)
1149	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1150	}
1151	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1152	return rc;
1153	}
1154
1155
1156	/**
1157	* Write access handler for the Guest PDs in PAE mode.
1158	*
1159	* This will try interpret the instruction, if failure fail back to the recompiler.
1160	* Check if the changed PDEs are marked present and conflicts with our
1161	* mappings. If conflict, we'll switch to the host context and resolve it there
1162	*
1163	* @returns VBox status code (appropritate for trap handling and GC return).
1164	* @param pVM VM Handle.
1165	* @param uErrorCode CPU Error code.
1166	* @param pRegFrame Trap register frame.
1167	* @param pvFault The fault address (cr2).
1168	* @param GCPhysFault The GC physical address corresponding to pvFault.
1169	* @param pvUser User argument.
1170	*/
1171	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1172	{
1173	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1174
1175	/*
1176	* Try interpret the instruction.
1177	*/
1178	uint32_t cb;
1179	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1180	if (RT_SUCCESS(rc) && cb)
1181	{
1182	/*
1183	* Figure out which of the 4 PDs this is.
1184	*/
1185	RTGCPTR i;
1186	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
1187	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1188	if (pGuestPDPT->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1189	{
1190	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1191	const RTGCPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1192	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1193	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1194
1195	Assert(cb > 0 && cb <= 8);
1196	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1197	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1198
1199	# ifdef LOG_ENABLED
1200	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%x)\n",
1201	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1202	if (iPD1 != iPD2)
1203	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%x)\n",
1204	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1205	# endif
1206
1207	if (!pVM->pgm.s.fMappingsFixed)
1208	{
1209	if ( ( pPDSrc->a[iPD1].n.u1Present
1210	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1211	\|\| ( iPD1 != iPD2
1212	&& pPDSrc->a[iPD2].n.u1Present
1213	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1214	)
1215	{
1216	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1217	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1218	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1219	return VINF_PGM_SYNC_CR3;
1220	}
1221	}
1222	break; /* ASSUMES no duplicate entries... */
1223	}
1224	Assert(i < 4);
1225
1226	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1227	}
1228	else
1229	{
1230	Assert(RT_FAILURE(rc));
1231	if (rc == VERR_EM_INTERPRETER)
1232	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1233	else
1234	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1235	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1236	}
1237	return rc;
1238	}
1239
1240	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1241

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 14153

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