PGMAllGst.h@ 16172

Last change on this file since 16172 was 16172, checked in by vboxsync, 16 years ago
Moved amd64 paging data to unified shadow paging section.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 47.3 KB

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1	/* $Id: PGMAllGst.h 16172 2009-01-22 15:09:31Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48	#undef GST_PDPE_PG_MASK
49	#undef GST_GET_PDE_BIG_PG_GCPHYS
50
51	#if PGM_GST_TYPE == PGM_TYPE_REAL \
52	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
53	# define GSTPT SHWPT
54	# define PGSTPT PSHWPT
55	# define GSTPTE SHWPTE
56	# define PGSTPTE PSHWPTE
57	# define GSTPD SHWPD
58	# define PGSTPD PSHWPD
59	# define GSTPDE SHWPDE
60	# define PGSTPDE PSHWPDE
61	# define GST_PTE_PG_MASK SHW_PTE_PG_MASK
62
63	#elif PGM_GST_TYPE == PGM_TYPE_32BIT
64	# define GSTPT X86PT
65	# define PGSTPT PX86PT
66	# define GSTPTE X86PTE
67	# define PGSTPTE PX86PTE
68	# define GSTPD X86PD
69	# define PGSTPD PX86PD
70	# define GSTPDE X86PDE
71	# define PGSTPDE PX86PDE
72	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
73	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
74	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
75	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
76	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeGst)
77	# define GST_PD_SHIFT X86_PD_SHIFT
78	# define GST_PD_MASK X86_PD_MASK
79	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
80	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
81	# define GST_PT_SHIFT X86_PT_SHIFT
82	# define GST_PT_MASK X86_PT_MASK
83	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
84
85	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
86	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
87	# define GSTPT X86PTPAE
88	# define PGSTPT PX86PTPAE
89	# define GSTPTE X86PTEPAE
90	# define PGSTPTE PX86PTEPAE
91	# define GSTPD X86PDPAE
92	# define PGSTPD PX86PDPAE
93	# define GSTPDE X86PDEPAE
94	# define PGSTPDE PX86PDEPAE
95	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
96	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
97	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
98	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
99	# define GST_GET_PDE_BIG_PG_GCPHYS(PdeGst) (PdeGst.u & GST_PDE_BIG_PG_MASK)
100	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
101	# define GST_PD_MASK X86_PD_PAE_MASK
102	# if PGM_GST_TYPE == PGM_TYPE_PAE
103	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
104	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
105	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
106	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
107	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
108	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
109	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
110	# else
111	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
112	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
113	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
114	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
115	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
116	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
117	# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
118	# endif
119	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
120	# define GST_PT_MASK X86_PT_PAE_MASK
121	#endif
122
123
124	/*******************************************************************************
125	* Internal Functions *
126	*******************************************************************************/
127	__BEGIN_DECLS
128	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
129	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
130	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE);
131	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
132	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
133	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
134	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
135	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
136	#endif
137	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
138	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
139	# ifndef IN_RING3
140	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
141	# if PGM_GST_TYPE == PGM_TYPE_PAE \
142	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
143	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
144	# endif
145	# endif
146	#endif
147	__END_DECLS
148
149
150
151	/**
152	* Gets effective Guest OS page information.
153	*
154	* When GCPtr is in a big page, the function will return as if it was a normal
155	* 4KB page. If the need for distinguishing between big and normal page becomes
156	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
157	* purpose.
158	*
159	* @returns VBox status.
160	* @param pVM VM Handle.
161	* @param GCPtr Guest Context virtual address of the page. Page aligned!
162	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
163	* @param pGCPhys Where to store the GC physical address of the page.
164	* This is page aligned. The fact that the
165	*/
166	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
167	{
168	#if PGM_GST_TYPE == PGM_TYPE_REAL \
169	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
170	/*
171	* Fake it.
172	*/
173	if (pfFlags)
174	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
175	if (pGCPhys)
176	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
177	return VINF_SUCCESS;
178
179	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
180
181	/*
182	* Get the PDE.
183	*/
184	# if PGM_GST_TYPE == PGM_TYPE_32BIT
185	X86PDE Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
186
187	#elif PGM_GST_TYPE == PGM_TYPE_PAE
188	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present.
189	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx). */
190	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
191	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
192
193	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
194	PX86PML4E pPml4e;
195	X86PDPE Pdpe;
196	X86PDEPAE Pde = pgmGstGetLongModePDEEx(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
197	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
198
199	Assert(pPml4e);
200	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
201	return VERR_PAGE_TABLE_NOT_PRESENT;
202
203	/* Merge accessed, write, user and no-execute bits into the PDE. */
204	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
205	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
206	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
207	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
208	# endif
209
210	/*
211	* Lookup the page.
212	*/
213	if (!Pde.n.u1Present)
214	return VERR_PAGE_TABLE_NOT_PRESENT;
215
216	if ( !Pde.b.u1Size
217	# if PGM_GST_TYPE != PGM_TYPE_AMD64
218	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
219	# endif
220	)
221	{
222	PGSTPT pPT;
223	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
224	if (RT_FAILURE(rc))
225	return rc;
226
227	/*
228	* Get PT entry and check presence.
229	*/
230	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
231	if (!Pte.n.u1Present)
232	return VERR_PAGE_NOT_PRESENT;
233
234	/*
235	* Store the result.
236	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
237	* where the PDPE is simplified.
238	*/
239	if (pfFlags)
240	{
241	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
242	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
243	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
244	/* The NX bit is determined by a bitwise OR between the PT and PD */
245	if (fNoExecuteBitValid)
246	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
247	# endif
248	}
249	if (pGCPhys)
250	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
251	}
252	else
253	{
254	/*
255	* Map big to 4k PTE and store the result
256	*/
257	if (pfFlags)
258	{
259	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
260	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
261	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
262	/* The NX bit is determined by a bitwise OR between the PT and PD */
263	if (fNoExecuteBitValid)
264	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
265	# endif
266	}
267	if (pGCPhys)
268	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
269	}
270	return VINF_SUCCESS;
271	#else
272	# error "shouldn't be here!"
273	/* something else... */
274	return VERR_NOT_SUPPORTED;
275	#endif
276	}
277
278
279	/**
280	* Modify page flags for a range of pages in the guest's tables
281	*
282	* The existing flags are ANDed with the fMask and ORed with the fFlags.
283	*
284	* @returns VBox status code.
285	* @param pVM VM handle.
286	* @param GCPtr Virtual address of the first page in the range. Page aligned!
287	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
288	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
289	* @param fMask The AND mask - page flags X86_PTE_*.
290	*/
291	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
292	{
293	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
294	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
295	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
296
297	for (;;)
298	{
299	/*
300	* Get the PD entry.
301	*/
302	# if PGM_GST_TYPE == PGM_TYPE_32BIT
303	PX86PDE pPde = pgmGstGet32bitPDEPtr(&pVM->pgm.s, GCPtr);
304
305	# elif PGM_GST_TYPE == PGM_TYPE_PAE
306	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
307	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
308	*/
309	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
310	Assert(pPde);
311	if (!pPde)
312	return VERR_PAGE_TABLE_NOT_PRESENT;
313	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
314	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
315	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
316	Assert(pPde);
317	if (!pPde)
318	return VERR_PAGE_TABLE_NOT_PRESENT;
319	# endif
320	GSTPDE Pde = *pPde;
321	Assert(Pde.n.u1Present);
322	if (!Pde.n.u1Present)
323	return VERR_PAGE_TABLE_NOT_PRESENT;
324
325	if ( !Pde.b.u1Size
326	# if PGM_GST_TYPE != PGM_TYPE_AMD64
327	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
328	# endif
329	)
330	{
331	/*
332	* 4KB Page table
333	*
334	* Walk page tables and pages till we're done.
335	*/
336	PGSTPT pPT;
337	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
338	if (RT_FAILURE(rc))
339	return rc;
340
341	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
342	while (iPTE < RT_ELEMENTS(pPT->a))
343	{
344	GSTPTE Pte = pPT->a[iPTE];
345	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
346	\| (fFlags & ~GST_PTE_PG_MASK);
347	pPT->a[iPTE] = Pte;
348
349	/* next page */
350	cb -= PAGE_SIZE;
351	if (!cb)
352	return VINF_SUCCESS;
353	GCPtr += PAGE_SIZE;
354	iPTE++;
355	}
356	}
357	else
358	{
359	/*
360	* 4MB Page table
361	*/
362	# if PGM_GST_TYPE == PGM_TYPE_32BIT
363	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
364	# else
365	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
366	# endif
367	\| (fFlags & ~GST_PTE_PG_MASK)
368	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
369	*pPde = Pde;
370
371	/* advance */
372	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
373	if (cbDone >= cb)
374	return VINF_SUCCESS;
375	cb -= cbDone;
376	GCPtr += cbDone;
377	}
378	}
379
380	#else
381	/* real / protected mode: ignore. */
382	return VINF_SUCCESS;
383	#endif
384	}
385
386
387	/**
388	* Retrieve guest PDE information
389	*
390	* @returns VBox status code.
391	* @param pVM The virtual machine.
392	* @param GCPtr Guest context pointer
393	* @param pPDE Pointer to guest PDE structure
394	*/
395	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPDE)
396	{
397	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
398	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
399	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
400
401	# if PGM_GST_TYPE == PGM_TYPE_32BIT
402	X86PDE Pde = pgmGstGet32bitPDE(&pVM->pgm.s, GCPtr);
403	# elif PGM_GST_TYPE == PGM_TYPE_PAE
404	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
405	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
406	X86PDEPAE Pde = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
407	# endif
408
409	pPDE->u = (X86PGPAEUINT)Pde.u;
410	return VINF_SUCCESS;
411	#else
412	AssertFailed();
413	return VERR_NOT_IMPLEMENTED;
414	#endif
415	}
416
417
418
419	/**
420	* Maps the CR3 into HMA in GC and locate it in HC.
421	*
422	* Note that a MapCR3 call is usually not followed by an UnmapCR3 call; whenever
423	* CR3 is updated we simply call MapCR3 again.
424	*
425	* @returns Strict VBox status code.
426	* @retval VINF_SUCCESS.
427	* @retval VINF_PGM_SYNC_CR3 if the shadow page pool overflowed.
428	*
429	* @param pVM VM handle.
430	* @param GCPhysCR3 The physical address in the CR3 register.
431	*/
432	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
433	{
434	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
435	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
436	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
437
438	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
439
440	/*
441	* Map the page CR3 points at.
442	*/
443	RTHCPHYS HCPhysGuestCR3;
444	RTHCPTR HCPtrGuestCR3;
445	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
446	if (RT_SUCCESS(rc))
447	{
448	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
449	if (RT_SUCCESS(rc))
450	{
451	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
452	# if PGM_GST_TYPE == PGM_TYPE_32BIT
453	pVM->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
454	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
455	pVM->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
456	# endif
457	pVM->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
458
459	# elif PGM_GST_TYPE == PGM_TYPE_PAE
460	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
461	pVM->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
462	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
463	pVM->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
464	# endif
465	pVM->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
466	Log(("Cached mapping %RGv\n", pVM->pgm.s.pGstPaePdptRC));
467
468	/*
469	* Map the 4 PDs too.
470	*/
471	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
472	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
473	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
474	{
475	if (pGuestPDPT->a[i].n.u1Present)
476	{
477	RTHCPTR HCPtr;
478	RTHCPHYS HCPhys;
479	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
480	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
481	if (RT_SUCCESS(rc2))
482	{
483	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
484	AssertRCReturn(rc, rc);
485
486	pVM->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
487	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
488	pVM->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
489	# endif
490	pVM->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
491	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
492	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
493	continue;
494	}
495	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
496	}
497
498	pVM->pgm.s.apGstPaePDsR3[i] = 0;
499	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
500	pVM->pgm.s.apGstPaePDsR0[i] = 0;
501	# endif
502	pVM->pgm.s.apGstPaePDsRC[i] = 0;
503	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
504	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
505	}
506
507	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
508	pVM->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
509	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
510	pVM->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
511	# endif
512	if (!HWACCMIsNestedPagingActive(pVM))
513	{
514	/*
515	* Update the shadow root page as well since that's not fixed.
516	*/
517	/** @todo Move this into PGMAllBth.h. */
518	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
519	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
520	{
521	/* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
522	/** @todo Coordinate this better with the pool. */
523	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3)->enmKind != PGMPOOLKIND_FREE)
524	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
525	pVM->pgm.s.pShwPageCR3R3 = 0;
526	pVM->pgm.s.pShwPageCR3R0 = 0;
527	pVM->pgm.s.pShwRootR3 = 0;
528	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
529	pVM->pgm.s.pShwRootR0 = 0;
530	# endif
531	pVM->pgm.s.HCPhysShwCR3 = 0;
532	}
533
534	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
535	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwPageCR3));
536	if (rc == VERR_PGM_POOL_FLUSHED)
537	{
538	Log(("MapCR3: PGM pool flushed -> signal sync cr3\n"));
539	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
540	return VINF_PGM_SYNC_CR3;
541	}
542	AssertRCReturn(rc, rc);
543	# ifdef IN_RING0
544	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
545	# else
546	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
547	# endif
548	pVM->pgm.s.pShwRootR3 = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
549	Assert(pVM->pgm.s.pShwRootR3);
550	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
551	pVM->pgm.s.pShwRootR0 = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
552	# endif
553	pVM->pgm.s.HCPhysShwCR3 = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
554	rc = VINF_SUCCESS; /* clear it - pgmPoolAlloc returns hints. */
555	}
556	# endif
557	}
558	else
559	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
560	}
561	else
562	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
563
564	#else /* prot/real stub */
565	int rc = VINF_SUCCESS;
566	#endif
567	return rc;
568	}
569
570
571	/**
572	* Unmaps the CR3.
573	*
574	* @returns VBox status, no specials.
575	* @param pVM VM handle.
576	*/
577	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
578	{
579	LogFlow(("UnmapCR3\n"));
580
581	int rc = VINF_SUCCESS;
582
583	#if PGM_GST_TYPE == PGM_TYPE_32BIT
584	pVM->pgm.s.pGst32BitPdR3 = 0;
585	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
586	pVM->pgm.s.pGst32BitPdR0 = 0;
587	#endif
588	pVM->pgm.s.pGst32BitPdRC = 0;
589
590	#elif PGM_GST_TYPE == PGM_TYPE_PAE
591	pVM->pgm.s.pGstPaePdptR3 = 0;
592	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
593	pVM->pgm.s.pGstPaePdptR0 = 0;
594	# endif
595	pVM->pgm.s.pGstPaePdptRC = 0;
596	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
597	{
598	pVM->pgm.s.apGstPaePDsR3[i] = 0;
599	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
600	pVM->pgm.s.apGstPaePDsR0[i] = 0;
601	# endif
602	pVM->pgm.s.apGstPaePDsRC[i] = 0;
603	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
604	}
605
606	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
607	pVM->pgm.s.pGstAmd64Pml4R3 = 0;
608	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
609	pVM->pgm.s.pGstAmd64Pml4R0 = 0;
610	# endif
611	if (!HWACCMIsNestedPagingActive(pVM))
612	{
613	pVM->pgm.s.pShwRootR3 = 0;
614	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
615	pVM->pgm.s.pShwRootR0 = 0;
616	# endif
617	pVM->pgm.s.HCPhysShwCR3 = 0;
618	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
619	{
620	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
621	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
622	pVM->pgm.s.pShwPageCR3R3 = 0;
623	pVM->pgm.s.pShwPageCR3R0 = 0;
624	}
625	}
626
627	#else /* prot/real mode stub */
628	/* nothing to do */
629	#endif
630	return rc;
631	}
632
633
634	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
635
636	#undef LOG_GROUP
637	#define LOG_GROUP LOG_GROUP_PGM_POOL
638
639	/**
640	* Registers physical page monitors for the necessary paging
641	* structures to detect conflicts with our guest mappings.
642	*
643	* This is always called after mapping CR3.
644	* This is never called with fixed mappings.
645	*
646	* @returns VBox status, no specials.
647	* @param pVM VM handle.
648	* @param GCPhysCR3 The physical address in the CR3 register.
649	*/
650	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
651	{
652	Assert(!pVM->pgm.s.fMappingsFixed);
653	int rc = VINF_SUCCESS;
654
655	/*
656	* Register/Modify write phys handler for guest's CR3 if it changed.
657	*/
658	#if PGM_GST_TYPE == PGM_TYPE_32BIT
659
660	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
661	{
662	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
663	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
664	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
665	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
666	else
667	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
668	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
669	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
670	pVM->pgm.s.pfnRCGstWriteHandlerCR3, 0,
671	pVM->pgm.s.pszR3GstWriteHandlerCR3);
672	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
673	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
674	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
675	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
676	? PGMPOOL_IDX_PAE_PD
677	: PGMPOOL_IDX_PD,
678	GCPhysCR3);
679	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
680	if (RT_FAILURE(rc))
681	{
682	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
683	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
684	return rc;
685	}
686	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
687	}
688
689	#elif PGM_GST_TYPE == PGM_TYPE_PAE
690	/* Monitor the PDPT page */
691	/*
692	* Register/Modify write phys handler for guest's CR3 if it changed.
693	*/
694	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
695	AssertFailed();
696	# endif
697	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
698	{
699	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
700	if (RT_FAILURE(rc))
701	{
702	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
703	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
704	return rc;
705	}
706	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
707	}
708
709	/*
710	* Do the 4 PDs.
711	*/
712	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
713	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
714	{
715	if (pGuestPDPT->a[i].n.u1Present)
716	{
717	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
718	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
719	{
720	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
721
722	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
723	}
724
725	if (RT_FAILURE(rc))
726	{
727	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
728	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
729	return rc;
730	}
731	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
732	}
733	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
734	{
735	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
736	AssertRC(rc);
737	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
738	}
739	}
740
741	#else
742	/* prot/real/amd64 mode stub */
743
744	#endif
745	return rc;
746	}
747
748	/**
749	* Deregisters any physical page monitors installed by MonitorCR3.
750	*
751	* @returns VBox status code, no specials.
752	* @param pVM The VM handle.
753	*/
754	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
755	{
756	int rc = VINF_SUCCESS;
757
758	/*
759	* Deregister the access handlers.
760	*
761	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
762	* before we enter GC again.
763	*/
764	#if PGM_GST_TYPE == PGM_TYPE_32BIT
765	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
766	{
767	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
768	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
769	AssertRCReturn(rc, rc);
770	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
771	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool),
772	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
773	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
774	? PGMPOOL_IDX_PAE_PD
775	: PGMPOOL_IDX_PD);
776	AssertRCReturn(rc, rc);
777	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
778	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
779	}
780
781	#elif PGM_GST_TYPE == PGM_TYPE_PAE
782	/* The PDPT page */
783	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
784	AssertFailed();
785	# endif
786
787	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
788	{
789	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PDPT);
790	AssertRC(rc);
791	}
792
793	/* The 4 PDs. */
794	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
795	{
796	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
797	{
798	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
799	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTX_SUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
800	AssertRC(rc2);
801	if (RT_FAILURE(rc2))
802	rc = rc2;
803	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
804	}
805	}
806	#else
807	/* prot/real/amd64 mode stub */
808	#endif
809	return rc;
810
811	}
812
813	#undef LOG_GROUP
814	#define LOG_GROUP LOG_GROUP_PGM
815
816	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
817
818
819	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
820	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
821	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
822	/**
823	* Updates one virtual handler range.
824	*
825	* @returns 0
826	* @param pNode Pointer to a PGMVIRTHANDLER.
827	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
828	*/
829	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
830	{
831	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
832	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
833	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
834
835	#if PGM_GST_TYPE == PGM_TYPE_32BIT
836	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pState->pVM->pgm.s);
837	#endif
838
839	RTGCPTR GCPtr = pCur->Core.Key;
840	#if PGM_GST_MODE != PGM_MODE_AMD64
841	/* skip all stuff above 4GB if not AMD64 mode. */
842	if (GCPtr >= _4GB)
843	return 0;
844	#endif
845
846	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
847	unsigned iPage = 0;
848	while (iPage < pCur->cPages)
849	{
850	#if PGM_GST_TYPE == PGM_TYPE_32BIT
851	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
852	#elif PGM_GST_TYPE == PGM_TYPE_PAE
853	X86PDEPAE Pde = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
854	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
855	X86PDEPAE Pde = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
856	#endif
857	if (Pde.n.u1Present)
858	{
859	if ( !Pde.b.u1Size
860	# if PGM_GST_TYPE != PGM_TYPE_AMD64
861	\|\| !(pState->cr4 & X86_CR4_PSE)
862	# endif
863	)
864	{
865	/*
866	* Normal page table.
867	*/
868	PGSTPT pPT;
869	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
870	if (RT_SUCCESS(rc))
871	{
872	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
873	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
874	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
875	{
876	GSTPTE Pte = pPT->a[iPTE];
877	RTGCPHYS GCPhysNew;
878	if (Pte.n.u1Present)
879	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
880	else
881	GCPhysNew = NIL_RTGCPHYS;
882	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
883	{
884	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
885	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
886	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
887	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
888	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
889	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
890	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
891	#endif
892	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
893	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
894	}
895	}
896	}
897	else
898	{
899	/* not-present. */
900	offPage = 0;
901	AssertRC(rc);
902	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
903	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
904	iPTE++, iPage++, GCPtr += PAGE_SIZE)
905	{
906	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
907	{
908	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
909	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
910	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
911	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
912	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
913	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
914	#endif
915	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
916	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
917	}
918	}
919	}
920	}
921	else
922	{
923	/*
924	* 2/4MB page.
925	*/
926	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
927	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
928	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
929	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
930	{
931	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
932	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
933	{
934	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
935	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
936	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
937	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
938	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
939	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
940	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
941	#endif
942	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
943	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
944	}
945	}
946	} /* pde type */
947	}
948	else
949	{
950	/* not-present. */
951	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
952	cPages && iPage < pCur->cPages;
953	iPage++, GCPtr += PAGE_SIZE)
954	{
955	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
956	{
957	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
958	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
959	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
960	}
961	}
962	offPage = 0;
963	}
964	} /* for pages in virtual mapping. */
965
966	return 0;
967	}
968	#endif /* 32BIT, PAE and AMD64 */
969
970
971	/**
972	* Updates the virtual page access handlers.
973	*
974	* @returns true if bits were flushed.
975	* @returns false if bits weren't flushed.
976	* @param pVM VM handle.
977	* @param pPDSrc The page directory.
978	* @param cr4 The cr4 register value.
979	*/
980	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
981	{
982	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
983	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
984	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
985
986	/** @todo
987	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
988	*/
989
990	/*
991	* Resolve any virtual address based access handlers to GC physical addresses.
992	* This should be fairly quick.
993	*/
994	PGMHVUSTATE State;
995
996	pgmLock(pVM);
997	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
998	State.pVM = pVM;
999	State.fTodo = pVM->pgm.s.fSyncFlags;
1000	State.cr4 = cr4;
1001	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
1002	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
1003
1004
1005	/*
1006	* Set / reset bits?
1007	*/
1008	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
1009	{
1010	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
1011	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
1012	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
1013	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
1014	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
1015	}
1016	pgmUnlock(pVM);
1017
1018	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
1019
1020	#else /* real / protected */
1021	return false;
1022	#endif
1023	}
1024
1025	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1026
1027	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
1028
1029	/**
1030	* Write access handler for the Guest CR3 page in 32-bit mode.
1031	*
1032	* This will try interpret the instruction, if failure fail back to the recompiler.
1033	* Check if the changed PDEs are marked present and conflicts with our
1034	* mappings. If conflict, we'll switch to the host context and resolve it there
1035	*
1036	* @returns VBox status code (appropritate for trap handling and GC return).
1037	* @param pVM VM Handle.
1038	* @param uErrorCode CPU Error code.
1039	* @param pRegFrame Trap register frame.
1040	* @param pvFault The fault address (cr2).
1041	* @param GCPhysFault The GC physical address corresponding to pvFault.
1042	* @param pvUser User argument.
1043	*/
1044	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1045	{
1046	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1047
1048	/*
1049	* Try interpret the instruction.
1050	*/
1051	uint32_t cb;
1052	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1053	if (RT_SUCCESS(rc) && cb)
1054	{
1055	/*
1056	* Check if the modified PDEs are present and mappings.
1057	*/
1058	const RTGCPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1059	const unsigned iPD1 = offPD / sizeof(X86PDE);
1060	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
1061
1062	Assert(cb > 0 && cb <= 8);
1063	Assert(iPD1 < X86_PG_ENTRIES);
1064	Assert(iPD2 < X86_PG_ENTRIES);
1065
1066	#ifdef DEBUG
1067	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%x\n", iPD1, iPD1 << X86_PD_SHIFT));
1068	if (iPD1 != iPD2)
1069	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%x\n", iPD2, iPD2 << X86_PD_SHIFT));
1070	#endif
1071
1072	if (!pVM->pgm.s.fMappingsFixed)
1073	{
1074	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
1075	if ( ( pPDSrc->a[iPD1].n.u1Present
1076	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
1077	\|\| ( iPD1 != iPD2
1078	&& pPDSrc->a[iPD2].n.u1Present
1079	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
1080	)
1081	{
1082	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1083	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1084	if (rc == VINF_SUCCESS)
1085	rc = VINF_PGM_SYNC_CR3;
1086	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
1087	return rc;
1088	}
1089	}
1090
1091	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1092	}
1093	else
1094	{
1095	Assert(RT_FAILURE(rc));
1096	if (rc == VERR_EM_INTERPRETER)
1097	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1098	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1099	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1100	}
1101	return rc;
1102	}
1103
1104	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
1105	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
1106
1107	/**
1108	* Write access handler for the Guest CR3 page in PAE mode.
1109	*
1110	* This will try interpret the instruction, if failure fail back to the recompiler.
1111	* Check if the changed PDEs are marked present and conflicts with our
1112	* mappings. If conflict, we'll switch to the host context and resolve it there
1113	*
1114	* @returns VBox status code (appropritate for trap handling and GC return).
1115	* @param pVM VM Handle.
1116	* @param uErrorCode CPU Error code.
1117	* @param pRegFrame Trap register frame.
1118	* @param pvFault The fault address (cr2).
1119	* @param GCPhysFault The GC physical address corresponding to pvFault.
1120	* @param pvUser User argument.
1121	*/
1122	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1123	{
1124	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1125
1126	/*
1127	* Try interpret the instruction.
1128	*/
1129	uint32_t cb;
1130	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1131	if (RT_SUCCESS(rc) && cb)
1132	{
1133	/*
1134	* Check if any of the PDs have changed.
1135	* We'll simply check all of them instead of figuring out which one/two to check.
1136	*/
1137	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
1138	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1139	{
1140	if ( pGuestPDPT->a[i].n.u1Present
1141	&& (pGuestPDPT->a[i].u & X86_PDPE_PG_MASK)
1142	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1143	{
1144	/*
1145	* The PDPE has changed.
1146	* We will schedule a monitoring update for the next TLB Flush,
1147	* InvalidatePage or SyncCR3.
1148	*
1149	* This isn't perfect, because a lazy page sync might be dealing with an half
1150	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1151	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1152	* executing.
1153	*/
1154	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1155	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%RGp\n",
1156	i, pGuestPDPT->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1157	}
1158	}
1159
1160	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1161	}
1162	else
1163	{
1164	Assert(RT_FAILURE(rc));
1165	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1166	if (rc == VERR_EM_INTERPRETER)
1167	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1168	}
1169	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1170	return rc;
1171	}
1172
1173
1174	/**
1175	* Write access handler for the Guest PDs in PAE mode.
1176	*
1177	* This will try interpret the instruction, if failure fail back to the recompiler.
1178	* Check if the changed PDEs are marked present and conflicts with our
1179	* mappings. If conflict, we'll switch to the host context and resolve it there
1180	*
1181	* @returns VBox status code (appropritate for trap handling and GC return).
1182	* @param pVM VM Handle.
1183	* @param uErrorCode CPU Error code.
1184	* @param pRegFrame Trap register frame.
1185	* @param pvFault The fault address (cr2).
1186	* @param GCPhysFault The GC physical address corresponding to pvFault.
1187	* @param pvUser User argument.
1188	*/
1189	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1190	{
1191	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1192
1193	/*
1194	* Try interpret the instruction.
1195	*/
1196	uint32_t cb;
1197	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1198	if (RT_SUCCESS(rc) && cb)
1199	{
1200	/*
1201	* Figure out which of the 4 PDs this is.
1202	*/
1203	RTGCPTR i;
1204	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
1205	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1206	if (pGuestPDPT->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1207	{
1208	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1209	const RTGCPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1210	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1211	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1212
1213	Assert(cb > 0 && cb <= 8);
1214	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1215	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1216
1217	# ifdef LOG_ENABLED
1218	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%x)\n",
1219	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1220	if (iPD1 != iPD2)
1221	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%x)\n",
1222	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1223	# endif
1224
1225	if (!pVM->pgm.s.fMappingsFixed)
1226	{
1227	if ( ( pPDSrc->a[iPD1].n.u1Present
1228	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1229	\|\| ( iPD1 != iPD2
1230	&& pPDSrc->a[iPD2].n.u1Present
1231	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1232	)
1233	{
1234	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1235	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteConflict);
1236	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1237	return VINF_PGM_SYNC_CR3;
1238	}
1239	}
1240	break; /* ASSUMES no duplicate entries... */
1241	}
1242	Assert(i < 4);
1243
1244	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteHandled);
1245	}
1246	else
1247	{
1248	Assert(RT_FAILURE(rc));
1249	if (rc == VERR_EM_INTERPRETER)
1250	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1251	else
1252	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1253	STAM_COUNTER_INC(&pVM->pgm.s.StatRZGuestCR3WriteUnhandled);
1254	}
1255	return rc;
1256	}
1257
1258	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1259
1260	#endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 16172

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