PGMAllGst.h@ 2744

Last change on this file since 2744 was 2227, checked in by vboxsync, 18 years ago
Ignore ModifyPage for real and protected mode without paging.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 28.8 KB

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1	/* $Id: PGMAllGst.h 2227 2007-04-19 13:51:54Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE4M_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44
45	#if PGM_GST_TYPE == PGM_TYPE_32BIT
46	# define GSTPT X86PT
47	# define PGSTPT PX86PT
48	# define GSTPTE X86PTE
49	# define PGSTPTE PX86PTE
50	# define GSTPD X86PD
51	# define PGSTPD PX86PD
52	# define GSTPDE X86PDE
53	# define PGSTPDE PX86PDE
54	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
55	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
56	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
57	# define GST_PDE4M_PG_MASK X86_PDE4M_PG_MASK
58	# define GST_PD_SHIFT X86_PD_SHIFT
59	# define GST_PD_MASK X86_PD_MASK
60	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
61	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
62	# define GST_PT_SHIFT X86_PT_SHIFT
63	# define GST_PT_MASK X86_PT_MASK
64	#else
65	# define GSTPT X86PTPAE
66	# define PGSTPT PX86PTPAE
67	# define GSTPTE X86PTEPAE
68	# define PGSTPTE PX86PTEPAE
69	# define GSTPD X86PDPAE
70	# define PGSTPD PX86PDPAE
71	# define GSTPDE X86PDEPAE
72	# define PGSTPDE PX86PDEPAE
73	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
74	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
75	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
76	# define GST_PDE4M_PG_MASK X86_PDE4M_PAE_PG_MASK
77	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
78	# define GST_PD_MASK X86_PD_PAE_MASK
79	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*4)
80	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
81	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
82	# define GST_PT_MASK X86_PT_PAE_MASK
83	#endif
84
85
86	/*******************************************************************************
87	* Internal Functions *
88	*******************************************************************************/
89	__BEGIN_DECLS
90	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
91	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
92	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
93	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
94	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
95	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
96	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
97	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
98	__END_DECLS
99
100
101
102	/**
103	* Gets effective Guest OS page information.
104	*
105	* When GCPtr is in a big page, the function will return as if it was a normal
106	* 4KB page. If the need for distinguishing between big and normal page becomes
107	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
108	* purpose.
109	*
110	* @returns VBox status.
111	* @param pVM VM Handle.
112	* @param GCPtr Guest Context virtual address of the page. Page aligned!
113	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
114	* @param pGCPhys Where to store the GC physical address of the page.
115	* This is page aligned. The fact that the
116	*/
117	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
118	{
119	#if PGM_GST_TYPE == PGM_TYPE_REAL \
120	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
121	/*
122	* Fake it.
123	*/
124	if (pfFlags)
125	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
126	if (pGCPhys)
127	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
128	return VINF_SUCCESS;
129
130	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
131	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
132	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
133
134	#if PGM_GST_TYPE == PGM_TYPE_AMD64
135	/* later */
136	AssertFailed();
137	return VERR_NOT_IMPLEMENTED;
138	#endif
139
140
141	/*
142	* Get the PDE.
143	*/
144	#if PGM_GST_TYPE == PGM_TYPE_32BIT
145	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
146	#else /* PAE */
147	X86PDEPAE Pde;
148	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
149	#endif
150
151	/*
152	* Lookup the page.
153	*/
154	if (!Pde.n.u1Present)
155	return VERR_PAGE_TABLE_NOT_PRESENT;
156
157	if ( !Pde.b.u1Size
158	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
159	{
160	PGSTPT pPT;
161	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
162	if (VBOX_FAILURE(rc))
163	return rc;
164
165	/*
166	* Get PT entry and check presentness.
167	*/
168	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
169	if (!Pte.n.u1Present)
170	return VERR_PAGE_NOT_PRESENT;
171
172	/*
173	* Store the result.
174	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
175	* where the PDPE is simplified.
176	*/
177	if (pfFlags)
178	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
179	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
180	if (pGCPhys)
181	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
182	}
183	else
184	{
185	/*
186	* Map big to 4k PTE and store the result
187	*/
188	if (pfFlags)
189	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
190	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
191	if (pGCPhys)
192	pGCPhys = (Pde.u & GST_PDE4M_PG_MASK) \| (GCPtr & (~GST_PDE4M_PG_MASK ^ ~GST_PTE_PG_MASK)); /* @todo pse36 */
193	}
194	return VINF_SUCCESS;
195	#else
196	/* something else... */
197	return VERR_NOT_SUPPORTED;
198	#endif
199	}
200
201
202	/**
203	* Modify page flags for a range of pages in the guest's tables
204	*
205	* The existing flags are ANDed with the fMask and ORed with the fFlags.
206	*
207	* @returns VBox status code.
208	* @param pVM VM handle.
209	* @param GCPtr Virtual address of the first page in the range. Page aligned!
210	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
211	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
212	* @param fMask The AND mask - page flags X86_PTE_*.
213	*/
214	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
215	{
216	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
217	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
218	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
219
220	#if PGM_GST_TYPE == PGM_TYPE_AMD64
221	/* later */
222	AssertFailed();
223	return VERR_NOT_IMPLEMENTED;
224	#endif
225
226	for (;;)
227	{
228	/*
229	* Get the PD entry.
230	*/
231	#if PGM_GST_TYPE == PGM_TYPE_32BIT
232	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
233	#else /* PAE */
234	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
235	Assert(pPde);
236	if (!pPde)
237	return VERR_PAGE_TABLE_NOT_PRESENT;
238	#endif
239	GSTPDE Pde = *pPde;
240	Assert(Pde.n.u1Present);
241	if (!Pde.n.u1Present)
242	return VERR_PAGE_TABLE_NOT_PRESENT;
243
244	if ( !Pde.b.u1Size
245	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
246	{
247	/*
248	* 4KB Page table
249	*
250	* Walk page tables and pages till we're done.
251	*/
252	PGSTPT pPT;
253	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
254	if (VBOX_FAILURE(rc))
255	return rc;
256
257	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
258	while (iPTE < ELEMENTS(pPT->a))
259	{
260	GSTPTE Pte = pPT->a[iPTE];
261	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
262	\| (fFlags & ~GST_PTE_PG_MASK);
263	pPT->a[iPTE] = Pte;
264
265	/* next page */
266	cb -= PAGE_SIZE;
267	if (!cb)
268	return VINF_SUCCESS;
269	GCPtr += PAGE_SIZE;
270	iPTE++;
271	}
272	}
273	else
274	{
275	/*
276	* 4MB Page table
277	*/
278	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| X86_PDE4M_PAE_PG_MASK \| X86_PDE4M_PS)) /** @todo pse36 */
279	\| (fFlags & ~GST_PTE_PG_MASK)
280	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
281	*pPde = Pde;
282
283	/* advance */
284	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
285	if (cbDone >= cb)
286	return VINF_SUCCESS;
287	cb -= cbDone;
288	GCPtr += cbDone;
289	}
290	}
291
292	#else
293	/* real / protected mode: ignore. */
294	return VINF_SUCCESS;
295	#endif
296	}
297
298
299	/**
300	* Retrieve guest PDE information
301	*
302	* @returns VBox status code.
303	* @param pVM The virtual machine.
304	* @param GCPtr Guest context pointer
305	* @param pPDE Pointer to guest PDE structure
306	*/
307	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
308	{
309	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
310	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
311	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
312
313	#if PGM_GST_TYPE == PGM_TYPE_AMD64
314	/* later */
315	AssertFailed();
316	return VERR_NOT_IMPLEMENTED;
317	#endif
318
319	# if PGM_GST_TYPE == PGM_TYPE_32BIT
320	X86PDE Pde;
321	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
322	# else
323	X86PDEPAE Pde;
324	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
325	# endif
326
327	pPDE->u = (X86PGPAEUINT)Pde.u;
328	return VINF_SUCCESS;
329	#else
330	AssertFailed();
331	return VERR_NOT_IMPLEMENTED;
332	#endif
333	}
334
335
336
337	/**
338	* Maps the CR3 into HMA in GC and locate it in HC.
339	*
340	* @returns VBox status, no specials.
341	* @param pVM VM handle.
342	* @param GCPhysCR3 The physical address in the CR3 register.
343	*/
344	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
345	{
346	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
347	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
348	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
349	/*
350	* Map the page CR3 points at.
351	*/
352	RTHCPHYS HCPhysGuestCR3;
353	RTHCPTR HCPtrGuestCR3;
354	int rc = PGMRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3, &HCPtrGuestCR3, &HCPhysGuestCR3);
355	if (VBOX_SUCCESS(rc))
356	{
357	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3 & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
358	if (VBOX_SUCCESS(rc))
359	{
360	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
361	#if PGM_GST_TYPE == PGM_TYPE_32BIT
362	pVM->pgm.s.pGuestPDHC = (HCPTRTYPE(PX86PD))HCPtrGuestCR3;
363	pVM->pgm.s.pGuestPDGC = (GCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
364
365	#elif PGM_GST_TYPE == PGM_TYPE_PAE
366	const unsigned off = GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
367	pVM->pgm.s.pGstPaePDPTRHC = (HCPTRTYPE(PX86PDPTR))((RTHCUINTPTR)HCPtrGuestCR3 \| off);
368	pVM->pgm.s.pGstPaePDPTRGC = (GCPTRTYPE(PX86PDPTR))((RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping \| off);
369
370	/*
371	* Map the 4 PDs too.
372	*/
373	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
374	for (unsigned i = 0; i < 4; i++, GCPtr += PAGE_SIZE)
375	{
376	if (pVM->pgm.s.CTXSUFF(pGstPaePDPTR)->a[i].n.u1Present)
377	{
378	RTHCPTR HCPtr;
379	RTHCPHYS HCPhys;
380	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPTR)->a[i].u & X86_PDPE_PG_MASK;
381	int rc2 = PGMRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
382	if (VBOX_SUCCESS(rc2))
383	{
384	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
385	AssertRCReturn(rc, rc);
386	pVM->pgm.s.apGstPaePDsHC[i] = (HCPTRTYPE(PX86PDPAE))HCPtr;
387	pVM->pgm.s.apGstPaePDsGC[i] = (GCPTRTYPE(PX86PDPAE))GCPtr;
388	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
389	PGM_INVL_PG(GCPtr);
390	continue;
391	}
392	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
393	}
394
395	pVM->pgm.s.apGstPaePDsHC[i] = 0;
396	pVM->pgm.s.apGstPaePDsGC[i] = 0;
397	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
398	PGM_INVL_PG(GCPtr);
399	}
400
401	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
402	rc = VERR_NOT_IMPLEMENTED;
403	#endif
404	}
405	}
406	else
407	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
408
409	#else /* prot/real mode stub */
410	int rc = VINF_SUCCESS;
411	#endif
412	return rc;
413	}
414
415
416	/**
417	* Unmaps the CR3.
418	*
419	* @returns VBox status, no specials.
420	* @param pVM VM handle.
421	* @param GCPhysCR3 The physical address in the CR3 register.
422	*/
423	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
424	{
425	int rc = VINF_SUCCESS;
426	#if PGM_GST_TYPE == PGM_TYPE_32BIT
427	pVM->pgm.s.pGuestPDHC = 0;
428	pVM->pgm.s.pGuestPDGC = 0;
429
430	#elif PGM_GST_TYPE == PGM_TYPE_PAE
431	pVM->pgm.s.pGstPaePDPTRHC = 0;
432	pVM->pgm.s.pGstPaePDPTRGC = 0;
433
434	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
435	//#error not implemented
436	rc = VERR_NOT_IMPLEMENTED;
437
438	#else /* prot/real mode stub */
439	/* nothing to do */
440	#endif
441	return rc;
442	}
443
444
445	#undef LOG_GROUP
446	#define LOG_GROUP LOG_GROUP_PGM_POOL
447
448	/**
449	* Registers physical page monitors for the necessary paging
450	* structures to detect conflicts with our guest mappings.
451	*
452	* This is always called after mapping CR3.
453	* This is never called with fixed mappings.
454	*
455	* @returns VBox status, no specials.
456	* @param pVM VM handle.
457	* @param GCPhysCR3 The physical address in the CR3 register.
458	*/
459	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
460	{
461	Assert(!pVM->pgm.s.fMappingsFixed);
462	int rc = VINF_SUCCESS;
463
464	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
465	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
466	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
467
468	/*
469	* Register/Modify write phys handler for guest's CR3 if it changed.
470	*/
471	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
472	{
473	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
474	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
475	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
476	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
477	else
478	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
479	pVM->pgm.s.pfnHCGstWriteHandlerCR3, 0,
480	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
481	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
482	pVM->pgm.s.pszHCGstWriteHandlerCR3);
483	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
484	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
485	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
486	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
487	? PGMPOOL_IDX_PAE_PD
488	: PGMPOOL_IDX_PD,
489	GCPhysCR3);
490	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
491	if (VBOX_FAILURE(rc))
492	{
493	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
494	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
495	return rc;
496	}
497	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
498	}
499
500	#if PGM_GST_TYPE == PGM_TYPE_PAE
501	AssertFatalFailed();
502	# if 0 /* later */
503	/*
504	* Do the 4 PDs.
505	*/
506	for (unsigned i = 0; i < 4; i++)
507	{
508	if (pVM->pgm.s.pGstPaePDPTRHC->a[i].n.u1Present)
509	{
510	RTGCPHYS GCPhys = pVM->pgm.s.pGstPaePDPTRHC->a[i].u & X86_PDPE_PG_MASK;
511	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
512	{
513	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
514	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys, GCPhys + PAGE_SIZE - 1);
515	else
516	rc = PGMR3HandlerPhysicalRegister(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhys, GCPhys + PAGE_SIZE - 1,
517	pgmR3GstPaePDWriteHandler, NULL,
518	NULL, "pgmGCGstPaePDWriteHandler", 0,
519	"Guest PD write access handler");
520	if (VBOX_SUCCESS(rc))
521	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
522	}
523	}
524	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
525	{
526	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]);
527	AssertRC(rc);
528	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
529	}
530	}
531	# endif
532	#endif /* PGM_GST_TYPE == PGM_TYPE_PAE */
533
534	#else
535	/* prot/real mode stub */
536
537	#endif
538	return rc;
539	}
540
541	/**
542	* Deregisters any physical page monitors installed by MonitorCR3.
543	*
544	* @returns VBox status code, no specials.
545	* @param pVM The VM handle.
546	*/
547	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
548	{
549	int rc = VINF_SUCCESS;
550
551	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
552	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
553	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
554
555	/*
556	* Deregister the access handlers.
557	*
558	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
559	* before we enter GC again.
560	*/
561	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
562	{
563	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
564	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
565	AssertRCReturn(rc, rc);
566	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
567	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
568	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
569	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
570	? PGMPOOL_IDX_PAE_PD
571	: PGMPOOL_IDX_PD);
572	AssertRCReturn(rc, rc);
573	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
574	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
575	}
576
577	# if PGM_GST_TYPE == PGM_TYPE_PAE
578	/* The 4 PDs. */
579	for (unsigned i = 0; i < 4; i++)
580	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
581	{
582	int rc2 = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]);
583	AssertRC(rc2);
584	if (VBOX_FAILURE(rc2))
585	rc = rc2;
586	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
587	}
588	# endif
589
590	#else
591	/* prot/real mode stub */
592	#endif
593	return rc;
594
595	}
596
597	#undef LOG_GROUP
598	#define LOG_GROUP LOG_GROUP_PGM
599
600
601	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
602	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
603	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
604	/**
605	* Updates one virtual handler range.
606	*
607	* @returns 0
608	* @param pNode Pointer to a PGMVIRTHANDLER.
609	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
610	*/
611	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
612	{
613	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
614	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
615
616	#if PGM_GST_TYPE == PGM_TYPE_32BIT
617	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
618	#endif
619
620	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
621	#if PGM_GST_MODE != PGM_MODE_AMD64
622	/* skip all stuff above 4GB if not AMD64 mode. */
623	if (GCPtr >= _4GB)
624	return 0;
625	#endif
626
627	unsigned fFlags;
628	switch (pCur->enmType)
629	{
630	case PGMVIRTHANDLERTYPE_EIP:
631	case PGMVIRTHANDLERTYPE_NORMAL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER; break;
632	case PGMVIRTHANDLERTYPE_WRITE: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE; break;
633	case PGMVIRTHANDLERTYPE_ALL: fFlags = MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_ALL; break;
634	/* hypervisor handlers need no flags and wouldn't have nowhere to put them in any case. */
635	case PGMVIRTHANDLERTYPE_HYPERVISOR:
636	return 0;
637	}
638
639	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
640	unsigned iPage = 0;
641	while (iPage < pCur->cPages)
642	{
643	#if PGM_GST_TYPE == PGM_TYPE_32BIT
644	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
645	#else
646	X86PDEPAE Pde;
647	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
648	#endif
649	if (Pde.n.u1Present)
650	{
651	if (!Pde.b.u1Size \|\| !(pState->cr4 & X86_CR4_PSE))
652	{
653	/*
654	* Normal page table.
655	*/
656	PGSTPT pPT;
657	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
658	if (VBOX_SUCCESS(rc))
659	{
660	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
661	iPTE < ELEMENTS(pPT->a) && iPage < pCur->cPages;
662	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
663	{
664	GSTPTE Pte = pPT->a[iPTE];
665	RTGCPHYS GCPhysNew;
666	if (Pte.n.u1Present)
667	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
668	else
669	GCPhysNew = NIL_RTGCPHYS;
670	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
671	{
672	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
673	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
674	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
675	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
676	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
677	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
678	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
679	#endif
680	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
681	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
682	}
683	}
684	}
685	else
686	{
687	/* not-present. */
688	offPage = 0;
689	AssertRC(rc);
690	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
691	iPTE < ELEMENTS(pPT->a) && iPage < pCur->cPages;
692	iPTE++, iPage++, GCPtr += PAGE_SIZE)
693	{
694	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
695	{
696	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
697	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
698	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
699	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
700	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
701	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
702	#endif
703	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
704	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
705	}
706	}
707	}
708	}
709	else
710	{
711	/*
712	* 2/4MB page.
713	*/
714	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
715	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
716	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
717	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
718	{
719	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
720	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
721	{
722	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
723	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
724	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
725	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
726	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
727	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
728	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
729	#endif
730	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
731	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
732	}
733	}
734	} /* pde type */
735	}
736	else
737	{
738	/* not-present. */
739	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
740	cPages && iPage < pCur->cPages;
741	iPage++, GCPtr += PAGE_SIZE)
742	{
743	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
744	{
745	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
746	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
747	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
748	}
749	}
750	offPage = 0;
751	}
752	} /* for pages in virtual mapping. */
753
754	return 0;
755	}
756	#endif /* 32BIT, PAE and AMD64 */
757
758
759	/**
760	* Updates the virtual page access handlers.
761	*
762	* @returns true if bits were flushed.
763	* @returns false if bits weren't flushed.
764	* @param pVM VM handle.
765	* @param pPDSrc The page directory.
766	* @param cr4 The cr4 register value.
767	*/
768	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
769	{
770	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
771	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
772	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
773	#if PGM_GST_TYPE == PGM_TYPE_AMD64
774	AssertFailed();
775	#endif
776
777	/** @todo
778	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
779	*/
780
781	/*
782	* Resolve any virtual address based access handlers to GC physical addresses.
783	* This should be fairly quick.
784	*/
785	PGMHVUSTATE State;
786
787	pgmLock(pVM);
788	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
789	State.pVM = pVM;
790	State.fTodo = pVM->pgm.s.fSyncFlags;
791	State.cr4 = cr4;
792	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
793	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
794
795
796	/*
797	* Set / reset bits?
798	*/
799	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
800	{
801	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
802	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
803	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
804	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
805	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
806	}
807	pgmUnlock(pVM);
808
809	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
810
811	#else /* real / protected */
812	return false;
813	#endif
814	}
815

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 2744

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