PGMAllGst.h@ 29450

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1	/* $Id: PGMAllGst.h 28800 2010-04-27 08:22:32Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Internal Functions *
21	*******************************************************************************/
22	RT_C_DECLS_BEGIN
23	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
24	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
25	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
26	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
27	RT_C_DECLS_END
28
29
30
31	/**
32	* Gets effective Guest OS page information.
33	*
34	* When GCPtr is in a big page, the function will return as if it was a normal
35	* 4KB page. If the need for distinguishing between big and normal page becomes
36	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
37	* purpose.
38	*
39	* @returns VBox status.
40	* @param pVCpu The VMCPU handle.
41	* @param GCPtr Guest Context virtual address of the page.
42	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
43	* @param pGCPhys Where to store the GC physical address of the page.
44	* This is page aligned!
45	*/
46	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
47	{
48	#if PGM_GST_TYPE == PGM_TYPE_REAL \
49	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
50	/*
51	* Fake it.
52	*/
53	if (pfFlags)
54	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
55	if (pGCPhys)
56	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
57	return VINF_SUCCESS;
58
59	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
60
61	#if PGM_GST_MODE != PGM_MODE_AMD64
62	/* Boundary check. */
63	if (GCPtr >= _4G)
64	return VERR_INVALID_ADDRESS;
65	# endif
66
67	PVM pVM = pVCpu->CTX_SUFF(pVM);
68	/*
69	* Get the PDE.
70	*/
71	# if PGM_GST_TYPE == PGM_TYPE_32BIT
72	X86PDE Pde = pgmGstGet32bitPDE(&pVCpu->pgm.s, GCPtr);
73
74	#elif PGM_GST_TYPE == PGM_TYPE_PAE
75	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present.
76	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx). */
77	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
78
79	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
80	PX86PML4E pPml4e;
81	X86PDPE Pdpe;
82	X86PDEPAE Pde = pgmGstGetLongModePDEEx(&pVCpu->pgm.s, GCPtr, &pPml4e, &Pdpe);
83
84	Assert(pPml4e);
85	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
86	return VERR_PAGE_TABLE_NOT_PRESENT;
87
88	/* Merge accessed, write, user and no-execute bits into the PDE. */
89	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
90	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
91	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
92	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
93	# endif
94
95	/*
96	* Lookup the page.
97	*/
98	if (!Pde.n.u1Present)
99	return VERR_PAGE_TABLE_NOT_PRESENT;
100
101	if ( !Pde.b.u1Size
102	# if PGM_GST_TYPE == PGM_TYPE_32BIT
103	\|\| !CPUMIsGuestPageSizeExtEnabled(pVCpu)
104	# endif
105	)
106	{
107	PGSTPT pPT;
108	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
109	if (RT_FAILURE(rc))
110	return rc;
111
112	/*
113	* Get PT entry and check presence.
114	*/
115	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
116	if (!Pte.n.u1Present)
117	return VERR_PAGE_NOT_PRESENT;
118
119	/*
120	* Store the result.
121	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
122	* where the PDPE is simplified.
123	*/
124	if (pfFlags)
125	{
126	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
127	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
128	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
129	/* The NX bit is determined by a bitwise OR between the PT and PD */
130	if ((Pte.u & Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) /** @todo the code is ANDing not ORing NX like the comment says... */
131	*pfFlags \|= X86_PTE_PAE_NX;
132	# endif
133	}
134	if (pGCPhys)
135	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
136	}
137	else
138	{
139	/*
140	* Map big to 4k PTE and store the result
141	*/
142	if (pfFlags)
143	{
144	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
145	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
146	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
147	if ((Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu))
148	*pfFlags \|= X86_PTE_PAE_NX;
149	# endif
150	}
151	if (pGCPhys)
152	*pGCPhys = GST_GET_PDE_BIG_PG_GCPHYS(Pde) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK));
153	}
154	return VINF_SUCCESS;
155	#else
156	# error "shouldn't be here!"
157	/* something else... */
158	return VERR_NOT_SUPPORTED;
159	#endif
160	}
161
162
163	/**
164	* Modify page flags for a range of pages in the guest's tables
165	*
166	* The existing flags are ANDed with the fMask and ORed with the fFlags.
167	*
168	* @returns VBox status code.
169	* @param pVCpu The VMCPU handle.
170	* @param GCPtr Virtual address of the first page in the range. Page aligned!
171	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
172	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
173	* @param fMask The AND mask - page flags X86_PTE_*.
174	*/
175	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
176	{
177	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
178	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
179	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
180
181	Assert((cb & PAGE_OFFSET_MASK) == 0);
182
183	#if PGM_GST_MODE != PGM_MODE_AMD64
184	/* Boundary check. */
185	if (GCPtr >= _4G)
186	return VERR_INVALID_ADDRESS;
187	# endif
188
189	PVM pVM = pVCpu->CTX_SUFF(pVM);
190	for (;;)
191	{
192	/*
193	* Get the PD entry.
194	*/
195	# if PGM_GST_TYPE == PGM_TYPE_32BIT
196	PX86PDE pPde = pgmGstGet32bitPDEPtr(&pVCpu->pgm.s, GCPtr);
197
198	# elif PGM_GST_TYPE == PGM_TYPE_PAE
199	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
200	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
201	*/
202	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVCpu->pgm.s, GCPtr);
203	Assert(pPde);
204	if (!pPde)
205	return VERR_PAGE_TABLE_NOT_PRESENT;
206	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
207	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
208	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVCpu->pgm.s, GCPtr);
209	Assert(pPde);
210	if (!pPde)
211	return VERR_PAGE_TABLE_NOT_PRESENT;
212	# endif
213	GSTPDE Pde = *pPde;
214	Assert(Pde.n.u1Present);
215	if (!Pde.n.u1Present)
216	return VERR_PAGE_TABLE_NOT_PRESENT;
217
218	if ( !Pde.b.u1Size
219	# if PGM_GST_TYPE == PGM_TYPE_32BIT
220	\|\| !CPUMIsGuestPageSizeExtEnabled(pVCpu)
221	# endif
222	)
223	{
224	/*
225	* 4KB Page table
226	*
227	* Walk page tables and pages till we're done.
228	*/
229	PGSTPT pPT;
230	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
231	if (RT_FAILURE(rc))
232	return rc;
233
234	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
235	while (iPTE < RT_ELEMENTS(pPT->a))
236	{
237	GSTPTE Pte = pPT->a[iPTE];
238	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
239	\| (fFlags & ~GST_PTE_PG_MASK);
240	pPT->a[iPTE] = Pte;
241
242	/* next page */
243	cb -= PAGE_SIZE;
244	if (!cb)
245	return VINF_SUCCESS;
246	GCPtr += PAGE_SIZE;
247	iPTE++;
248	}
249	}
250	else
251	{
252	/*
253	* 4MB Page table
254	*/
255	# if PGM_GST_TYPE == PGM_TYPE_32BIT
256	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
257	# else
258	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
259	# endif
260	\| (fFlags & ~GST_PTE_PG_MASK)
261	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
262	*pPde = Pde;
263
264	/* advance */
265	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
266	if (cbDone >= cb)
267	return VINF_SUCCESS;
268	cb -= cbDone;
269	GCPtr += cbDone;
270	}
271	}
272
273	#else
274	/* real / protected mode: ignore. */
275	return VINF_SUCCESS;
276	#endif
277	}
278
279
280	/**
281	* Retrieve guest PDE information
282	*
283	* @returns VBox status code.
284	* @param pVCpu The VMCPU handle.
285	* @param GCPtr Guest context pointer
286	* @param pPDE Pointer to guest PDE structure
287	*/
288	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE)
289	{
290	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
291	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
292	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
293
294	#if PGM_GST_MODE != PGM_MODE_AMD64
295	/* Boundary check. */
296	if (GCPtr >= _4G)
297	return VERR_INVALID_ADDRESS;
298	# endif
299
300	# if PGM_GST_TYPE == PGM_TYPE_32BIT
301	X86PDE Pde = pgmGstGet32bitPDE(&pVCpu->pgm.s, GCPtr);
302	# elif PGM_GST_TYPE == PGM_TYPE_PAE
303	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
304	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
305	X86PDEPAE Pde = pgmGstGetLongModePDE(&pVCpu->pgm.s, GCPtr);
306	# endif
307
308	pPDE->u = (X86PGPAEUINT)Pde.u;
309	return VINF_SUCCESS;
310	#else
311	AssertFailed();
312	return VERR_NOT_IMPLEMENTED;
313	#endif
314	}
315
316
317	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
318	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
319	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
320	/**
321	* Updates one virtual handler range.
322	*
323	* @returns 0
324	* @param pNode Pointer to a PGMVIRTHANDLER.
325	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
326	*/
327	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
328	{
329	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
330	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
331	PVM pVM = pState->pVM;
332	PVMCPU pVCpu = pState->pVCpu;
333	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
334
335	#if PGM_GST_TYPE == PGM_TYPE_32BIT
336	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
337	#endif
338
339	RTGCPTR GCPtr = pCur->Core.Key;
340	#if PGM_GST_MODE != PGM_MODE_AMD64
341	/* skip all stuff above 4GB if not AMD64 mode. */
342	if (GCPtr >= _4GB)
343	return 0;
344	#endif
345
346	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
347	unsigned iPage = 0;
348	while (iPage < pCur->cPages)
349	{
350	#if PGM_GST_TYPE == PGM_TYPE_32BIT
351	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
352	#elif PGM_GST_TYPE == PGM_TYPE_PAE
353	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
354	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
355	X86PDEPAE Pde = pgmGstGetLongModePDE(&pVCpu->pgm.s, GCPtr);
356	#endif
357	if (Pde.n.u1Present)
358	{
359	if ( !Pde.b.u1Size
360	# if PGM_GST_TYPE == PGM_TYPE_32BIT
361	\|\| !(pState->cr4 & X86_CR4_PSE)
362	# endif
363	)
364	{
365	/*
366	* Normal page table.
367	*/
368	PGSTPT pPT;
369	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
370	if (RT_SUCCESS(rc))
371	{
372	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
373	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
374	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
375	{
376	GSTPTE Pte = pPT->a[iPTE];
377	RTGCPHYS GCPhysNew;
378	if (Pte.n.u1Present)
379	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
380	else
381	GCPhysNew = NIL_RTGCPHYS;
382	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
383	{
384	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
385	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
386	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
387	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
388	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
389	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
390	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
391	#endif
392	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
393	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
394	}
395	}
396	}
397	else
398	{
399	/* not-present. */
400	offPage = 0;
401	AssertRC(rc);
402	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
403	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
404	iPTE++, iPage++, GCPtr += PAGE_SIZE)
405	{
406	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
407	{
408	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
409	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
410	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
411	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
412	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
413	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
414	#endif
415	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
416	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
417	}
418	}
419	}
420	}
421	else
422	{
423	/*
424	* 2/4MB page.
425	*/
426	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
427	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
428	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
429	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
430	{
431	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
432	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
433	{
434	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
435	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
436	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
437	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
438	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
439	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
440	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
441	#endif
442	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
443	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
444	}
445	}
446	} /* pde type */
447	}
448	else
449	{
450	/* not-present. */
451	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
452	cPages && iPage < pCur->cPages;
453	iPage++, GCPtr += PAGE_SIZE)
454	{
455	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
456	{
457	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
458	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
459	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
460	}
461	}
462	offPage = 0;
463	}
464	} /* for pages in virtual mapping. */
465
466	return 0;
467	}
468	#endif /* 32BIT, PAE and AMD64 */
469
470
471	/**
472	* Updates the virtual page access handlers.
473	*
474	* @returns true if bits were flushed.
475	* @returns false if bits weren't flushed.
476	* @param pVM VM handle.
477	* @param pPDSrc The page directory.
478	* @param cr4 The cr4 register value.
479	*/
480	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
481	{
482	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
483	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
484	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
485
486	/** @todo
487	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
488	*/
489
490	/*
491	* Resolve any virtual address based access handlers to GC physical addresses.
492	* This should be fairly quick.
493	*/
494	RTUINT fTodo = 0;
495
496	pgmLock(pVM);
497	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
498
499	for (VMCPUID i = 0; i < pVM->cCpus; i++)
500	{
501	PGMHVUSTATE State;
502	PVMCPU pVCpu = &pVM->aCpus[i];
503
504	State.pVM = pVM;
505	State.pVCpu = pVCpu;
506	State.fTodo = pVCpu->pgm.s.fSyncFlags;
507	State.cr4 = cr4;
508	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
509
510	fTodo \|= State.fTodo;
511	}
512	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
513
514
515	/*
516	* Set / reset bits?
517	*/
518	if (fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
519	{
520	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
521	Log(("HandlerVirtualUpdate: resets bits\n"));
522	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
523
524	for (VMCPUID i = 0; i < pVM->cCpus; i++)
525	{
526	PVMCPU pVCpu = &pVM->aCpus[i];
527	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
528	}
529
530	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
531	}
532	pgmUnlock(pVM);
533
534	return !!(fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
535
536	#else /* real / protected */
537	return false;
538	#endif
539	}
540

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 29450

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