PGMAllGst.h@ 31054

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1	/* $Id: PGMAllGst.h 30896 2010-07-17 02:33:46Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Internal Functions *
21	*******************************************************************************/
22	RT_C_DECLS_BEGIN
23	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
24	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
25	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
26	PGM_GST_DECL(int, Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk);
27	#endif
28	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
29	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
30	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE);
31	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
32	RT_C_DECLS_END
33
34
35	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
36	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
37	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
38
39
40	DECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
41	{
42	NOREF(iLevel);
43	pWalk->Core.fNotPresent = true;
44	pWalk->Core.uLevel = (uint8_t)iLevel;
45	return VERR_PAGE_TABLE_NOT_PRESENT;
46	}
47
48	DECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPU pVCpu, PGSTPTWALK pWalk, int rc, int iLevel)
49	{
50	AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc));
51	pWalk->Core.fBadPhysAddr = true;
52	pWalk->Core.uLevel = (uint8_t)iLevel;
53	return VERR_PAGE_TABLE_NOT_PRESENT;
54	}
55
56	DECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPU pVCpu, PGSTPTWALK pWalk, int iLevel)
57	{
58	pWalk->Core.fRsvdError = true;
59	pWalk->Core.uLevel = (uint8_t)iLevel;
60	return VERR_PAGE_TABLE_NOT_PRESENT;
61	}
62
63
64	/**
65	* Performs a guest page table walk.
66	*
67	* @returns VBox status code.
68	* @retval VINF_SUCCESS on success.
69	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
70	*
71	* @param pVCpu The current CPU.
72	* @param GCPtr The guest virtual address to walk by.
73	* @param pWalk Where to return the walk result. This is always set.
74	*/
75	PGM_GST_DECL(int, Walk)(PVMCPU pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk)
76	{
77	int rc;
78
79	/*
80	* Init the walking structure.
81	*/
82	RT_ZERO(*pWalk);
83	pWalk->Core.GCPtr = GCPtr;
84
85	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
86	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
87	/*
88	* Boundary check for PAE and 32-bit (prevents trouble further down).
89	*/
90	if (RT_UNLIKELY(GCPtr >= _4G))
91	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
92	# endif
93
94	{
95	# if PGM_GST_TYPE == PGM_TYPE_AMD64
96	/*
97	* The PMLE4.
98	*/
99	rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pWalk->pPml4);
100	if (RT_FAILURE(rc))
101	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
102
103	PX86PML4 register pPml4 = pWalk->pPml4;
104	X86PML4E register Pml4e;
105	PX86PML4E register pPml4e;
106
107	pWalk->pPml4e = pPml4e = &pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
108	pWalk->Pml4e.u = Pml4e.u = pPml4e->u;
109	if (!Pml4e.n.u1Present)
110	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
111	if (RT_UNLIKELY(!GST_IS_PML4E_VALID(pVCpu, Pml4e)))
112	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
113
114	/*
115	* The PDPE.
116	*/
117	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & X86_PML4E_PG_MASK_FULL, &pWalk->pPdpt);
118	if (RT_FAILURE(rc))
119	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
120
121	# elif PGM_GST_TYPE == PGM_TYPE_PAE
122	rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pWalk->pPdpt);
123	if (RT_FAILURE(rc))
124	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
125	# endif
126	}
127	{
128	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
129	PX86PDPT register pPdpt = pWalk->pPdpt;
130	PX86PDPE register pPdpe;
131	X86PDPE register Pdpe;
132
133	pWalk->pPdpe = pPdpe = &pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
134	pWalk->Pdpe.u = Pdpe.u = pPdpe->u;
135	if (!Pdpe.n.u1Present)
136	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
137	if (RT_UNLIKELY(!GST_IS_PDPE_VALID(pVCpu, Pdpe)))
138	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
139
140	/*
141	* The PDE.
142	*/
143	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpe.u & X86_PDPE_PG_MASK_FULL, &pWalk->pPd);
144	if (RT_FAILURE(rc))
145	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
146	# elif PGM_GST_TYPE == PGM_TYPE_32BIT
147	rc = pgmGstGet32bitPDPtrEx(pVCpu, &pWalk->pPd);
148	if (RT_FAILURE(rc))
149	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
150	# endif
151	}
152	{
153	PGSTPD register pPd = pWalk->pPd;
154	PGSTPDE register pPde;
155	GSTPDE Pde;
156
157	pWalk->pPde = pPde = &pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
158	pWalk->Pde.u = Pde.u = pPde->u;
159	if (!Pde.n.u1Present)
160	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
161	if (Pde.n.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
162	{
163	if (RT_UNLIKELY(!GST_IS_BIG_PDE_VALID(pVCpu, Pde)))
164	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
165
166	pWalk->Core.GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
167	\| (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
168	pWalk->Core.fBigPage = true;
169	pWalk->Core.fSucceeded = true;
170	return VINF_SUCCESS;
171	}
172
173	if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
174	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
175
176	/*
177	* The PTE.
178	*/
179	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pde.u & GST_PDE_PG_MASK, &pWalk->pPt);
180	if (RT_FAILURE(rc))
181	return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
182	}
183	{
184	PGSTPT register pPt = pWalk->pPt;
185	PGSTPTE register pPte;
186	GSTPTE register Pte;
187
188	pWalk->pPte = pPte = &pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
189	pWalk->Pte.u = Pte.u = pPte->u;
190	if (!Pte.n.u1Present)
191	return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
192	if (RT_UNLIKELY(!GST_IS_PTE_VALID(pVCpu, Pte)))
193	return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
194
195	/*
196	* We're done.
197	*/
198	pWalk->Core.GCPhys = (Pte.u & GST_PDE_PG_MASK)
199	\| (GCPtr & PAGE_OFFSET_MASK);
200	pWalk->Core.fSucceeded = true;
201	return VINF_SUCCESS;
202	}
203	}
204
205	#endif /* 32BIT, PAE, AMD64 */
206
207	/**
208	* Gets effective Guest OS page information.
209	*
210	* When GCPtr is in a big page, the function will return as if it was a normal
211	* 4KB page. If the need for distinguishing between big and normal page becomes
212	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
213	* purpose.
214	*
215	* @returns VBox status.
216	* @param pVCpu The VMCPU handle.
217	* @param GCPtr Guest Context virtual address of the page.
218	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
219	* @param pGCPhys Where to store the GC physical address of the page.
220	* This is page aligned!
221	*/
222	PGM_GST_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
223	{
224	#if PGM_GST_TYPE == PGM_TYPE_REAL \
225	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
226	/*
227	* Fake it.
228	*/
229	if (pfFlags)
230	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
231	if (pGCPhys)
232	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
233	return VINF_SUCCESS;
234
235	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
236	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
237	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
238
239	GSTPTWALK Walk;
240	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
241	if (RT_FAILURE(rc))
242	return rc;
243
244	if (pGCPhys)
245	*pGCPhys = Walk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
246
247	if (pfFlags)
248	{
249	/* The RW and US flags are determined via bitwise AND across all levels. */
250	uint64_t fUpperRwUs = (X86_PTE_RW \| X86_PTE_US)
251	# if PGM_GST_TYPE == PGM_TYPE_AMD64
252	& Walk.Pml4e.u
253	& Walk.Pdpe.u
254	# endif
255	& Walk.Pde.u;
256	fUpperRwUs \|= ~(uint64_t)(X86_PTE_RW \| X86_PTE_US);
257
258	/* The RW and US flags are determined via bitwise AND across all levels. */
259	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
260	uint32_t fUpperNx = 0
261	# if PGM_GST_TYPE == PGM_TYPE_AMD64
262	\| Walk.Pml4e.n.u1NoExecute
263	\| Walk.Pdpe.lm.u1NoExecute
264	# endif
265	\| Walk.Pde.n.u1NoExecute;
266	# endif
267
268	if (!Walk.Core.fBigPage)
269	{
270	*pfFlags = (Walk.Pte.u & ~GST_PTE_PG_MASK) & fUpperRwUs;
271	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
272	if (Walk.Pte.n.u1NoExecute \|\| fUpperNx)
273	{
274	Assert(GST_IS_NX_ACTIVE(pVCpu)); /* should trigger RSVD error otherwise. */
275	*pfFlags \|= X86_PTE_PAE_NX;
276	}
277	# endif
278	}
279	else
280	{
281	*pfFlags = ( (Walk.Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
282	\| ((Walk.Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT))
283	& fUpperRwUs;
284	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
285	if (fUpperNx)
286	{
287	Assert(GST_IS_NX_ACTIVE(pVCpu)); /* should trigger RSVD error otherwise. */
288	*pfFlags \|= X86_PTE_PAE_NX;
289	}
290	# endif
291	}
292	}
293
294	return VINF_SUCCESS;
295
296	#else
297	# error "shouldn't be here!"
298	/* something else... */
299	return VERR_NOT_SUPPORTED;
300	#endif
301	}
302
303
304	/**
305	* Modify page flags for a range of pages in the guest's tables
306	*
307	* The existing flags are ANDed with the fMask and ORed with the fFlags.
308	*
309	* @returns VBox status code.
310	* @param pVCpu The VMCPU handle.
311	* @param GCPtr Virtual address of the first page in the range. Page aligned!
312	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
313	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
314	* @param fMask The AND mask - page flags X86_PTE_*.
315	*/
316	PGM_GST_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
317	{
318	Assert((cb & PAGE_OFFSET_MASK) == 0);
319
320	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
321	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
322	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
323	for (;;)
324	{
325	GSTPTWALK Walk;
326	int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
327	if (RT_FAILURE(rc))
328	return rc;
329
330	if (!Walk.Core.fBigPage)
331	{
332	/*
333	* 4KB Page table, process
334	*
335	* Walk pages till we're done.
336	*/
337	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
338	while (iPTE < RT_ELEMENTS(Walk.pPt->a))
339	{
340	GSTPTE Pte = Walk.pPt->a[iPTE];
341	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
342	\| (fFlags & ~GST_PTE_PG_MASK);
343	Walk.pPt->a[iPTE] = Pte;
344
345	/* next page */
346	cb -= PAGE_SIZE;
347	if (!cb)
348	return VINF_SUCCESS;
349	GCPtr += PAGE_SIZE;
350	iPTE++;
351	}
352	}
353	else
354	{
355	/*
356	* 4MB Page table
357	*/
358	GSTPDE PdeNew;
359	# if PGM_GST_TYPE == PGM_TYPE_32BIT
360	PdeNew.u = (Walk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PG_HIGH_MASK \| X86_PDE4M_PS))
361	# else
362	PdeNew.u = (Walk.Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS))
363	# endif
364	\| (fFlags & ~GST_PTE_PG_MASK)
365	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
366	*Walk.pPde = PdeNew;
367
368	/* advance */
369	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
370	if (cbDone >= cb)
371	return VINF_SUCCESS;
372	cb -= cbDone;
373	GCPtr += cbDone;
374	}
375	}
376
377	#else
378	/* real / protected mode: ignore. */
379	return VINF_SUCCESS;
380	#endif
381	}
382
383
384	/**
385	* Retrieve guest PDE information.
386	*
387	* @returns VBox status code.
388	* @param pVCpu The VMCPU handle.
389	* @param GCPtr Guest context pointer.
390	* @param pPDE Pointer to guest PDE structure.
391	*/
392	PGM_GST_DECL(int, GetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPDE)
393	{
394	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
395	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
396	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
397
398	# if PGM_GST_TYPE != PGM_TYPE_AMD64
399	/* Boundary check. */
400	if (RT_UNLIKELY(GCPtr >= _4G))
401	return VERR_PAGE_TABLE_NOT_PRESENT;
402	# endif
403
404	# if PGM_GST_TYPE == PGM_TYPE_32BIT
405	unsigned iPd = (GCPtr >> GST_PD_SHIFT) & GST_PD_MASK;
406	PX86PD pPd = pgmGstGet32bitPDPtr(pVCpu);
407
408	# elif PGM_GST_TYPE == PGM_TYPE_PAE
409	unsigned iPd = 0; /* shut up gcc */
410	PCX86PDPAE pPd = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPd, NULL);
411
412	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
413	PX86PML4E pPml4eIgn;
414	X86PDPE PdpeIgn;
415	unsigned iPd = 0; /* shut up gcc */
416	PCX86PDPAE pPd = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eIgn, &PdpeIgn, &iPd);
417	/* Note! We do not return an effective PDE here like we do for the PTE in GetPage method. */
418	# endif
419
420	if (RT_LIKELY(pPd))
421	pPDE->u = (X86PGPAEUINT)pPd->a[iPd].u;
422	else
423	pPDE->u = 0;
424	return VINF_SUCCESS;
425
426	#else
427	AssertFailed();
428	return VERR_NOT_IMPLEMENTED;
429	#endif
430	}
431
432
433	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
434	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
435	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
436	/**
437	* Updates one virtual handler range.
438	*
439	* @returns 0
440	* @param pNode Pointer to a PGMVIRTHANDLER.
441	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
442	*/
443	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
444	{
445	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
446	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
447	PVM pVM = pState->pVM;
448	PVMCPU pVCpu = pState->pVCpu;
449	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
450
451	# if PGM_GST_TYPE == PGM_TYPE_32BIT
452	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
453	# endif
454
455	RTGCPTR GCPtr = pCur->Core.Key;
456	# if PGM_GST_TYPE != PGM_TYPE_AMD64
457	/* skip all stuff above 4GB if not AMD64 mode. */
458	if (RT_UNLIKELY(GCPtr >= _4G))
459	return 0;
460	# endif
461
462	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
463	unsigned iPage = 0;
464	while (iPage < pCur->cPages)
465	{
466	# if PGM_GST_TYPE == PGM_TYPE_32BIT
467	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
468	# elif PGM_GST_TYPE == PGM_TYPE_PAE
469	X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
470	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
471	X86PDEPAE Pde = pgmGstGetLongModePDE(pVCpu, GCPtr);
472	# endif
473	# if PGM_GST_TYPE == PGM_TYPE_32BIT
474	bool const fBigPage = Pde.b.u1Size;
475	# else
476	bool const fBigPage = Pde.b.u1Size && !(pState->cr4 & X86_CR4_PSE);
477	# endif
478	if ( Pde.n.u1Present
479	&& ( !fBigPage
480	? GST_IS_PDE_VALID(pVCpu, Pde)
481	: GST_IS_BIG_PDE_VALID(pVCpu, Pde)) )
482	{
483	if (!fBigPage)
484	{
485	/*
486	* Normal page table.
487	*/
488	PGSTPT pPT;
489	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
490	if (RT_SUCCESS(rc))
491	{
492	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
493	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
494	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
495	{
496	GSTPTE Pte = pPT->a[iPTE];
497	RTGCPHYS GCPhysNew;
498	if (Pte.n.u1Present)
499	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
500	else
501	GCPhysNew = NIL_RTGCPHYS;
502	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
503	{
504	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
505	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
506	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
507	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
508	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
509	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
510	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
511	#endif
512	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
513	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
514	}
515	}
516	}
517	else
518	{
519	/* not-present. */
520	offPage = 0;
521	AssertRC(rc);
522	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
523	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
524	iPTE++, iPage++, GCPtr += PAGE_SIZE)
525	{
526	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
527	{
528	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
529	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
530	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
531	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
532	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
533	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
534	#endif
535	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
536	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
537	}
538	}
539	}
540	}
541	else
542	{
543	/*
544	* 2/4MB page.
545	*/
546	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
547	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
548	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
549	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
550	{
551	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
552	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
553	{
554	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
555	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
556	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
557	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
558	("{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%RGp\n",
559	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
560	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
561	#endif
562	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
563	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
564	}
565	}
566	} /* pde type */
567	}
568	else
569	{
570	/* not-present / invalid. */
571	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
572	cPages && iPage < pCur->cPages;
573	iPage++, GCPtr += PAGE_SIZE)
574	{
575	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
576	{
577	pgmHandlerVirtualClearPage(&pVM->pgm.s, pCur, iPage);
578	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
579	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
580	}
581	}
582	offPage = 0;
583	}
584	} /* for pages in virtual mapping. */
585
586	return 0;
587	}
588	#endif /* 32BIT, PAE and AMD64 */
589
590
591	/**
592	* Updates the virtual page access handlers.
593	*
594	* @returns true if bits were flushed.
595	* @returns false if bits weren't flushed.
596	* @param pVM VM handle.
597	* @param pPDSrc The page directory.
598	* @param cr4 The cr4 register value.
599	*/
600	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
601	{
602	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
603	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
604	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
605
606	/** @todo
607	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
608	*/
609
610	/*
611	* Resolve any virtual address based access handlers to GC physical addresses.
612	* This should be fairly quick.
613	*/
614	RTUINT fTodo = 0;
615
616	pgmLock(pVM);
617	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
618
619	for (VMCPUID i = 0; i < pVM->cCpus; i++)
620	{
621	PGMHVUSTATE State;
622	PVMCPU pVCpu = &pVM->aCpus[i];
623
624	State.pVM = pVM;
625	State.pVCpu = pVCpu;
626	State.fTodo = pVCpu->pgm.s.fSyncFlags;
627	State.cr4 = cr4;
628	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
629
630	fTodo \|= State.fTodo;
631	}
632	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualUpdate), a);
633
634
635	/*
636	* Set / reset bits?
637	*/
638	if (fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
639	{
640	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
641	Log(("HandlerVirtualUpdate: resets bits\n"));
642	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
643
644	for (VMCPUID i = 0; i < pVM->cCpus; i++)
645	{
646	PVMCPU pVCpu = &pVM->aCpus[i];
647	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
648	}
649
650	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3HandlerVirtualReset), b);
651	}
652	pgmUnlock(pVM);
653
654	return !!(fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
655
656	#else /* real / protected */
657	return false;
658	#endif
659	}
660

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 31054

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