VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 7730

Last change on this file since 7730 was 7730, checked in by vboxsync, 17 years ago

Added CPUMSet/GetGuestEFER.
Corrected NX bit handling.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 41.2 KB
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1/* $Id: PGMAllGst.h 7730 2008-04-03 16:30:35Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Guest Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Defined Constants And Macros *
21*******************************************************************************/
22#undef GSTPT
23#undef PGSTPT
24#undef GSTPTE
25#undef PGSTPTE
26#undef GSTPD
27#undef PGSTPD
28#undef GSTPDE
29#undef PGSTPDE
30#undef GST_BIG_PAGE_SIZE
31#undef GST_BIG_PAGE_OFFSET_MASK
32#undef GST_PDE_PG_MASK
33#undef GST_PDE_BIG_PG_MASK
34#undef GST_PD_SHIFT
35#undef GST_PD_MASK
36#undef GST_PTE_PG_MASK
37#undef GST_PT_SHIFT
38#undef GST_PT_MASK
39#undef GST_TOTAL_PD_ENTRIES
40#undef GST_CR3_PAGE_MASK
41#undef GST_PDPE_ENTRIES
42#undef GST_PDPT_SHIFT
43#undef GST_PDPT_MASK
44
45#if PGM_GST_TYPE == PGM_TYPE_32BIT \
46 || PGM_GST_TYPE == PGM_TYPE_REAL \
47 || PGM_GST_TYPE == PGM_TYPE_PROT
48# define GSTPT X86PT
49# define PGSTPT PX86PT
50# define GSTPTE X86PTE
51# define PGSTPTE PX86PTE
52# define GSTPD X86PD
53# define PGSTPD PX86PD
54# define GSTPDE X86PDE
55# define PGSTPDE PX86PDE
56# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
57# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
58# define GST_PDE_PG_MASK X86_PDE_PG_MASK
59# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
60# define GST_PD_SHIFT X86_PD_SHIFT
61# define GST_PD_MASK X86_PD_MASK
62# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
63# define GST_PTE_PG_MASK X86_PTE_PG_MASK
64# define GST_PT_SHIFT X86_PT_SHIFT
65# define GST_PT_MASK X86_PT_MASK
66# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
67#elif PGM_GST_TYPE == PGM_TYPE_PAE \
68 || PGM_GST_TYPE == PGM_TYPE_AMD64
69# define GSTPT X86PTPAE
70# define PGSTPT PX86PTPAE
71# define GSTPTE X86PTEPAE
72# define PGSTPTE PX86PTEPAE
73# define GSTPD X86PDPAE
74# define PGSTPD PX86PDPAE
75# define GSTPDE X86PDEPAE
76# define PGSTPDE PX86PDEPAE
77# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
78# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
79# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
80# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
81# define GST_PD_SHIFT X86_PD_PAE_SHIFT
82# define GST_PD_MASK X86_PD_PAE_MASK
83# if PGM_GST_TYPE == PGM_TYPE_PAE
84# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
85# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
86# define GST_PDPT_SHIFT X86_PDPT_SHIFT
87# define GST_PDPT_MASK X86_PDPT_MASK_PAE
88# else
89# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
90# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
91# define GST_PDPT_SHIFT X86_PDPT_SHIFT
92# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
93# endif
94# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
95# define GST_PT_SHIFT X86_PT_PAE_SHIFT
96# define GST_PT_MASK X86_PT_PAE_MASK
97# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
98#endif
99
100
101/*******************************************************************************
102* Internal Functions *
103*******************************************************************************/
104__BEGIN_DECLS
105PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
106PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
107PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
108PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
109PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
110PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
111PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
112PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
113#ifndef IN_RING3
114PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
115# if PGM_GST_TYPE == PGM_TYPE_PAE \
116 || PGM_GST_TYPE == PGM_TYPE_AMD64
117PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
118# endif
119#endif
120__END_DECLS
121
122
123
124/**
125 * Gets effective Guest OS page information.
126 *
127 * When GCPtr is in a big page, the function will return as if it was a normal
128 * 4KB page. If the need for distinguishing between big and normal page becomes
129 * necessary at a later point, a PGMGstGetPage Ex() will be created for that
130 * purpose.
131 *
132 * @returns VBox status.
133 * @param pVM VM Handle.
134 * @param GCPtr Guest Context virtual address of the page. Page aligned!
135 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
136 * @param pGCPhys Where to store the GC physical address of the page.
137 * This is page aligned. The fact that the
138 */
139PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
140{
141#if PGM_GST_TYPE == PGM_TYPE_REAL \
142 || PGM_GST_TYPE == PGM_TYPE_PROT
143 /*
144 * Fake it.
145 */
146 if (pfFlags)
147 *pfFlags = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
148 if (pGCPhys)
149 *pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
150 return VINF_SUCCESS;
151
152#elif PGM_GST_TYPE == PGM_TYPE_AMD64
153 /* later */
154 /* check level 3 & 4 bits as well (r/w, u/s, nxe) */
155 AssertFailed();
156 return VERR_NOT_IMPLEMENTED;
157
158#elif PGM_GST_TYPE == PGM_GST_32BIT || PGM_GST_TYPE == PGM_GST_PAE
159
160 /*
161 * Get the PDE.
162 */
163# if PGM_GST_TYPE == PGM_TYPE_32BIT
164 const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
165# else /* PAE */
166 X86PDEPAE Pde;
167 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
168
169 /* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
170 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
171 */
172 Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
173# endif
174
175 /*
176 * Lookup the page.
177 */
178 if (!Pde.n.u1Present)
179 return VERR_PAGE_TABLE_NOT_PRESENT;
180
181 if ( !Pde.b.u1Size
182 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
183 {
184 PGSTPT pPT;
185 int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
186 if (VBOX_FAILURE(rc))
187 return rc;
188
189 /*
190 * Get PT entry and check presentness.
191 */
192 const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
193 if (!Pte.n.u1Present)
194 return VERR_PAGE_NOT_PRESENT;
195
196 /*
197 * Store the result.
198 * RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
199 * where the PDPE is simplified.
200 */
201 if (pfFlags)
202 {
203 *pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
204 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
205# if PGM_WITH_NX(PGM_GST_TYPE)
206 /* The NX bit is determined by a bitwise OR between the PT and PD */
207 if (fNoExecuteBitValid)
208 *pFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
209# endif
210 }
211 if (pGCPhys)
212 *pGCPhys = Pte.u & GST_PTE_PG_MASK;
213 }
214 else
215 {
216 /*
217 * Map big to 4k PTE and store the result
218 */
219 if (pfFlags)
220 {
221 *pfFlags = (Pde.u & ~(GST_PTE_PG_MASK | X86_PTE_PAT))
222 | ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
223# if PGM_WITH_NX(PGM_GST_TYPE)
224 /* The NX bit is determined by a bitwise OR between the PT and PD */
225 if (fNoExecuteBitValid)
226 *pfFlags |= (Pde.u & X86_PTE_PAE_NX);
227# endif
228 }
229 if (pGCPhys)
230 *pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) | (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /** @todo pse36 */
231 }
232 return VINF_SUCCESS;
233#else
234 /* something else... */
235 return VERR_NOT_SUPPORTED;
236#endif
237}
238
239
240/**
241 * Modify page flags for a range of pages in the guest's tables
242 *
243 * The existing flags are ANDed with the fMask and ORed with the fFlags.
244 *
245 * @returns VBox status code.
246 * @param pVM VM handle.
247 * @param GCPtr Virtual address of the first page in the range. Page aligned!
248 * @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
249 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
250 * @param fMask The AND mask - page flags X86_PTE_*.
251 */
252PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
253{
254#if PGM_GST_TYPE == PGM_TYPE_32BIT \
255 || PGM_GST_TYPE == PGM_TYPE_PAE \
256 || PGM_GST_TYPE == PGM_TYPE_AMD64
257
258#if PGM_GST_TYPE == PGM_TYPE_AMD64
259 /* later */
260 /* check level 3 & 4 bits as well (r/w, u/s, nxe) */
261 AssertFailed();
262 return VERR_NOT_IMPLEMENTED;
263#endif
264
265 for (;;)
266 {
267 /*
268 * Get the PD entry.
269 */
270#if PGM_GST_TYPE == PGM_TYPE_32BIT
271 PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
272#else /* PAE */
273 /* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
274 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
275 */
276 PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
277 Assert(pPde);
278 if (!pPde)
279 return VERR_PAGE_TABLE_NOT_PRESENT;
280#endif
281 GSTPDE Pde = *pPde;
282 Assert(Pde.n.u1Present);
283 if (!Pde.n.u1Present)
284 return VERR_PAGE_TABLE_NOT_PRESENT;
285
286 if ( !Pde.b.u1Size
287 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
288 {
289 /*
290 * 4KB Page table
291 *
292 * Walk page tables and pages till we're done.
293 */
294 PGSTPT pPT;
295 int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
296 if (VBOX_FAILURE(rc))
297 return rc;
298
299 unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
300 while (iPTE < RT_ELEMENTS(pPT->a))
301 {
302 GSTPTE Pte = pPT->a[iPTE];
303 Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK))
304 | (fFlags & ~GST_PTE_PG_MASK);
305 pPT->a[iPTE] = Pte;
306
307 /* next page */
308 cb -= PAGE_SIZE;
309 if (!cb)
310 return VINF_SUCCESS;
311 GCPtr += PAGE_SIZE;
312 iPTE++;
313 }
314 }
315 else
316 {
317 /*
318 * 4MB Page table
319 */
320 Pde.u = (Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PS)) /** @todo pse36 */
321 | (fFlags & ~GST_PTE_PG_MASK)
322 | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
323 *pPde = Pde;
324
325 /* advance */
326 const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
327 if (cbDone >= cb)
328 return VINF_SUCCESS;
329 cb -= cbDone;
330 GCPtr += cbDone;
331 }
332 }
333
334#else
335 /* real / protected mode: ignore. */
336 return VINF_SUCCESS;
337#endif
338}
339
340
341/**
342 * Retrieve guest PDE information
343 *
344 * @returns VBox status code.
345 * @param pVM The virtual machine.
346 * @param GCPtr Guest context pointer
347 * @param pPDE Pointer to guest PDE structure
348 */
349PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
350{
351#if PGM_GST_TYPE == PGM_TYPE_32BIT \
352 || PGM_GST_TYPE == PGM_TYPE_PAE \
353 || PGM_GST_TYPE == PGM_TYPE_AMD64
354
355#if PGM_GST_TYPE == PGM_TYPE_AMD64
356 /* later */
357 AssertFailed();
358 return VERR_NOT_IMPLEMENTED;
359#endif
360
361# if PGM_GST_TYPE == PGM_TYPE_32BIT
362 X86PDE Pde;
363 Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
364# else
365 X86PDEPAE Pde;
366 Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
367# endif
368
369 pPDE->u = (X86PGPAEUINT)Pde.u;
370 return VINF_SUCCESS;
371#else
372 AssertFailed();
373 return VERR_NOT_IMPLEMENTED;
374#endif
375}
376
377
378
379/**
380 * Maps the CR3 into HMA in GC and locate it in HC.
381 *
382 * @returns VBox status, no specials.
383 * @param pVM VM handle.
384 * @param GCPhysCR3 The physical address in the CR3 register.
385 */
386PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
387{
388#if PGM_GST_TYPE == PGM_TYPE_32BIT \
389 || PGM_GST_TYPE == PGM_TYPE_PAE \
390 || PGM_GST_TYPE == PGM_TYPE_AMD64
391 /*
392 * Map the page CR3 points at.
393 */
394 RTHCPHYS HCPhysGuestCR3;
395 RTHCPTR HCPtrGuestCR3;
396 int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3, &HCPtrGuestCR3, &HCPhysGuestCR3);
397 if (VBOX_SUCCESS(rc))
398 {
399 rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3 & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
400 if (VBOX_SUCCESS(rc))
401 {
402 PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
403#if PGM_GST_TYPE == PGM_TYPE_32BIT
404 pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
405 pVM->pgm.s.pGuestPDGC = (GCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
406
407#elif PGM_GST_TYPE == PGM_TYPE_PAE
408 const unsigned off = GCPhysCR3 & X86_CR3_PAE_PAGE_MASK;
409 pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT))((RTHCUINTPTR)HCPtrGuestCR3 | off);
410 pVM->pgm.s.pGstPaePDPTGC = (GCPTRTYPE(PX86PDPT))((RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping | off);
411
412 /*
413 * Map the 4 PDs too.
414 */
415 RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
416 for (unsigned i = 0; i < 4; i++, GCPtr += PAGE_SIZE)
417 {
418 if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
419 {
420 RTHCPTR HCPtr;
421 RTHCPHYS HCPhys;
422 RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
423 int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
424 if (VBOX_SUCCESS(rc2))
425 {
426 rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
427 AssertRCReturn(rc, rc);
428 pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
429 pVM->pgm.s.apGstPaePDsGC[i] = (GCPTRTYPE(PX86PDPAE))GCPtr;
430 pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
431 PGM_INVL_PG(GCPtr);
432 continue;
433 }
434 AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
435 }
436
437 pVM->pgm.s.apGstPaePDsHC[i] = 0;
438 pVM->pgm.s.apGstPaePDsGC[i] = 0;
439 pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
440 PGM_INVL_PG(GCPtr);
441 }
442
443#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
444 rc = VERR_NOT_IMPLEMENTED;
445#endif
446 }
447 }
448 else
449 AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
450
451#else /* prot/real mode stub */
452 int rc = VINF_SUCCESS;
453#endif
454 return rc;
455}
456
457
458/**
459 * Unmaps the CR3.
460 *
461 * @returns VBox status, no specials.
462 * @param pVM VM handle.
463 * @param GCPhysCR3 The physical address in the CR3 register.
464 */
465PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
466{
467 int rc = VINF_SUCCESS;
468#if PGM_GST_TYPE == PGM_TYPE_32BIT
469 pVM->pgm.s.pGuestPDHC = 0;
470 pVM->pgm.s.pGuestPDGC = 0;
471
472#elif PGM_GST_TYPE == PGM_TYPE_PAE
473 pVM->pgm.s.pGstPaePDPTHC = 0;
474 pVM->pgm.s.pGstPaePDPTGC = 0;
475 /** PAE todo: pVM->pgm.s.apGstPaePDsHC? -> unmap?? */
476 AssertFailed();
477
478#elif PGM_GST_TYPE == PGM_TYPE_AMD64
479//#error not implemented
480 rc = VERR_NOT_IMPLEMENTED;
481
482#else /* prot/real mode stub */
483 /* nothing to do */
484#endif
485 return rc;
486}
487
488
489#undef LOG_GROUP
490#define LOG_GROUP LOG_GROUP_PGM_POOL
491
492/**
493 * Registers physical page monitors for the necessary paging
494 * structures to detect conflicts with our guest mappings.
495 *
496 * This is always called after mapping CR3.
497 * This is never called with fixed mappings.
498 *
499 * @returns VBox status, no specials.
500 * @param pVM VM handle.
501 * @param GCPhysCR3 The physical address in the CR3 register.
502 */
503PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
504{
505 Assert(!pVM->pgm.s.fMappingsFixed);
506 int rc = VINF_SUCCESS;
507
508#if PGM_GST_TYPE == PGM_TYPE_32BIT \
509 || PGM_GST_TYPE == PGM_TYPE_PAE \
510 || PGM_GST_TYPE == PGM_TYPE_AMD64
511
512 /*
513 * Register/Modify write phys handler for guest's CR3 if it changed.
514 */
515 if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
516 {
517# ifndef PGMPOOL_WITH_MIXED_PT_CR3
518 const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
519 if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
520 rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
521 else
522 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
523 pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
524 pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
525 pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
526 pVM->pgm.s.pszR3GstWriteHandlerCR3);
527# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
528 rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
529 pVM->pgm.s.enmShadowMode == PGMMODE_PAE
530 || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
531 ? PGMPOOL_IDX_PAE_PD
532 : PGMPOOL_IDX_PD,
533 GCPhysCR3);
534# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
535 if (VBOX_FAILURE(rc))
536 {
537 AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
538 rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
539 return rc;
540 }
541 pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
542 }
543
544#if PGM_GST_TYPE == PGM_TYPE_PAE
545 /*
546 * Do the 4 PDs.
547 */
548 for (unsigned i = 0; i < 4; i++)
549 {
550 if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
551 {
552 RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
553# ifndef PGMPOOL_WITH_MIXED_PT_CR3
554 if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
555 {
556 if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
557 rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys, GCPhys + PAGE_SIZE - 1);
558 else
559 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhys, GCPhys + PAGE_SIZE - 1,
560 pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3, 0,
561 pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3, 0,
562 pVM->pgm.s.pfnGCGstPAEWriteHandlerCR3, 0,
563 pVM->pgm.s.pszR3GstPAEWriteHandlerCR3);
564 if (VBOX_SUCCESS(rc))
565 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
566 }
567# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
568 /** PAE todo */
569 AssertFailed();
570 rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
571 pVM->pgm.s.enmShadowMode == PGMMODE_PAE
572 || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
573 ? PGMPOOL_IDX_PAE_PD
574 : PGMPOOL_IDX_PD,
575 GCPhys);
576# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
577 if (VBOX_FAILURE(rc))
578 {
579 AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
580 rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
581 return rc;
582 }
583 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
584 }
585 else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
586 {
587 rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]);
588 AssertRC(rc);
589 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
590 }
591 }
592#endif /* PGM_GST_TYPE == PGM_TYPE_PAE */
593
594#else
595 /* prot/real mode stub */
596
597#endif
598 return rc;
599}
600
601/**
602 * Deregisters any physical page monitors installed by MonitorCR3.
603 *
604 * @returns VBox status code, no specials.
605 * @param pVM The VM handle.
606 */
607PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
608{
609 int rc = VINF_SUCCESS;
610
611#if PGM_GST_TYPE == PGM_TYPE_32BIT \
612 || PGM_GST_TYPE == PGM_TYPE_PAE \
613 || PGM_GST_TYPE == PGM_TYPE_AMD64
614
615 /*
616 * Deregister the access handlers.
617 *
618 * PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
619 * before we enter GC again.
620 */
621 if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
622 {
623# ifndef PGMPOOL_WITH_MIXED_PT_CR3
624 rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
625 AssertRCReturn(rc, rc);
626# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
627 rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
628 pVM->pgm.s.enmShadowMode == PGMMODE_PAE
629 || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
630 ? PGMPOOL_IDX_PAE_PD
631 : PGMPOOL_IDX_PD);
632 AssertRCReturn(rc, rc);
633# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
634 pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
635 }
636
637# if PGM_GST_TYPE == PGM_TYPE_PAE
638 /* The 4 PDs. */
639 for (unsigned i = 0; i < 4; i++)
640 if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
641 {
642# ifndef PGMPOOL_WITH_MIXED_PT_CR3
643 int rc2 = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]);
644# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
645 /** PAE todo */
646 AssertFailed();
647 int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
648 pVM->pgm.s.enmShadowMode == PGMMODE_PAE
649 || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
650 ? PGMPOOL_IDX_PAE_PD
651 : PGMPOOL_IDX_PD);
652# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
653 AssertRC(rc2);
654 if (VBOX_FAILURE(rc2))
655 rc = rc2;
656 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
657 }
658# endif
659
660#else
661 /* prot/real mode stub */
662#endif
663 return rc;
664
665}
666
667#undef LOG_GROUP
668#define LOG_GROUP LOG_GROUP_PGM
669
670
671#if PGM_GST_TYPE == PGM_TYPE_32BIT \
672 || PGM_GST_TYPE == PGM_TYPE_PAE \
673 || PGM_GST_TYPE == PGM_TYPE_AMD64
674/**
675 * Updates one virtual handler range.
676 *
677 * @returns 0
678 * @param pNode Pointer to a PGMVIRTHANDLER.
679 * @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
680 */
681static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
682{
683 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
684 PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
685 Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
686
687#if PGM_GST_TYPE == PGM_TYPE_32BIT
688 PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
689#endif
690
691 RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
692#if PGM_GST_MODE != PGM_MODE_AMD64
693 /* skip all stuff above 4GB if not AMD64 mode. */
694 if (GCPtr >= _4GB)
695 return 0;
696#endif
697
698 unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
699 unsigned iPage = 0;
700 while (iPage < pCur->cPages)
701 {
702#if PGM_GST_TYPE == PGM_TYPE_32BIT
703 X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
704#else
705 X86PDEPAE Pde;
706 Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
707#endif
708 if (Pde.n.u1Present)
709 {
710 if (!Pde.b.u1Size || !(pState->cr4 & X86_CR4_PSE))
711 {
712 /*
713 * Normal page table.
714 */
715 PGSTPT pPT;
716 int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
717 if (VBOX_SUCCESS(rc))
718 {
719 for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
720 iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
721 iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
722 {
723 GSTPTE Pte = pPT->a[iPTE];
724 RTGCPHYS GCPhysNew;
725 if (Pte.n.u1Present)
726 GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
727 else
728 GCPhysNew = NIL_RTGCPHYS;
729 if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
730 {
731 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
732 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
733#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
734 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
735 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
736 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
737 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
738#endif
739 pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
740 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
741 }
742 }
743 }
744 else
745 {
746 /* not-present. */
747 offPage = 0;
748 AssertRC(rc);
749 for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
750 iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
751 iPTE++, iPage++, GCPtr += PAGE_SIZE)
752 {
753 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
754 {
755 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
756#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
757 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
758 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
759 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
760 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
761#endif
762 pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
763 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
764 }
765 }
766 }
767 }
768 else
769 {
770 /*
771 * 2/4MB page.
772 */
773 RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
774 for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
775 i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
776 i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
777 {
778 RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
779 if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
780 {
781 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
782 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
783#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
784 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
785 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
786 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
787 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
788#endif
789 pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
790 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
791 }
792 }
793 } /* pde type */
794 }
795 else
796 {
797 /* not-present. */
798 for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
799 cPages && iPage < pCur->cPages;
800 iPage++, GCPtr += PAGE_SIZE)
801 {
802 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
803 {
804 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
805 pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
806 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
807 }
808 }
809 offPage = 0;
810 }
811 } /* for pages in virtual mapping. */
812
813 return 0;
814}
815#endif /* 32BIT, PAE and AMD64 */
816
817
818/**
819 * Updates the virtual page access handlers.
820 *
821 * @returns true if bits were flushed.
822 * @returns false if bits weren't flushed.
823 * @param pVM VM handle.
824 * @param pPDSrc The page directory.
825 * @param cr4 The cr4 register value.
826 */
827PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
828{
829#if PGM_GST_TYPE == PGM_TYPE_32BIT \
830 || PGM_GST_TYPE == PGM_TYPE_PAE \
831 || PGM_GST_TYPE == PGM_TYPE_AMD64
832
833#if PGM_GST_TYPE == PGM_TYPE_AMD64
834 AssertFailed();
835#endif
836
837 /** @todo
838 * In theory this is not sufficient: the guest can change a single page in a range with invlpg
839 */
840
841 /*
842 * Resolve any virtual address based access handlers to GC physical addresses.
843 * This should be fairly quick.
844 */
845 PGMHVUSTATE State;
846
847 pgmLock(pVM);
848 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
849 State.pVM = pVM;
850 State.fTodo = pVM->pgm.s.fSyncFlags;
851 State.cr4 = cr4;
852 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
853 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
854
855
856 /*
857 * Set / reset bits?
858 */
859 if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
860 {
861 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
862 Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
863 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
864 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
865 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
866 }
867 pgmUnlock(pVM);
868
869 return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
870
871#else /* real / protected */
872 return false;
873#endif
874}
875
876
877#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
878
879/**
880 * Write access handler for the Guest CR3 page in 32-bit mode.
881 *
882 * This will try interpret the instruction, if failure fail back to the recompiler.
883 * Check if the changed PDEs are marked present and conflicts with our
884 * mappings. If conflict, we'll switch to the host context and resolve it there
885 *
886 * @returns VBox status code (appropritate for trap handling and GC return).
887 * @param pVM VM Handle.
888 * @param uErrorCode CPU Error code.
889 * @param pRegFrame Trap register frame.
890 * @param pvFault The fault address (cr2).
891 * @param GCPhysFault The GC physical address corresponding to pvFault.
892 * @param pvUser User argument.
893 */
894PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
895{
896 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
897
898 /*
899 * Try interpret the instruction.
900 */
901 uint32_t cb;
902 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
903 if (VBOX_SUCCESS(rc) && cb)
904 {
905 /*
906 * Check if the modified PDEs are present and mappings.
907 */
908 const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
909 const unsigned iPD1 = offPD / sizeof(X86PDE);
910 const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
911
912 Assert(cb > 0 && cb <= 8);
913 Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
914 Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
915
916#ifdef DEBUG
917 Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
918 if (iPD1 != iPD2)
919 Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
920#endif
921
922 if (!pVM->pgm.s.fMappingsFixed)
923 {
924 PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
925 if ( ( pPDSrc->a[iPD1].n.u1Present
926 && pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
927 || ( iPD1 != iPD2
928 && pPDSrc->a[iPD2].n.u1Present
929 && pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
930 )
931 {
932 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
933 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
934 if (rc == VINF_SUCCESS)
935 rc = VINF_PGM_SYNC_CR3;
936 Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
937 return rc;
938 }
939 }
940
941 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
942 }
943 else
944 {
945 Assert(VBOX_FAILURE(rc));
946 if (rc == VERR_EM_INTERPRETER)
947 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
948 Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
949 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
950 }
951 return rc;
952}
953
954#endif /* PGM_TYPE_32BIT && !IN_RING3 */
955
956
957#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
958
959/**
960 * Write access handler for the Guest CR3 page in PAE mode.
961 *
962 * This will try interpret the instruction, if failure fail back to the recompiler.
963 * Check if the changed PDEs are marked present and conflicts with our
964 * mappings. If conflict, we'll switch to the host context and resolve it there
965 *
966 * @returns VBox status code (appropritate for trap handling and GC return).
967 * @param pVM VM Handle.
968 * @param uErrorCode CPU Error code.
969 * @param pRegFrame Trap register frame.
970 * @param pvFault The fault address (cr2).
971 * @param GCPhysFault The GC physical address corresponding to pvFault.
972 * @param pvUser User argument.
973 */
974PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
975{
976 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
977
978 /*
979 * Try interpret the instruction.
980 */
981 uint32_t cb;
982 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
983 if (VBOX_SUCCESS(rc) && cb)
984 {
985 /*
986 * Check if any of the PDs have changed.
987 * We'll simply check all of them instead of figuring out which one/two to check.
988 */
989 for (unsigned i = 0; i < 4; i++)
990 {
991 if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
992 && ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
993 != pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
994 {
995 /*
996 * The PDPE has changed.
997 * We will schedule a monitoring update for the next TLB Flush,
998 * InvalidatePage or SyncCR3.
999 *
1000 * This isn't perfect, because a lazy page sync might be dealing with an half
1001 * updated PDPE. However, we assume that the guest OS is disabling interrupts
1002 * and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1003 * executing.
1004 */
1005 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1006 Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1007 i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1008 }
1009 }
1010
1011 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1012 }
1013 else
1014 {
1015 Assert(VBOX_FAILURE(rc));
1016 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1017 if (rc == VERR_EM_INTERPRETER)
1018 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1019 }
1020 Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1021 return rc;
1022}
1023
1024
1025/**
1026 * Write access handler for the Guest PDs in PAE mode.
1027 *
1028 * This will try interpret the instruction, if failure fail back to the recompiler.
1029 * Check if the changed PDEs are marked present and conflicts with our
1030 * mappings. If conflict, we'll switch to the host context and resolve it there
1031 *
1032 * @returns VBox status code (appropritate for trap handling and GC return).
1033 * @param pVM VM Handle.
1034 * @param uErrorCode CPU Error code.
1035 * @param pRegFrame Trap register frame.
1036 * @param pvFault The fault address (cr2).
1037 * @param GCPhysFault The GC physical address corresponding to pvFault.
1038 * @param pvUser User argument.
1039 */
1040PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1041{
1042 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1043
1044 /*
1045 * Try interpret the instruction.
1046 */
1047 uint32_t cb;
1048 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1049 if (VBOX_SUCCESS(rc) && cb)
1050 {
1051 /*
1052 * Figure out which of the 4 PDs this is.
1053 */
1054 RTGCUINTPTR i;
1055 for (i = 0; i < 4; i++)
1056 if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1057 {
1058 PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1059 const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1060 const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1061 const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1062
1063 Assert(cb > 0 && cb <= 8);
1064 Assert(iPD1 < X86_PG_PAE_ENTRIES);
1065 Assert(iPD2 < X86_PG_PAE_ENTRIES);
1066
1067#ifdef DEBUG
1068 Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1069 i, iPD1, (i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT)));
1070 if (iPD1 != iPD2)
1071 Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1072 i, iPD2, (i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT)));
1073#endif
1074
1075 if (!pVM->pgm.s.fMappingsFixed)
1076 {
1077 if ( ( pPDSrc->a[iPD1].n.u1Present
1078 && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT))) )
1079 || ( iPD1 != iPD2
1080 && pPDSrc->a[iPD2].n.u1Present
1081 && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT))) )
1082 )
1083 {
1084 Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1085 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1086 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1087 return VINF_PGM_SYNC_CR3;
1088 }
1089 }
1090 break; /* ASSUMES no duplicate entries... */
1091 }
1092 Assert(i < 4);
1093
1094 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1095 }
1096 else
1097 {
1098 Assert(VBOX_FAILURE(rc));
1099 if (rc == VERR_EM_INTERPRETER)
1100 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1101 else
1102 Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1103 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1104 }
1105 return rc;
1106}
1107
1108#endif /* PGM_TYPE_PAE && !IN_RING3 */
1109
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