VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 8160

Last change on this file since 8160 was 8160, checked in by vboxsync, 17 years ago

All CRx registers are now 64 bits.
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File size: 41.2 KB
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1/* $Id: PGMAllGst.h 8160 2008-04-18 16:15:42Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Guest Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Defined Constants And Macros *
25*******************************************************************************/
26#undef GSTPT
27#undef PGSTPT
28#undef GSTPTE
29#undef PGSTPTE
30#undef GSTPD
31#undef PGSTPD
32#undef GSTPDE
33#undef PGSTPDE
34#undef GST_BIG_PAGE_SIZE
35#undef GST_BIG_PAGE_OFFSET_MASK
36#undef GST_PDE_PG_MASK
37#undef GST_PDE_BIG_PG_MASK
38#undef GST_PD_SHIFT
39#undef GST_PD_MASK
40#undef GST_PTE_PG_MASK
41#undef GST_PT_SHIFT
42#undef GST_PT_MASK
43#undef GST_TOTAL_PD_ENTRIES
44#undef GST_CR3_PAGE_MASK
45#undef GST_PDPE_ENTRIES
46#undef GST_PDPT_SHIFT
47#undef GST_PDPT_MASK
48
49#if PGM_GST_TYPE == PGM_TYPE_32BIT \
50 || PGM_GST_TYPE == PGM_TYPE_REAL \
51 || PGM_GST_TYPE == PGM_TYPE_PROT
52# define GSTPT X86PT
53# define PGSTPT PX86PT
54# define GSTPTE X86PTE
55# define PGSTPTE PX86PTE
56# define GSTPD X86PD
57# define PGSTPD PX86PD
58# define GSTPDE X86PDE
59# define PGSTPDE PX86PDE
60# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
61# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
62# define GST_PDE_PG_MASK X86_PDE_PG_MASK
63# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
64# define GST_PD_SHIFT X86_PD_SHIFT
65# define GST_PD_MASK X86_PD_MASK
66# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
67# define GST_PTE_PG_MASK X86_PTE_PG_MASK
68# define GST_PT_SHIFT X86_PT_SHIFT
69# define GST_PT_MASK X86_PT_MASK
70# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
71#elif PGM_GST_TYPE == PGM_TYPE_PAE \
72 || PGM_GST_TYPE == PGM_TYPE_AMD64
73# define GSTPT X86PTPAE
74# define PGSTPT PX86PTPAE
75# define GSTPTE X86PTEPAE
76# define PGSTPTE PX86PTEPAE
77# define GSTPD X86PDPAE
78# define PGSTPD PX86PDPAE
79# define GSTPDE X86PDEPAE
80# define PGSTPDE PX86PDEPAE
81# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
82# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
83# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
84# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
85# define GST_PD_SHIFT X86_PD_PAE_SHIFT
86# define GST_PD_MASK X86_PD_PAE_MASK
87# if PGM_GST_TYPE == PGM_TYPE_PAE
88# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
89# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
90# define GST_PDPT_SHIFT X86_PDPT_SHIFT
91# define GST_PDPT_MASK X86_PDPT_MASK_PAE
92# else
93# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
94# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
95# define GST_PDPT_SHIFT X86_PDPT_SHIFT
96# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
97# endif
98# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
99# define GST_PT_SHIFT X86_PT_PAE_SHIFT
100# define GST_PT_MASK X86_PT_PAE_MASK
101# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
102#endif
103
104
105/*******************************************************************************
106* Internal Functions *
107*******************************************************************************/
108__BEGIN_DECLS
109PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
110PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
111PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
112PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
113PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
114PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
115PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
116PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
117#ifndef IN_RING3
118PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
119# if PGM_GST_TYPE == PGM_TYPE_PAE \
120 || PGM_GST_TYPE == PGM_TYPE_AMD64
121PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
122# endif
123#endif
124__END_DECLS
125
126
127
128/**
129 * Gets effective Guest OS page information.
130 *
131 * When GCPtr is in a big page, the function will return as if it was a normal
132 * 4KB page. If the need for distinguishing between big and normal page becomes
133 * necessary at a later point, a PGMGstGetPage Ex() will be created for that
134 * purpose.
135 *
136 * @returns VBox status.
137 * @param pVM VM Handle.
138 * @param GCPtr Guest Context virtual address of the page. Page aligned!
139 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
140 * @param pGCPhys Where to store the GC physical address of the page.
141 * This is page aligned. The fact that the
142 */
143PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
144{
145#if PGM_GST_TYPE == PGM_TYPE_REAL \
146 || PGM_GST_TYPE == PGM_TYPE_PROT
147 /*
148 * Fake it.
149 */
150 if (pfFlags)
151 *pfFlags = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
152 if (pGCPhys)
153 *pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
154 return VINF_SUCCESS;
155
156#elif PGM_GST_TYPE == PGM_TYPE_AMD64
157 /* later */
158 /* check level 3 & 4 bits as well (r/w, u/s, nxe) */
159 AssertFailed();
160 return VERR_NOT_IMPLEMENTED;
161
162#elif PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE
163
164 /*
165 * Get the PDE.
166 */
167# if PGM_GST_TYPE == PGM_TYPE_32BIT
168 const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
169# else /* PAE */
170 X86PDEPAE Pde;
171 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
172
173 /* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
174 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
175 */
176 Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
177# endif
178
179 /*
180 * Lookup the page.
181 */
182 if (!Pde.n.u1Present)
183 return VERR_PAGE_TABLE_NOT_PRESENT;
184
185 if ( !Pde.b.u1Size
186 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
187 {
188 PGSTPT pPT;
189 int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
190 if (VBOX_FAILURE(rc))
191 return rc;
192
193 /*
194 * Get PT entry and check presence.
195 */
196 const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
197 if (!Pte.n.u1Present)
198 return VERR_PAGE_NOT_PRESENT;
199
200 /*
201 * Store the result.
202 * RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
203 * where the PDPE is simplified.
204 */
205 if (pfFlags)
206 {
207 *pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
208 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
209# if PGM_WITH_NX(PGM_GST_TYPE)
210 /* The NX bit is determined by a bitwise OR between the PT and PD */
211 if (fNoExecuteBitValid)
212 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
213# endif
214 }
215 if (pGCPhys)
216 *pGCPhys = Pte.u & GST_PTE_PG_MASK;
217 }
218 else
219 {
220 /*
221 * Map big to 4k PTE and store the result
222 */
223 if (pfFlags)
224 {
225 *pfFlags = (Pde.u & ~(GST_PTE_PG_MASK | X86_PTE_PAT))
226 | ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
227# if PGM_WITH_NX(PGM_GST_TYPE)
228 /* The NX bit is determined by a bitwise OR between the PT and PD */
229 if (fNoExecuteBitValid)
230 *pfFlags |= (Pde.u & X86_PTE_PAE_NX);
231# endif
232 }
233 if (pGCPhys)
234 *pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) | (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /** @todo pse36 */
235 }
236 return VINF_SUCCESS;
237#else
238# error "shouldn't be here!"
239 /* something else... */
240 return VERR_NOT_SUPPORTED;
241#endif
242}
243
244
245/**
246 * Modify page flags for a range of pages in the guest's tables
247 *
248 * The existing flags are ANDed with the fMask and ORed with the fFlags.
249 *
250 * @returns VBox status code.
251 * @param pVM VM handle.
252 * @param GCPtr Virtual address of the first page in the range. Page aligned!
253 * @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
254 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
255 * @param fMask The AND mask - page flags X86_PTE_*.
256 */
257PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
258{
259#if PGM_GST_TYPE == PGM_TYPE_32BIT \
260 || PGM_GST_TYPE == PGM_TYPE_PAE \
261 || PGM_GST_TYPE == PGM_TYPE_AMD64
262
263#if PGM_GST_TYPE == PGM_TYPE_AMD64
264 /* later */
265 /* check level 3 & 4 bits as well (r/w, u/s, nxe) */
266 AssertFailed();
267 return VERR_NOT_IMPLEMENTED;
268#endif
269
270 for (;;)
271 {
272 /*
273 * Get the PD entry.
274 */
275#if PGM_GST_TYPE == PGM_TYPE_32BIT
276 PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
277#else /* PAE */
278 /* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
279 * All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
280 */
281 PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
282 Assert(pPde);
283 if (!pPde)
284 return VERR_PAGE_TABLE_NOT_PRESENT;
285#endif
286 GSTPDE Pde = *pPde;
287 Assert(Pde.n.u1Present);
288 if (!Pde.n.u1Present)
289 return VERR_PAGE_TABLE_NOT_PRESENT;
290
291 if ( !Pde.b.u1Size
292 || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
293 {
294 /*
295 * 4KB Page table
296 *
297 * Walk page tables and pages till we're done.
298 */
299 PGSTPT pPT;
300 int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
301 if (VBOX_FAILURE(rc))
302 return rc;
303
304 unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
305 while (iPTE < RT_ELEMENTS(pPT->a))
306 {
307 GSTPTE Pte = pPT->a[iPTE];
308 Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK))
309 | (fFlags & ~GST_PTE_PG_MASK);
310 pPT->a[iPTE] = Pte;
311
312 /* next page */
313 cb -= PAGE_SIZE;
314 if (!cb)
315 return VINF_SUCCESS;
316 GCPtr += PAGE_SIZE;
317 iPTE++;
318 }
319 }
320 else
321 {
322 /*
323 * 4MB Page table
324 */
325 Pde.u = (Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PS)) /** @todo pse36 */
326 | (fFlags & ~GST_PTE_PG_MASK)
327 | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
328 *pPde = Pde;
329
330 /* advance */
331 const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
332 if (cbDone >= cb)
333 return VINF_SUCCESS;
334 cb -= cbDone;
335 GCPtr += cbDone;
336 }
337 }
338
339#else
340 /* real / protected mode: ignore. */
341 return VINF_SUCCESS;
342#endif
343}
344
345
346/**
347 * Retrieve guest PDE information
348 *
349 * @returns VBox status code.
350 * @param pVM The virtual machine.
351 * @param GCPtr Guest context pointer
352 * @param pPDE Pointer to guest PDE structure
353 */
354PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
355{
356#if PGM_GST_TYPE == PGM_TYPE_32BIT \
357 || PGM_GST_TYPE == PGM_TYPE_PAE \
358 || PGM_GST_TYPE == PGM_TYPE_AMD64
359
360#if PGM_GST_TYPE == PGM_TYPE_AMD64
361 /* later */
362 AssertFailed();
363 return VERR_NOT_IMPLEMENTED;
364#endif
365
366# if PGM_GST_TYPE == PGM_TYPE_32BIT
367 X86PDE Pde;
368 Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
369# else
370 X86PDEPAE Pde;
371 Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
372# endif
373
374 pPDE->u = (X86PGPAEUINT)Pde.u;
375 return VINF_SUCCESS;
376#else
377 AssertFailed();
378 return VERR_NOT_IMPLEMENTED;
379#endif
380}
381
382
383
384/**
385 * Maps the CR3 into HMA in GC and locate it in HC.
386 *
387 * @returns VBox status, no specials.
388 * @param pVM VM handle.
389 * @param GCPhysCR3 The physical address in the CR3 register.
390 */
391PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
392{
393#if PGM_GST_TYPE == PGM_TYPE_32BIT \
394 || PGM_GST_TYPE == PGM_TYPE_PAE \
395 || PGM_GST_TYPE == PGM_TYPE_AMD64
396
397 LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
398
399 /*
400 * Map the page CR3 points at.
401 */
402 RTHCPHYS HCPhysGuestCR3;
403 RTHCPTR HCPtrGuestCR3;
404 int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
405 if (VBOX_SUCCESS(rc))
406 {
407 rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
408 if (VBOX_SUCCESS(rc))
409 {
410 PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
411#if PGM_GST_TYPE == PGM_TYPE_32BIT
412 pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
413 pVM->pgm.s.pGuestPDGC = (GCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
414
415#elif PGM_GST_TYPE == PGM_TYPE_PAE
416 unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
417 pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
418 pVM->pgm.s.pGstPaePDPTGC = (GCPTRTYPE(PX86PDPT)) ((GCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
419 Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
420
421 /*
422 * Map the 4 PDs too.
423 */
424 RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
425 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
426 {
427 if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
428 {
429 RTHCPTR HCPtr;
430 RTHCPHYS HCPhys;
431 RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
432 int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
433 if (VBOX_SUCCESS(rc2))
434 {
435 rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
436 AssertRCReturn(rc, rc);
437 pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
438 pVM->pgm.s.apGstPaePDsGC[i] = (GCPTRTYPE(PX86PDPAE))GCPtr;
439 pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
440 PGM_INVL_PG(GCPtr);
441 continue;
442 }
443 AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
444 }
445
446 pVM->pgm.s.apGstPaePDsHC[i] = 0;
447 pVM->pgm.s.apGstPaePDsGC[i] = 0;
448 pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
449 PGM_INVL_PG(GCPtr);
450 }
451
452#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
453 rc = VERR_NOT_IMPLEMENTED;
454#endif
455 }
456 else
457 AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
458 }
459 else
460 AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
461
462#else /* prot/real mode stub */
463 int rc = VINF_SUCCESS;
464#endif
465 return rc;
466}
467
468
469/**
470 * Unmaps the CR3.
471 *
472 * @returns VBox status, no specials.
473 * @param pVM VM handle.
474 * @param GCPhysCR3 The physical address in the CR3 register.
475 */
476PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
477{
478 LogFlow(("UnmapCR3\n"));
479
480 int rc = VINF_SUCCESS;
481#if PGM_GST_TYPE == PGM_TYPE_32BIT
482 pVM->pgm.s.pGuestPDHC = 0;
483 pVM->pgm.s.pGuestPDGC = 0;
484
485#elif PGM_GST_TYPE == PGM_TYPE_PAE
486 pVM->pgm.s.pGstPaePDPTHC = 0;
487 pVM->pgm.s.pGstPaePDPTGC = 0;
488 for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
489 {
490 pVM->pgm.s.apGstPaePDsHC[i] = 0;
491 pVM->pgm.s.apGstPaePDsGC[i] = 0;
492 pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
493 }
494
495#elif PGM_GST_TYPE == PGM_TYPE_AMD64
496//#error not implemented
497 rc = VERR_NOT_IMPLEMENTED;
498
499#else /* prot/real mode stub */
500 /* nothing to do */
501#endif
502 return rc;
503}
504
505
506#undef LOG_GROUP
507#define LOG_GROUP LOG_GROUP_PGM_POOL
508
509/**
510 * Registers physical page monitors for the necessary paging
511 * structures to detect conflicts with our guest mappings.
512 *
513 * This is always called after mapping CR3.
514 * This is never called with fixed mappings.
515 *
516 * @returns VBox status, no specials.
517 * @param pVM VM handle.
518 * @param GCPhysCR3 The physical address in the CR3 register.
519 */
520PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
521{
522 Assert(!pVM->pgm.s.fMappingsFixed);
523 int rc = VINF_SUCCESS;
524
525 /*
526 * Register/Modify write phys handler for guest's CR3 if it changed.
527 */
528#if PGM_GST_TYPE == PGM_TYPE_32BIT
529
530 if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
531 {
532# ifndef PGMPOOL_WITH_MIXED_PT_CR3
533 const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
534 if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
535 rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
536 else
537 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
538 pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
539 pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
540 pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
541 pVM->pgm.s.pszR3GstWriteHandlerCR3);
542# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
543 rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
544 pVM->pgm.s.enmShadowMode == PGMMODE_PAE
545 || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
546 ? PGMPOOL_IDX_PAE_PD
547 : PGMPOOL_IDX_PD,
548 GCPhysCR3);
549# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
550 if (VBOX_FAILURE(rc))
551 {
552 AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
553 rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
554 return rc;
555 }
556 pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
557 }
558
559#elif PGM_GST_TYPE == PGM_TYPE_PAE
560 /* Monitor the PDPT page */
561 /*
562 * Register/Modify write phys handler for guest's CR3 if it changed.
563 */
564# ifndef PGMPOOL_WITH_MIXED_PT_CR3
565 AssertFailed();
566# endif
567 if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
568 {
569 rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
570 if (VBOX_FAILURE(rc))
571 {
572 AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
573 rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
574 return rc;
575 }
576 pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
577 }
578 /*
579 * Do the 4 PDs.
580 */
581 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
582 {
583 if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
584 {
585 RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
586 if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
587 {
588 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
589
590 rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
591 }
592
593 if (VBOX_FAILURE(rc))
594 {
595 AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
596 rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
597 return rc;
598 }
599 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
600 }
601 else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
602 {
603 rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
604 AssertRC(rc);
605 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
606 }
607 }
608
609#elif PGM_GST_TYPE == PGM_TYPE_AMD64
610 AssertFailed();
611#else
612 /* prot/real mode stub */
613
614#endif
615 return rc;
616}
617
618/**
619 * Deregisters any physical page monitors installed by MonitorCR3.
620 *
621 * @returns VBox status code, no specials.
622 * @param pVM The VM handle.
623 */
624PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
625{
626 int rc = VINF_SUCCESS;
627
628 /*
629 * Deregister the access handlers.
630 *
631 * PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
632 * before we enter GC again.
633 */
634#if PGM_GST_TYPE == PGM_TYPE_32BIT
635 if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
636 {
637# ifndef PGMPOOL_WITH_MIXED_PT_CR3
638 rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
639 AssertRCReturn(rc, rc);
640# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
641 rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
642 pVM->pgm.s.enmShadowMode == PGMMODE_PAE
643 || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
644 ? PGMPOOL_IDX_PAE_PD
645 : PGMPOOL_IDX_PD);
646 AssertRCReturn(rc, rc);
647# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
648 pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
649 }
650
651#elif PGM_GST_TYPE == PGM_TYPE_PAE
652 /* The PDPT page */
653# ifndef PGMPOOL_WITH_MIXED_PT_CR3
654 AssertFailed();
655# endif
656
657 if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
658 {
659 rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
660 AssertRC(rc);
661 }
662
663 /* The 4 PDs. */
664 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
665 {
666 if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
667 {
668 Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE || pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
669 int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
670 AssertRC(rc2);
671 if (VBOX_FAILURE(rc2))
672 rc = rc2;
673 pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
674 }
675 }
676#elif PGM_GST_TYPE == PGM_TYPE_AMD64
677 AssertFailed();
678#else
679 /* prot/real mode stub */
680#endif
681 return rc;
682
683}
684
685#undef LOG_GROUP
686#define LOG_GROUP LOG_GROUP_PGM
687
688
689#if PGM_GST_TYPE == PGM_TYPE_32BIT \
690 || PGM_GST_TYPE == PGM_TYPE_PAE \
691 || PGM_GST_TYPE == PGM_TYPE_AMD64
692/**
693 * Updates one virtual handler range.
694 *
695 * @returns 0
696 * @param pNode Pointer to a PGMVIRTHANDLER.
697 * @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
698 */
699static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
700{
701 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
702 PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
703 Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
704
705#if PGM_GST_TYPE == PGM_TYPE_32BIT
706 PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
707#endif
708
709 RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
710#if PGM_GST_MODE != PGM_MODE_AMD64
711 /* skip all stuff above 4GB if not AMD64 mode. */
712 if (GCPtr >= _4GB)
713 return 0;
714#endif
715
716 unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
717 unsigned iPage = 0;
718 while (iPage < pCur->cPages)
719 {
720#if PGM_GST_TYPE == PGM_TYPE_32BIT
721 X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
722#else
723 X86PDEPAE Pde;
724 Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
725#endif
726 if (Pde.n.u1Present)
727 {
728 if (!Pde.b.u1Size || !(pState->cr4 & X86_CR4_PSE))
729 {
730 /*
731 * Normal page table.
732 */
733 PGSTPT pPT;
734 int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
735 if (VBOX_SUCCESS(rc))
736 {
737 for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
738 iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
739 iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
740 {
741 GSTPTE Pte = pPT->a[iPTE];
742 RTGCPHYS GCPhysNew;
743 if (Pte.n.u1Present)
744 GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
745 else
746 GCPhysNew = NIL_RTGCPHYS;
747 if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
748 {
749 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
750 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
751#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
752 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
753 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
754 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
755 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
756#endif
757 pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
758 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
759 }
760 }
761 }
762 else
763 {
764 /* not-present. */
765 offPage = 0;
766 AssertRC(rc);
767 for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
768 iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
769 iPTE++, iPage++, GCPtr += PAGE_SIZE)
770 {
771 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
772 {
773 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
774#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
775 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
776 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
777 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
778 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
779#endif
780 pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
781 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
782 }
783 }
784 }
785 }
786 else
787 {
788 /*
789 * 2/4MB page.
790 */
791 RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
792 for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
793 i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
794 i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
795 {
796 RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
797 if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
798 {
799 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
800 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
801#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
802 AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
803 ("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
804 pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
805 pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
806#endif
807 pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
808 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
809 }
810 }
811 } /* pde type */
812 }
813 else
814 {
815 /* not-present. */
816 for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
817 cPages && iPage < pCur->cPages;
818 iPage++, GCPtr += PAGE_SIZE)
819 {
820 if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
821 {
822 pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
823 pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
824 pState->fTodo |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
825 }
826 }
827 offPage = 0;
828 }
829 } /* for pages in virtual mapping. */
830
831 return 0;
832}
833#endif /* 32BIT, PAE and AMD64 */
834
835
836/**
837 * Updates the virtual page access handlers.
838 *
839 * @returns true if bits were flushed.
840 * @returns false if bits weren't flushed.
841 * @param pVM VM handle.
842 * @param pPDSrc The page directory.
843 * @param cr4 The cr4 register value.
844 */
845PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
846{
847#if PGM_GST_TYPE == PGM_TYPE_32BIT \
848 || PGM_GST_TYPE == PGM_TYPE_PAE \
849 || PGM_GST_TYPE == PGM_TYPE_AMD64
850
851#if PGM_GST_TYPE == PGM_TYPE_AMD64
852 AssertFailed();
853#endif
854
855 /** @todo
856 * In theory this is not sufficient: the guest can change a single page in a range with invlpg
857 */
858
859 /*
860 * Resolve any virtual address based access handlers to GC physical addresses.
861 * This should be fairly quick.
862 */
863 PGMHVUSTATE State;
864
865 pgmLock(pVM);
866 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
867 State.pVM = pVM;
868 State.fTodo = pVM->pgm.s.fSyncFlags;
869 State.cr4 = cr4;
870 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
871 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
872
873
874 /*
875 * Set / reset bits?
876 */
877 if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
878 {
879 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
880 Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
881 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
882 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
883 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
884 }
885 pgmUnlock(pVM);
886
887 return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
888
889#else /* real / protected */
890 return false;
891#endif
892}
893
894
895#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
896
897/**
898 * Write access handler for the Guest CR3 page in 32-bit mode.
899 *
900 * This will try interpret the instruction, if failure fail back to the recompiler.
901 * Check if the changed PDEs are marked present and conflicts with our
902 * mappings. If conflict, we'll switch to the host context and resolve it there
903 *
904 * @returns VBox status code (appropritate for trap handling and GC return).
905 * @param pVM VM Handle.
906 * @param uErrorCode CPU Error code.
907 * @param pRegFrame Trap register frame.
908 * @param pvFault The fault address (cr2).
909 * @param GCPhysFault The GC physical address corresponding to pvFault.
910 * @param pvUser User argument.
911 */
912PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
913{
914 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
915
916 /*
917 * Try interpret the instruction.
918 */
919 uint32_t cb;
920 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
921 if (VBOX_SUCCESS(rc) && cb)
922 {
923 /*
924 * Check if the modified PDEs are present and mappings.
925 */
926 const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
927 const unsigned iPD1 = offPD / sizeof(X86PDE);
928 const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
929
930 Assert(cb > 0 && cb <= 8);
931 Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
932 Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
933
934#ifdef DEBUG
935 Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
936 if (iPD1 != iPD2)
937 Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
938#endif
939
940 if (!pVM->pgm.s.fMappingsFixed)
941 {
942 PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
943 if ( ( pPDSrc->a[iPD1].n.u1Present
944 && pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
945 || ( iPD1 != iPD2
946 && pPDSrc->a[iPD2].n.u1Present
947 && pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
948 )
949 {
950 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
951 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
952 if (rc == VINF_SUCCESS)
953 rc = VINF_PGM_SYNC_CR3;
954 Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
955 return rc;
956 }
957 }
958
959 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
960 }
961 else
962 {
963 Assert(VBOX_FAILURE(rc));
964 if (rc == VERR_EM_INTERPRETER)
965 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
966 Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
967 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
968 }
969 return rc;
970}
971
972#endif /* PGM_TYPE_32BIT && !IN_RING3 */
973
974
975#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
976
977/**
978 * Write access handler for the Guest CR3 page in PAE mode.
979 *
980 * This will try interpret the instruction, if failure fail back to the recompiler.
981 * Check if the changed PDEs are marked present and conflicts with our
982 * mappings. If conflict, we'll switch to the host context and resolve it there
983 *
984 * @returns VBox status code (appropritate for trap handling and GC return).
985 * @param pVM VM Handle.
986 * @param uErrorCode CPU Error code.
987 * @param pRegFrame Trap register frame.
988 * @param pvFault The fault address (cr2).
989 * @param GCPhysFault The GC physical address corresponding to pvFault.
990 * @param pvUser User argument.
991 */
992PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
993{
994 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
995
996 /*
997 * Try interpret the instruction.
998 */
999 uint32_t cb;
1000 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1001 if (VBOX_SUCCESS(rc) && cb)
1002 {
1003 /*
1004 * Check if any of the PDs have changed.
1005 * We'll simply check all of them instead of figuring out which one/two to check.
1006 */
1007 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1008 {
1009 if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1010 && ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1011 != pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1012 {
1013 /*
1014 * The PDPE has changed.
1015 * We will schedule a monitoring update for the next TLB Flush,
1016 * InvalidatePage or SyncCR3.
1017 *
1018 * This isn't perfect, because a lazy page sync might be dealing with an half
1019 * updated PDPE. However, we assume that the guest OS is disabling interrupts
1020 * and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1021 * executing.
1022 */
1023 pVM->pgm.s.fSyncFlags |= PGM_SYNC_MONITOR_CR3;
1024 Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1025 i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1026 }
1027 }
1028
1029 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1030 }
1031 else
1032 {
1033 Assert(VBOX_FAILURE(rc));
1034 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1035 if (rc == VERR_EM_INTERPRETER)
1036 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1037 }
1038 Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1039 return rc;
1040}
1041
1042
1043/**
1044 * Write access handler for the Guest PDs in PAE mode.
1045 *
1046 * This will try interpret the instruction, if failure fail back to the recompiler.
1047 * Check if the changed PDEs are marked present and conflicts with our
1048 * mappings. If conflict, we'll switch to the host context and resolve it there
1049 *
1050 * @returns VBox status code (appropritate for trap handling and GC return).
1051 * @param pVM VM Handle.
1052 * @param uErrorCode CPU Error code.
1053 * @param pRegFrame Trap register frame.
1054 * @param pvFault The fault address (cr2).
1055 * @param GCPhysFault The GC physical address corresponding to pvFault.
1056 * @param pvUser User argument.
1057 */
1058PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1059{
1060 AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1061
1062 /*
1063 * Try interpret the instruction.
1064 */
1065 uint32_t cb;
1066 int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1067 if (VBOX_SUCCESS(rc) && cb)
1068 {
1069 /*
1070 * Figure out which of the 4 PDs this is.
1071 */
1072 RTGCUINTPTR i;
1073 for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1074 if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1075 {
1076 PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1077 const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1078 const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1079 const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1080
1081 Assert(cb > 0 && cb <= 8);
1082 Assert(iPD1 < X86_PG_PAE_ENTRIES);
1083 Assert(iPD2 < X86_PG_PAE_ENTRIES);
1084
1085#ifdef DEBUG
1086 Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1087 i, iPD1, (i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT)));
1088 if (iPD1 != iPD2)
1089 Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1090 i, iPD2, (i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT)));
1091#endif
1092
1093 if (!pVM->pgm.s.fMappingsFixed)
1094 {
1095 if ( ( pPDSrc->a[iPD1].n.u1Present
1096 && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD1 << X86_PD_PAE_SHIFT))) )
1097 || ( iPD1 != iPD2
1098 && pPDSrc->a[iPD2].n.u1Present
1099 && pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) | (iPD2 << X86_PD_PAE_SHIFT))) )
1100 )
1101 {
1102 Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1103 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1104 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1105 return VINF_PGM_SYNC_CR3;
1106 }
1107 }
1108 break; /* ASSUMES no duplicate entries... */
1109 }
1110 Assert(i < 4);
1111
1112 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1113 }
1114 else
1115 {
1116 Assert(VBOX_FAILURE(rc));
1117 if (rc == VERR_EM_INTERPRETER)
1118 rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1119 else
1120 Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1121 STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1122 }
1123 return rc;
1124}
1125
1126#endif /* PGM_TYPE_PAE && !IN_RING3 */
1127
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