PGMAllGst.h@ 8861

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1	/* $Id: PGMAllGst.h 8537 2008-05-02 17:00:34Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48
49	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
50	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
51	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
52	# define GSTPT X86PT
53	# define PGSTPT PX86PT
54	# define GSTPTE X86PTE
55	# define PGSTPTE PX86PTE
56	# define GSTPD X86PD
57	# define PGSTPD PX86PD
58	# define GSTPDE X86PDE
59	# define PGSTPDE PX86PDE
60	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
61	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
62	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
63	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
64	# define GST_PD_SHIFT X86_PD_SHIFT
65	# define GST_PD_MASK X86_PD_MASK
66	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
67	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
68	# define GST_PT_SHIFT X86_PT_SHIFT
69	# define GST_PT_MASK X86_PT_MASK
70	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
71	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
72	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
73	# define GSTPT X86PTPAE
74	# define PGSTPT PX86PTPAE
75	# define GSTPTE X86PTEPAE
76	# define PGSTPTE PX86PTEPAE
77	# define GSTPD X86PDPAE
78	# define PGSTPD PX86PDPAE
79	# define GSTPDE X86PDEPAE
80	# define PGSTPDE PX86PDEPAE
81	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
82	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
83	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
84	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
85	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
86	# define GST_PD_MASK X86_PD_PAE_MASK
87	# if PGM_GST_TYPE == PGM_TYPE_PAE
88	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
89	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
90	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
91	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
92	# else
93	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
94	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
95	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
96	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
97	# endif
98	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
99	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
100	# define GST_PT_MASK X86_PT_PAE_MASK
101	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
102	#endif
103
104
105	/*******************************************************************************
106	* Internal Functions *
107	*******************************************************************************/
108	__BEGIN_DECLS
109	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
110	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
111	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
112	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
113	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
114	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
115	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
116	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
117	#ifndef IN_RING3
118	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
119	# if PGM_GST_TYPE == PGM_TYPE_PAE \
120	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
121	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
122	# endif
123	#endif
124	__END_DECLS
125
126
127
128	/**
129	* Gets effective Guest OS page information.
130	*
131	* When GCPtr is in a big page, the function will return as if it was a normal
132	* 4KB page. If the need for distinguishing between big and normal page becomes
133	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
134	* purpose.
135	*
136	* @returns VBox status.
137	* @param pVM VM Handle.
138	* @param GCPtr Guest Context virtual address of the page. Page aligned!
139	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
140	* @param pGCPhys Where to store the GC physical address of the page.
141	* This is page aligned. The fact that the
142	*/
143	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
144	{
145	#if PGM_GST_TYPE == PGM_TYPE_REAL \
146	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
147	/*
148	* Fake it.
149	*/
150	if (pfFlags)
151	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
152	if (pGCPhys)
153	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
154	return VINF_SUCCESS;
155
156	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
157
158	/*
159	* Get the PDE.
160	*/
161	# if PGM_GST_TYPE == PGM_TYPE_32BIT
162	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
163	#elif PGM_GST_TYPE == PGM_TYPE_PAE
164	X86PDEPAE Pde;
165	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
166
167	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
168	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
169	*/
170	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
171	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
172	PX86PML4E pPml4e;
173	X86PDPE Pdpe;
174	X86PDEPAE Pde;
175	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
176
177	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
178	Assert(pPml4e);
179	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
180	return VERR_PAGE_TABLE_NOT_PRESENT;
181
182	/* Merge accessed, write, user and no-execute bits into the PDE. */
183	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
184	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
185	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
186	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
187	# endif
188
189	/*
190	* Lookup the page.
191	*/
192	if (!Pde.n.u1Present)
193	return VERR_PAGE_TABLE_NOT_PRESENT;
194
195	if ( !Pde.b.u1Size
196	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
197	{
198	PGSTPT pPT;
199	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
200	if (VBOX_FAILURE(rc))
201	return rc;
202
203	/*
204	* Get PT entry and check presence.
205	*/
206	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
207	if (!Pte.n.u1Present)
208	return VERR_PAGE_NOT_PRESENT;
209
210	/*
211	* Store the result.
212	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
213	* where the PDPE is simplified.
214	*/
215	if (pfFlags)
216	{
217	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
218	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
219	# if PGM_WITH_NX(PGM_GST_TYPE)
220	/* The NX bit is determined by a bitwise OR between the PT and PD */
221	if (fNoExecuteBitValid)
222	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
223	# endif
224	}
225	if (pGCPhys)
226	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
227	}
228	else
229	{
230	/*
231	* Map big to 4k PTE and store the result
232	*/
233	if (pfFlags)
234	{
235	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
236	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
237	# if PGM_WITH_NX(PGM_GST_TYPE)
238	/* The NX bit is determined by a bitwise OR between the PT and PD */
239	if (fNoExecuteBitValid)
240	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
241	# endif
242	}
243	if (pGCPhys)
244	pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /* @todo pse36 */
245	}
246	return VINF_SUCCESS;
247	#else
248	# error "shouldn't be here!"
249	/* something else... */
250	return VERR_NOT_SUPPORTED;
251	#endif
252	}
253
254
255	/**
256	* Modify page flags for a range of pages in the guest's tables
257	*
258	* The existing flags are ANDed with the fMask and ORed with the fFlags.
259	*
260	* @returns VBox status code.
261	* @param pVM VM handle.
262	* @param GCPtr Virtual address of the first page in the range. Page aligned!
263	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
264	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
265	* @param fMask The AND mask - page flags X86_PTE_*.
266	*/
267	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
268	{
269	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
270	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
271	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
272
273	for (;;)
274	{
275	/*
276	* Get the PD entry.
277	*/
278	#if PGM_GST_TYPE == PGM_TYPE_32BIT
279	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
280	#elif PGM_GST_TYPE == PGM_TYPE_PAE
281	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
282	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
283	*/
284	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
285	Assert(pPde);
286	if (!pPde)
287	return VERR_PAGE_TABLE_NOT_PRESENT;
288	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
289	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
290	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
291	Assert(pPde);
292	if (!pPde)
293	return VERR_PAGE_TABLE_NOT_PRESENT;
294	#endif
295	GSTPDE Pde = *pPde;
296	Assert(Pde.n.u1Present);
297	if (!Pde.n.u1Present)
298	return VERR_PAGE_TABLE_NOT_PRESENT;
299
300	if ( !Pde.b.u1Size
301	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
302	{
303	/*
304	* 4KB Page table
305	*
306	* Walk page tables and pages till we're done.
307	*/
308	PGSTPT pPT;
309	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
310	if (VBOX_FAILURE(rc))
311	return rc;
312
313	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
314	while (iPTE < RT_ELEMENTS(pPT->a))
315	{
316	GSTPTE Pte = pPT->a[iPTE];
317	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
318	\| (fFlags & ~GST_PTE_PG_MASK);
319	pPT->a[iPTE] = Pte;
320
321	/* next page */
322	cb -= PAGE_SIZE;
323	if (!cb)
324	return VINF_SUCCESS;
325	GCPtr += PAGE_SIZE;
326	iPTE++;
327	}
328	}
329	else
330	{
331	/*
332	* 4MB Page table
333	*/
334	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS)) /** @todo pse36 */
335	\| (fFlags & ~GST_PTE_PG_MASK)
336	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
337	*pPde = Pde;
338
339	/* advance */
340	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
341	if (cbDone >= cb)
342	return VINF_SUCCESS;
343	cb -= cbDone;
344	GCPtr += cbDone;
345	}
346	}
347
348	#else
349	/* real / protected mode: ignore. */
350	return VINF_SUCCESS;
351	#endif
352	}
353
354
355	/**
356	* Retrieve guest PDE information
357	*
358	* @returns VBox status code.
359	* @param pVM The virtual machine.
360	* @param GCPtr Guest context pointer
361	* @param pPDE Pointer to guest PDE structure
362	*/
363	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
364	{
365	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
366	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
367	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
368
369	# if PGM_GST_TYPE == PGM_TYPE_32BIT
370	X86PDE Pde;
371	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
372	# elif PGM_GST_TYPE == PGM_TYPE_PAE
373	X86PDEPAE Pde;
374	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
375	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
376	X86PDEPAE Pde;
377	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
378	# endif
379
380	pPDE->u = (X86PGPAEUINT)Pde.u;
381	return VINF_SUCCESS;
382	#else
383	AssertFailed();
384	return VERR_NOT_IMPLEMENTED;
385	#endif
386	}
387
388
389
390	/**
391	* Maps the CR3 into HMA in GC and locate it in HC.
392	*
393	* @returns VBox status, no specials.
394	* @param pVM VM handle.
395	* @param GCPhysCR3 The physical address in the CR3 register.
396	*/
397	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
398	{
399	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
400	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
401	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
402
403	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
404
405	/*
406	* Map the page CR3 points at.
407	*/
408	RTHCPHYS HCPhysGuestCR3;
409	RTHCPTR HCPtrGuestCR3;
410	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
411	if (VBOX_SUCCESS(rc))
412	{
413	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
414	if (VBOX_SUCCESS(rc))
415	{
416	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
417	#if PGM_GST_TYPE == PGM_TYPE_32BIT
418	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
419	pVM->pgm.s.pGuestPDGC = (GCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
420
421	#elif PGM_GST_TYPE == PGM_TYPE_PAE
422	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
423	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
424	pVM->pgm.s.pGstPaePDPTGC = (GCPTRTYPE(PX86PDPT)) ((GCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
425	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
426
427	/*
428	* Map the 4 PDs too.
429	*/
430	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
431	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
432	{
433	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
434	{
435	RTHCPTR HCPtr;
436	RTHCPHYS HCPhys;
437	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
438	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
439	if (VBOX_SUCCESS(rc2))
440	{
441	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
442	AssertRCReturn(rc, rc);
443	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
444	pVM->pgm.s.apGstPaePDsGC[i] = (GCPTRTYPE(PX86PDPAE))GCPtr;
445	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
446	PGM_INVL_PG(GCPtr);
447	continue;
448	}
449	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
450	}
451
452	pVM->pgm.s.apGstPaePDsHC[i] = 0;
453	pVM->pgm.s.apGstPaePDsGC[i] = 0;
454	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
455	PGM_INVL_PG(GCPtr);
456	}
457
458	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
459	rc = VERR_NOT_IMPLEMENTED;
460	#endif
461	}
462	else
463	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
464	}
465	else
466	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
467
468	#else /* prot/real mode stub */
469	int rc = VINF_SUCCESS;
470	#endif
471	return rc;
472	}
473
474
475	/**
476	* Unmaps the CR3.
477	*
478	* @returns VBox status, no specials.
479	* @param pVM VM handle.
480	* @param GCPhysCR3 The physical address in the CR3 register.
481	*/
482	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
483	{
484	LogFlow(("UnmapCR3\n"));
485
486	int rc = VINF_SUCCESS;
487	#if PGM_GST_TYPE == PGM_TYPE_32BIT
488	pVM->pgm.s.pGuestPDHC = 0;
489	pVM->pgm.s.pGuestPDGC = 0;
490
491	#elif PGM_GST_TYPE == PGM_TYPE_PAE
492	pVM->pgm.s.pGstPaePDPTHC = 0;
493	pVM->pgm.s.pGstPaePDPTGC = 0;
494	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
495	{
496	pVM->pgm.s.apGstPaePDsHC[i] = 0;
497	pVM->pgm.s.apGstPaePDsGC[i] = 0;
498	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
499	}
500
501	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
502	//#error not implemented
503	rc = VERR_NOT_IMPLEMENTED;
504
505	#else /* prot/real mode stub */
506	/* nothing to do */
507	#endif
508	return rc;
509	}
510
511
512	#undef LOG_GROUP
513	#define LOG_GROUP LOG_GROUP_PGM_POOL
514
515	/**
516	* Registers physical page monitors for the necessary paging
517	* structures to detect conflicts with our guest mappings.
518	*
519	* This is always called after mapping CR3.
520	* This is never called with fixed mappings.
521	*
522	* @returns VBox status, no specials.
523	* @param pVM VM handle.
524	* @param GCPhysCR3 The physical address in the CR3 register.
525	*/
526	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
527	{
528	Assert(!pVM->pgm.s.fMappingsFixed);
529	int rc = VINF_SUCCESS;
530
531	/*
532	* Register/Modify write phys handler for guest's CR3 if it changed.
533	*/
534	#if PGM_GST_TYPE == PGM_TYPE_32BIT
535
536	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
537	{
538	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
539	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
540	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
541	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
542	else
543	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
544	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
545	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
546	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
547	pVM->pgm.s.pszR3GstWriteHandlerCR3);
548	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
549	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
550	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
551	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
552	? PGMPOOL_IDX_PAE_PD
553	: PGMPOOL_IDX_PD,
554	GCPhysCR3);
555	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
556	if (VBOX_FAILURE(rc))
557	{
558	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
559	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
560	return rc;
561	}
562	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
563	}
564
565	#elif PGM_GST_TYPE == PGM_TYPE_PAE
566	/* Monitor the PDPT page */
567	/*
568	* Register/Modify write phys handler for guest's CR3 if it changed.
569	*/
570	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
571	AssertFailed();
572	# endif
573	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
574	{
575	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
576	if (VBOX_FAILURE(rc))
577	{
578	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
579	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
580	return rc;
581	}
582	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
583	}
584	/*
585	* Do the 4 PDs.
586	*/
587	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
588	{
589	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
590	{
591	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
592	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
593	{
594	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
595
596	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
597	}
598
599	if (VBOX_FAILURE(rc))
600	{
601	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
602	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
603	return rc;
604	}
605	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
606	}
607	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
608	{
609	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
610	AssertRC(rc);
611	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
612	}
613	}
614
615	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
616	AssertFailed();
617	#else
618	/* prot/real mode stub */
619
620	#endif
621	return rc;
622	}
623
624	/**
625	* Deregisters any physical page monitors installed by MonitorCR3.
626	*
627	* @returns VBox status code, no specials.
628	* @param pVM The VM handle.
629	*/
630	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
631	{
632	int rc = VINF_SUCCESS;
633
634	/*
635	* Deregister the access handlers.
636	*
637	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
638	* before we enter GC again.
639	*/
640	#if PGM_GST_TYPE == PGM_TYPE_32BIT
641	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
642	{
643	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
644	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
645	AssertRCReturn(rc, rc);
646	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
647	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
648	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
649	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
650	? PGMPOOL_IDX_PAE_PD
651	: PGMPOOL_IDX_PD);
652	AssertRCReturn(rc, rc);
653	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
654	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
655	}
656
657	#elif PGM_GST_TYPE == PGM_TYPE_PAE
658	/* The PDPT page */
659	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
660	AssertFailed();
661	# endif
662
663	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
664	{
665	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
666	AssertRC(rc);
667	}
668
669	/* The 4 PDs. */
670	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
671	{
672	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
673	{
674	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
675	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
676	AssertRC(rc2);
677	if (VBOX_FAILURE(rc2))
678	rc = rc2;
679	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
680	}
681	}
682	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
683	AssertFailed();
684	#else
685	/* prot/real mode stub */
686	#endif
687	return rc;
688
689	}
690
691	#undef LOG_GROUP
692	#define LOG_GROUP LOG_GROUP_PGM
693
694
695	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
696	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
697	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
698	/**
699	* Updates one virtual handler range.
700	*
701	* @returns 0
702	* @param pNode Pointer to a PGMVIRTHANDLER.
703	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
704	*/
705	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
706	{
707	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
708	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
709	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
710
711	#if PGM_GST_TYPE == PGM_TYPE_32BIT
712	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
713	#endif
714
715	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
716	#if PGM_GST_MODE != PGM_MODE_AMD64
717	/* skip all stuff above 4GB if not AMD64 mode. */
718	if (GCPtr >= _4GB)
719	return 0;
720	#endif
721
722	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
723	unsigned iPage = 0;
724	while (iPage < pCur->cPages)
725	{
726	#if PGM_GST_TYPE == PGM_TYPE_32BIT
727	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
728	#elif PGM_GST_TYPE == PGM_TYPE_PAE
729	X86PDEPAE Pde;
730	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
731	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
732	X86PDEPAE Pde;
733	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
734	#endif
735	if (Pde.n.u1Present)
736	{
737	if (!Pde.b.u1Size \|\| !(pState->cr4 & X86_CR4_PSE))
738	{
739	/*
740	* Normal page table.
741	*/
742	PGSTPT pPT;
743	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
744	if (VBOX_SUCCESS(rc))
745	{
746	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
747	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
748	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
749	{
750	GSTPTE Pte = pPT->a[iPTE];
751	RTGCPHYS GCPhysNew;
752	if (Pte.n.u1Present)
753	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
754	else
755	GCPhysNew = NIL_RTGCPHYS;
756	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
757	{
758	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
759	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
760	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
761	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
762	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
763	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
764	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
765	#endif
766	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
767	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
768	}
769	}
770	}
771	else
772	{
773	/* not-present. */
774	offPage = 0;
775	AssertRC(rc);
776	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
777	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
778	iPTE++, iPage++, GCPtr += PAGE_SIZE)
779	{
780	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
781	{
782	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
783	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
784	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
785	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
786	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
787	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
788	#endif
789	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
790	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
791	}
792	}
793	}
794	}
795	else
796	{
797	/*
798	* 2/4MB page.
799	*/
800	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
801	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
802	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
803	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
804	{
805	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
806	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
807	{
808	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
809	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
810	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
811	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
812	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
813	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
814	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
815	#endif
816	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
817	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
818	}
819	}
820	} /* pde type */
821	}
822	else
823	{
824	/* not-present. */
825	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
826	cPages && iPage < pCur->cPages;
827	iPage++, GCPtr += PAGE_SIZE)
828	{
829	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
830	{
831	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
832	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
833	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
834	}
835	}
836	offPage = 0;
837	}
838	} /* for pages in virtual mapping. */
839
840	return 0;
841	}
842	#endif /* 32BIT, PAE and AMD64 */
843
844
845	/**
846	* Updates the virtual page access handlers.
847	*
848	* @returns true if bits were flushed.
849	* @returns false if bits weren't flushed.
850	* @param pVM VM handle.
851	* @param pPDSrc The page directory.
852	* @param cr4 The cr4 register value.
853	*/
854	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
855	{
856	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
857	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
858	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
859
860	#if PGM_GST_TYPE == PGM_TYPE_AMD64
861	AssertFailed();
862	#endif
863
864	/** @todo
865	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
866	*/
867
868	/*
869	* Resolve any virtual address based access handlers to GC physical addresses.
870	* This should be fairly quick.
871	*/
872	PGMHVUSTATE State;
873
874	pgmLock(pVM);
875	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
876	State.pVM = pVM;
877	State.fTodo = pVM->pgm.s.fSyncFlags;
878	State.cr4 = cr4;
879	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
880	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
881
882
883	/*
884	* Set / reset bits?
885	*/
886	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
887	{
888	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
889	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
890	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
891	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
892	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
893	}
894	pgmUnlock(pVM);
895
896	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
897
898	#else /* real / protected */
899	return false;
900	#endif
901	}
902
903
904	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
905
906	/**
907	* Write access handler for the Guest CR3 page in 32-bit mode.
908	*
909	* This will try interpret the instruction, if failure fail back to the recompiler.
910	* Check if the changed PDEs are marked present and conflicts with our
911	* mappings. If conflict, we'll switch to the host context and resolve it there
912	*
913	* @returns VBox status code (appropritate for trap handling and GC return).
914	* @param pVM VM Handle.
915	* @param uErrorCode CPU Error code.
916	* @param pRegFrame Trap register frame.
917	* @param pvFault The fault address (cr2).
918	* @param GCPhysFault The GC physical address corresponding to pvFault.
919	* @param pvUser User argument.
920	*/
921	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
922	{
923	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
924
925	/*
926	* Try interpret the instruction.
927	*/
928	uint32_t cb;
929	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
930	if (VBOX_SUCCESS(rc) && cb)
931	{
932	/*
933	* Check if the modified PDEs are present and mappings.
934	*/
935	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
936	const unsigned iPD1 = offPD / sizeof(X86PDE);
937	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
938
939	Assert(cb > 0 && cb <= 8);
940	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
941	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
942
943	#ifdef DEBUG
944	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
945	if (iPD1 != iPD2)
946	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
947	#endif
948
949	if (!pVM->pgm.s.fMappingsFixed)
950	{
951	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
952	if ( ( pPDSrc->a[iPD1].n.u1Present
953	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
954	\|\| ( iPD1 != iPD2
955	&& pPDSrc->a[iPD2].n.u1Present
956	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
957	)
958	{
959	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
960	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
961	if (rc == VINF_SUCCESS)
962	rc = VINF_PGM_SYNC_CR3;
963	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
964	return rc;
965	}
966	}
967
968	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
969	}
970	else
971	{
972	Assert(VBOX_FAILURE(rc));
973	if (rc == VERR_EM_INTERPRETER)
974	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
975	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
976	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
977	}
978	return rc;
979	}
980
981	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
982
983
984	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
985
986	/**
987	* Write access handler for the Guest CR3 page in PAE mode.
988	*
989	* This will try interpret the instruction, if failure fail back to the recompiler.
990	* Check if the changed PDEs are marked present and conflicts with our
991	* mappings. If conflict, we'll switch to the host context and resolve it there
992	*
993	* @returns VBox status code (appropritate for trap handling and GC return).
994	* @param pVM VM Handle.
995	* @param uErrorCode CPU Error code.
996	* @param pRegFrame Trap register frame.
997	* @param pvFault The fault address (cr2).
998	* @param GCPhysFault The GC physical address corresponding to pvFault.
999	* @param pvUser User argument.
1000	*/
1001	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1002	{
1003	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1004
1005	/*
1006	* Try interpret the instruction.
1007	*/
1008	uint32_t cb;
1009	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1010	if (VBOX_SUCCESS(rc) && cb)
1011	{
1012	/*
1013	* Check if any of the PDs have changed.
1014	* We'll simply check all of them instead of figuring out which one/two to check.
1015	*/
1016	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1017	{
1018	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1019	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1020	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1021	{
1022	/*
1023	* The PDPE has changed.
1024	* We will schedule a monitoring update for the next TLB Flush,
1025	* InvalidatePage or SyncCR3.
1026	*
1027	* This isn't perfect, because a lazy page sync might be dealing with an half
1028	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1029	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1030	* executing.
1031	*/
1032	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1033	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1034	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1035	}
1036	}
1037
1038	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1039	}
1040	else
1041	{
1042	Assert(VBOX_FAILURE(rc));
1043	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1044	if (rc == VERR_EM_INTERPRETER)
1045	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1046	}
1047	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1048	return rc;
1049	}
1050
1051
1052	/**
1053	* Write access handler for the Guest PDs in PAE mode.
1054	*
1055	* This will try interpret the instruction, if failure fail back to the recompiler.
1056	* Check if the changed PDEs are marked present and conflicts with our
1057	* mappings. If conflict, we'll switch to the host context and resolve it there
1058	*
1059	* @returns VBox status code (appropritate for trap handling and GC return).
1060	* @param pVM VM Handle.
1061	* @param uErrorCode CPU Error code.
1062	* @param pRegFrame Trap register frame.
1063	* @param pvFault The fault address (cr2).
1064	* @param GCPhysFault The GC physical address corresponding to pvFault.
1065	* @param pvUser User argument.
1066	*/
1067	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1068	{
1069	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1070
1071	/*
1072	* Try interpret the instruction.
1073	*/
1074	uint32_t cb;
1075	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1076	if (VBOX_SUCCESS(rc) && cb)
1077	{
1078	/*
1079	* Figure out which of the 4 PDs this is.
1080	*/
1081	RTGCUINTPTR i;
1082	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1083	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1084	{
1085	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1086	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1087	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1088	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1089
1090	Assert(cb > 0 && cb <= 8);
1091	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1092	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1093
1094	#ifdef DEBUG
1095	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1096	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1097	if (iPD1 != iPD2)
1098	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1099	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1100	#endif
1101
1102	if (!pVM->pgm.s.fMappingsFixed)
1103	{
1104	if ( ( pPDSrc->a[iPD1].n.u1Present
1105	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1106	\|\| ( iPD1 != iPD2
1107	&& pPDSrc->a[iPD2].n.u1Present
1108	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1109	)
1110	{
1111	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1112	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1113	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1114	return VINF_PGM_SYNC_CR3;
1115	}
1116	}
1117	break; /* ASSUMES no duplicate entries... */
1118	}
1119	Assert(i < 4);
1120
1121	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1122	}
1123	else
1124	{
1125	Assert(VBOX_FAILURE(rc));
1126	if (rc == VERR_EM_INTERPRETER)
1127	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1128	else
1129	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1130	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1131	}
1132	return rc;
1133	}
1134
1135	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1136

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 8861

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