VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 92296

Last change on this file since 92296 was 92296, checked in by vboxsync, 3 years ago

VMM: Nested VMX: bugref:10092 Use the computed effective page attributes in the guest (GetPage) template function.
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1/* $Id: PGMAllGst.h 92296 2021-11-09 15:56:26Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Guest Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Internal Functions *
21*********************************************************************************************************************************/
22RT_C_DECLS_BEGIN
23#if PGM_GST_TYPE == PGM_TYPE_32BIT \
24 || PGM_GST_TYPE == PGM_TYPE_PAE \
25 || PGM_GST_TYPE == PGM_TYPE_AMD64
26DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk);
27#endif
28PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
29PGM_GST_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
30
31#ifdef IN_RING3 /* r3 only for now. */
32PGM_GST_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
33PGM_GST_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
34PGM_GST_DECL(int, Exit)(PVMCPUCC pVCpu);
35#endif
36RT_C_DECLS_END
37
38
39/**
40 * Enters the guest mode.
41 *
42 * @returns VBox status code.
43 * @param pVCpu The cross context virtual CPU structure.
44 * @param GCPhysCR3 The physical address from the CR3 register.
45 */
46PGM_GST_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
47{
48 /*
49 * Map and monitor CR3
50 */
51 uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
52 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
53 AssertReturn(g_aPgmBothModeData[idxBth].pfnMapCR3, VERR_PGM_MODE_IPE);
54 return g_aPgmBothModeData[idxBth].pfnMapCR3(pVCpu, GCPhysCR3, false /* fPdpesMapped */);
55}
56
57
58/**
59 * Exits the guest mode.
60 *
61 * @returns VBox status code.
62 * @param pVCpu The cross context virtual CPU structure.
63 */
64PGM_GST_DECL(int, Exit)(PVMCPUCC pVCpu)
65{
66 uintptr_t idxBth = pVCpu->pgm.s.idxBothModeData;
67 AssertReturn(idxBth < RT_ELEMENTS(g_aPgmBothModeData), VERR_PGM_MODE_IPE);
68 AssertReturn(g_aPgmBothModeData[idxBth].pfnUnmapCR3, VERR_PGM_MODE_IPE);
69 return g_aPgmBothModeData[idxBth].pfnUnmapCR3(pVCpu);
70}
71
72
73#if PGM_GST_TYPE == PGM_TYPE_32BIT \
74 || PGM_GST_TYPE == PGM_TYPE_PAE \
75 || PGM_GST_TYPE == PGM_TYPE_AMD64
76
77
78DECLINLINE(int) PGM_GST_NAME(WalkReturnNotPresent)(PVMCPUCC pVCpu, PGSTPTWALK pWalk, int iLevel)
79{
80 NOREF(iLevel); NOREF(pVCpu);
81 pWalk->Core.fNotPresent = true;
82 pWalk->Core.uLevel = (uint8_t)iLevel;
83 return VERR_PAGE_TABLE_NOT_PRESENT;
84}
85
86DECLINLINE(int) PGM_GST_NAME(WalkReturnBadPhysAddr)(PVMCPUCC pVCpu, PGSTPTWALK pWalk, int iLevel, int rc)
87{
88 AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
89 pWalk->Core.fBadPhysAddr = true;
90 pWalk->Core.uLevel = (uint8_t)iLevel;
91 return VERR_PAGE_TABLE_NOT_PRESENT;
92}
93
94DECLINLINE(int) PGM_GST_NAME(WalkReturnRsvdError)(PVMCPUCC pVCpu, PGSTPTWALK pWalk, int iLevel)
95{
96 NOREF(pVCpu);
97 pWalk->Core.fRsvdError = true;
98 pWalk->Core.uLevel = (uint8_t)iLevel;
99 return VERR_PAGE_TABLE_NOT_PRESENT;
100}
101
102
103/**
104 * Performs a guest page table walk.
105 *
106 * @returns VBox status code.
107 * @retval VINF_SUCCESS on success.
108 * @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
109 *
110 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
111 * @param GCPtr The guest virtual address to walk by.
112 * @param pWalk Where to return the walk result. This is always set.
113 */
114DECLINLINE(int) PGM_GST_NAME(Walk)(PVMCPUCC pVCpu, RTGCPTR GCPtr, PGSTPTWALK pWalk)
115{
116 int rc;
117
118#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
119# define PGM_GST_SLAT_WALK(a_pVCpu, a_GCPtrNested, a_GCPhysNested, a_GCPhysOut, a_pWalk) \
120 do { \
121 if ((a_pVCpu)->pgm.s.enmGuestSlatMode != PGMSLAT_DIRECT) \
122 { \
123 PGMPTWALKGST SlatWalk; \
124 int const rcX = pgmGstSlatWalk(a_pVCpu, a_GCPhysNested, true /* fIsLinearAddrValid */, a_GCPtrNested, &SlatWalk); \
125 if (RT_SUCCESS(rcX)) \
126 (a_GCPhysOut) = SlatWalk.u.Core.GCPhys; \
127 else \
128 { \
129 (a_pWalk)->Core = SlatWalk.u.Core; \
130 return rcX; \
131 } \
132 } \
133 } while (0)
134#endif
135
136 /*
137 * Init the walking structure.
138 */
139 RT_ZERO(*pWalk);
140 pWalk->Core.GCPtr = GCPtr;
141
142# if PGM_GST_TYPE == PGM_TYPE_32BIT \
143 || PGM_GST_TYPE == PGM_TYPE_PAE
144 /*
145 * Boundary check for PAE and 32-bit (prevents trouble further down).
146 */
147 if (RT_UNLIKELY(GCPtr >= _4G))
148 return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 8);
149# endif
150
151 uint64_t fEffective = X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | 1;
152 {
153# if PGM_GST_TYPE == PGM_TYPE_AMD64
154 /*
155 * The PML4 table.
156 */
157 rc = pgmGstGetLongModePML4PtrEx(pVCpu, &pWalk->pPml4);
158 if (RT_SUCCESS(rc)) { /* probable */ }
159 else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
160
161 PX86PML4E pPml4e;
162 pWalk->pPml4e = pPml4e = &pWalk->pPml4->a[(GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK];
163 X86PML4E Pml4e;
164 pWalk->Pml4e.u = Pml4e.u = pPml4e->u;
165
166 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
167 else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 4);
168
169 if (RT_LIKELY(GST_IS_PML4E_VALID(pVCpu, Pml4e))) { /* likely */ }
170 else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 4);
171
172 pWalk->Core.fEffective = fEffective = (Pml4e.u & (X86_PML4E_RW | X86_PML4E_US | X86_PML4E_PWT | X86_PML4E_PCD | X86_PML4E_A))
173 | ((Pml4e.u >> 63) ^ 1) /*NX */;
174
175 /*
176 * The PDPT.
177 */
178 RTGCPHYS GCPhysPdpt = Pml4e.u & X86_PML4E_PG_MASK;
179#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
180 PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPdpt, GCPhysPdpt, pWalk);
181#endif
182 rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPdpt, &pWalk->pPdpt);
183 if (RT_SUCCESS(rc)) { /* probable */ }
184 else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
185
186# elif PGM_GST_TYPE == PGM_TYPE_PAE
187 rc = pgmGstGetPaePDPTPtrEx(pVCpu, &pWalk->pPdpt);
188 if (RT_SUCCESS(rc)) { /* probable */ }
189 else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
190#endif
191 }
192 {
193# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
194 PX86PDPE pPdpe;
195 pWalk->pPdpe = pPdpe = &pWalk->pPdpt->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
196 X86PDPE Pdpe;
197 pWalk->Pdpe.u = Pdpe.u = pPdpe->u;
198
199 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pdpe)) { /* probable */ }
200 else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 3);
201
202 if (RT_LIKELY(GST_IS_PDPE_VALID(pVCpu, Pdpe))) { /* likely */ }
203 else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 3);
204
205# if PGM_GST_TYPE == PGM_TYPE_AMD64
206 pWalk->Core.fEffective = fEffective &= (Pdpe.u & (X86_PDPE_RW | X86_PDPE_US | X86_PDPE_PWT | X86_PDPE_PCD | X86_PDPE_A))
207 | ((Pdpe.u >> 63) ^ 1) /*NX */;
208# else
209 pWalk->Core.fEffective = fEffective = X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A
210 | (Pdpe.u & (X86_PDPE_PWT | X86_PDPE_PCD))
211 | ((Pdpe.u >> 63) ^ 1) /*NX */;
212# endif
213
214 /*
215 * The PD.
216 */
217 RTGCPHYS GCPhysPd = Pdpe.u & X86_PDPE_PG_MASK;
218# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
219 PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPd, GCPhysPd, pWalk);
220# endif
221 rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPd, &pWalk->pPd);
222 if (RT_SUCCESS(rc)) { /* probable */ }
223 else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 2, rc);
224
225# elif PGM_GST_TYPE == PGM_TYPE_32BIT
226 rc = pgmGstGet32bitPDPtrEx(pVCpu, &pWalk->pPd);
227 if (RT_SUCCESS(rc)) { /* probable */ }
228 else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 8, rc);
229# endif
230 }
231 {
232 PGSTPDE pPde;
233 pWalk->pPde = pPde = &pWalk->pPd->a[(GCPtr >> GST_PD_SHIFT) & GST_PD_MASK];
234 GSTPDE Pde;
235 pWalk->Pde.u = Pde.u = pPde->u;
236 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
237 else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 2);
238 if ((Pde.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
239 {
240 if (RT_LIKELY(GST_IS_BIG_PDE_VALID(pVCpu, Pde))) { /* likely */ }
241 else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
242
243 /*
244 * We're done.
245 */
246# if PGM_GST_TYPE == PGM_TYPE_32BIT
247 fEffective &= Pde.u & (X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PWT | X86_PDE4M_PCD | X86_PDE4M_A);
248# else
249 fEffective &= (Pde.u & (X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PWT | X86_PDE4M_PCD | X86_PDE4M_A))
250 | ((Pde.u >> 63) ^ 1) /*NX */;
251# endif
252 fEffective |= Pde.u & (X86_PDE4M_D | X86_PDE4M_G);
253 fEffective |= (Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT;
254 pWalk->Core.fEffective = fEffective;
255
256 pWalk->Core.fEffectiveRW = !!(fEffective & X86_PTE_RW);
257 pWalk->Core.fEffectiveUS = !!(fEffective & X86_PTE_US);
258# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
259 pWalk->Core.fEffectiveNX = !(fEffective & 1) && GST_IS_NX_ACTIVE(pVCpu);
260# else
261 pWalk->Core.fEffectiveNX = false;
262# endif
263 pWalk->Core.fBigPage = true;
264 pWalk->Core.fSucceeded = true;
265
266 RTGCPHYS GCPhysPde = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
267 | (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
268# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
269 PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPde, GCPhysPde, pWalk);
270# endif
271 pWalk->Core.GCPhys = GCPhysPde;
272 PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->Core.GCPhys);
273 return VINF_SUCCESS;
274 }
275
276 if (RT_UNLIKELY(!GST_IS_PDE_VALID(pVCpu, Pde)))
277 return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 2);
278# if PGM_GST_TYPE == PGM_TYPE_32BIT
279 pWalk->Core.fEffective = fEffective &= Pde.u & (X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD | X86_PDE_A);
280# else
281 pWalk->Core.fEffective = fEffective &= (Pde.u & (X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD | X86_PDE_A))
282 | ((Pde.u >> 63) ^ 1) /*NX */;
283# endif
284
285 /*
286 * The PT.
287 */
288 RTGCPHYS GCPhysPt = GST_GET_PDE_GCPHYS(Pde);
289# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
290 PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPt, GCPhysPt, pWalk);
291# endif
292 rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhysPt, &pWalk->pPt);
293 if (RT_SUCCESS(rc)) { /* probable */ }
294 else return PGM_GST_NAME(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
295 }
296 {
297 PGSTPTE pPte;
298 pWalk->pPte = pPte = &pWalk->pPt->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
299 GSTPTE Pte;
300 pWalk->Pte.u = Pte.u = pPte->u;
301
302 if (GST_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
303 else return PGM_GST_NAME(WalkReturnNotPresent)(pVCpu, pWalk, 1);
304
305 if (RT_LIKELY(GST_IS_PTE_VALID(pVCpu, Pte))) { /* likely */ }
306 else return PGM_GST_NAME(WalkReturnRsvdError)(pVCpu, pWalk, 1);
307
308 /*
309 * We're done.
310 */
311# if PGM_GST_TYPE == PGM_TYPE_32BIT
312 fEffective &= Pte.u & (X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A);
313# else
314 fEffective &= (Pte.u & (X86_PTE_RW | X86_PTE_US | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A))
315 | ((Pte.u >> 63) ^ 1) /*NX */;
316# endif
317 fEffective |= Pte.u & (X86_PTE_D | X86_PTE_PAT | X86_PTE_G);
318 pWalk->Core.fEffective = fEffective;
319
320 pWalk->Core.fEffectiveRW = !!(fEffective & X86_PTE_RW);
321 pWalk->Core.fEffectiveUS = !!(fEffective & X86_PTE_US);
322# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
323 pWalk->Core.fEffectiveNX = !(fEffective & 1) && GST_IS_NX_ACTIVE(pVCpu);
324# else
325 pWalk->Core.fEffectiveNX = false;
326# endif
327 pWalk->Core.fSucceeded = true;
328
329 RTGCPHYS GCPhysPte = GST_GET_PDE_GCPHYS(Pte) /** @todo This should be GST_GET_PTE_GCPHYS. */
330 | (GCPtr & PAGE_OFFSET_MASK);
331# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
332 PGM_GST_SLAT_WALK(pVCpu, GCPtr, GCPhysPte, GCPhysPte, pWalk);
333# endif
334 pWalk->Core.GCPhys = GCPhysPte;
335 return VINF_SUCCESS;
336 }
337}
338
339#endif /* 32BIT, PAE, AMD64 */
340
341/**
342 * Gets effective Guest OS page information.
343 *
344 * When GCPtr is in a big page, the function will return as if it was a normal
345 * 4KB page. If the need for distinguishing between big and normal page becomes
346 * necessary at a later point, a PGMGstGetPage Ex() will be created for that
347 * purpose.
348 *
349 * @returns VBox status code.
350 * @param pVCpu The cross context virtual CPU structure.
351 * @param GCPtr Guest Context virtual address of the page.
352 * @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
353 * @param pGCPhys Where to store the GC physical address of the page.
354 * This is page aligned!
355 */
356PGM_GST_DECL(int, GetPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
357{
358#if PGM_GST_TYPE == PGM_TYPE_REAL \
359 || PGM_GST_TYPE == PGM_TYPE_PROT
360 /*
361 * Fake it.
362 */
363 if (pfFlags)
364 *pfFlags = X86_PTE_P | X86_PTE_RW | X86_PTE_US;
365 if (pGCPhys)
366 *pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
367 NOREF(pVCpu);
368 return VINF_SUCCESS;
369
370#elif PGM_GST_TYPE == PGM_TYPE_32BIT \
371 || PGM_GST_TYPE == PGM_TYPE_PAE \
372 || PGM_GST_TYPE == PGM_TYPE_AMD64
373
374 GSTPTWALK Walk;
375 int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
376 if (RT_FAILURE(rc))
377 return rc;
378
379 if (pGCPhys)
380 *pGCPhys = Walk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
381
382 if (pfFlags)
383 {
384 if (!Walk.Core.fBigPage)
385 *pfFlags = (Walk.Pte.u & ~(GST_PTE_PG_MASK | X86_PTE_RW | X86_PTE_US)) /* NX not needed */
386 | (Walk.Core.fEffective & ( PGM_PTATTRS_RW_MASK
387 | PGM_PTATTRS_US_MASK))
388# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
389 | (RT_BF_GET(Walk.Core.fEffective, PGM_PTATTRS_X) << X86_PTE_PAE_BIT_NX)
390# endif
391 ;
392 else
393 {
394 *pfFlags = (Walk.Pde.u & ~(GST_PTE_PG_MASK | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PS)) /* NX not needed */
395 | (Walk.Core.fEffective & ( PGM_PTATTRS_RW_MASK
396 | PGM_PTATTRS_US_MASK
397 | PGM_PTATTRS_PAT_MASK))
398# if PGM_WITH_NX(PGM_GST_TYPE, PGM_GST_TYPE)
399 | (RT_BF_GET(Walk.Core.fEffective, PGM_PTATTRS_X) << X86_PTE_PAE_BIT_NX)
400# endif
401 ;
402 }
403 }
404
405 return VINF_SUCCESS;
406
407#else
408# error "shouldn't be here!"
409 /* something else... */
410 return VERR_NOT_SUPPORTED;
411#endif
412}
413
414
415/**
416 * Modify page flags for a range of pages in the guest's tables
417 *
418 * The existing flags are ANDed with the fMask and ORed with the fFlags.
419 *
420 * @returns VBox status code.
421 * @param pVCpu The cross context virtual CPU structure.
422 * @param GCPtr Virtual address of the first page in the range. Page aligned!
423 * @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
424 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
425 * @param fMask The AND mask - page flags X86_PTE_*.
426 */
427PGM_GST_DECL(int, ModifyPage)(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
428{
429 Assert((cb & PAGE_OFFSET_MASK) == 0); RT_NOREF_PV(cb);
430
431#if PGM_GST_TYPE == PGM_TYPE_32BIT \
432 || PGM_GST_TYPE == PGM_TYPE_PAE \
433 || PGM_GST_TYPE == PGM_TYPE_AMD64
434 for (;;)
435 {
436 GSTPTWALK Walk;
437 int rc = PGM_GST_NAME(Walk)(pVCpu, GCPtr, &Walk);
438 if (RT_FAILURE(rc))
439 return rc;
440
441 if (!Walk.Core.fBigPage)
442 {
443 /*
444 * 4KB Page table, process
445 *
446 * Walk pages till we're done.
447 */
448 unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
449 while (iPTE < RT_ELEMENTS(Walk.pPt->a))
450 {
451 GSTPTE Pte = Walk.pPt->a[iPTE];
452 Pte.u = (Pte.u & (fMask | X86_PTE_PAE_PG_MASK))
453 | (fFlags & ~GST_PTE_PG_MASK);
454 Walk.pPt->a[iPTE] = Pte;
455
456 /* next page */
457 cb -= PAGE_SIZE;
458 if (!cb)
459 return VINF_SUCCESS;
460 GCPtr += PAGE_SIZE;
461 iPTE++;
462 }
463 }
464 else
465 {
466 /*
467 * 2/4MB Page table
468 */
469 GSTPDE PdeNew;
470# if PGM_GST_TYPE == PGM_TYPE_32BIT
471 PdeNew.u = (Walk.Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PG_HIGH_MASK | X86_PDE4M_PS))
472# else
473 PdeNew.u = (Walk.Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE_BIG_PG_MASK | X86_PDE4M_PS))
474# endif
475 | (fFlags & ~GST_PTE_PG_MASK)
476 | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
477 *Walk.pPde = PdeNew;
478
479 /* advance */
480 const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
481 if (cbDone >= cb)
482 return VINF_SUCCESS;
483 cb -= cbDone;
484 GCPtr += cbDone;
485 }
486 }
487
488#else
489 /* real / protected mode: ignore. */
490 NOREF(pVCpu); NOREF(GCPtr); NOREF(fFlags); NOREF(fMask);
491 return VINF_SUCCESS;
492#endif
493}
494
495
496#ifdef IN_RING3
497/**
498 * Relocate any GC pointers related to guest mode paging.
499 *
500 * @returns VBox status code.
501 * @param pVCpu The cross context virtual CPU structure.
502 * @param offDelta The relocation offset.
503 */
504PGM_GST_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta)
505{
506 RT_NOREF(pVCpu, offDelta);
507 return VINF_SUCCESS;
508}
509#endif
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