PGMAllGst.h@ 9871

Last change on this file since 9871 was 9858, checked in by vboxsync, 17 years ago
Wrong mask
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 42.3 KB

Line
1	/* $Id: PGMAllGst.h 9858 2008-06-20 14:40:30Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48	#undef GST_PDPE_PG_MASK
49
50	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
51	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
52	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
53	# define GSTPT X86PT
54	# define PGSTPT PX86PT
55	# define GSTPTE X86PTE
56	# define PGSTPTE PX86PTE
57	# define GSTPD X86PD
58	# define PGSTPD PX86PD
59	# define GSTPDE X86PDE
60	# define PGSTPDE PX86PDE
61	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
62	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
63	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
64	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
65	# define GST_PD_SHIFT X86_PD_SHIFT
66	# define GST_PD_MASK X86_PD_MASK
67	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
68	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
69	# define GST_PT_SHIFT X86_PT_SHIFT
70	# define GST_PT_MASK X86_PT_MASK
71	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
72	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
73	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
74	# define GSTPT X86PTPAE
75	# define PGSTPT PX86PTPAE
76	# define GSTPTE X86PTEPAE
77	# define PGSTPTE PX86PTEPAE
78	# define GSTPD X86PDPAE
79	# define PGSTPD PX86PDPAE
80	# define GSTPDE X86PDEPAE
81	# define PGSTPDE PX86PDEPAE
82	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
83	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
84	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK
85	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
86	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
87	# define GST_PD_MASK X86_PD_PAE_MASK
88	# if PGM_GST_TYPE == PGM_TYPE_PAE
89	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
90	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
91	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK
92	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
93	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
94	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
95	# else
96	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
97	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
98	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
99	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
100	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
101	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
102	# endif
103	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
104	# define GST_PT_MASK X86_PT_PAE_MASK
105	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
106	#endif
107
108
109	/*******************************************************************************
110	* Internal Functions *
111	*******************************************************************************/
112	__BEGIN_DECLS
113	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
114	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
115	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
116	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
117	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
118	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
119	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
120	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
121	#ifndef IN_RING3
122	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
123	# if PGM_GST_TYPE == PGM_TYPE_PAE \
124	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
125	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
126	# endif
127	#endif
128	__END_DECLS
129
130
131
132	/**
133	* Gets effective Guest OS page information.
134	*
135	* When GCPtr is in a big page, the function will return as if it was a normal
136	* 4KB page. If the need for distinguishing between big and normal page becomes
137	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
138	* purpose.
139	*
140	* @returns VBox status.
141	* @param pVM VM Handle.
142	* @param GCPtr Guest Context virtual address of the page. Page aligned!
143	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
144	* @param pGCPhys Where to store the GC physical address of the page.
145	* This is page aligned. The fact that the
146	*/
147	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
148	{
149	#if PGM_GST_TYPE == PGM_TYPE_REAL \
150	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
151	/*
152	* Fake it.
153	*/
154	if (pfFlags)
155	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
156	if (pGCPhys)
157	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
158	return VINF_SUCCESS;
159
160	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
161
162	/*
163	* Get the PDE.
164	*/
165	# if PGM_GST_TYPE == PGM_TYPE_32BIT
166	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
167	#elif PGM_GST_TYPE == PGM_TYPE_PAE
168	X86PDEPAE Pde;
169	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
170
171	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
172	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
173	*/
174	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
175	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
176	PX86PML4E pPml4e;
177	X86PDPE Pdpe;
178	X86PDEPAE Pde;
179	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
180
181	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
182	Assert(pPml4e);
183	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
184	return VERR_PAGE_TABLE_NOT_PRESENT;
185
186	/* Merge accessed, write, user and no-execute bits into the PDE. */
187	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
188	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
189	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
190	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
191	# endif
192
193	/*
194	* Lookup the page.
195	*/
196	if (!Pde.n.u1Present)
197	return VERR_PAGE_TABLE_NOT_PRESENT;
198
199	if ( !Pde.b.u1Size
200	# if PGM_GST_TYPE != PGM_TYPE_AMD64
201	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
202	# endif
203	)
204	{
205	PGSTPT pPT;
206	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
207	if (VBOX_FAILURE(rc))
208	return rc;
209
210	/*
211	* Get PT entry and check presence.
212	*/
213	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
214	if (!Pte.n.u1Present)
215	return VERR_PAGE_NOT_PRESENT;
216
217	/*
218	* Store the result.
219	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
220	* where the PDPE is simplified.
221	*/
222	if (pfFlags)
223	{
224	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
225	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
226	# if PGM_WITH_NX(PGM_GST_TYPE)
227	/* The NX bit is determined by a bitwise OR between the PT and PD */
228	if (fNoExecuteBitValid)
229	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
230	# endif
231	}
232	if (pGCPhys)
233	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
234	}
235	else
236	{
237	/*
238	* Map big to 4k PTE and store the result
239	*/
240	if (pfFlags)
241	{
242	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
243	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
244	# if PGM_WITH_NX(PGM_GST_TYPE)
245	/* The NX bit is determined by a bitwise OR between the PT and PD */
246	if (fNoExecuteBitValid)
247	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
248	# endif
249	}
250	if (pGCPhys)
251	pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /* @todo pse36 */
252	}
253	return VINF_SUCCESS;
254	#else
255	# error "shouldn't be here!"
256	/* something else... */
257	return VERR_NOT_SUPPORTED;
258	#endif
259	}
260
261
262	/**
263	* Modify page flags for a range of pages in the guest's tables
264	*
265	* The existing flags are ANDed with the fMask and ORed with the fFlags.
266	*
267	* @returns VBox status code.
268	* @param pVM VM handle.
269	* @param GCPtr Virtual address of the first page in the range. Page aligned!
270	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
271	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
272	* @param fMask The AND mask - page flags X86_PTE_*.
273	*/
274	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
275	{
276	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
277	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
278	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
279
280	for (;;)
281	{
282	/*
283	* Get the PD entry.
284	*/
285	# if PGM_GST_TYPE == PGM_TYPE_32BIT
286	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
287	# elif PGM_GST_TYPE == PGM_TYPE_PAE
288	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
289	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
290	*/
291	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
292	Assert(pPde);
293	if (!pPde)
294	return VERR_PAGE_TABLE_NOT_PRESENT;
295	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
296	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
297	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
298	Assert(pPde);
299	if (!pPde)
300	return VERR_PAGE_TABLE_NOT_PRESENT;
301	# endif
302	GSTPDE Pde = *pPde;
303	Assert(Pde.n.u1Present);
304	if (!Pde.n.u1Present)
305	return VERR_PAGE_TABLE_NOT_PRESENT;
306
307	if ( !Pde.b.u1Size
308	# if PGM_GST_TYPE != PGM_TYPE_AMD64
309	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
310	# endif
311	)
312	{
313	/*
314	* 4KB Page table
315	*
316	* Walk page tables and pages till we're done.
317	*/
318	PGSTPT pPT;
319	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
320	if (VBOX_FAILURE(rc))
321	return rc;
322
323	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
324	while (iPTE < RT_ELEMENTS(pPT->a))
325	{
326	GSTPTE Pte = pPT->a[iPTE];
327	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
328	\| (fFlags & ~GST_PTE_PG_MASK);
329	pPT->a[iPTE] = Pte;
330
331	/* next page */
332	cb -= PAGE_SIZE;
333	if (!cb)
334	return VINF_SUCCESS;
335	GCPtr += PAGE_SIZE;
336	iPTE++;
337	}
338	}
339	else
340	{
341	/*
342	* 4MB Page table
343	*/
344	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS)) /** @todo pse36 */
345	\| (fFlags & ~GST_PTE_PG_MASK)
346	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
347	*pPde = Pde;
348
349	/* advance */
350	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
351	if (cbDone >= cb)
352	return VINF_SUCCESS;
353	cb -= cbDone;
354	GCPtr += cbDone;
355	}
356	}
357
358	#else
359	/* real / protected mode: ignore. */
360	return VINF_SUCCESS;
361	#endif
362	}
363
364
365	/**
366	* Retrieve guest PDE information
367	*
368	* @returns VBox status code.
369	* @param pVM The virtual machine.
370	* @param GCPtr Guest context pointer
371	* @param pPDE Pointer to guest PDE structure
372	*/
373	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
374	{
375	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
376	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
377	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
378
379	# if PGM_GST_TYPE == PGM_TYPE_32BIT
380	X86PDE Pde;
381	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
382	# elif PGM_GST_TYPE == PGM_TYPE_PAE
383	X86PDEPAE Pde;
384	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
385	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
386	X86PDEPAE Pde;
387	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
388	# endif
389
390	pPDE->u = (X86PGPAEUINT)Pde.u;
391	return VINF_SUCCESS;
392	#else
393	AssertFailed();
394	return VERR_NOT_IMPLEMENTED;
395	#endif
396	}
397
398
399
400	/**
401	* Maps the CR3 into HMA in GC and locate it in HC.
402	*
403	* @returns VBox status, no specials.
404	* @param pVM VM handle.
405	* @param GCPhysCR3 The physical address in the CR3 register.
406	*/
407	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
408	{
409	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
410	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
411	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
412
413	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
414
415	/*
416	* Map the page CR3 points at.
417	*/
418	RTHCPHYS HCPhysGuestCR3;
419	RTHCPTR HCPtrGuestCR3;
420	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
421	if (VBOX_SUCCESS(rc))
422	{
423	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
424	if (VBOX_SUCCESS(rc))
425	{
426	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
427	# if PGM_GST_TYPE == PGM_TYPE_32BIT
428	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
429	pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
430
431	# elif PGM_GST_TYPE == PGM_TYPE_PAE
432	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
433	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
434	pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
435	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
436
437	/*
438	* Map the 4 PDs too.
439	*/
440	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
441	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
442	{
443	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
444	{
445	RTHCPTR HCPtr;
446	RTHCPHYS HCPhys;
447	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
448	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
449	if (VBOX_SUCCESS(rc2))
450	{
451	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
452	AssertRCReturn(rc, rc);
453	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
454	pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
455	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
456	PGM_INVL_PG(GCPtr);
457	continue;
458	}
459	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
460	}
461
462	pVM->pgm.s.apGstPaePDsHC[i] = 0;
463	pVM->pgm.s.apGstPaePDsGC[i] = 0;
464	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
465	PGM_INVL_PG(GCPtr);
466	}
467	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
468	pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
469	# endif
470	}
471	else
472	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
473	}
474	else
475	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
476
477	#else /* prot/real stub */
478	int rc = VINF_SUCCESS;
479	#endif
480	return rc;
481	}
482
483
484	/**
485	* Unmaps the CR3.
486	*
487	* @returns VBox status, no specials.
488	* @param pVM VM handle.
489	* @param GCPhysCR3 The physical address in the CR3 register.
490	*/
491	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
492	{
493	LogFlow(("UnmapCR3\n"));
494
495	int rc = VINF_SUCCESS;
496	#if PGM_GST_TYPE == PGM_TYPE_32BIT
497	pVM->pgm.s.pGuestPDHC = 0;
498	pVM->pgm.s.pGuestPDGC = 0;
499
500	#elif PGM_GST_TYPE == PGM_TYPE_PAE
501	pVM->pgm.s.pGstPaePDPTHC = 0;
502	pVM->pgm.s.pGstPaePDPTGC = 0;
503	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
504	{
505	pVM->pgm.s.apGstPaePDsHC[i] = 0;
506	pVM->pgm.s.apGstPaePDsGC[i] = 0;
507	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
508	}
509
510	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
511	pVM->pgm.s.pGstPaePML4HC = 0;
512	#else /* prot/real mode stub */
513	/* nothing to do */
514	#endif
515	return rc;
516	}
517
518
519	#undef LOG_GROUP
520	#define LOG_GROUP LOG_GROUP_PGM_POOL
521
522	/**
523	* Registers physical page monitors for the necessary paging
524	* structures to detect conflicts with our guest mappings.
525	*
526	* This is always called after mapping CR3.
527	* This is never called with fixed mappings.
528	*
529	* @returns VBox status, no specials.
530	* @param pVM VM handle.
531	* @param GCPhysCR3 The physical address in the CR3 register.
532	*/
533	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
534	{
535	Assert(!pVM->pgm.s.fMappingsFixed);
536	int rc = VINF_SUCCESS;
537
538	/*
539	* Register/Modify write phys handler for guest's CR3 if it changed.
540	*/
541	#if PGM_GST_TYPE == PGM_TYPE_32BIT
542
543	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
544	{
545	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
546	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
547	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
548	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
549	else
550	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
551	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
552	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
553	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
554	pVM->pgm.s.pszR3GstWriteHandlerCR3);
555	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
556	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
557	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
558	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
559	? PGMPOOL_IDX_PAE_PD
560	: PGMPOOL_IDX_PD,
561	GCPhysCR3);
562	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
563	if (VBOX_FAILURE(rc))
564	{
565	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
566	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
567	return rc;
568	}
569	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
570	}
571
572	#elif PGM_GST_TYPE == PGM_TYPE_PAE
573	/* Monitor the PDPT page */
574	/*
575	* Register/Modify write phys handler for guest's CR3 if it changed.
576	*/
577	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
578	AssertFailed();
579	# endif
580	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
581	{
582	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
583	if (VBOX_FAILURE(rc))
584	{
585	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
586	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
587	return rc;
588	}
589	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
590	}
591	/*
592	* Do the 4 PDs.
593	*/
594	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
595	{
596	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
597	{
598	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
599	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
600	{
601	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
602
603	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
604	}
605
606	if (VBOX_FAILURE(rc))
607	{
608	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
609	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
610	return rc;
611	}
612	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
613	}
614	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
615	{
616	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
617	AssertRC(rc);
618	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
619	}
620	}
621
622	#else
623	/* prot/real/amd64 mode stub */
624
625	#endif
626	return rc;
627	}
628
629	/**
630	* Deregisters any physical page monitors installed by MonitorCR3.
631	*
632	* @returns VBox status code, no specials.
633	* @param pVM The VM handle.
634	*/
635	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
636	{
637	int rc = VINF_SUCCESS;
638
639	/*
640	* Deregister the access handlers.
641	*
642	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
643	* before we enter GC again.
644	*/
645	#if PGM_GST_TYPE == PGM_TYPE_32BIT
646	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
647	{
648	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
649	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
650	AssertRCReturn(rc, rc);
651	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
652	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
653	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
654	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
655	? PGMPOOL_IDX_PAE_PD
656	: PGMPOOL_IDX_PD);
657	AssertRCReturn(rc, rc);
658	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
659	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
660	}
661
662	#elif PGM_GST_TYPE == PGM_TYPE_PAE
663	/* The PDPT page */
664	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
665	AssertFailed();
666	# endif
667
668	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
669	{
670	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
671	AssertRC(rc);
672	}
673
674	/* The 4 PDs. */
675	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
676	{
677	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
678	{
679	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
680	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
681	AssertRC(rc2);
682	if (VBOX_FAILURE(rc2))
683	rc = rc2;
684	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
685	}
686	}
687	#else
688	/* prot/real/amd64 mode stub */
689	#endif
690	return rc;
691
692	}
693
694	#undef LOG_GROUP
695	#define LOG_GROUP LOG_GROUP_PGM
696
697
698	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
699	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
700	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
701	/**
702	* Updates one virtual handler range.
703	*
704	* @returns 0
705	* @param pNode Pointer to a PGMVIRTHANDLER.
706	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
707	*/
708	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
709	{
710	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
711	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
712	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
713
714	#if PGM_GST_TYPE == PGM_TYPE_32BIT
715	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
716	#endif
717
718	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
719	#if PGM_GST_MODE != PGM_MODE_AMD64
720	/* skip all stuff above 4GB if not AMD64 mode. */
721	if (GCPtr >= _4GB)
722	return 0;
723	#endif
724
725	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
726	unsigned iPage = 0;
727	while (iPage < pCur->cPages)
728	{
729	#if PGM_GST_TYPE == PGM_TYPE_32BIT
730	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
731	#elif PGM_GST_TYPE == PGM_TYPE_PAE
732	X86PDEPAE Pde;
733	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
734	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
735	X86PDEPAE Pde;
736	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
737	#endif
738	if (Pde.n.u1Present)
739	{
740	if ( !Pde.b.u1Size
741	# if PGM_GST_TYPE != PGM_TYPE_AMD64
742	\|\| !(pState->cr4 & X86_CR4_PSE)
743	# endif
744	)
745	{
746	/*
747	* Normal page table.
748	*/
749	PGSTPT pPT;
750	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
751	if (VBOX_SUCCESS(rc))
752	{
753	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
754	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
755	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
756	{
757	GSTPTE Pte = pPT->a[iPTE];
758	RTGCPHYS GCPhysNew;
759	if (Pte.n.u1Present)
760	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
761	else
762	GCPhysNew = NIL_RTGCPHYS;
763	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
764	{
765	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
766	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
767	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
768	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
769	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
770	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
771	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
772	#endif
773	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
774	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
775	}
776	}
777	}
778	else
779	{
780	/* not-present. */
781	offPage = 0;
782	AssertRC(rc);
783	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
784	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
785	iPTE++, iPage++, GCPtr += PAGE_SIZE)
786	{
787	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
788	{
789	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
790	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
791	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
792	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
793	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
794	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
795	#endif
796	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
797	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
798	}
799	}
800	}
801	}
802	else
803	{
804	/*
805	* 2/4MB page.
806	*/
807	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
808	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
809	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
810	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
811	{
812	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
813	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
814	{
815	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
816	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
817	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
818	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
819	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
820	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
821	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
822	#endif
823	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
824	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
825	}
826	}
827	} /* pde type */
828	}
829	else
830	{
831	/* not-present. */
832	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
833	cPages && iPage < pCur->cPages;
834	iPage++, GCPtr += PAGE_SIZE)
835	{
836	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
837	{
838	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
839	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
840	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
841	}
842	}
843	offPage = 0;
844	}
845	} /* for pages in virtual mapping. */
846
847	return 0;
848	}
849	#endif /* 32BIT, PAE and AMD64 */
850
851
852	/**
853	* Updates the virtual page access handlers.
854	*
855	* @returns true if bits were flushed.
856	* @returns false if bits weren't flushed.
857	* @param pVM VM handle.
858	* @param pPDSrc The page directory.
859	* @param cr4 The cr4 register value.
860	*/
861	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
862	{
863	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
864	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
865	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
866
867	/** @todo
868	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
869	*/
870
871	/*
872	* Resolve any virtual address based access handlers to GC physical addresses.
873	* This should be fairly quick.
874	*/
875	PGMHVUSTATE State;
876
877	pgmLock(pVM);
878	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
879	State.pVM = pVM;
880	State.fTodo = pVM->pgm.s.fSyncFlags;
881	State.cr4 = cr4;
882	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
883	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
884
885
886	/*
887	* Set / reset bits?
888	*/
889	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
890	{
891	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
892	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
893	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
894	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
895	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
896	}
897	pgmUnlock(pVM);
898
899	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
900
901	#else /* real / protected */
902	return false;
903	#endif
904	}
905
906
907	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
908
909	/**
910	* Write access handler for the Guest CR3 page in 32-bit mode.
911	*
912	* This will try interpret the instruction, if failure fail back to the recompiler.
913	* Check if the changed PDEs are marked present and conflicts with our
914	* mappings. If conflict, we'll switch to the host context and resolve it there
915	*
916	* @returns VBox status code (appropritate for trap handling and GC return).
917	* @param pVM VM Handle.
918	* @param uErrorCode CPU Error code.
919	* @param pRegFrame Trap register frame.
920	* @param pvFault The fault address (cr2).
921	* @param GCPhysFault The GC physical address corresponding to pvFault.
922	* @param pvUser User argument.
923	*/
924	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
925	{
926	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
927
928	/*
929	* Try interpret the instruction.
930	*/
931	uint32_t cb;
932	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
933	if (VBOX_SUCCESS(rc) && cb)
934	{
935	/*
936	* Check if the modified PDEs are present and mappings.
937	*/
938	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
939	const unsigned iPD1 = offPD / sizeof(X86PDE);
940	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
941
942	Assert(cb > 0 && cb <= 8);
943	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
944	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
945
946	#ifdef DEBUG
947	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
948	if (iPD1 != iPD2)
949	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
950	#endif
951
952	if (!pVM->pgm.s.fMappingsFixed)
953	{
954	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
955	if ( ( pPDSrc->a[iPD1].n.u1Present
956	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
957	\|\| ( iPD1 != iPD2
958	&& pPDSrc->a[iPD2].n.u1Present
959	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
960	)
961	{
962	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
963	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
964	if (rc == VINF_SUCCESS)
965	rc = VINF_PGM_SYNC_CR3;
966	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
967	return rc;
968	}
969	}
970
971	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
972	}
973	else
974	{
975	Assert(VBOX_FAILURE(rc));
976	if (rc == VERR_EM_INTERPRETER)
977	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
978	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
979	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
980	}
981	return rc;
982	}
983
984	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
985
986
987	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
988
989	/**
990	* Write access handler for the Guest CR3 page in PAE mode.
991	*
992	* This will try interpret the instruction, if failure fail back to the recompiler.
993	* Check if the changed PDEs are marked present and conflicts with our
994	* mappings. If conflict, we'll switch to the host context and resolve it there
995	*
996	* @returns VBox status code (appropritate for trap handling and GC return).
997	* @param pVM VM Handle.
998	* @param uErrorCode CPU Error code.
999	* @param pRegFrame Trap register frame.
1000	* @param pvFault The fault address (cr2).
1001	* @param GCPhysFault The GC physical address corresponding to pvFault.
1002	* @param pvUser User argument.
1003	*/
1004	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1005	{
1006	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1007
1008	/*
1009	* Try interpret the instruction.
1010	*/
1011	uint32_t cb;
1012	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1013	if (VBOX_SUCCESS(rc) && cb)
1014	{
1015	/*
1016	* Check if any of the PDs have changed.
1017	* We'll simply check all of them instead of figuring out which one/two to check.
1018	*/
1019	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1020	{
1021	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1022	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1023	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1024	{
1025	/*
1026	* The PDPE has changed.
1027	* We will schedule a monitoring update for the next TLB Flush,
1028	* InvalidatePage or SyncCR3.
1029	*
1030	* This isn't perfect, because a lazy page sync might be dealing with an half
1031	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1032	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1033	* executing.
1034	*/
1035	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1036	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1037	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1038	}
1039	}
1040
1041	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1042	}
1043	else
1044	{
1045	Assert(VBOX_FAILURE(rc));
1046	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1047	if (rc == VERR_EM_INTERPRETER)
1048	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1049	}
1050	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1051	return rc;
1052	}
1053
1054
1055	/**
1056	* Write access handler for the Guest PDs in PAE mode.
1057	*
1058	* This will try interpret the instruction, if failure fail back to the recompiler.
1059	* Check if the changed PDEs are marked present and conflicts with our
1060	* mappings. If conflict, we'll switch to the host context and resolve it there
1061	*
1062	* @returns VBox status code (appropritate for trap handling and GC return).
1063	* @param pVM VM Handle.
1064	* @param uErrorCode CPU Error code.
1065	* @param pRegFrame Trap register frame.
1066	* @param pvFault The fault address (cr2).
1067	* @param GCPhysFault The GC physical address corresponding to pvFault.
1068	* @param pvUser User argument.
1069	*/
1070	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1071	{
1072	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1073
1074	/*
1075	* Try interpret the instruction.
1076	*/
1077	uint32_t cb;
1078	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1079	if (VBOX_SUCCESS(rc) && cb)
1080	{
1081	/*
1082	* Figure out which of the 4 PDs this is.
1083	*/
1084	RTGCUINTPTR i;
1085	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1086	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1087	{
1088	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1089	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1090	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1091	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1092
1093	Assert(cb > 0 && cb <= 8);
1094	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1095	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1096
1097	#ifdef DEBUG
1098	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1099	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1100	if (iPD1 != iPD2)
1101	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1102	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1103	#endif
1104
1105	if (!pVM->pgm.s.fMappingsFixed)
1106	{
1107	if ( ( pPDSrc->a[iPD1].n.u1Present
1108	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1109	\|\| ( iPD1 != iPD2
1110	&& pPDSrc->a[iPD2].n.u1Present
1111	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1112	)
1113	{
1114	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1115	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1116	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1117	return VINF_PGM_SYNC_CR3;
1118	}
1119	}
1120	break; /* ASSUMES no duplicate entries... */
1121	}
1122	Assert(i < 4);
1123
1124	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1125	}
1126	else
1127	{
1128	Assert(VBOX_FAILURE(rc));
1129	if (rc == VERR_EM_INTERPRETER)
1130	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1131	else
1132	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1133	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1134	}
1135	return rc;
1136	}
1137
1138	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1139

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 9871

Download in other formats: