PGMAllGst.h@ 9893

Last change on this file since 9893 was 9893, checked in by vboxsync, 17 years ago
Attempt to fix PAE (can't verify now). AMD64 paging updates.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 43.4 KB

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1	/* $Id: PGMAllGst.h 9893 2008-06-24 15:56:57Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Defined Constants And Macros *
25	*******************************************************************************/
26	#undef GSTPT
27	#undef PGSTPT
28	#undef GSTPTE
29	#undef PGSTPTE
30	#undef GSTPD
31	#undef PGSTPD
32	#undef GSTPDE
33	#undef PGSTPDE
34	#undef GST_BIG_PAGE_SIZE
35	#undef GST_BIG_PAGE_OFFSET_MASK
36	#undef GST_PDE_PG_MASK
37	#undef GST_PDE_BIG_PG_MASK
38	#undef GST_PD_SHIFT
39	#undef GST_PD_MASK
40	#undef GST_PTE_PG_MASK
41	#undef GST_PT_SHIFT
42	#undef GST_PT_MASK
43	#undef GST_TOTAL_PD_ENTRIES
44	#undef GST_CR3_PAGE_MASK
45	#undef GST_PDPE_ENTRIES
46	#undef GST_PDPT_SHIFT
47	#undef GST_PDPT_MASK
48	#undef GST_PDPE_PG_MASK
49
50	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
51	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
52	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
53	# define GSTPT X86PT
54	# define PGSTPT PX86PT
55	# define GSTPTE X86PTE
56	# define PGSTPTE PX86PTE
57	# define GSTPD X86PD
58	# define PGSTPD PX86PD
59	# define GSTPDE X86PDE
60	# define PGSTPDE PX86PDE
61	# define GST_BIG_PAGE_SIZE X86_PAGE_4M_SIZE
62	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_4M_OFFSET_MASK
63	# define GST_PDE_PG_MASK X86_PDE_PG_MASK
64	# define GST_PDE_BIG_PG_MASK X86_PDE4M_PG_MASK
65	# define GST_PD_SHIFT X86_PD_SHIFT
66	# define GST_PD_MASK X86_PD_MASK
67	# define GST_TOTAL_PD_ENTRIES X86_PG_ENTRIES
68	# define GST_PTE_PG_MASK X86_PTE_PG_MASK
69	# define GST_PT_SHIFT X86_PT_SHIFT
70	# define GST_PT_MASK X86_PT_MASK
71	# define GST_CR3_PAGE_MASK X86_CR3_PAGE_MASK
72	#elif PGM_GST_TYPE == PGM_TYPE_PAE \
73	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
74	# define GSTPT X86PTPAE
75	# define PGSTPT PX86PTPAE
76	# define GSTPTE X86PTEPAE
77	# define PGSTPTE PX86PTEPAE
78	# define GSTPD X86PDPAE
79	# define PGSTPD PX86PDPAE
80	# define GSTPDE X86PDEPAE
81	# define PGSTPDE PX86PDEPAE
82	# define GST_BIG_PAGE_SIZE X86_PAGE_2M_SIZE
83	# define GST_BIG_PAGE_OFFSET_MASK X86_PAGE_2M_OFFSET_MASK
84	# define GST_PDE_PG_MASK X86_PDE_PAE_PG_MASK_FULL
85	# define GST_PDE_BIG_PG_MASK X86_PDE2M_PAE_PG_MASK
86	# define GST_PD_SHIFT X86_PD_PAE_SHIFT
87	# define GST_PD_MASK X86_PD_PAE_MASK
88	# if PGM_GST_TYPE == PGM_TYPE_PAE
89	# define GST_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
90	# define GST_PDPE_ENTRIES X86_PG_PAE_PDPE_ENTRIES
91	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
92	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
93	# define GST_PDPT_MASK X86_PDPT_MASK_PAE
94	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK
95	# define GST_CR3_PAGE_MASK X86_CR3_PAE_PAGE_MASK
96	# else
97	# define GST_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES * X86_PG_AMD64_PDPE_ENTRIES)
98	# define GST_PDPE_ENTRIES X86_PG_AMD64_PDPE_ENTRIES
99	# define GST_PDPT_SHIFT X86_PDPT_SHIFT
100	# define GST_PDPE_PG_MASK X86_PDPE_PG_MASK_FULL
101	# define GST_PDPT_MASK X86_PDPT_MASK_AMD64
102	# define GST_PTE_PG_MASK X86_PTE_PAE_PG_MASK_FULL
103	# define GST_CR3_PAGE_MASK X86_CR3_AMD64_PAGE_MASK
104	# endif
105	# define GST_PT_SHIFT X86_PT_PAE_SHIFT
106	# define GST_PT_MASK X86_PT_PAE_MASK
107	#endif
108
109
110	/*******************************************************************************
111	* Internal Functions *
112	*******************************************************************************/
113	__BEGIN_DECLS
114	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
115	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
116	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE);
117	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
118	PGM_GST_DECL(int, UnmapCR3)(PVM pVM);
119	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
120	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM);
121	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4);
122	#ifndef IN_RING3
123	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
124	# if PGM_GST_TYPE == PGM_TYPE_PAE \
125	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
126	PGM_GST_DECL(int, PAEWriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
127	# endif
128	#endif
129	__END_DECLS
130
131
132
133	/**
134	* Gets effective Guest OS page information.
135	*
136	* When GCPtr is in a big page, the function will return as if it was a normal
137	* 4KB page. If the need for distinguishing between big and normal page becomes
138	* necessary at a later point, a PGMGstGetPage Ex() will be created for that
139	* purpose.
140	*
141	* @returns VBox status.
142	* @param pVM VM Handle.
143	* @param GCPtr Guest Context virtual address of the page. Page aligned!
144	* @param pfFlags Where to store the flags. These are X86_PTE_*, even for big pages.
145	* @param pGCPhys Where to store the GC physical address of the page.
146	* This is page aligned. The fact that the
147	*/
148	PGM_GST_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys)
149	{
150	#if PGM_GST_TYPE == PGM_TYPE_REAL \
151	\|\| PGM_GST_TYPE == PGM_TYPE_PROT
152	/*
153	* Fake it.
154	*/
155	if (pfFlags)
156	*pfFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US;
157	if (pGCPhys)
158	*pGCPhys = GCPtr & PAGE_BASE_GC_MASK;
159	return VINF_SUCCESS;
160
161	#elif PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
162
163	/*
164	* Get the PDE.
165	*/
166	# if PGM_GST_TYPE == PGM_TYPE_32BIT
167	const X86PDE Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
168	#elif PGM_GST_TYPE == PGM_TYPE_PAE
169	X86PDEPAE Pde;
170	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
171
172	/* pgmGstGetPaePDE will return 0 if the PDPTE is marked as not present
173	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
174	*/
175	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
176	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
177	PX86PML4E pPml4e;
178	X86PDPE Pdpe;
179	X86PDEPAE Pde;
180	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
181
182	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr, &pPml4e, &Pdpe);
183	Assert(pPml4e);
184	if (!(pPml4e->n.u1Present & Pdpe.n.u1Present))
185	return VERR_PAGE_TABLE_NOT_PRESENT;
186
187	/* Merge accessed, write, user and no-execute bits into the PDE. */
188	Pde.n.u1Accessed &= pPml4e->n.u1Accessed & Pdpe.lm.u1Accessed;
189	Pde.n.u1Write &= pPml4e->n.u1Write & Pdpe.lm.u1Write;
190	Pde.n.u1User &= pPml4e->n.u1User & Pdpe.lm.u1User;
191	Pde.n.u1NoExecute &= pPml4e->n.u1NoExecute & Pdpe.lm.u1NoExecute;
192	# endif
193
194	/*
195	* Lookup the page.
196	*/
197	if (!Pde.n.u1Present)
198	return VERR_PAGE_TABLE_NOT_PRESENT;
199
200	if ( !Pde.b.u1Size
201	# if PGM_GST_TYPE != PGM_TYPE_AMD64
202	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
203	# endif
204	)
205	{
206	PGSTPT pPT;
207	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
208	if (VBOX_FAILURE(rc))
209	return rc;
210
211	/*
212	* Get PT entry and check presence.
213	*/
214	const GSTPTE Pte = pPT->a[(GCPtr >> GST_PT_SHIFT) & GST_PT_MASK];
215	if (!Pte.n.u1Present)
216	return VERR_PAGE_NOT_PRESENT;
217
218	/*
219	* Store the result.
220	* RW and US flags depend on all levels (bitwise AND) - except for legacy PAE
221	* where the PDPE is simplified.
222	*/
223	if (pfFlags)
224	{
225	*pfFlags = (Pte.u & ~GST_PTE_PG_MASK)
226	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
227	# if PGM_WITH_NX(PGM_GST_TYPE)
228	/* The NX bit is determined by a bitwise OR between the PT and PD */
229	if (fNoExecuteBitValid)
230	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
231	# endif
232	}
233	if (pGCPhys)
234	*pGCPhys = Pte.u & GST_PTE_PG_MASK;
235	}
236	else
237	{
238	/*
239	* Map big to 4k PTE and store the result
240	*/
241	if (pfFlags)
242	{
243	*pfFlags = (Pde.u & ~(GST_PTE_PG_MASK \| X86_PTE_PAT))
244	\| ((Pde.u & X86_PDE4M_PAT) >> X86_PDE4M_PAT_SHIFT);
245	# if PGM_WITH_NX(PGM_GST_TYPE)
246	/* The NX bit is determined by a bitwise OR between the PT and PD */
247	if (fNoExecuteBitValid)
248	*pfFlags \|= (Pde.u & X86_PTE_PAE_NX);
249	# endif
250	}
251	if (pGCPhys)
252	pGCPhys = (Pde.u & GST_PDE_BIG_PG_MASK) \| (GCPtr & (~GST_PDE_BIG_PG_MASK ^ ~GST_PTE_PG_MASK)); /* @todo pse36 */
253	}
254	return VINF_SUCCESS;
255	#else
256	# error "shouldn't be here!"
257	/* something else... */
258	return VERR_NOT_SUPPORTED;
259	#endif
260	}
261
262
263	/**
264	* Modify page flags for a range of pages in the guest's tables
265	*
266	* The existing flags are ANDed with the fMask and ORed with the fFlags.
267	*
268	* @returns VBox status code.
269	* @param pVM VM handle.
270	* @param GCPtr Virtual address of the first page in the range. Page aligned!
271	* @param cb Size (in bytes) of the page range to apply the modification to. Page aligned!
272	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
273	* @param fMask The AND mask - page flags X86_PTE_*.
274	*/
275	PGM_GST_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
276	{
277	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
278	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
279	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
280
281	for (;;)
282	{
283	/*
284	* Get the PD entry.
285	*/
286	# if PGM_GST_TYPE == PGM_TYPE_32BIT
287	PX86PDE pPde = &CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> X86_PD_SHIFT];
288	# elif PGM_GST_TYPE == PGM_TYPE_PAE
289	/* pgmGstGetPaePDEPtr will return 0 if the PDPTE is marked as not present
290	* All the other bits in the PDPTE are only valid in long mode (r/w, u/s, nx)
291	*/
292	PX86PDEPAE pPde = pgmGstGetPaePDEPtr(&pVM->pgm.s, GCPtr);
293	Assert(pPde);
294	if (!pPde)
295	return VERR_PAGE_TABLE_NOT_PRESENT;
296	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
297	/** @todo Setting the r/w, u/s & nx bits might have no effect depending on the pdpte & pml4 values */
298	PX86PDEPAE pPde = pgmGstGetLongModePDEPtr(&pVM->pgm.s, GCPtr);
299	Assert(pPde);
300	if (!pPde)
301	return VERR_PAGE_TABLE_NOT_PRESENT;
302	# endif
303	GSTPDE Pde = *pPde;
304	Assert(Pde.n.u1Present);
305	if (!Pde.n.u1Present)
306	return VERR_PAGE_TABLE_NOT_PRESENT;
307
308	if ( !Pde.b.u1Size
309	# if PGM_GST_TYPE != PGM_TYPE_AMD64
310	\|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE)
311	# endif
312	)
313	{
314	/*
315	* 4KB Page table
316	*
317	* Walk page tables and pages till we're done.
318	*/
319	PGSTPT pPT;
320	int rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
321	if (VBOX_FAILURE(rc))
322	return rc;
323
324	unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
325	while (iPTE < RT_ELEMENTS(pPT->a))
326	{
327	GSTPTE Pte = pPT->a[iPTE];
328	Pte.u = (Pte.u & (fMask \| X86_PTE_PAE_PG_MASK))
329	\| (fFlags & ~GST_PTE_PG_MASK);
330	pPT->a[iPTE] = Pte;
331
332	/* next page */
333	cb -= PAGE_SIZE;
334	if (!cb)
335	return VINF_SUCCESS;
336	GCPtr += PAGE_SIZE;
337	iPTE++;
338	}
339	}
340	else
341	{
342	/*
343	* 4MB Page table
344	*/
345	Pde.u = (Pde.u & (fMask \| ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) \| GST_PDE_BIG_PG_MASK \| X86_PDE4M_PS)) /** @todo pse36 */
346	\| (fFlags & ~GST_PTE_PG_MASK)
347	\| ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);
348	*pPde = Pde;
349
350	/* advance */
351	const unsigned cbDone = GST_BIG_PAGE_SIZE - (GCPtr & GST_BIG_PAGE_OFFSET_MASK);
352	if (cbDone >= cb)
353	return VINF_SUCCESS;
354	cb -= cbDone;
355	GCPtr += cbDone;
356	}
357	}
358
359	#else
360	/* real / protected mode: ignore. */
361	return VINF_SUCCESS;
362	#endif
363	}
364
365
366	/**
367	* Retrieve guest PDE information
368	*
369	* @returns VBox status code.
370	* @param pVM The virtual machine.
371	* @param GCPtr Guest context pointer
372	* @param pPDE Pointer to guest PDE structure
373	*/
374	PGM_GST_DECL(int, GetPDE)(PVM pVM, RTGCUINTPTR GCPtr, PX86PDEPAE pPDE)
375	{
376	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
377	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
378	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
379
380	# if PGM_GST_TYPE == PGM_TYPE_32BIT
381	X86PDE Pde;
382	Pde = CTXSUFF(pVM->pgm.s.pGuestPD)->a[GCPtr >> GST_PD_SHIFT];
383	# elif PGM_GST_TYPE == PGM_TYPE_PAE
384	X86PDEPAE Pde;
385	Pde.u = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
386	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
387	X86PDEPAE Pde;
388	Pde.u = pgmGstGetLongModePDE(&pVM->pgm.s, GCPtr);
389	# endif
390
391	pPDE->u = (X86PGPAEUINT)Pde.u;
392	return VINF_SUCCESS;
393	#else
394	AssertFailed();
395	return VERR_NOT_IMPLEMENTED;
396	#endif
397	}
398
399
400
401	/**
402	* Maps the CR3 into HMA in GC and locate it in HC.
403	*
404	* @returns VBox status, no specials.
405	* @param pVM VM handle.
406	* @param GCPhysCR3 The physical address in the CR3 register.
407	*/
408	PGM_GST_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
409	{
410	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
411	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
412	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
413
414	LogFlow(("MapCR3: %VGp\n", GCPhysCR3));
415
416	/*
417	* Map the page CR3 points at.
418	*/
419	RTHCPHYS HCPhysGuestCR3;
420	RTHCPTR HCPtrGuestCR3;
421	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
422	if (VBOX_SUCCESS(rc))
423	{
424	rc = PGMMap(pVM, (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
425	if (VBOX_SUCCESS(rc))
426	{
427	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
428	# if PGM_GST_TYPE == PGM_TYPE_32BIT
429	pVM->pgm.s.pGuestPDHC = (R3R0PTRTYPE(PX86PD))HCPtrGuestCR3;
430	pVM->pgm.s.pGuestPDGC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
431
432	# elif PGM_GST_TYPE == PGM_TYPE_PAE
433	unsigned offset = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
434	pVM->pgm.s.pGstPaePDPTHC = (R3R0PTRTYPE(PX86PDPT)) HCPtrGuestCR3;
435	pVM->pgm.s.pGstPaePDPTGC = (RCPTRTYPE(PX86PDPT)) ((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + offset);
436	Log(("Cached mapping %VGv\n", pVM->pgm.s.pGstPaePDPTGC));
437
438	/*
439	* Map the 4 PDs too.
440	*/
441	RTGCUINTPTR GCPtr = (RTGCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
442	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
443	{
444	if (pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].n.u1Present)
445	{
446	RTHCPTR HCPtr;
447	RTHCPHYS HCPhys;
448	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
449	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
450	if (VBOX_SUCCESS(rc2))
451	{
452	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
453	AssertRCReturn(rc, rc);
454	pVM->pgm.s.apGstPaePDsHC[i] = (R3R0PTRTYPE(PX86PDPAE))HCPtr;
455	pVM->pgm.s.apGstPaePDsGC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
456	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
457	PGM_INVL_PG(GCPtr);
458	continue;
459	}
460	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
461	}
462
463	pVM->pgm.s.apGstPaePDsHC[i] = 0;
464	pVM->pgm.s.apGstPaePDsGC[i] = 0;
465	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
466	PGM_INVL_PG(GCPtr);
467	}
468	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
469	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
470
471	pVM->pgm.s.pGstPaePML4HC = (R3R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
472
473	if (pVM->pgm.s.pShwAmd64CR3)
474	pgmPoolFreeByPage(pPool, pVM->pgm.s.pShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pShwAmd64CR3->GCPhys >> PAGE_SHIFT);
475
476	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
477	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pShwAmd64CR3);
478	if (rc == VERR_PGM_POOL_FLUSHED)
479	{
480	AssertFailed(); /* check if we handle this properly!! */
481	return VINF_PGM_SYNC_CR3;
482	}
483	pVM->pgm.s.pHCPaePML4 = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTXSUFF(pVM), pVM->pgm.s.pShwAmd64CR3);
484	# endif
485	}
486	else
487	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
488	}
489	else
490	AssertMsgFailed(("rc=%Vrc GCPhysGuestPD=%VGp\n", rc, GCPhysCR3));
491
492	#else /* prot/real stub */
493	int rc = VINF_SUCCESS;
494	#endif
495	return rc;
496	}
497
498
499	/**
500	* Unmaps the CR3.
501	*
502	* @returns VBox status, no specials.
503	* @param pVM VM handle.
504	* @param GCPhysCR3 The physical address in the CR3 register.
505	*/
506	PGM_GST_DECL(int, UnmapCR3)(PVM pVM)
507	{
508	LogFlow(("UnmapCR3\n"));
509
510	int rc = VINF_SUCCESS;
511	#if PGM_GST_TYPE == PGM_TYPE_32BIT
512	pVM->pgm.s.pGuestPDHC = 0;
513	pVM->pgm.s.pGuestPDGC = 0;
514
515	#elif PGM_GST_TYPE == PGM_TYPE_PAE
516	pVM->pgm.s.pGstPaePDPTHC = 0;
517	pVM->pgm.s.pGstPaePDPTGC = 0;
518	for (unsigned i=0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
519	{
520	pVM->pgm.s.apGstPaePDsHC[i] = 0;
521	pVM->pgm.s.apGstPaePDsGC[i] = 0;
522	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
523	}
524
525	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
526	pVM->pgm.s.pGstPaePML4HC = 0;
527	pVM->pgm.s.pHCPaePML4 = 0;
528	if (pVM->pgm.s.pShwAmd64CR3)
529	{
530	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
531	pgmPoolFreeByPage(pPool, pVM->pgm.s.pShwAmd64CR3, PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.pShwAmd64CR3->GCPhys >> PAGE_SHIFT);
532	pVM->pgm.s.pShwAmd64CR3 = NULL;
533	}
534
535	#else /* prot/real mode stub */
536	/* nothing to do */
537	#endif
538	return rc;
539	}
540
541
542	#undef LOG_GROUP
543	#define LOG_GROUP LOG_GROUP_PGM_POOL
544
545	/**
546	* Registers physical page monitors for the necessary paging
547	* structures to detect conflicts with our guest mappings.
548	*
549	* This is always called after mapping CR3.
550	* This is never called with fixed mappings.
551	*
552	* @returns VBox status, no specials.
553	* @param pVM VM handle.
554	* @param GCPhysCR3 The physical address in the CR3 register.
555	*/
556	PGM_GST_DECL(int, MonitorCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
557	{
558	Assert(!pVM->pgm.s.fMappingsFixed);
559	int rc = VINF_SUCCESS;
560
561	/*
562	* Register/Modify write phys handler for guest's CR3 if it changed.
563	*/
564	#if PGM_GST_TYPE == PGM_TYPE_32BIT
565
566	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
567	{
568	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
569	const unsigned cbCR3Stuff = PGM_GST_TYPE == PGM_TYPE_PAE ? 32 : PAGE_SIZE;
570	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
571	rc = PGMHandlerPhysicalModify(pVM, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1);
572	else
573	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE, GCPhysCR3, GCPhysCR3 + cbCR3Stuff - 1,
574	pVM->pgm.s.pfnR3GstWriteHandlerCR3, 0,
575	pVM->pgm.s.pfnR0GstWriteHandlerCR3, 0,
576	pVM->pgm.s.pfnGCGstWriteHandlerCR3, 0,
577	pVM->pgm.s.pszR3GstWriteHandlerCR3);
578	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
579	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
580	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
581	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
582	? PGMPOOL_IDX_PAE_PD
583	: PGMPOOL_IDX_PD,
584	GCPhysCR3);
585	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
586	if (VBOX_FAILURE(rc))
587	{
588	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
589	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
590	return rc;
591	}
592	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
593	}
594
595	#elif PGM_GST_TYPE == PGM_TYPE_PAE
596	/* Monitor the PDPT page */
597	/*
598	* Register/Modify write phys handler for guest's CR3 if it changed.
599	*/
600	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
601	AssertFailed();
602	# endif
603	if (pVM->pgm.s.GCPhysGstCR3Monitored != GCPhysCR3)
604	{
605	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT, GCPhysCR3);
606	if (VBOX_FAILURE(rc))
607	{
608	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
609	rc, pVM->pgm.s.GCPhysGstCR3Monitored, GCPhysCR3));
610	return rc;
611	}
612	pVM->pgm.s.GCPhysGstCR3Monitored = GCPhysCR3;
613	}
614	/*
615	* Do the 4 PDs.
616	*/
617	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
618	{
619	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present)
620	{
621	RTGCPHYS GCPhys = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
622	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != GCPhys)
623	{
624	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
625
626	rc = pgmPoolMonitorMonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i, GCPhys);
627	}
628
629	if (VBOX_FAILURE(rc))
630	{
631	AssertMsgFailed(("PGMHandlerPhysicalModify/PGMR3HandlerPhysicalRegister failed, rc=%Rrc GCPhysGstCR3Monitored=%RGp GCPhysCR3=%RGp\n",
632	rc, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i], GCPhys));
633	return rc;
634	}
635	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = GCPhys;
636	}
637	else if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
638	{
639	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
640	AssertRC(rc);
641	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
642	}
643	}
644
645	#else
646	/* prot/real/amd64 mode stub */
647
648	#endif
649	return rc;
650	}
651
652	/**
653	* Deregisters any physical page monitors installed by MonitorCR3.
654	*
655	* @returns VBox status code, no specials.
656	* @param pVM The VM handle.
657	*/
658	PGM_GST_DECL(int, UnmonitorCR3)(PVM pVM)
659	{
660	int rc = VINF_SUCCESS;
661
662	/*
663	* Deregister the access handlers.
664	*
665	* PGMSyncCR3 will reinstall it if required and PGMSyncCR3 will be executed
666	* before we enter GC again.
667	*/
668	#if PGM_GST_TYPE == PGM_TYPE_32BIT
669	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
670	{
671	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
672	rc = PGMHandlerPhysicalDeregister(pVM, pVM->pgm.s.GCPhysGstCR3Monitored);
673	AssertRCReturn(rc, rc);
674	# else /* PGMPOOL_WITH_MIXED_PT_CR3 */
675	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool),
676	pVM->pgm.s.enmShadowMode == PGMMODE_PAE
677	\|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX
678	? PGMPOOL_IDX_PAE_PD
679	: PGMPOOL_IDX_PD);
680	AssertRCReturn(rc, rc);
681	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
682	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
683	}
684
685	#elif PGM_GST_TYPE == PGM_TYPE_PAE
686	/* The PDPT page */
687	# ifndef PGMPOOL_WITH_MIXED_PT_CR3
688	AssertFailed();
689	# endif
690
691	if (pVM->pgm.s.GCPhysGstCR3Monitored != NIL_RTGCPHYS)
692	{
693	rc = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PDPT);
694	AssertRC(rc);
695	}
696
697	/* The 4 PDs. */
698	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
699	{
700	if (pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] != NIL_RTGCPHYS)
701	{
702	Assert(pVM->pgm.s.enmShadowMode == PGMMODE_PAE \|\| pVM->pgm.s.enmShadowMode == PGMMODE_PAE_NX);
703	int rc2 = pgmPoolMonitorUnmonitorCR3(pVM->pgm.s.CTXSUFF(pPool), PGMPOOL_IDX_PAE_PD_0 + i);
704	AssertRC(rc2);
705	if (VBOX_FAILURE(rc2))
706	rc = rc2;
707	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
708	}
709	}
710	#else
711	/* prot/real/amd64 mode stub */
712	#endif
713	return rc;
714
715	}
716
717	#undef LOG_GROUP
718	#define LOG_GROUP LOG_GROUP_PGM
719
720
721	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
722	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
723	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
724	/**
725	* Updates one virtual handler range.
726	*
727	* @returns 0
728	* @param pNode Pointer to a PGMVIRTHANDLER.
729	* @param pvUser Pointer to a PGMVHUARGS structure (see PGM.cpp).
730	*/
731	static DECLCALLBACK(int) PGM_GST_NAME(VirtHandlerUpdateOne)(PAVLROGCPTRNODECORE pNode, void *pvUser)
732	{
733	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
734	PPGMHVUSTATE pState = (PPGMHVUSTATE)pvUser;
735	Assert(pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR);
736
737	#if PGM_GST_TYPE == PGM_TYPE_32BIT
738	PX86PD pPDSrc = pState->pVM->pgm.s.CTXSUFF(pGuestPD);
739	#endif
740
741	RTGCUINTPTR GCPtr = (RTUINTPTR)pCur->GCPtr;
742	#if PGM_GST_MODE != PGM_MODE_AMD64
743	/* skip all stuff above 4GB if not AMD64 mode. */
744	if (GCPtr >= _4GB)
745	return 0;
746	#endif
747
748	unsigned offPage = GCPtr & PAGE_OFFSET_MASK;
749	unsigned iPage = 0;
750	while (iPage < pCur->cPages)
751	{
752	#if PGM_GST_TYPE == PGM_TYPE_32BIT
753	X86PDE Pde = pPDSrc->a[GCPtr >> X86_PD_SHIFT];
754	#elif PGM_GST_TYPE == PGM_TYPE_PAE
755	X86PDEPAE Pde;
756	Pde.u = pgmGstGetPaePDE(&pState->pVM->pgm.s, GCPtr);
757	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
758	X86PDEPAE Pde;
759	Pde.u = pgmGstGetLongModePDE(&pState->pVM->pgm.s, GCPtr);
760	#endif
761	if (Pde.n.u1Present)
762	{
763	if ( !Pde.b.u1Size
764	# if PGM_GST_TYPE != PGM_TYPE_AMD64
765	\|\| !(pState->cr4 & X86_CR4_PSE)
766	# endif
767	)
768	{
769	/*
770	* Normal page table.
771	*/
772	PGSTPT pPT;
773	int rc = PGM_GCPHYS_2_PTR(pState->pVM, Pde.u & GST_PDE_PG_MASK, &pPT);
774	if (VBOX_SUCCESS(rc))
775	{
776	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
777	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
778	iPTE++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
779	{
780	GSTPTE Pte = pPT->a[iPTE];
781	RTGCPHYS GCPhysNew;
782	if (Pte.n.u1Present)
783	GCPhysNew = (RTGCPHYS)(pPT->a[iPTE].u & GST_PTE_PG_MASK) + offPage;
784	else
785	GCPhysNew = NIL_RTGCPHYS;
786	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
787	{
788	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
789	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
790	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
791	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
792	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
793	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
794	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
795	#endif
796	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
797	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
798	}
799	}
800	}
801	else
802	{
803	/* not-present. */
804	offPage = 0;
805	AssertRC(rc);
806	for (unsigned iPTE = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
807	iPTE < RT_ELEMENTS(pPT->a) && iPage < pCur->cPages;
808	iPTE++, iPage++, GCPtr += PAGE_SIZE)
809	{
810	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
811	{
812	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
813	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
814	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
815	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
816	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
817	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias));
818	#endif
819	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
820	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
821	}
822	}
823	}
824	}
825	else
826	{
827	/*
828	* 2/4MB page.
829	*/
830	RTGCPHYS GCPhys = (RTGCPHYS)(Pde.u & GST_PDE_PG_MASK);
831	for (unsigned i4KB = (GCPtr >> GST_PT_SHIFT) & GST_PT_MASK;
832	i4KB < PAGE_SIZE / sizeof(GSTPDE) && iPage < pCur->cPages;
833	i4KB++, iPage++, GCPtr += PAGE_SIZE, offPage = 0)
834	{
835	RTGCPHYS GCPhysNew = GCPhys + (i4KB << PAGE_SHIFT) + offPage;
836	if (pCur->aPhysToVirt[iPage].Core.Key != GCPhysNew)
837	{
838	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
839	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
840	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
841	AssertReleaseMsg(!pCur->aPhysToVirt[iPage].offNextAlias,
842	("{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} GCPhysNew=%VGp\n",
843	pCur->aPhysToVirt[iPage].Core.Key, pCur->aPhysToVirt[iPage].Core.KeyLast,
844	pCur->aPhysToVirt[iPage].offVirtHandler, pCur->aPhysToVirt[iPage].offNextAlias, GCPhysNew));
845	#endif
846	pCur->aPhysToVirt[iPage].Core.Key = GCPhysNew;
847	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
848	}
849	}
850	} /* pde type */
851	}
852	else
853	{
854	/* not-present. */
855	for (unsigned cPages = (GST_PT_MASK + 1) - ((GCPtr >> GST_PT_SHIFT) & GST_PT_MASK);
856	cPages && iPage < pCur->cPages;
857	iPage++, GCPtr += PAGE_SIZE)
858	{
859	if (pCur->aPhysToVirt[iPage].Core.Key != NIL_RTGCPHYS)
860	{
861	pgmHandlerVirtualClearPage(&pState->pVM->pgm.s, pCur, iPage);
862	pCur->aPhysToVirt[iPage].Core.Key = NIL_RTGCPHYS;
863	pState->fTodo \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
864	}
865	}
866	offPage = 0;
867	}
868	} /* for pages in virtual mapping. */
869
870	return 0;
871	}
872	#endif /* 32BIT, PAE and AMD64 */
873
874
875	/**
876	* Updates the virtual page access handlers.
877	*
878	* @returns true if bits were flushed.
879	* @returns false if bits weren't flushed.
880	* @param pVM VM handle.
881	* @param pPDSrc The page directory.
882	* @param cr4 The cr4 register value.
883	*/
884	PGM_GST_DECL(bool, HandlerVirtualUpdate)(PVM pVM, uint32_t cr4)
885	{
886	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
887	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
888	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
889
890	/** @todo
891	* In theory this is not sufficient: the guest can change a single page in a range with invlpg
892	*/
893
894	/*
895	* Resolve any virtual address based access handlers to GC physical addresses.
896	* This should be fairly quick.
897	*/
898	PGMHVUSTATE State;
899
900	pgmLock(pVM);
901	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
902	State.pVM = pVM;
903	State.fTodo = pVM->pgm.s.fSyncFlags;
904	State.cr4 = cr4;
905	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, PGM_GST_NAME(VirtHandlerUpdateOne), &State);
906	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualUpdate), a);
907
908
909	/*
910	* Set / reset bits?
911	*/
912	if (State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL)
913	{
914	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
915	Log(("pgmR3VirtualHandlersUpdate: resets bits\n"));
916	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.CTXSUFF(pTrees)->VirtHandlers, true, pgmHandlerVirtualResetOne, pVM);
917	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
918	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3HandlerVirtualReset), b);
919	}
920	pgmUnlock(pVM);
921
922	return !!(State.fTodo & PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL);
923
924	#else /* real / protected */
925	return false;
926	#endif
927	}
928
929
930	#if PGM_GST_TYPE == PGM_TYPE_32BIT && !defined(IN_RING3)
931
932	/**
933	* Write access handler for the Guest CR3 page in 32-bit mode.
934	*
935	* This will try interpret the instruction, if failure fail back to the recompiler.
936	* Check if the changed PDEs are marked present and conflicts with our
937	* mappings. If conflict, we'll switch to the host context and resolve it there
938	*
939	* @returns VBox status code (appropritate for trap handling and GC return).
940	* @param pVM VM Handle.
941	* @param uErrorCode CPU Error code.
942	* @param pRegFrame Trap register frame.
943	* @param pvFault The fault address (cr2).
944	* @param GCPhysFault The GC physical address corresponding to pvFault.
945	* @param pvUser User argument.
946	*/
947	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
948	{
949	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
950
951	/*
952	* Try interpret the instruction.
953	*/
954	uint32_t cb;
955	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
956	if (VBOX_SUCCESS(rc) && cb)
957	{
958	/*
959	* Check if the modified PDEs are present and mappings.
960	*/
961	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
962	const unsigned iPD1 = offPD / sizeof(X86PDE);
963	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDE);
964
965	Assert(cb > 0 && cb <= 8);
966	Assert(iPD1 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a)); /// @todo R3/R0 separation.
967	Assert(iPD2 < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(pGuestPD)->a));
968
969	#ifdef DEBUG
970	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD1, iPD1 << X86_PD_SHIFT));
971	if (iPD1 != iPD2)
972	Log(("pgmXXGst32BitWriteHandlerCR3: emulated change to PD %#x addr=%VGv\n", iPD2, iPD2 << X86_PD_SHIFT));
973	#endif
974
975	if (!pVM->pgm.s.fMappingsFixed)
976	{
977	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
978	if ( ( pPDSrc->a[iPD1].n.u1Present
979	&& pgmGetMapping(pVM, (RTGCPTR)(iPD1 << X86_PD_SHIFT)) )
980	\|\| ( iPD1 != iPD2
981	&& pPDSrc->a[iPD2].n.u1Present
982	&& pgmGetMapping(pVM, (RTGCPTR)(iPD2 << X86_PD_SHIFT)) )
983	)
984	{
985	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
986	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
987	if (rc == VINF_SUCCESS)
988	rc = VINF_PGM_SYNC_CR3;
989	Log(("pgmXXGst32BitWriteHandlerCR3: detected conflict iPD1=%#x iPD2=%#x - returns %Rrc\n", iPD1, iPD2, rc));
990	return rc;
991	}
992	}
993
994	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
995	}
996	else
997	{
998	Assert(VBOX_FAILURE(rc));
999	if (rc == VERR_EM_INTERPRETER)
1000	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1001	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1002	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1003	}
1004	return rc;
1005	}
1006
1007	#endif /* PGM_TYPE_32BIT && !IN_RING3 */
1008
1009
1010	#if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(IN_RING3)
1011
1012	/**
1013	* Write access handler for the Guest CR3 page in PAE mode.
1014	*
1015	* This will try interpret the instruction, if failure fail back to the recompiler.
1016	* Check if the changed PDEs are marked present and conflicts with our
1017	* mappings. If conflict, we'll switch to the host context and resolve it there
1018	*
1019	* @returns VBox status code (appropritate for trap handling and GC return).
1020	* @param pVM VM Handle.
1021	* @param uErrorCode CPU Error code.
1022	* @param pRegFrame Trap register frame.
1023	* @param pvFault The fault address (cr2).
1024	* @param GCPhysFault The GC physical address corresponding to pvFault.
1025	* @param pvUser User argument.
1026	*/
1027	PGM_GST_DECL(int, WriteHandlerCR3)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1028	{
1029	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1030
1031	/*
1032	* Try interpret the instruction.
1033	*/
1034	uint32_t cb;
1035	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1036	if (VBOX_SUCCESS(rc) && cb)
1037	{
1038	/*
1039	* Check if any of the PDs have changed.
1040	* We'll simply check all of them instead of figuring out which one/two to check.
1041	*/
1042	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1043	{
1044	if ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].n.u1Present
1045	&& ( CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK)
1046	!= pVM->pgm.s.aGCPhysGstPaePDsMonitored[i])
1047	{
1048	/*
1049	* The PDPE has changed.
1050	* We will schedule a monitoring update for the next TLB Flush,
1051	* InvalidatePage or SyncCR3.
1052	*
1053	* This isn't perfect, because a lazy page sync might be dealing with an half
1054	* updated PDPE. However, we assume that the guest OS is disabling interrupts
1055	* and being extremely careful (cmpxchg8b) when updating a PDPE where it's
1056	* executing.
1057	*/
1058	pVM->pgm.s.fSyncFlags \|= PGM_SYNC_MONITOR_CR3;
1059	Log(("pgmXXGstPaeWriteHandlerCR3: detected updated PDPE; [%d] = %#llx, Old GCPhys=%VGp\n",
1060	i, CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u, pVM->pgm.s.aGCPhysGstPaePDsMonitored[i]));
1061	}
1062	}
1063
1064	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1065	}
1066	else
1067	{
1068	Assert(VBOX_FAILURE(rc));
1069	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1070	if (rc == VERR_EM_INTERPRETER)
1071	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1072	}
1073	Log(("pgmXXGstPaeWriteHandlerCR3: returns %Rrc\n", rc));
1074	return rc;
1075	}
1076
1077
1078	/**
1079	* Write access handler for the Guest PDs in PAE mode.
1080	*
1081	* This will try interpret the instruction, if failure fail back to the recompiler.
1082	* Check if the changed PDEs are marked present and conflicts with our
1083	* mappings. If conflict, we'll switch to the host context and resolve it there
1084	*
1085	* @returns VBox status code (appropritate for trap handling and GC return).
1086	* @param pVM VM Handle.
1087	* @param uErrorCode CPU Error code.
1088	* @param pRegFrame Trap register frame.
1089	* @param pvFault The fault address (cr2).
1090	* @param GCPhysFault The GC physical address corresponding to pvFault.
1091	* @param pvUser User argument.
1092	*/
1093	PGM_GST_DECL(int, WriteHandlerPD)(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1094	{
1095	AssertMsg(!pVM->pgm.s.fMappingsFixed, ("Shouldn't be registered when mappings are fixed!\n"));
1096
1097	/*
1098	* Try interpret the instruction.
1099	*/
1100	uint32_t cb;
1101	int rc = EMInterpretInstruction(pVM, pRegFrame, pvFault, &cb);
1102	if (VBOX_SUCCESS(rc) && cb)
1103	{
1104	/*
1105	* Figure out which of the 4 PDs this is.
1106	*/
1107	RTGCUINTPTR i;
1108	for (i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
1109	if (CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[i].u == (GCPhysFault & X86_PTE_PAE_PG_MASK))
1110	{
1111	PX86PDPAE pPDSrc = pgmGstGetPaePD(&pVM->pgm.s, i << X86_PDPT_SHIFT);
1112	const RTGCUINTPTR offPD = GCPhysFault & PAGE_OFFSET_MASK;
1113	const unsigned iPD1 = offPD / sizeof(X86PDEPAE);
1114	const unsigned iPD2 = (offPD + cb - 1) / sizeof(X86PDEPAE);
1115
1116	Assert(cb > 0 && cb <= 8);
1117	Assert(iPD1 < X86_PG_PAE_ENTRIES);
1118	Assert(iPD2 < X86_PG_PAE_ENTRIES);
1119
1120	#ifdef DEBUG
1121	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD1=%#05x (%VGv)\n",
1122	i, iPD1, (i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT)));
1123	if (iPD1 != iPD2)
1124	Log(("pgmXXGstPaeWriteHandlerPD: emulated change to i=%d iPD2=%#05x (%VGv)\n",
1125	i, iPD2, (i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT)));
1126	#endif
1127
1128	if (!pVM->pgm.s.fMappingsFixed)
1129	{
1130	if ( ( pPDSrc->a[iPD1].n.u1Present
1131	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD1 << X86_PD_PAE_SHIFT))) )
1132	\|\| ( iPD1 != iPD2
1133	&& pPDSrc->a[iPD2].n.u1Present
1134	&& pgmGetMapping(pVM, (RTGCPTR)((i << X86_PDPT_SHIFT) \| (iPD2 << X86_PD_PAE_SHIFT))) )
1135	)
1136	{
1137	Log(("pgmXXGstPaeWriteHandlerPD: detected conflict iPD1=%#x iPD2=%#x\n", iPD1, iPD2));
1138	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteConflict);
1139	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1140	return VINF_PGM_SYNC_CR3;
1141	}
1142	}
1143	break; /* ASSUMES no duplicate entries... */
1144	}
1145	Assert(i < 4);
1146
1147	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteHandled);
1148	}
1149	else
1150	{
1151	Assert(VBOX_FAILURE(rc));
1152	if (rc == VERR_EM_INTERPRETER)
1153	rc = VINF_EM_RAW_EMULATE_INSTR_PD_FAULT;
1154	else
1155	Log(("pgmXXGst32BitWriteHandlerCR3: returns %Rrc\n", rc));
1156	STAM_COUNTER_INC(&pVM->pgm.s.StatGCGuestCR3WriteUnhandled);
1157	}
1158	return rc;
1159	}
1160
1161	#endif /* PGM_TYPE_PAE && !IN_RING3 */
1162

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGst.h@ 9893

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