PGMAllGstSlatEpt.cpp.h@ 92780

Last change on this file since 92780 was 92685, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Started with constructing EPT-violation VM-exit for iemInitDecoderAndPrefetchOpcodes.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
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1	/* $Id: PGMAllGstSlatEpt.cpp.h 92685 2021-12-02 05:59:39Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest EPT SLAT - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#if PGM_GST_TYPE == PGM_TYPE_EPT
19	DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(PCVMCPUCC pVCpu, uint64_t uEntry)
20	{
21	if (!(uEntry & VMX_BF_EPT_PT_READ_MASK))
22	{
23	if (uEntry & VMX_BF_EPT_PT_WRITE_MASK)
24	return false;
25
26	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
27	if ( !RT_BF_GET(pVCpu->pgm.s.uEptVpidCapMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY)
28	&& (uEntry & VMX_BF_EPT_PT_EXECUTE_MASK))
29	return false;
30	}
31	return true;
32	}
33
34
35	DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(uint64_t uEntry, uint8_t uLevel)
36	{
37	Assert(uLevel >= 3 && uLevel <= 1); NOREF(uLevel);
38	uint64_t const fEptMemTypeMask = uEntry & VMX_BF_EPT_PT_MEMTYPE_MASK;
39	if ( fEptMemTypeMask == EPT_E_MEMTYPE_INVALID_2
40	\|\| fEptMemTypeMask == EPT_E_MEMTYPE_INVALID_3
41	\|\| fEptMemTypeMask == EPT_E_MEMTYPE_INVALID_7)
42	return false;
43	return true;
44	}
45
46
47	DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint64_t uEntry, uint8_t uLevel)
48	{
49	static PGMWALKFAIL const s_afEptViolations[] = { PGM_WALKFAIL_EPT_VIOLATION, PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE };
50	uint8_t const fEptVeSupported = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxEptXcptVe;
51	uint8_t const idxViolationType = fEptVeSupported & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
52
53	pWalk->fNotPresent = true;
54	pWalk->uLevel = uLevel;
55	pWalk->fFailed \|= s_afEptViolations[idxViolationType];
56	return VERR_PAGE_TABLE_NOT_PRESENT;
57	}
58
59
60	DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel, int rc)
61	{
62	AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
63	pWalk->fBadPhysAddr = true;
64	pWalk->uLevel = uLevel;
65	pWalk->fFailed \|= PGM_WALKFAIL_EPT_VIOLATION;
66	return VERR_PAGE_TABLE_NOT_PRESENT;
67	}
68
69
70	DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint64_t uEntry, uint8_t uLevel)
71	{
72	static PGMWALKFAIL const s_afEptViolations[] = { PGM_WALKFAIL_EPT_VIOLATION, PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE };
73	uint8_t const fEptVeSupported = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxEptXcptVe;
74	uint8_t const fConvertible = RT_BOOL(uLevel == 1 \|\| (uEntry & EPT_E_BIT_LEAF));
75	uint8_t const idxViolationType = fEptVeSupported & fConvertible & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
76
77	pWalk->fRsvdError = true;
78	pWalk->uLevel = uLevel;
79	pWalk->fFailed \|= s_afEptViolations[idxViolationType];
80	return VERR_PAGE_TABLE_NOT_PRESENT;
81	}
82
83
84	/**
85	* Performs an EPT walk (second-level address translation).
86	*
87	* @returns VBox status code.
88	* @retval VINF_SUCCESS on success.
89	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
90	*
91	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
92	* @param GCPhysNested The nested-guest physical address to walk.
93	* @param fIsLinearAddrValid Whether the linear-address in @c GCPtrNested caused
94	* this page walk. If this is false, @c GCPtrNested
95	* must be 0.
96	* @param GCPtrNested The nested-guest linear address that caused this
97	* page walk.
98	* @param pWalk The page walk info.
99	* @param pGstWalk The guest mode specific page walk info.
100	*/
101	DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(Walk)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested,
102	PPGMPTWALK pWalk, PGSTPTWALK pGstWalk)
103	{
104	Assert(fIsLinearAddrValid \|\| GCPtrNested == 0);
105
106	/*
107	* Init walk structures.
108	*/
109	RT_ZERO(*pWalk);
110	RT_ZERO(*pGstWalk);
111
112	pWalk->GCPtr = GCPtrNested;
113	pWalk->GCPhysNested = GCPhysNested;
114	pWalk->fIsLinearAddrValid = fIsLinearAddrValid;
115	pWalk->fIsSlat = true;
116
117	/*
118	* Figure out EPT attributes that are cumulative (logical-AND) across page walks.
119	* - R, W, X_SUPER are unconditionally cumulative.
120	* See Intel spec. Table 26-7 "Exit Qualification for EPT Violations".
121	*
122	* - X_USER is cumulative but relevant only when mode-based execute control for EPT
123	* which we currently don't support it (asserted below).
124	*
125	* - MEMTYPE is not cumulative and only applicable to the final paging entry.
126	*
127	* - A, D EPT bits map to the regular page-table bit positions. Thus, they're not
128	* included in the mask below and handled separately. Accessed bits are
129	* cumulative but dirty bits are not cumulative as they're only applicable to
130	* the final paging entry.
131	*/
132	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
133	uint64_t const fCumulativeEpt = PGM_PTATTRS_EPT_R_MASK
134	\| PGM_PTATTRS_EPT_W_MASK
135	\| PGM_PTATTRS_EPT_X_SUPER_MASK;
136
137	/*
138	* Do the walk.
139	*/
140	uint64_t fEffective;
141	{
142	/*
143	* Start with reading the EPT PML4E pointer.
144	*
145	* We currently only support 4 level EPT paging.
146	* EPT 5 level paging was documented at some point (bit 7 of MSR_IA32_VMX_EPT_VPID_CAP)
147	* but for some reason seems to have been removed from subsequent specs.
148	*/
149	int const rc = pgmGstGetEptPML4PtrEx(pVCpu, &pGstWalk->pPml4);
150	if (RT_SUCCESS(rc))
151	{ /* likely */ }
152	else
153	return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
154	}
155	{
156	/*
157	* PML4E.
158	*/
159	PEPTPML4E pPml4e;
160	pGstWalk->pPml4e = pPml4e = &pGstWalk->pPml4->a[(GCPhysNested >> EPT_PML4_SHIFT) & EPT_PML4_MASK];
161	EPTPML4E Pml4e;
162	pGstWalk->Pml4e.u = Pml4e.u = pPml4e->u;
163
164	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
165	else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pml4e.u, 4);
166
167	if (RT_LIKELY(GST_IS_PML4E_VALID(pVCpu, Pml4e))) { /* likely */ }
168	else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, Pml4e.u, 4);
169
170	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
171	uint64_t const fEptAttrs = Pml4e.u & EPT_PML4E_ATTR_MASK;
172	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
173	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
174	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
175	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
176	fEffective = RT_BF_MAKE(PGM_PTATTRS_R, fRead)
177	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
178	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
179	\| fEffectiveEpt;
180	pWalk->fEffective = fEffective;
181
182	int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & EPT_PML4E_PG_MASK, &pGstWalk->pPdpt);
183	if (RT_SUCCESS(rc)) { /* probable */ }
184	else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
185	}
186	{
187	/*
188	* PDPTE.
189	*/
190	PEPTPDPTE pPdpte;
191	pGstWalk->pPdpte = pPdpte = &pGstWalk->pPdpt->a[(GCPhysNested >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
192	EPTPDPTE Pdpte;
193	pGstWalk->Pdpte.u = Pdpte.u = pPdpte->u;
194
195	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pdpte)) { /* probable */ }
196	else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pdpte.u, 3);
197
198	/* The order of the following 2 "if" statements matter. */
199	if (GST_IS_PDPE_VALID(pVCpu, Pdpte))
200	{
201	uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE_ATTR_MASK;
202	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
203	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
204	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
205	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
206	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
207	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
208	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
209	\| (fEffectiveEpt & fCumulativeEpt);
210	pWalk->fEffective = fEffective;
211	}
212	else if ( GST_IS_BIG_PDPE_VALID(pVCpu, Pdpte)
213	&& PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pdpte.u, 3))
214	{
215	uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE1G_ATTR_MASK;
216	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
217	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
218	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
219	uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
220	uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
221	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
222	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
223	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
224	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
225	\| (fEffectiveEpt & fCumulativeEpt);
226	fEffective \|= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
227	\| RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
228	pWalk->fEffective = fEffective;
229
230	pWalk->fGigantPage = true;
231	pWalk->fSucceeded = true;
232	pWalk->GCPhys = GST_GET_BIG_PDPE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pdpte)
233	\| (GCPhysNested & GST_GIGANT_PAGE_OFFSET_MASK);
234	PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
235	return VINF_SUCCESS;
236	}
237	else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, Pdpte.u, 3);
238
239	int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpte.u & EPT_PDPTE_PG_MASK, &pGstWalk->pPd);
240	if (RT_SUCCESS(rc)) { /* probable */ }
241	else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
242	}
243	{
244	/*
245	* PDE.
246	*/
247	PGSTPDE pPde;
248	pGstWalk->pPde = pPde = &pGstWalk->pPd->a[(GCPhysNested >> GST_PD_SHIFT) & GST_PD_MASK];
249	GSTPDE Pde;
250	pGstWalk->Pde.u = Pde.u = pPde->u;
251
252	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
253	else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pde.u, 2);
254
255	/* The order of the following 2 "if" statements matter. */
256	if (GST_IS_PDE_VALID(pVCpu, Pde))
257	{
258	uint64_t const fEptAttrs = Pde.u & EPT_PDE_ATTR_MASK;
259	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
260	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
261	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
262	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
263	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
264	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
265	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
266	\| (fEffectiveEpt & fCumulativeEpt);
267	pWalk->fEffective = fEffective;
268
269	}
270	else if ( GST_IS_BIG_PDE_VALID(pVCpu, Pde)
271	&& PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pde.u, 2))
272	{
273	uint64_t const fEptAttrs = Pde.u & EPT_PDE2M_ATTR_MASK;
274	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
275	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
276	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
277	uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
278	uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
279	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
280	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
281	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
282	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
283	\| (fEffectiveEpt & fCumulativeEpt);
284	fEffective \|= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
285	\| RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
286	pWalk->fEffective = fEffective;
287
288	pWalk->fBigPage = true;
289	pWalk->fSucceeded = true;
290	pWalk->GCPhys = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
291	\| (GCPhysNested & GST_BIG_PAGE_OFFSET_MASK);
292	PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
293	return VINF_SUCCESS;
294	}
295	else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, Pde.u, 2);
296
297	int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GST_GET_PDE_GCPHYS(Pde), &pGstWalk->pPt);
298	if (RT_SUCCESS(rc)) { /* probable */ }
299	else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
300	}
301	{
302	/*
303	* PTE.
304	*/
305	PGSTPTE pPte;
306	pGstWalk->pPte = pPte = &pGstWalk->pPt->a[(GCPhysNested >> GST_PT_SHIFT) & GST_PT_MASK];
307	GSTPTE Pte;
308	pGstWalk->Pte.u = Pte.u = pPte->u;
309
310	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
311	else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pte.u, 1);
312
313	if ( GST_IS_PTE_VALID(pVCpu, Pte)
314	&& PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pte.u, 1))
315	{ /* likely*/ }
316	else
317	return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, Pte.u, 1);
318
319	uint64_t const fEptAttrs = Pte.u & EPT_PTE_ATTR_MASK;
320	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
321	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
322	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
323	uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
324	uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
325	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
326	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
327	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
328	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
329	\| (fEffectiveEpt & fCumulativeEpt);
330	fEffective \|= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
331	\| RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
332	pWalk->fEffective = fEffective;
333
334	pWalk->fSucceeded = true;
335	pWalk->GCPhys = GST_GET_PTE_GCPHYS(Pte) \| (GCPhysNested & PAGE_OFFSET_MASK);
336	return VINF_SUCCESS;
337	}
338	}
339	#else
340	# error "Guest paging type must be EPT."
341	#endif
342

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGstSlatEpt.cpp.h@ 92780

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