PGMAllGstSlatEpt.cpp.h@ 94884

Last change on this file since 94884 was 93922, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 EPT VM-exit handling with HM ring-0 code.
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1	/* $Id: PGMAllGstSlatEpt.cpp.h 93922 2022-02-24 15:14:31Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Guest EPT SLAT - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2021-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#if PGM_GST_TYPE == PGM_TYPE_EPT
19	DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(PCVMCPUCC pVCpu, uint64_t uEntry)
20	{
21	if (!(uEntry & EPT_E_READ))
22	{
23	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
24	Assert(!RT_BF_GET(pVCpu->pgm.s.uEptVpidCapMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY));
25	NOREF(pVCpu);
26	if (uEntry & (EPT_E_WRITE \| EPT_E_EXECUTE))
27	return false;
28	}
29	return true;
30	}
31
32
33	DECLINLINE(bool) PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(uint64_t uEntry, uint8_t uLevel)
34	{
35	Assert(uLevel <= 3 && uLevel >= 1); NOREF(uLevel);
36	uint8_t const fEptMemTypeMask = uEntry & VMX_BF_EPT_PT_MEMTYPE_MASK;
37	switch (fEptMemTypeMask)
38	{
39	case EPT_E_MEMTYPE_WB:
40	case EPT_E_MEMTYPE_UC:
41	case EPT_E_MEMTYPE_WP:
42	case EPT_E_MEMTYPE_WT:
43	case EPT_E_MEMTYPE_WC:
44	return true;
45	}
46	return false;
47	}
48
49
50	DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint64_t uEntry, uint8_t uLevel)
51	{
52	static PGMWALKFAIL const s_afEptViolations[] = { PGM_WALKFAIL_EPT_VIOLATION, PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE };
53	uint8_t const fEptVeSupported = pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxEptXcptVe;
54	uint8_t const fConvertible = RT_BOOL(uLevel == 1 \|\| (uEntry & EPT_E_BIT_LEAF));
55	uint8_t const idxViolationType = fEptVeSupported & fConvertible & !RT_BF_GET(uEntry, VMX_BF_EPT_PT_SUPPRESS_VE);
56
57	pWalk->fNotPresent = true;
58	pWalk->uLevel = uLevel;
59	pWalk->fFailed = s_afEptViolations[idxViolationType];
60	return VERR_PAGE_TABLE_NOT_PRESENT;
61	}
62
63
64	DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(PCVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel, int rc)
65	{
66	AssertMsg(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc)); NOREF(rc); NOREF(pVCpu);
67	pWalk->fBadPhysAddr = true;
68	pWalk->uLevel = uLevel;
69	pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION;
70	return VERR_PAGE_TABLE_NOT_PRESENT;
71	}
72
73
74	DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint8_t uLevel)
75	{
76	NOREF(pVCpu);
77	pWalk->fRsvdError = true;
78	pWalk->uLevel = uLevel;
79	pWalk->fFailed = PGM_WALKFAIL_EPT_MISCONFIG;
80	return VERR_PAGE_TABLE_NOT_PRESENT;
81	}
82
83
84	/**
85	* Performs an EPT walk (second-level address translation).
86	*
87	* @returns VBox status code.
88	* @retval VINF_SUCCESS on success.
89	* @retval VERR_PAGE_TABLE_NOT_PRESENT on failure. Check pWalk for details.
90	*
91	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
92	* @param GCPhysNested The nested-guest physical address to walk.
93	* @param fIsLinearAddrValid Whether the linear-address in @c GCPtrNested caused
94	* this page walk.
95	* @param GCPtrNested The nested-guest linear address that caused this
96	* page walk. If @c fIsLinearAddrValid is false, pass
97	* 0.
98	* @param pWalk The page walk info.
99	* @param pGstWalk The guest mode specific page walk info.
100	*/
101	DECLINLINE(int) PGM_GST_SLAT_NAME_EPT(Walk)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNested, bool fIsLinearAddrValid, RTGCPTR GCPtrNested,
102	PPGMPTWALK pWalk, PGSTPTWALK pGstWalk)
103	{
104	Assert(fIsLinearAddrValid \|\| GCPtrNested == 0);
105
106	/*
107	* Init walk structures.
108	*/
109	RT_ZERO(*pWalk);
110	RT_ZERO(*pGstWalk);
111
112	pWalk->GCPtr = GCPtrNested;
113	pWalk->GCPhysNested = GCPhysNested;
114	pWalk->fIsLinearAddrValid = fIsLinearAddrValid;
115	pWalk->fIsSlat = true;
116
117	/*
118	* Figure out EPT attributes that are cumulative (logical-AND) across page walks.
119	* - R, W, X_SUPER are unconditionally cumulative.
120	* See Intel spec. Table 26-7 "Exit Qualification for EPT Violations".
121	*
122	* - X_USER is cumulative but relevant only when mode-based execute control for EPT
123	* which we currently don't support it (asserted below).
124	*
125	* - MEMTYPE is not cumulative and only applicable to the final paging entry.
126	*
127	* - A, D EPT bits map to the regular page-table bit positions. Thus, they're not
128	* included in the mask below and handled separately. Accessed bits are
129	* cumulative but dirty bits are not cumulative as they're only applicable to
130	* the final paging entry.
131	*/
132	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
133	uint64_t const fCumulativeEpt = PGM_PTATTRS_EPT_R_MASK
134	\| PGM_PTATTRS_EPT_W_MASK
135	\| PGM_PTATTRS_EPT_X_SUPER_MASK;
136
137	/*
138	* Do the walk.
139	*/
140	uint64_t fEffective;
141	{
142	/*
143	* EPTP.
144	*
145	* We currently only support 4-level EPT paging.
146	* EPT 5-level paging was documented at some point (bit 7 of MSR_IA32_VMX_EPT_VPID_CAP)
147	* but for some reason seems to have been removed from subsequent specs.
148	*/
149	int const rc = pgmGstGetEptPML4PtrEx(pVCpu, &pGstWalk->pPml4);
150	if (RT_SUCCESS(rc))
151	{ /* likely */ }
152	else
153	return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 4, rc);
154	}
155	{
156	/*
157	* PML4E.
158	*/
159	PEPTPML4E pPml4e;
160	pGstWalk->pPml4e = pPml4e = &pGstWalk->pPml4->a[(GCPhysNested >> EPT_PML4_SHIFT) & EPT_PML4_MASK];
161	EPTPML4E Pml4e;
162	pGstWalk->Pml4e.u = Pml4e.u = pPml4e->u;
163
164	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pml4e)) { /* probable */ }
165	else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pml4e.u, 4);
166
167	if (RT_LIKELY( GST_IS_PML4E_VALID(pVCpu, Pml4e)
168	&& PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pml4e.u)))
169	{ /* likely */ }
170	else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 4);
171
172	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
173	uint64_t const fEptAttrs = Pml4e.u & EPT_PML4E_ATTR_MASK;
174	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
175	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
176	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
177	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
178	fEffective = RT_BF_MAKE(PGM_PTATTRS_R, fRead)
179	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
180	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
181	\| fEffectiveEpt;
182	pWalk->fEffective = fEffective;
183
184	int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pml4e.u & EPT_PML4E_PG_MASK, &pGstWalk->pPdpt);
185	if (RT_SUCCESS(rc)) { /* probable */ }
186	else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
187	}
188	{
189	/*
190	* PDPTE.
191	*/
192	PEPTPDPTE pPdpte;
193	pGstWalk->pPdpte = pPdpte = &pGstWalk->pPdpt->a[(GCPhysNested >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
194	EPTPDPTE Pdpte;
195	pGstWalk->Pdpte.u = Pdpte.u = pPdpte->u;
196
197	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pdpte)) { /* probable */ }
198	else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pdpte.u, 3);
199
200	/* The order of the following "if" and "else if" statements matter. */
201	if ( GST_IS_PDPE_VALID(pVCpu, Pdpte)
202	&& PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u))
203	{
204	uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE_ATTR_MASK;
205	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
206	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
207	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
208	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
209	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
210	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
211	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
212	\| (fEffectiveEpt & fCumulativeEpt);
213	pWalk->fEffective = fEffective;
214	}
215	else if ( GST_IS_BIG_PDPE_VALID(pVCpu, Pdpte)
216	&& PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pdpte.u)
217	&& PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pdpte.u, 3))
218	{
219	uint64_t const fEptAttrs = Pdpte.u & EPT_PDPTE1G_ATTR_MASK;
220	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
221	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
222	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
223	uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
224	uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
225	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
226	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
227	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
228	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
229	\| (fEffectiveEpt & fCumulativeEpt);
230	fEffective \|= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
231	\| RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
232	pWalk->fEffective = fEffective;
233
234	pWalk->fGigantPage = true;
235	pWalk->fSucceeded = true;
236	pWalk->GCPhys = GST_GET_BIG_PDPE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pdpte)
237	\| (GCPhysNested & GST_GIGANT_PAGE_OFFSET_MASK);
238	PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
239	return VINF_SUCCESS;
240	}
241	else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 3);
242
243	int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, Pdpte.u & EPT_PDPTE_PG_MASK, &pGstWalk->pPd);
244	if (RT_SUCCESS(rc)) { /* probable */ }
245	else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 3, rc);
246	}
247	{
248	/*
249	* PDE.
250	*/
251	PGSTPDE pPde;
252	pGstWalk->pPde = pPde = &pGstWalk->pPd->a[(GCPhysNested >> GST_PD_SHIFT) & GST_PD_MASK];
253	GSTPDE Pde;
254	pGstWalk->Pde.u = Pde.u = pPde->u;
255
256	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pde)) { /* probable */ }
257	else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pde.u, 2);
258
259	/* The order of the following "if" and "else if" statements matter. */
260	if ( GST_IS_PDE_VALID(pVCpu, Pde)
261	&& PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u))
262	{
263	uint64_t const fEptAttrs = Pde.u & EPT_PDE_ATTR_MASK;
264	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
265	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
266	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
267	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
268	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
269	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
270	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
271	\| (fEffectiveEpt & fCumulativeEpt);
272	pWalk->fEffective = fEffective;
273
274	}
275	else if ( GST_IS_BIG_PDE_VALID(pVCpu, Pde)
276	&& PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pde.u)
277	&& PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pde.u, 2))
278	{
279	uint64_t const fEptAttrs = Pde.u & EPT_PDE2M_ATTR_MASK;
280	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
281	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
282	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
283	uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
284	uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
285	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
286	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
287	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
288	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
289	\| (fEffectiveEpt & fCumulativeEpt);
290	fEffective \|= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
291	\| RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
292	pWalk->fEffective = fEffective;
293
294	pWalk->fBigPage = true;
295	pWalk->fSucceeded = true;
296	pWalk->GCPhys = GST_GET_BIG_PDE_GCPHYS(pVCpu->CTX_SUFF(pVM), Pde)
297	\| (GCPhysNested & GST_BIG_PAGE_OFFSET_MASK);
298	PGM_A20_APPLY_TO_VAR(pVCpu, pWalk->GCPhys);
299	return VINF_SUCCESS;
300	}
301	else return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 2);
302
303	int const rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GST_GET_PDE_GCPHYS(Pde), &pGstWalk->pPt);
304	if (RT_SUCCESS(rc)) { /* probable */ }
305	else return PGM_GST_SLAT_NAME_EPT(WalkReturnBadPhysAddr)(pVCpu, pWalk, 1, rc);
306	}
307	{
308	/*
309	* PTE.
310	*/
311	PGSTPTE pPte;
312	pGstWalk->pPte = pPte = &pGstWalk->pPt->a[(GCPhysNested >> GST_PT_SHIFT) & GST_PT_MASK];
313	GSTPTE Pte;
314	pGstWalk->Pte.u = Pte.u = pPte->u;
315
316	if (GST_IS_PGENTRY_PRESENT(pVCpu, Pte)) { /* probable */ }
317	else return PGM_GST_SLAT_NAME_EPT(WalkReturnNotPresent)(pVCpu, pWalk, Pte.u, 1);
318
319	if ( GST_IS_PTE_VALID(pVCpu, Pte)
320	&& PGM_GST_SLAT_NAME_EPT(WalkIsPermValid)(pVCpu, Pte.u)
321	&& PGM_GST_SLAT_NAME_EPT(WalkIsMemTypeValid)(Pte.u, 1))
322	{ /* likely*/ }
323	else
324	return PGM_GST_SLAT_NAME_EPT(WalkReturnRsvdError)(pVCpu, pWalk, 1);
325
326	uint64_t const fEptAttrs = Pte.u & EPT_PTE_ATTR_MASK;
327	uint8_t const fRead = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_READ);
328	uint8_t const fWrite = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_WRITE);
329	uint8_t const fAccessed = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_ACCESSED);
330	uint8_t const fDirty = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_DIRTY);
331	uint8_t const fMemType = RT_BF_GET(fEptAttrs, VMX_BF_EPT_PT_MEMTYPE);
332	uint64_t const fEffectiveEpt = (fEptAttrs << PGM_PTATTRS_EPT_SHIFT) & PGM_PTATTRS_EPT_MASK;
333	fEffective &= RT_BF_MAKE(PGM_PTATTRS_R, fRead)
334	\| RT_BF_MAKE(PGM_PTATTRS_W, fWrite)
335	\| RT_BF_MAKE(PGM_PTATTRS_A, fAccessed)
336	\| (fEffectiveEpt & fCumulativeEpt);
337	fEffective \|= RT_BF_MAKE(PGM_PTATTRS_D, fDirty)
338	\| RT_BF_MAKE(PGM_PTATTRS_EPT_MEMTYPE, fMemType);
339	pWalk->fEffective = fEffective;
340
341	pWalk->fSucceeded = true;
342	pWalk->GCPhys = GST_GET_PTE_GCPHYS(Pte) \| (GCPhysNested & GUEST_PAGE_OFFSET_MASK);
343	return VINF_SUCCESS;
344	}
345	}
346	#else
347	# error "Guest paging type must be EPT."
348	#endif
349

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllGstSlatEpt.cpp.h@ 94884

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