PGMAllMap.cpp@ 17059

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1	/* $Id: PGMAllMap.cpp 17017 2009-02-23 13:15:27Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include "PGMInternal.h"
28	#include <VBox/vm.h>
29	#include <iprt/assert.h>
30	#include <iprt/asm.h>
31	#include <VBox/err.h>
32
33
34	/**
35	* Maps a range of physical pages at a given virtual address
36	* in the guest context.
37	*
38	* The GC virtual address range must be within an existing mapping.
39	*
40	* @returns VBox status code.
41	* @param pVM The virtual machine.
42	* @param GCPtr Where to map the page(s). Must be page aligned.
43	* @param HCPhys Start of the range of physical pages. Must be page aligned.
44	* @param cbPages Number of bytes to map. Must be page aligned.
45	* @param fFlags Page flags (X86_PTE_*).
46	*/
47	VMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
48	{
49	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
50
51	/*
52	* Validate input.
53	*/
54	AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
55	AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
56	AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
57
58	/* hypervisor defaults */
59	if (!fFlags)
60	fFlags = X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
61
62	/*
63	* Find the mapping.
64	*/
65	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
66	while (pCur)
67	{
68	if (GCPtr - pCur->GCPtr < pCur->cb)
69	{
70	if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
71	{
72	AssertMsgFailed(("Invalid range!!\n"));
73	return VERR_INVALID_PARAMETER;
74	}
75
76	/*
77	* Setup PTE.
78	*/
79	X86PTEPAE Pte;
80	Pte.u = fFlags \| (HCPhys & X86_PTE_PAE_PG_MASK);
81
82	/*
83	* Update the page tables.
84	*/
85	for (;;)
86	{
87	RTGCUINTPTR off = GCPtr - pCur->GCPtr;
88	const unsigned iPT = off >> X86_PD_SHIFT;
89	const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
90
91	/* 32-bit */
92	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
93
94	/* pae */
95	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512].u = Pte.u;
96
97	/* next */
98	cbPages -= PAGE_SIZE;
99	if (!cbPages)
100	break;
101	GCPtr += PAGE_SIZE;
102	Pte.u += PAGE_SIZE;
103	}
104
105	return VINF_SUCCESS;
106	}
107
108	/* next */
109	pCur = pCur->CTX_SUFF(pNext);
110	}
111
112	AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
113	return VERR_INVALID_PARAMETER;
114	}
115
116
117	/**
118	* Sets (replaces) the page flags for a range of pages in a mapping.
119	*
120	* @returns VBox status.
121	* @param pVM VM handle.
122	* @param GCPtr Virtual address of the first page in the range.
123	* @param cb Size (in bytes) of the range to apply the modification to.
124	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
125	*/
126	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
127	{
128	return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
129	}
130
131
132	/**
133	* Modify page flags for a range of pages in a mapping.
134	*
135	* The existing flags are ANDed with the fMask and ORed with the fFlags.
136	*
137	* @returns VBox status code.
138	* @param pVM VM handle.
139	* @param GCPtr Virtual address of the first page in the range.
140	* @param cb Size (in bytes) of the range to apply the modification to.
141	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
142	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
143	*/
144	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
145	{
146	/*
147	* Validate input.
148	*/
149	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#x\n", fFlags));
150	Assert(cb);
151
152	/*
153	* Align the input.
154	*/
155	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
156	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
157	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
158
159	/*
160	* Find the mapping.
161	*/
162	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
163	while (pCur)
164	{
165	RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
166	if (off < pCur->cb)
167	{
168	AssertMsgReturn(off + cb <= pCur->cb,
169	("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
170	GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
171	VERR_INVALID_PARAMETER);
172
173	/*
174	* Perform the requested operation.
175	*/
176	while (cb > 0)
177	{
178	unsigned iPT = off >> X86_PD_SHIFT;
179	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
180	while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
181	{
182	/* 32-Bit */
183	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask \| X86_PTE_PG_MASK;
184	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u \|= fFlags & ~X86_PTE_PG_MASK;
185
186	/* PAE */
187	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u &= fMask \| X86_PTE_PAE_PG_MASK;
188	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u \|= fFlags & ~X86_PTE_PAE_PG_MASK;
189
190	/* invalidate tls */
191	PGM_INVL_PG((RTGCUINTPTR)pCur->GCPtr + off);
192
193	/* next */
194	iPTE++;
195	cb -= PAGE_SIZE;
196	off += PAGE_SIZE;
197	}
198	}
199
200	return VINF_SUCCESS;
201	}
202	/* next */
203	pCur = pCur->CTX_SUFF(pNext);
204	}
205
206	AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
207	return VERR_INVALID_PARAMETER;
208	}
209
210
211	#ifndef IN_RING0
212	/**
213	* Sets all PDEs involved with the mapping in the shadow page table.
214	*
215	* @param pVM The VM handle.
216	* @param pMap Pointer to the mapping in question.
217	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
218	*/
219	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
220	{
221	Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
222
223	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
224	return;
225
226	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
227	if (!pVM->pgm.s.CTX_SUFF(pShwPageCR3))
228	return; /* too early */
229	#endif
230
231	PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
232	Assert(enmShadowMode <= PGMMODE_PAE_NX);
233
234	/*
235	* Init the page tables and insert them into the page directories.
236	*/
237	unsigned i = pMap->cPTs;
238	iNewPDE += i;
239	while (i-- > 0)
240	{
241	iNewPDE--;
242
243	switch(enmShadowMode)
244	{
245	case PGMMODE_32_BIT:
246	{
247	PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
248	AssertFatal(pShw32BitPd);
249
250	if (pShw32BitPd->a[iNewPDE].n.u1Present)
251	{
252	Assert(!(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING));
253	pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
254	}
255
256	X86PDE Pde;
257	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
258	Pde.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT;
259	pShw32BitPd->a[iNewPDE] = Pde;
260	break;
261	}
262
263	case PGMMODE_PAE:
264	case PGMMODE_PAE_NX:
265	{
266	PX86PDPT pShwPdpt;
267	PX86PDPAE pShwPaePd;
268	const unsigned iPdPt = iNewPDE / 256;
269	unsigned iPDE = iNewPDE * 2 % 512;
270
271	pShwPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
272	Assert(pShwPdpt);
273	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPdPt << X86_PDPT_SHIFT));
274	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
275	if (!pShwPaePd)
276	{
277	X86PDPE GstPdpe;
278
279	if (PGMGetGuestMode(pVM) < PGMMODE_PAE)
280	{
281	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
282	GstPdpe.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
283	}
284	else
285	{
286	PX86PDPE pGstPdpe;
287	pGstPdpe = pgmGstGetPaePDPEPtr(&pVM->pgm.s, (iPdPt << X86_PDPT_SHIFT));
288	if (pGstPdpe)
289	GstPdpe = *pGstPdpe;
290	else
291	GstPdpe.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
292	}
293	int rc = pgmShwSyncPaePDPtr(pVM, (iPdPt << X86_PDPT_SHIFT), &GstPdpe, &pShwPaePd);
294	AssertFatal(RT_SUCCESS(rc));
295	if (rc != VINF_SUCCESS)
296	{
297	rc = pgmShwSyncPaePDPtr(pVM, (iPdPt << X86_PDPT_SHIFT), &GstPdpe, &pShwPaePd);
298	AssertFatalMsg(rc == VINF_SUCCESS, ("rc = %Rrc\n", rc));
299	}
300	}
301	#endif
302	AssertFatal(pShwPaePd);
303
304	PPGMPOOLPAGE pPoolPagePde = pgmPoolGetPageByHCPhys(pVM, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
305	AssertFatal(pPoolPagePde);
306
307	if (pShwPaePd->a[iPDE].n.u1Present)
308	{
309	Assert(!(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING));
310	pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePde->idx, iNewPDE);
311	}
312
313	X86PDEPAE PdePae0;
314	PdePae0.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0;
315	pShwPaePd->a[iPDE] = PdePae0;
316
317	/* 2nd 2 MB PDE of the 4 MB region */
318	iPDE++;
319	AssertFatal(iPDE < 512);
320
321	if (pShwPaePd->a[iPDE].n.u1Present)
322	{
323	Assert(!(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING));
324	pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePde->idx, iNewPDE);
325	}
326
327	X86PDEPAE PdePae1;
328	PdePae1.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1;
329	pShwPaePd->a[iPDE] = PdePae1;
330
331	/* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
332	pShwPdpt->a[iPdPt].u \|= PGM_PLXFLAGS_MAPPING;
333	break;
334	}
335
336	default:
337	AssertFailed();
338	break;
339	}
340	}
341	}
342
343	/**
344	* Clears all PDEs involved with the mapping in the shadow page table.
345	*
346	* @param pVM The VM handle.
347	* @param pShwPageCR3 CR3 root page
348	* @param pMap Pointer to the mapping in question.
349	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
350	*/
351	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE)
352	{
353	Log(("pgmMapClearShadowPDEs old pde %x (mappings enabled %d)\n", iOldPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
354
355	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
356	return;
357
358	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
359	Assert(pShwPageCR3);
360	#endif
361
362	unsigned i = pMap->cPTs;
363	PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
364
365	iOldPDE += i;
366	while (i-- > 0)
367	{
368	iOldPDE--;
369
370	switch(enmShadowMode)
371	{
372	case PGMMODE_32_BIT:
373	{
374	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
375	PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
376	#else
377	PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
378	#endif
379	AssertFatal(pShw32BitPd);
380
381	pShw32BitPd->a[iOldPDE].u = 0;
382	break;
383	}
384
385	case PGMMODE_PAE:
386	case PGMMODE_PAE_NX:
387	{
388	PX86PDPT pPdpt = NULL;
389	PX86PDPAE pShwPaePd = NULL;
390
391	const unsigned iPD = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
392	unsigned iPDE = iOldPDE * 2 % 512;
393	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
394	pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
395	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, pPdpt, (iPD << X86_PDPT_SHIFT));
396	#else
397	pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
398	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPD << X86_PDPT_SHIFT));
399	#endif
400	AssertFatal(pShwPaePd);
401
402	pShwPaePd->a[iPDE].u = 0;
403
404	iPDE++;
405	AssertFatal(iPDE < 512);
406
407	pShwPaePd->a[iPDE].u = 0;
408	/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
409	pPdpt->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
410	break;
411	}
412
413	default:
414	AssertFailed();
415	break;
416	}
417	}
418	}
419	#endif /* !IN_RING0 */
420
421	#ifdef VBOX_STRICT
422	/**
423	* Clears all PDEs involved with the mapping in the shadow page table.
424	*
425	* @param pVM The VM handle.
426	* @param pShwPageCR3 CR3 root page
427	* @param pMap Pointer to the mapping in question.
428	* @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
429	*/
430	void pgmMapCheckShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
431	{
432	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
433	return;
434
435	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
436	Assert(pShwPageCR3);
437	#endif
438
439	unsigned i = pMap->cPTs;
440	PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
441
442	iPDE += i;
443	while (i-- > 0)
444	{
445	iPDE--;
446
447	switch(enmShadowMode)
448	{
449	case PGMMODE_32_BIT:
450	{
451	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
452	PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
453	#else
454	PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
455	#endif
456	AssertFatal(pShw32BitPd);
457
458	AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT),
459	("Expected %x vs %x\n", pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT)));
460	break;
461	}
462
463	case PGMMODE_PAE:
464	case PGMMODE_PAE_NX:
465	{
466	PX86PDPT pPdpt = NULL;
467	PX86PDPAE pShwPaePd = NULL;
468
469	const unsigned iPD = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
470	unsigned iPaePDE = iPDE * 2 % 512;
471	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
472	pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
473	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, pPdpt, (iPD << X86_PDPT_SHIFT));
474	#else
475	pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
476	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPD << X86_PDPT_SHIFT));
477	#endif
478	AssertFatal(pShwPaePd);
479
480	AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0),
481	("Expected %RX64 vs %RX64\n", pShwPaePd->a[iPDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT)));
482
483	iPaePDE++;
484	AssertFatal(iPaePDE < 512);
485
486	AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1),
487	("Expected %RX64 vs %RX64\n", pShwPaePd->a[iPDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT)));
488	break;
489	}
490
491	default:
492	AssertFailed();
493	break;
494	}
495	}
496	}
497
498	/**
499	* Check the hypervisor mappings in the active CR3.
500	*
501	* @param pVM The virtual machine.
502	*/
503	VMMDECL(void) PGMMapCheck(PVM pVM)
504	{
505	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
506	/*
507	* Can skip this if mappings are disabled.
508	*/
509	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
510	return;
511
512	# ifdef IN_RING0
513	AssertFailed();
514	# else
515	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
516	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
517	# endif
518
519	/*
520	* Iterate mappings.
521	*/
522	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
523	{
524	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
525
526	pgmMapCheckShadowPDEs(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
527	}
528	# endif /* IN_RING0 */
529	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
530	}
531	#endif
532
533	/**
534	* Apply the hypervisor mappings to the active CR3.
535	*
536	* @returns VBox status.
537	* @param pVM The virtual machine.
538	*/
539	VMMDECL(int) PGMMapActivateAll(PVM pVM)
540	{
541	/* @note A log flush (in RC) can cause problems when called from MapCR3 (inconsistent state will trigger assertions). */
542	Log4(("PGMMapActivateAll fixed mappings=%d\n", pVM->pgm.s.fMappingsFixed));
543
544	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
545	/*
546	* Can skip this if mappings are disabled.
547	*/
548	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
549	#else
550	/*
551	* Can skip this if mappings are safely fixed.
552	*/
553	if (pVM->pgm.s.fMappingsFixed)
554	#endif
555	return VINF_SUCCESS;
556
557	#ifdef IN_RING0
558	AssertFailed();
559	return VERR_INTERNAL_ERROR;
560	#else
561	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
562	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
563	# endif
564
565	/*
566	* Iterate mappings.
567	*/
568	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
569	{
570	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
571
572	pgmMapSetShadowPDEs(pVM, pCur, iPDE);
573	}
574	return VINF_SUCCESS;
575	#endif /* IN_RING0 */
576	}
577
578	/**
579	* Remove the hypervisor mappings from the active CR3
580	*
581	* @returns VBox status.
582	* @param pVM The virtual machine.
583	*/
584	VMMDECL(int) PGMMapDeactivateAll(PVM pVM)
585	{
586	Log(("PGMMapDeactivateAll fixed mappings=%d\n", pVM->pgm.s.fMappingsFixed));
587
588	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
589	/*
590	* Can skip this if mappings are disabled.
591	*/
592	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
593	#else
594	/*
595	* Can skip this if mappings are safely fixed.
596	*/
597	if (pVM->pgm.s.fMappingsFixed)
598	#endif
599	return VINF_SUCCESS;
600
601	#ifdef IN_RING0
602	AssertFailed();
603	return VERR_INTERNAL_ERROR;
604	#else
605	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
606	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
607	# endif
608
609	/*
610	* Iterate mappings.
611	*/
612	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
613	{
614	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
615
616	pgmMapClearShadowPDEs(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
617	}
618	return VINF_SUCCESS;
619	#endif /* IN_RING0 */
620	}
621
622
623	/**
624	* Remove the hypervisor mappings from the specified CR3
625	*
626	* @returns VBox status.
627	* @param pVM The virtual machine.
628	* @param pShwPageCR3 CR3 root page
629	*/
630	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
631	{
632	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
633	/*
634	* Can skip this if mappings are disabled.
635	*/
636	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
637	#else
638	/*
639	* Can skip this if mappings are safely fixed.
640	*/
641	if (pVM->pgm.s.fMappingsFixed)
642	#endif
643	return VINF_SUCCESS;
644
645	#ifdef IN_RING0
646	AssertFailed();
647	return VERR_INTERNAL_ERROR;
648	#else
649	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
650	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
651	# endif
652
653	/*
654	* Iterate mappings.
655	*/
656	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
657	{
658	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
659
660	pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE);
661	}
662	return VINF_SUCCESS;
663	#endif /* IN_RING0 */
664	}
665
666	#ifndef IN_RING0
667	/**
668	* Checks guest PD for conflicts with VMM GC mappings.
669	*
670	* @returns true if conflict detected.
671	* @returns false if not.
672	* @param pVM The virtual machine.
673	*/
674	VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
675	{
676	/*
677	* Can skip this if mappings are safely fixed.
678	*/
679	if (pVM->pgm.s.fMappingsFixed)
680	return false;
681
682	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
683	Assert(enmGuestMode <= PGMMODE_PAE_NX);
684
685	/*
686	* Iterate mappings.
687	*/
688	if (enmGuestMode == PGMMODE_32_BIT)
689	{
690	/*
691	* Resolve the page directory.
692	*/
693	PX86PD pPD = pgmGstGet32bitPDPtr(&pVM->pgm.s);
694	Assert(pPD);
695
696	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
697	{
698	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
699	unsigned iPT = pCur->cPTs;
700	while (iPT-- > 0)
701	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
702	&& (pVM->fRawR0Enabled \|\| pPD->a[iPDE + iPT].n.u1User))
703	{
704	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
705
706	#ifdef IN_RING3
707	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
708	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
709	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
710	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
711	#else
712	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
713	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
714	(iPT + iPDE) << X86_PD_SHIFT,
715	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
716	#endif
717	return true;
718	}
719	}
720	}
721	else if ( enmGuestMode == PGMMODE_PAE
722	\|\| enmGuestMode == PGMMODE_PAE_NX)
723	{
724	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
725	{
726	RTGCPTR GCPtr = pCur->GCPtr;
727
728	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
729	while (iPT-- > 0)
730	{
731	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
732
733	if ( Pde.n.u1Present
734	&& (pVM->fRawR0Enabled \|\| Pde.n.u1User))
735	{
736	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
737	#ifdef IN_RING3
738	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
739	" PDE=%016RX64.\n",
740	GCPtr, pCur->pszDesc, Pde.u));
741	#else
742	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
743	" PDE=%016RX64.\n",
744	GCPtr, Pde.u));
745	#endif
746	return true;
747	}
748	GCPtr += (1 << X86_PD_PAE_SHIFT);
749	}
750	}
751	}
752	else
753	AssertFailed();
754
755	return false;
756	}
757
758	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
759	/**
760	* Checks and resolves (ring 3 only) guest conflicts with VMM GC mappings.
761	*
762	* @returns VBox status.
763	* @param pVM The virtual machine.
764	*/
765	VMMDECL(int) PGMMapResolveConflicts(PVM pVM)
766	{
767	/*
768	* Can skip this if mappings are safely fixed.
769	*/
770	if (pVM->pgm.s.fMappingsFixed)
771	return VINF_SUCCESS;
772
773	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
774	Assert(enmGuestMode <= PGMMODE_PAE_NX);
775
776	/*
777	* Iterate mappings.
778	*/
779	if (enmGuestMode == PGMMODE_32_BIT)
780	{
781	/*
782	* Resolve the page directory.
783	*/
784	PX86PD pPD = pgmGstGet32bitPDPtr(&pVM->pgm.s);
785	Assert(pPD);
786
787	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
788	{
789	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
790	unsigned iPT = pCur->cPTs;
791	while (iPT-- > 0)
792	{
793	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
794	&& (pVM->fRawR0Enabled \|\| pPD->a[iPDE + iPT].n.u1User))
795	{
796	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
797
798	#ifdef IN_RING3
799	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
800	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
801	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
802	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
803	int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
804	AssertRCReturn(rc, rc);
805
806	/*
807	* Update pCur.
808	*/
809	pCur = pVM->pgm.s.CTX_SUFF(pMappings);
810	while (pCur && pCur->GCPtr < (iPDE << X86_PD_SHIFT))
811	pCur = pCur->CTX_SUFF(pNext);
812	break;
813	#else
814	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
815	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
816	(iPT + iPDE) << X86_PD_SHIFT,
817	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
818	return VINF_PGM_SYNC_CR3;
819	#endif
820	}
821	}
822	if (!pCur)
823	break;
824	}
825	}
826	else if ( enmGuestMode == PGMMODE_PAE
827	\|\| enmGuestMode == PGMMODE_PAE_NX)
828	{
829	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
830	{
831	RTGCPTR GCPtr = pCur->GCPtr;
832
833	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
834	while (iPT-- > 0)
835	{
836	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
837
838	if ( Pde.n.u1Present
839	&& (pVM->fRawR0Enabled \|\| Pde.n.u1User))
840	{
841	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
842	#ifdef IN_RING3
843	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
844	" PDE=%016RX64.\n",
845	GCPtr, pCur->pszDesc, Pde.u));
846	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, GCPtr);
847	AssertRCReturn(rc, rc);
848
849	/*
850	* Update pCur.
851	*/
852	pCur = pVM->pgm.s.CTX_SUFF(pMappings);
853	while (pCur && pCur->GCPtr < GCPtr)
854	pCur = pCur->CTX_SUFF(pNext);
855	break;
856	#else
857	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
858	" PDE=%016RX64.\n",
859	GCPtr, Pde.u));
860	return VINF_PGM_SYNC_CR3;
861	#endif
862	}
863	GCPtr += (1 << X86_PD_PAE_SHIFT);
864	}
865	if (!pCur)
866	break;
867	}
868	}
869	else
870	AssertFailed();
871
872	return VINF_SUCCESS;
873	}
874	# endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
875
876	#endif /* IN_RING0 */
877

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp@ 17059

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