PGMAllMap.cpp@ 17206

Last change on this file since 17206 was 17195, checked in by vboxsync, 16 years ago
VBOX_WITH_PGMPOOL_PAGING_ONLY: deal with hypervisor mappings in guest pae pds that are not yet present
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1	/* $Id: PGMAllMap.cpp 17195 2009-02-27 11:02:41Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_PGM
26	#include <VBox/pgm.h>
27	#include "PGMInternal.h"
28	#include <VBox/vm.h>
29	#include <iprt/assert.h>
30	#include <iprt/asm.h>
31	#include <VBox/err.h>
32
33
34	/**
35	* Maps a range of physical pages at a given virtual address
36	* in the guest context.
37	*
38	* The GC virtual address range must be within an existing mapping.
39	*
40	* @returns VBox status code.
41	* @param pVM The virtual machine.
42	* @param GCPtr Where to map the page(s). Must be page aligned.
43	* @param HCPhys Start of the range of physical pages. Must be page aligned.
44	* @param cbPages Number of bytes to map. Must be page aligned.
45	* @param fFlags Page flags (X86_PTE_*).
46	*/
47	VMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
48	{
49	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
50
51	/*
52	* Validate input.
53	*/
54	AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
55	AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
56	AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
57
58	/* hypervisor defaults */
59	if (!fFlags)
60	fFlags = X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
61
62	/*
63	* Find the mapping.
64	*/
65	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
66	while (pCur)
67	{
68	if (GCPtr - pCur->GCPtr < pCur->cb)
69	{
70	if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
71	{
72	AssertMsgFailed(("Invalid range!!\n"));
73	return VERR_INVALID_PARAMETER;
74	}
75
76	/*
77	* Setup PTE.
78	*/
79	X86PTEPAE Pte;
80	Pte.u = fFlags \| (HCPhys & X86_PTE_PAE_PG_MASK);
81
82	/*
83	* Update the page tables.
84	*/
85	for (;;)
86	{
87	RTGCUINTPTR off = GCPtr - pCur->GCPtr;
88	const unsigned iPT = off >> X86_PD_SHIFT;
89	const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
90
91	/* 32-bit */
92	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
93
94	/* pae */
95	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512].u = Pte.u;
96
97	/* next */
98	cbPages -= PAGE_SIZE;
99	if (!cbPages)
100	break;
101	GCPtr += PAGE_SIZE;
102	Pte.u += PAGE_SIZE;
103	}
104
105	return VINF_SUCCESS;
106	}
107
108	/* next */
109	pCur = pCur->CTX_SUFF(pNext);
110	}
111
112	AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
113	return VERR_INVALID_PARAMETER;
114	}
115
116
117	/**
118	* Sets (replaces) the page flags for a range of pages in a mapping.
119	*
120	* @returns VBox status.
121	* @param pVM VM handle.
122	* @param GCPtr Virtual address of the first page in the range.
123	* @param cb Size (in bytes) of the range to apply the modification to.
124	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
125	*/
126	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
127	{
128	return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
129	}
130
131
132	/**
133	* Modify page flags for a range of pages in a mapping.
134	*
135	* The existing flags are ANDed with the fMask and ORed with the fFlags.
136	*
137	* @returns VBox status code.
138	* @param pVM VM handle.
139	* @param GCPtr Virtual address of the first page in the range.
140	* @param cb Size (in bytes) of the range to apply the modification to.
141	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
142	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
143	*/
144	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
145	{
146	/*
147	* Validate input.
148	*/
149	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#x\n", fFlags));
150	Assert(cb);
151
152	/*
153	* Align the input.
154	*/
155	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
156	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
157	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
158
159	/*
160	* Find the mapping.
161	*/
162	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
163	while (pCur)
164	{
165	RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
166	if (off < pCur->cb)
167	{
168	AssertMsgReturn(off + cb <= pCur->cb,
169	("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
170	GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
171	VERR_INVALID_PARAMETER);
172
173	/*
174	* Perform the requested operation.
175	*/
176	while (cb > 0)
177	{
178	unsigned iPT = off >> X86_PD_SHIFT;
179	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
180	while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
181	{
182	/* 32-Bit */
183	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask \| X86_PTE_PG_MASK;
184	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u \|= fFlags & ~X86_PTE_PG_MASK;
185
186	/* PAE */
187	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u &= fMask \| X86_PTE_PAE_PG_MASK;
188	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u \|= fFlags & ~X86_PTE_PAE_PG_MASK;
189
190	/* invalidate tls */
191	PGM_INVL_PG((RTGCUINTPTR)pCur->GCPtr + off);
192
193	/* next */
194	iPTE++;
195	cb -= PAGE_SIZE;
196	off += PAGE_SIZE;
197	}
198	}
199
200	return VINF_SUCCESS;
201	}
202	/* next */
203	pCur = pCur->CTX_SUFF(pNext);
204	}
205
206	AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
207	return VERR_INVALID_PARAMETER;
208	}
209
210
211	#ifndef IN_RING0
212	/**
213	* Sets all PDEs involved with the mapping in the shadow page table.
214	*
215	* @param pVM The VM handle.
216	* @param pMap Pointer to the mapping in question.
217	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
218	*/
219	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
220	{
221	Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
222
223	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
224	return;
225
226	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
227	if (!pVM->pgm.s.CTX_SUFF(pShwPageCR3))
228	return; /* too early */
229	#endif
230
231	PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
232	Assert(enmShadowMode <= PGMMODE_PAE_NX);
233
234	/*
235	* Init the page tables and insert them into the page directories.
236	*/
237	unsigned i = pMap->cPTs;
238	iNewPDE += i;
239	while (i-- > 0)
240	{
241	iNewPDE--;
242
243	switch(enmShadowMode)
244	{
245	case PGMMODE_32_BIT:
246	{
247	PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
248	AssertFatal(pShw32BitPd);
249
250	if (pShw32BitPd->a[iNewPDE].n.u1Present)
251	{
252	Assert(!(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING));
253	pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
254	}
255
256	X86PDE Pde;
257	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags */
258	Pde.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT;
259	pShw32BitPd->a[iNewPDE] = Pde;
260	break;
261	}
262
263	case PGMMODE_PAE:
264	case PGMMODE_PAE_NX:
265	{
266	PX86PDPT pShwPdpt;
267	PX86PDPAE pShwPaePd;
268	const unsigned iPdPt = iNewPDE / 256;
269	unsigned iPDE = iNewPDE * 2 % 512;
270
271	pShwPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
272	Assert(pShwPdpt);
273	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPdPt << X86_PDPT_SHIFT));
274	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
275	if (!pShwPaePd)
276	{
277	X86PDPE GstPdpe;
278
279	if (PGMGetGuestMode(pVM) < PGMMODE_PAE)
280	{
281	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
282	GstPdpe.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
283	}
284	else
285	{
286	PX86PDPE pGstPdpe;
287	pGstPdpe = pgmGstGetPaePDPEPtr(&pVM->pgm.s, (iPdPt << X86_PDPT_SHIFT));
288	if (pGstPdpe)
289	GstPdpe = *pGstPdpe;
290	else
291	GstPdpe.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
292	}
293	int rc = pgmShwSyncPaePDPtr(pVM, (iPdPt << X86_PDPT_SHIFT), &GstPdpe, &pShwPaePd);
294	AssertFatal(RT_SUCCESS(rc));
295	if (rc != VINF_SUCCESS)
296	{
297	rc = pgmShwSyncPaePDPtr(pVM, (iPdPt << X86_PDPT_SHIFT), &GstPdpe, &pShwPaePd);
298	AssertFatalMsg(rc == VINF_SUCCESS, ("rc = %Rrc\n", rc));
299	}
300	}
301	#endif
302	AssertFatal(pShwPaePd);
303
304	PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPageByHCPhys(pVM, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
305	AssertFatal(pPoolPagePd);
306
307	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
308	if (!pgmPoolIsPageLocked(&pVM->pgm.s, pPoolPagePd))
309	{
310	/* Mark the page as locked; disallow flushing. */
311	pgmPoolLockPage(pVM->pgm.s.CTX_SUFF(pPool), pPoolPagePd);
312	}
313	#endif
314	if (pShwPaePd->a[iPDE].n.u1Present)
315	{
316	Assert(!(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING));
317	pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iNewPDE);
318	}
319
320	X86PDEPAE PdePae0;
321	PdePae0.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0;
322	pShwPaePd->a[iPDE] = PdePae0;
323
324	/* 2nd 2 MB PDE of the 4 MB region */
325	iPDE++;
326	AssertFatal(iPDE < 512);
327
328	if (pShwPaePd->a[iPDE].n.u1Present)
329	{
330	Assert(!(pShwPaePd->a[iPDE].u & PGM_PDFLAGS_MAPPING));
331	pgmPoolFree(pVM, pShwPaePd->a[iPDE].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iNewPDE);
332	}
333
334	X86PDEPAE PdePae1;
335	PdePae1.u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1;
336	pShwPaePd->a[iPDE] = PdePae1;
337
338	/* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode) */
339	pShwPdpt->a[iPdPt].u \|= PGM_PLXFLAGS_MAPPING;
340	break;
341	}
342
343	default:
344	AssertFailed();
345	break;
346	}
347	}
348	}
349
350	/**
351	* Clears all PDEs involved with the mapping in the shadow page table.
352	*
353	* @param pVM The VM handle.
354	* @param pShwPageCR3 CR3 root page
355	* @param pMap Pointer to the mapping in question.
356	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
357	*/
358	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE)
359	{
360	Log(("pgmMapClearShadowPDEs old pde %x (mappings enabled %d)\n", iOldPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
361
362	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
363	return;
364
365	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
366	Assert(pShwPageCR3);
367	#endif
368
369	unsigned i = pMap->cPTs;
370	PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
371
372	iOldPDE += i;
373	while (i-- > 0)
374	{
375	iOldPDE--;
376
377	switch(enmShadowMode)
378	{
379	case PGMMODE_32_BIT:
380	{
381	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
382	PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
383	#else
384	PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
385	#endif
386	AssertFatal(pShw32BitPd);
387
388	pShw32BitPd->a[iOldPDE].u = 0;
389	break;
390	}
391
392	case PGMMODE_PAE:
393	case PGMMODE_PAE_NX:
394	{
395	PX86PDPT pShwPdpt = NULL;
396	PX86PDPAE pShwPaePd = NULL;
397
398	const unsigned iPD = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
399	unsigned iPDE = iOldPDE * 2 % 512;
400	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
401	pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
402	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, pShwPdpt, (iPD << X86_PDPT_SHIFT));
403	#else
404	pShwPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
405	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPD << X86_PDPT_SHIFT));
406	#endif
407	AssertFatal(pShwPaePd);
408
409	pShwPaePd->a[iPDE].u = 0;
410
411	iPDE++;
412	AssertFatal(iPDE < 512);
413
414	pShwPaePd->a[iPDE].u = 0;
415	/* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode) */
416	pShwPdpt->a[iPD].u &= ~PGM_PLXFLAGS_MAPPING;
417
418	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
419	PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPageByHCPhys(pVM, pShwPdpt->a[iPD].u & X86_PDPE_PG_MASK);
420	AssertFatal(pPoolPagePd);
421
422	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPoolPagePd))
423	{
424	/* Mark the page as unlocked; allow flushing again. */
425	pgmPoolUnlockPage(pVM->pgm.s.CTX_SUFF(pPool), pPoolPagePd);
426	}
427	#endif
428
429	break;
430	}
431
432	default:
433	AssertFailed();
434	break;
435	}
436	}
437	}
438	#endif /* !IN_RING0 */
439
440	#if defined(VBOX_STRICT) && !defined(IN_RING0)
441	/**
442	* Clears all PDEs involved with the mapping in the shadow page table.
443	*
444	* @param pVM The VM handle.
445	* @param pShwPageCR3 CR3 root page
446	* @param pMap Pointer to the mapping in question.
447	* @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
448	*/
449	void pgmMapCheckShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
450	{
451	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
452	Assert(pShwPageCR3);
453	#endif
454
455	unsigned i = pMap->cPTs;
456	PGMMODE enmShadowMode = PGMGetShadowMode(pVM);
457
458	iPDE += i;
459	while (i-- > 0)
460	{
461	iPDE--;
462
463	switch(enmShadowMode)
464	{
465	case PGMMODE_32_BIT:
466	{
467	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
468	PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
469	#else
470	PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVM->pgm.s);
471	#endif
472	AssertFatal(pShw32BitPd);
473
474	AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT),
475	("Expected %x vs %x\n", pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT)));
476	break;
477	}
478
479	case PGMMODE_PAE:
480	case PGMMODE_PAE_NX:
481	{
482	PX86PDPT pPdpt = NULL;
483	PX86PDPAE pShwPaePd = NULL;
484
485	const unsigned iPD = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
486	unsigned iPaePDE = iPDE * 2 % 512;
487	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
488	pPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
489	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, pPdpt, (iPD << X86_PDPT_SHIFT));
490	#else
491	pPdpt = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
492	pShwPaePd = pgmShwGetPaePDPtr(&pVM->pgm.s, (iPD << X86_PDPT_SHIFT));
493	#endif
494	AssertFatal(pShwPaePd);
495
496	AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0),
497	("Expected %RX64 vs %RX64\n", pShwPaePd->a[iPDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPaePT0)));
498
499	iPaePDE++;
500	AssertFatal(iPaePDE < 512);
501
502	AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1),
503	("Expected %RX64 vs %RX64\n", pShwPaePd->a[iPDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPaePT1)));
504
505	Assert(pPdpt->a[iPD].u & PGM_PLXFLAGS_MAPPING);
506	break;
507	}
508
509	default:
510	AssertFailed();
511	break;
512	}
513	}
514	}
515
516	/**
517	* Check the hypervisor mappings in the active CR3.
518	*
519	* @param pVM The virtual machine.
520	*/
521	VMMDECL(void) PGMMapCheck(PVM pVM)
522	{
523	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
524	/*
525	* Can skip this if mappings are disabled.
526	*/
527	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
528	return;
529
530	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
531	Assert(pVM->pgm.s.CTX_SUFF(pShwPageCR3));
532	# endif
533
534	/*
535	* Iterate mappings.
536	*/
537	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
538	{
539	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
540
541	pgmMapCheckShadowPDEs(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
542	}
543	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
544	}
545	#endif /* defined(VBOX_STRICT) && !defined(IN_RING0) */
546
547	#ifndef IN_RING0
548	/**
549	* Apply the hypervisor mappings to the active CR3.
550	*
551	* @returns VBox status.
552	* @param pVM The virtual machine.
553	* @param pShwPageCR3 CR3 root page
554	*/
555	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
556	{
557	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
558	/*
559	* Can skip this if mappings are disabled.
560	*/
561	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
562	#else
563	/*
564	* Can skip this if mappings are safely fixed.
565	*/
566	if (pVM->pgm.s.fMappingsFixed)
567	#endif
568	return VINF_SUCCESS;
569
570	/* @note A log flush (in RC) can cause problems when called from MapCR3 (inconsistent state will trigger assertions). */
571	Log4(("PGMMapActivateAll fixed mappings=%d\n", pVM->pgm.s.fMappingsFixed));
572
573	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
574	Assert(pShwPageCR3 && pShwPageCR3 == pVM->pgm.s.CTX_SUFF(pShwPageCR3));
575	# endif
576
577	/*
578	* Iterate mappings.
579	*/
580	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
581	{
582	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
583
584	pgmMapSetShadowPDEs(pVM, pCur, iPDE);
585	}
586	return VINF_SUCCESS;
587	}
588
589
590	/**
591	* Remove the hypervisor mappings from the specified CR3
592	*
593	* @returns VBox status.
594	* @param pVM The virtual machine.
595	* @param pShwPageCR3 CR3 root page
596	*/
597	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
598	{
599	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
600	/*
601	* Can skip this if mappings are disabled.
602	*/
603	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
604	#else
605	/*
606	* Can skip this if mappings are safely fixed.
607	*/
608	if (pVM->pgm.s.fMappingsFixed)
609	#endif
610	return VINF_SUCCESS;
611
612	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
613	Assert(pShwPageCR3);
614	# endif
615
616	/*
617	* Iterate mappings.
618	*/
619	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
620	{
621	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
622
623	pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE);
624	}
625	return VINF_SUCCESS;
626	}
627
628	/**
629	* Checks guest PD for conflicts with VMM GC mappings.
630	*
631	* @returns true if conflict detected.
632	* @returns false if not.
633	* @param pVM The virtual machine.
634	*/
635	VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
636	{
637	/*
638	* Can skip this if mappings are safely fixed.
639	*/
640	if (pVM->pgm.s.fMappingsFixed)
641	return false;
642
643	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
644	Assert(enmGuestMode <= PGMMODE_PAE_NX);
645
646	/*
647	* Iterate mappings.
648	*/
649	if (enmGuestMode == PGMMODE_32_BIT)
650	{
651	/*
652	* Resolve the page directory.
653	*/
654	PX86PD pPD = pgmGstGet32bitPDPtr(&pVM->pgm.s);
655	Assert(pPD);
656
657	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
658	{
659	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
660	unsigned iPT = pCur->cPTs;
661	while (iPT-- > 0)
662	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
663	&& (pVM->fRawR0Enabled \|\| pPD->a[iPDE + iPT].n.u1User))
664	{
665	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
666
667	#ifdef IN_RING3
668	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
669	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
670	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
671	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
672	#else
673	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
674	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
675	(iPT + iPDE) << X86_PD_SHIFT,
676	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
677	#endif
678	return true;
679	}
680	}
681	}
682	else if ( enmGuestMode == PGMMODE_PAE
683	\|\| enmGuestMode == PGMMODE_PAE_NX)
684	{
685	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
686	{
687	RTGCPTR GCPtr = pCur->GCPtr;
688
689	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
690	while (iPT-- > 0)
691	{
692	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
693
694	if ( Pde.n.u1Present
695	&& (pVM->fRawR0Enabled \|\| Pde.n.u1User))
696	{
697	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
698	#ifdef IN_RING3
699	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
700	" PDE=%016RX64.\n",
701	GCPtr, pCur->pszDesc, Pde.u));
702	#else
703	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
704	" PDE=%016RX64.\n",
705	GCPtr, Pde.u));
706	#endif
707	return true;
708	}
709	GCPtr += (1 << X86_PD_PAE_SHIFT);
710	}
711	}
712	}
713	else
714	AssertFailed();
715
716	return false;
717	}
718
719	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
720	/**
721	* Checks and resolves (ring 3 only) guest conflicts with VMM GC mappings.
722	*
723	* @returns VBox status.
724	* @param pVM The virtual machine.
725	*/
726	VMMDECL(int) PGMMapResolveConflicts(PVM pVM)
727	{
728	/*
729	* Can skip this if mappings are safely fixed.
730	*/
731	if (pVM->pgm.s.fMappingsFixed)
732	return VINF_SUCCESS;
733
734	PGMMODE const enmGuestMode = PGMGetGuestMode(pVM);
735	Assert(enmGuestMode <= PGMMODE_PAE_NX);
736
737	/*
738	* Iterate mappings.
739	*/
740	if (enmGuestMode == PGMMODE_32_BIT)
741	{
742	/*
743	* Resolve the page directory.
744	*/
745	PX86PD pPD = pgmGstGet32bitPDPtr(&pVM->pgm.s);
746	Assert(pPD);
747
748	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
749	{
750	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
751	unsigned iPT = pCur->cPTs;
752	while (iPT-- > 0)
753	{
754	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
755	&& (pVM->fRawR0Enabled \|\| pPD->a[iPDE + iPT].n.u1User))
756	{
757	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
758
759	#ifdef IN_RING3
760	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
761	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
762	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
763	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
764	int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
765	AssertRCReturn(rc, rc);
766
767	/*
768	* Update pCur.
769	*/
770	pCur = pVM->pgm.s.CTX_SUFF(pMappings);
771	while (pCur && pCur->GCPtr < (iPDE << X86_PD_SHIFT))
772	pCur = pCur->CTX_SUFF(pNext);
773	break;
774	#else
775	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
776	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
777	(iPT + iPDE) << X86_PD_SHIFT,
778	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
779	return VINF_PGM_SYNC_CR3;
780	#endif
781	}
782	}
783	if (!pCur)
784	break;
785	}
786	}
787	else if ( enmGuestMode == PGMMODE_PAE
788	\|\| enmGuestMode == PGMMODE_PAE_NX)
789	{
790	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
791	{
792	RTGCPTR GCPtr = pCur->GCPtr;
793
794	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
795	while (iPT-- > 0)
796	{
797	X86PDEPAE Pde = pgmGstGetPaePDE(&pVM->pgm.s, GCPtr);
798
799	if ( Pde.n.u1Present
800	&& (pVM->fRawR0Enabled \|\| Pde.n.u1User))
801	{
802	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
803	#ifdef IN_RING3
804	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
805	" PDE=%016RX64.\n",
806	GCPtr, pCur->pszDesc, Pde.u));
807	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, GCPtr);
808	AssertRCReturn(rc, rc);
809
810	/*
811	* Update pCur.
812	*/
813	pCur = pVM->pgm.s.CTX_SUFF(pMappings);
814	while (pCur && pCur->GCPtr < GCPtr)
815	pCur = pCur->CTX_SUFF(pNext);
816	break;
817	#else
818	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
819	" PDE=%016RX64.\n",
820	GCPtr, Pde.u));
821	return VINF_PGM_SYNC_CR3;
822	#endif
823	}
824	GCPtr += (1 << X86_PD_PAE_SHIFT);
825	}
826	if (!pCur)
827	break;
828	}
829	}
830	else
831	AssertFailed();
832
833	return VINF_SUCCESS;
834	}
835	# endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
836
837	#endif /* IN_RING0 */
838

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp@ 17206

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