VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp@ 21773

Last change on this file since 21773 was 20865, checked in by vboxsync, 15 years ago

PGMAllMap: avoid lock owner assertions in PGMMapCheck.

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1/* $Id: PGMAllMap.cpp 20865 2009-06-23 19:27:16Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_PGM
26#include <VBox/pgm.h>
27#include "PGMInternal.h"
28#include <VBox/vm.h>
29#include <iprt/assert.h>
30#include <iprt/asm.h>
31#include <VBox/err.h>
32
33
34/**
35 * Maps a range of physical pages at a given virtual address
36 * in the guest context.
37 *
38 * The GC virtual address range must be within an existing mapping.
39 *
40 * @returns VBox status code.
41 * @param pVM The virtual machine.
42 * @param GCPtr Where to map the page(s). Must be page aligned.
43 * @param HCPhys Start of the range of physical pages. Must be page aligned.
44 * @param cbPages Number of bytes to map. Must be page aligned.
45 * @param fFlags Page flags (X86_PTE_*).
46 */
47VMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
48{
49 AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
50
51 /*
52 * Validate input.
53 */
54 AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
55 AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
56 AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
57
58 /* hypervisor defaults */
59 if (!fFlags)
60 fFlags = X86_PTE_P | X86_PTE_A | X86_PTE_D;
61
62 /*
63 * Find the mapping.
64 */
65 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
66 while (pCur)
67 {
68 if (GCPtr - pCur->GCPtr < pCur->cb)
69 {
70 if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
71 {
72 AssertMsgFailed(("Invalid range!!\n"));
73 return VERR_INVALID_PARAMETER;
74 }
75
76 /*
77 * Setup PTE.
78 */
79 X86PTEPAE Pte;
80 Pte.u = fFlags | (HCPhys & X86_PTE_PAE_PG_MASK);
81
82 /*
83 * Update the page tables.
84 */
85 for (;;)
86 {
87 RTGCUINTPTR off = GCPtr - pCur->GCPtr;
88 const unsigned iPT = off >> X86_PD_SHIFT;
89 const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
90
91 /* 32-bit */
92 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
93
94 /* pae */
95 pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512].u = Pte.u;
96
97 /* next */
98 cbPages -= PAGE_SIZE;
99 if (!cbPages)
100 break;
101 GCPtr += PAGE_SIZE;
102 Pte.u += PAGE_SIZE;
103 }
104
105 return VINF_SUCCESS;
106 }
107
108 /* next */
109 pCur = pCur->CTX_SUFF(pNext);
110 }
111
112 AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
113 return VERR_INVALID_PARAMETER;
114}
115
116
117/**
118 * Sets (replaces) the page flags for a range of pages in a mapping.
119 *
120 * @returns VBox status.
121 * @param pVM VM handle.
122 * @param GCPtr Virtual address of the first page in the range.
123 * @param cb Size (in bytes) of the range to apply the modification to.
124 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
125 */
126VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
127{
128 return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
129}
130
131
132/**
133 * Modify page flags for a range of pages in a mapping.
134 *
135 * The existing flags are ANDed with the fMask and ORed with the fFlags.
136 *
137 * @returns VBox status code.
138 * @param pVM VM handle.
139 * @param GCPtr Virtual address of the first page in the range.
140 * @param cb Size (in bytes) of the range to apply the modification to.
141 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
142 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
143 */
144VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
145{
146 /*
147 * Validate input.
148 */
149 AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#x\n", fFlags));
150 Assert(cb);
151
152 /*
153 * Align the input.
154 */
155 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
156 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
157 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
158
159 /*
160 * Find the mapping.
161 */
162 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
163 while (pCur)
164 {
165 RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
166 if (off < pCur->cb)
167 {
168 AssertMsgReturn(off + cb <= pCur->cb,
169 ("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
170 GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
171 VERR_INVALID_PARAMETER);
172
173 /*
174 * Perform the requested operation.
175 */
176 while (cb > 0)
177 {
178 unsigned iPT = off >> X86_PD_SHIFT;
179 unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
180 while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
181 {
182 /* 32-Bit */
183 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask | X86_PTE_PG_MASK;
184 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u |= fFlags & ~X86_PTE_PG_MASK;
185
186 /* PAE */
187 pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u &= fMask | X86_PTE_PAE_PG_MASK;
188 pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u |= fFlags & ~X86_PTE_PAE_PG_MASK;
189
190 /* invalidate tls */
191 PGM_INVL_PG(VMMGetCpu(pVM), (RTGCUINTPTR)pCur->GCPtr + off);
192
193 /* next */
194 iPTE++;
195 cb -= PAGE_SIZE;
196 off += PAGE_SIZE;
197 }
198 }
199
200 return VINF_SUCCESS;
201 }
202 /* next */
203 pCur = pCur->CTX_SUFF(pNext);
204 }
205
206 AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
207 return VERR_INVALID_PARAMETER;
208}
209
210
211#ifndef IN_RING0
212/**
213 * Sets all PDEs involved with the mapping in the shadow page table.
214 *
215 * @param pVM The VM handle.
216 * @param pMap Pointer to the mapping in question.
217 * @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
218 */
219void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
220{
221 Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
222
223 if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s)
224 || pVM->cCPUs > 1)
225 return;
226
227 /* This only applies to raw mode where we only support 1 VCPU. */
228 PVMCPU pVCpu = VMMGetCpu0(pVM);
229 if (!pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
230 return; /* too early */
231
232 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
233 Assert(enmShadowMode <= PGMMODE_PAE_NX);
234
235 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
236
237 /*
238 * Insert the page tables into the shadow page directories.
239 */
240 unsigned i = pMap->cPTs;
241 iNewPDE += i;
242 while (i-- > 0)
243 {
244 iNewPDE--;
245
246 switch (enmShadowMode)
247 {
248 case PGMMODE_32_BIT:
249 {
250 PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
251 AssertFatal(pShw32BitPd);
252#ifdef IN_RC /* Lock mapping to prevent it from being reused during pgmPoolFree. */
253 PGMDynLockHCPage(pVM, (uint8_t *)pShw32BitPd);
254#endif
255 /* Free any previous user, unless it's us. */
256 Assert( (pShw32BitPd->a[iNewPDE].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
257 || (pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK) == pMap->aPTs[i].HCPhysPT);
258 if ( pShw32BitPd->a[iNewPDE].n.u1Present
259 && !(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING))
260 pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
261
262 /* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags. */
263 pShw32BitPd->a[iNewPDE].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
264 | (uint32_t)pMap->aPTs[i].HCPhysPT;
265#ifdef IN_RC
266 /* Unlock dynamic mappings again. */
267 PGMDynUnlockHCPage(pVM, (uint8_t *)pShw32BitPd);
268#endif
269 break;
270 }
271
272 case PGMMODE_PAE:
273 case PGMMODE_PAE_NX:
274 {
275 const uint32_t iPdPt = iNewPDE / 256;
276 unsigned iPaePde = iNewPDE * 2 % 512;
277 PX86PDPT pShwPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
278 Assert(pShwPdpt);
279#ifdef IN_RC /* Lock mapping to prevent it from being reused during pgmShwSyncPaePDPtr. */
280 PGMDynLockHCPage(pVM, (uint8_t *)pShwPdpt);
281#endif
282
283 /*
284 * Get the shadow PD.
285 * If no PD, sync it (PAE guest) or fake (not present or 32-bit guest).
286 * Note! The RW, US and A bits are reserved for PAE PDPTEs. Setting the
287 * accessed bit causes invalid VT-x guest state errors.
288 */
289 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(&pVCpu->pgm.s, iPdPt << X86_PDPT_SHIFT);
290 if (!pShwPaePd)
291 {
292 X86PDPE GstPdpe;
293 if (PGMGetGuestMode(pVCpu) < PGMMODE_PAE)
294 GstPdpe.u = X86_PDPE_P;
295 else
296 {
297 PX86PDPE pGstPdpe = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, iPdPt << X86_PDPT_SHIFT);
298 if (pGstPdpe)
299 GstPdpe = *pGstPdpe;
300 else
301 GstPdpe.u = X86_PDPE_P;
302 }
303 int rc = pgmShwSyncPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT, &GstPdpe, &pShwPaePd);
304 AssertFatalRC(rc);
305 }
306 Assert(pShwPaePd);
307#ifdef IN_RC /* Lock mapping to prevent it from being reused during pgmPoolFree. */
308 PGMDynLockHCPage(pVM, (uint8_t *)pShwPaePd);
309#endif
310
311 /*
312 * Mark the page as locked; disallow flushing.
313 */
314 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
315 AssertFatal(pPoolPagePd);
316 if (!pgmPoolIsPageLocked(&pVM->pgm.s, pPoolPagePd))
317 pgmPoolLockPage(pPool, pPoolPagePd);
318#ifdef VBOX_STRICT
319 else if (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING)
320 {
321 Assert(PGMGetGuestMode(pVCpu) >= PGMMODE_PAE); /** @todo We may hit this during reset, will fix later. */
322 AssertFatalMsg( (pShwPaePd->a[iPaePde].u & X86_PDE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0
323 || !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
324 ("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PG_MASK, pMap->aPTs[i].HCPhysPaePT0));
325 Assert(pShwPaePd->a[iPaePde+1].u & PGM_PDFLAGS_MAPPING);
326 AssertFatalMsg( (pShwPaePd->a[iPaePde+1].u & X86_PDE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1
327 || !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
328 ("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PG_MASK, pMap->aPTs[i].HCPhysPaePT1));
329 }
330#endif
331
332 /*
333 * Insert our first PT, freeing anything we might be replacing unless it's a mapping (i.e. us).
334 */
335 Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
336 || (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0);
337 if ( pShwPaePd->a[iPaePde].n.u1Present
338 && !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
339 {
340 Assert(!(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
341 pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iPaePde);
342 }
343 pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
344 | pMap->aPTs[i].HCPhysPaePT0;
345
346 /* 2nd 2 MB PDE of the 4 MB region, same as above. */
347 iPaePde++;
348 AssertFatal(iPaePde < 512);
349 Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
350 || (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1);
351 if ( pShwPaePd->a[iPaePde].n.u1Present
352 && !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
353 pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iPaePde);
354 pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
355 | pMap->aPTs[i].HCPhysPaePT1;
356
357 /*
358 * Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode)
359 */
360 pShwPdpt->a[iPdPt].u |= PGM_PLXFLAGS_MAPPING;
361
362#ifdef IN_RC
363 /* Unlock dynamic mappings again. */
364 PGMDynUnlockHCPage(pVM, (uint8_t *)pShwPaePd);
365 PGMDynUnlockHCPage(pVM, (uint8_t *)pShwPdpt);
366#endif
367 break;
368 }
369
370 default:
371 AssertFailed();
372 break;
373 }
374 }
375}
376
377
378/**
379 * Clears all PDEs involved with the mapping in the shadow page table.
380 *
381 * @param pVM The VM handle.
382 * @param pShwPageCR3 CR3 root page
383 * @param pMap Pointer to the mapping in question.
384 * @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
385 * @param fDeactivateCR3 Set if it's pgmMapDeactivateCR3 calling.
386 */
387void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3)
388{
389 Log(("pgmMapClearShadowPDEs: old pde %x (cPTs=%x) (mappings enabled %d) fDeactivateCR3=%RTbool\n", iOldPDE, pMap->cPTs, pgmMapAreMappingsEnabled(&pVM->pgm.s), fDeactivateCR3));
390
391 if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s)
392 || pVM->cCPUs > 1)
393 return;
394
395 Assert(pShwPageCR3);
396
397 /* This only applies to raw mode where we only support 1 VCPU. */
398 PVMCPU pVCpu = VMMGetCpu0(pVM);
399# ifdef IN_RC
400 Assert(pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
401# endif
402
403 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
404
405 PX86PDPT pCurrentShwPdpt = NULL;
406 if ( PGMGetGuestMode(pVCpu) >= PGMMODE_PAE
407 && pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
408 {
409 pCurrentShwPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
410#ifdef IN_RC /* Lock mapping to prevent it from being reused (currently not possible). */
411 if (pCurrentShwPdpt)
412 PGMDynLockHCPage(pVM, (uint8_t *)pCurrentShwPdpt);
413#endif
414 }
415
416 unsigned i = pMap->cPTs;
417 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
418
419 iOldPDE += i;
420 while (i-- > 0)
421 {
422 iOldPDE--;
423
424 switch(enmShadowMode)
425 {
426 case PGMMODE_32_BIT:
427 {
428 PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
429 AssertFatal(pShw32BitPd);
430
431 Assert(!pShw32BitPd->a[iOldPDE].n.u1Present || (pShw32BitPd->a[iOldPDE].u & PGM_PDFLAGS_MAPPING));
432 pShw32BitPd->a[iOldPDE].u = 0;
433 break;
434 }
435
436 case PGMMODE_PAE:
437 case PGMMODE_PAE_NX:
438 {
439 const unsigned iPdpt = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
440 unsigned iPaePde = iOldPDE * 2 % 512;
441 PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
442 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(&pVCpu->pgm.s, pShwPdpt, (iPdpt << X86_PDPT_SHIFT));
443
444 /*
445 * Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode)
446 */
447 if (fDeactivateCR3)
448 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
449 else if (pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING)
450 {
451 /* See if there are any other mappings here. This is suboptimal code. */
452 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
453 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
454 if ( pCur != pMap
455 && ( (pCur->GCPtr >> X86_PDPT_SHIFT) == iPdpt
456 || (pCur->GCPtrLast >> X86_PDPT_SHIFT) == iPdpt))
457 {
458 pShwPdpt->a[iPdpt].u |= PGM_PLXFLAGS_MAPPING;
459 break;
460 }
461 }
462
463 /*
464 * If the page directory of the old CR3 is reused in the new one, then don't
465 * clear the hypervisor mappings.
466 */
467 if ( pCurrentShwPdpt
468 && (pCurrentShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) == (pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) )
469 {
470 LogFlow(("pgmMapClearShadowPDEs: Pdpe %d reused -> don't clear hypervisor mappings!\n", iPdpt));
471 break;
472 }
473
474 /*
475 * Clear the mappings in the PD.
476 */
477 AssertFatal(pShwPaePd);
478 Assert(!pShwPaePd->a[iPaePde].n.u1Present || (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
479 pShwPaePd->a[iPaePde].u = 0;
480
481 iPaePde++;
482 AssertFatal(iPaePde < 512);
483 Assert(!pShwPaePd->a[iPaePde].n.u1Present || (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
484 pShwPaePd->a[iPaePde].u = 0;
485
486 /*
487 * Unlock the shadow pool PD page if the PDPTE no longer holds any mappings.
488 */
489 if ( fDeactivateCR3
490 || !(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
491 {
492 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
493 AssertFatal(pPoolPagePd);
494 if (pgmPoolIsPageLocked(&pVM->pgm.s, pPoolPagePd))
495 pgmPoolUnlockPage(pPool, pPoolPagePd);
496 }
497 break;
498 }
499
500 default:
501 AssertFailed();
502 break;
503 }
504 }
505#ifdef IN_RC
506 /* Unlock dynamic mappings again. */
507 if (pCurrentShwPdpt)
508 PGMDynUnlockHCPage(pVM, (uint8_t *)pCurrentShwPdpt);
509#endif
510}
511#endif /* !IN_RING0 */
512
513#if defined(VBOX_STRICT) && !defined(IN_RING0)
514/**
515 * Clears all PDEs involved with the mapping in the shadow page table.
516 *
517 * @param pVM The VM handle.
518 * @param pVCpu The VMCPU handle.
519 * @param pShwPageCR3 CR3 root page
520 * @param pMap Pointer to the mapping in question.
521 * @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
522 */
523static void pgmMapCheckShadowPDEs(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
524{
525 Assert(pShwPageCR3);
526
527 uint32_t i = pMap->cPTs;
528 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
529 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
530
531 iPDE += i;
532 while (i-- > 0)
533 {
534 iPDE--;
535
536 switch (enmShadowMode)
537 {
538 case PGMMODE_32_BIT:
539 {
540 PCX86PD pShw32BitPd = (PCX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
541 AssertFatal(pShw32BitPd);
542
543 AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
544 ("Expected %x vs %x; iPDE=%#x %RGv %s\n",
545 pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
546 iPDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
547 break;
548 }
549
550 case PGMMODE_PAE:
551 case PGMMODE_PAE_NX:
552 {
553 const unsigned iPdpt = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
554 unsigned iPaePDE = iPDE * 2 % 512;
555 PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
556 PCX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(&pVCpu->pgm.s, pShwPdpt, iPdpt << X86_PDPT_SHIFT);
557 AssertFatal(pShwPaePd);
558
559 AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
560 ("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
561 pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
562 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
563
564 iPaePDE++;
565 AssertFatal(iPaePDE < 512);
566
567 AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
568 ("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
569 pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
570 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
571
572 AssertMsg(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING,
573 ("%RX64; iPdpt=%#x iPDE=%#x iPaePDE=%#x %RGv %s\n",
574 pShwPdpt->a[iPdpt].u,
575 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
576
577 PCPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
578 AssertFatal(pPoolPagePd);
579 AssertMsg(pPoolPagePd->cLocked, (".idx=%d .type=%d\n", pPoolPagePd->idx, pPoolPagePd->enmKind));
580 break;
581 }
582
583 default:
584 AssertFailed();
585 break;
586 }
587 }
588}
589
590
591/**
592 * Check the hypervisor mappings in the active CR3.
593 *
594 * @param pVM The virtual machine.
595 */
596VMMDECL(void) PGMMapCheck(PVM pVM)
597{
598 /*
599 * Can skip this if mappings are disabled.
600 */
601 if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
602 return;
603
604 Assert(pVM->cCPUs == 1);
605
606 /* This only applies to raw mode where we only support 1 VCPU. */
607 PVMCPU pVCpu = VMMGetCpu0(pVM);
608 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
609
610 /*
611 * Iterate mappings.
612 */
613 pgmLock(pVM); /* to avoid assertions */
614 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
615 {
616 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
617 pgmMapCheckShadowPDEs(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
618 }
619 pgmUnlock(pVM);
620}
621#endif /* defined(VBOX_STRICT) && !defined(IN_RING0) */
622
623#ifndef IN_RING0
624
625/**
626 * Apply the hypervisor mappings to the active CR3.
627 *
628 * @returns VBox status.
629 * @param pVM The virtual machine.
630 * @param pShwPageCR3 CR3 root page
631 */
632int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
633{
634 /*
635 * Can skip this if mappings are disabled.
636 */
637 if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s)
638 || pVM->cCPUs > 1)
639 return VINF_SUCCESS;
640
641 /* Note. A log flush (in RC) can cause problems when called from MapCR3 (inconsistent state will trigger assertions). */
642 Log4(("pgmMapActivateCR3: fixed mappings=%d idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
643
644#ifdef VBOX_STRICT
645 PVMCPU pVCpu = VMMGetCpu0(pVM);
646 Assert(pShwPageCR3 && pShwPageCR3 == pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
647#endif
648
649 /*
650 * Iterate mappings.
651 */
652 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
653 {
654 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
655 pgmMapSetShadowPDEs(pVM, pCur, iPDE);
656 }
657 return VINF_SUCCESS;
658}
659
660
661/**
662 * Remove the hypervisor mappings from the specified CR3
663 *
664 * @returns VBox status.
665 * @param pVM The virtual machine.
666 * @param pShwPageCR3 CR3 root page
667 */
668int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
669{
670 /*
671 * Can skip this if mappings are disabled.
672 */
673 if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s)
674 || pVM->cCPUs > 1)
675 return VINF_SUCCESS;
676
677 Assert(pShwPageCR3);
678 Log4(("pgmMapDeactivateCR3: fixed mappings=%d idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
679
680 /*
681 * Iterate mappings.
682 */
683 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
684 {
685 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
686 pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE, true /*fDeactivateCR3*/);
687 }
688 return VINF_SUCCESS;
689}
690
691
692/**
693 * Checks guest PD for conflicts with VMM GC mappings.
694 *
695 * @returns true if conflict detected.
696 * @returns false if not.
697 * @param pVM The virtual machine.
698 */
699VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
700{
701 /*
702 * Can skip this if mappings are safely fixed.
703 */
704 if (pVM->pgm.s.fMappingsFixed)
705 return false;
706
707 Assert(pVM->cCPUs == 1);
708
709 /* This only applies to raw mode where we only support 1 VCPU. */
710 PVMCPU pVCpu = &pVM->aCpus[0];
711
712 PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
713 Assert(enmGuestMode <= PGMMODE_PAE_NX);
714
715 /*
716 * Iterate mappings.
717 */
718 if (enmGuestMode == PGMMODE_32_BIT)
719 {
720 /*
721 * Resolve the page directory.
722 */
723 PX86PD pPD = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
724 Assert(pPD);
725
726 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
727 {
728 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
729 unsigned iPT = pCur->cPTs;
730 while (iPT-- > 0)
731 if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
732 && (pVM->fRawR0Enabled || pPD->a[iPDE + iPT].n.u1User))
733 {
734 STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
735
736#ifdef IN_RING3
737 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
738 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
739 (iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
740 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
741#else
742 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
743 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
744 (iPT + iPDE) << X86_PD_SHIFT,
745 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
746#endif
747 return true;
748 }
749 }
750 }
751 else if ( enmGuestMode == PGMMODE_PAE
752 || enmGuestMode == PGMMODE_PAE_NX)
753 {
754 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
755 {
756 RTGCPTR GCPtr = pCur->GCPtr;
757
758 unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
759 while (iPT-- > 0)
760 {
761 X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
762
763 if ( Pde.n.u1Present
764 && (pVM->fRawR0Enabled || Pde.n.u1User))
765 {
766 STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
767#ifdef IN_RING3
768 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
769 " PDE=%016RX64.\n",
770 GCPtr, pCur->pszDesc, Pde.u));
771#else
772 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
773 " PDE=%016RX64.\n",
774 GCPtr, Pde.u));
775#endif
776 return true;
777 }
778 GCPtr += (1 << X86_PD_PAE_SHIFT);
779 }
780 }
781 }
782 else
783 AssertFailed();
784
785 return false;
786}
787
788
789/**
790 * Checks and resolves (ring 3 only) guest conflicts with VMM GC mappings.
791 *
792 * @returns VBox status.
793 * @param pVM The virtual machine.
794 */
795VMMDECL(int) PGMMapResolveConflicts(PVM pVM)
796{
797 /*
798 * Can skip this if mappings are safely fixed.
799 */
800 if (pVM->pgm.s.fMappingsFixed)
801 return VINF_SUCCESS;
802
803 Assert(pVM->cCPUs == 1);
804
805 /* This only applies to raw mode where we only support 1 VCPU. */
806 PVMCPU pVCpu = &pVM->aCpus[0];
807
808 PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
809 Assert(enmGuestMode <= PGMMODE_PAE_NX);
810
811 if (enmGuestMode == PGMMODE_32_BIT)
812 {
813 /*
814 * Resolve the page directory.
815 */
816 PX86PD pPD = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
817 Assert(pPD);
818
819 /*
820 * Iterate mappings.
821 */
822 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; )
823 {
824 PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
825 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
826 unsigned iPT = pCur->cPTs;
827 while (iPT-- > 0)
828 {
829 if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
830 && ( pVM->fRawR0Enabled
831 || pPD->a[iPDE + iPT].n.u1User))
832 {
833 STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
834
835#ifdef IN_RING3
836 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
837 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
838 (iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
839 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
840 int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
841 AssertRCReturn(rc, rc);
842 break;
843#else
844 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
845 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
846 (iPT + iPDE) << X86_PD_SHIFT,
847 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
848 return VINF_PGM_SYNC_CR3;
849#endif
850 }
851 }
852 pCur = pNext;
853 }
854 }
855 else if ( enmGuestMode == PGMMODE_PAE
856 || enmGuestMode == PGMMODE_PAE_NX)
857 {
858 /*
859 * Iterate mappings.
860 */
861 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur;)
862 {
863 PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
864 RTGCPTR GCPtr = pCur->GCPtr;
865 unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
866 while (iPT-- > 0)
867 {
868 X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
869
870 if ( Pde.n.u1Present
871 && (pVM->fRawR0Enabled || Pde.n.u1User))
872 {
873 STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
874#ifdef IN_RING3
875 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
876 " PDE=%016RX64.\n",
877 GCPtr, pCur->pszDesc, Pde.u));
878 int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, pCur->GCPtr);
879 AssertRCReturn(rc, rc);
880 break;
881#else
882 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
883 " PDE=%016RX64.\n",
884 GCPtr, Pde.u));
885 return VINF_PGM_SYNC_CR3;
886#endif
887 }
888 GCPtr += (1 << X86_PD_PAE_SHIFT);
889 }
890 pCur = pNext;
891 }
892 }
893 else
894 AssertFailed();
895
896 Assert(!PGMMapHasConflicts(pVM));
897 return VINF_SUCCESS;
898}
899
900#endif /* IN_RING0 */
901
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