PGMAllMap.cpp@ 30164

Last change on this file since 30164 was 29250, checked in by vboxsync, 15 years ago
iprt/asm.h: split out asm-math.h, don't include asm-.h from asm.h, don't include asm.h from sup.h. Fixed a couple file headers.
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1	/* $Id: PGMAllMap.cpp 29250 2010-05-09 17:53:58Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_PGM
22	#include <VBox/pgm.h>
23	#include "../PGMInternal.h"
24	#include <VBox/vm.h>
25	#include "../PGMInline.h"
26	#include <VBox/err.h>
27	#include <iprt/asm-amd64-x86.h>
28	#include <iprt/assert.h>
29
30
31	/**
32	* Maps a range of physical pages at a given virtual address
33	* in the guest context.
34	*
35	* The GC virtual address range must be within an existing mapping.
36	*
37	* @returns VBox status code.
38	* @param pVM The virtual machine.
39	* @param GCPtr Where to map the page(s). Must be page aligned.
40	* @param HCPhys Start of the range of physical pages. Must be page aligned.
41	* @param cbPages Number of bytes to map. Must be page aligned.
42	* @param fFlags Page flags (X86_PTE_*).
43	*/
44	VMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
45	{
46	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
47
48	/*
49	* Validate input.
50	*/
51	AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
52	AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
53	AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
54
55	/* hypervisor defaults */
56	if (!fFlags)
57	fFlags = X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
58
59	/*
60	* Find the mapping.
61	*/
62	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
63	while (pCur)
64	{
65	if (GCPtr - pCur->GCPtr < pCur->cb)
66	{
67	if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
68	{
69	AssertMsgFailed(("Invalid range!!\n"));
70	return VERR_INVALID_PARAMETER;
71	}
72
73	/*
74	* Setup PTE.
75	*/
76	X86PTEPAE Pte;
77	Pte.u = fFlags \| (HCPhys & X86_PTE_PAE_PG_MASK);
78
79	/*
80	* Update the page tables.
81	*/
82	for (;;)
83	{
84	RTGCUINTPTR off = GCPtr - pCur->GCPtr;
85	const unsigned iPT = off >> X86_PD_SHIFT;
86	const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
87
88	/* 32-bit */
89	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
90
91	/* pae */
92	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512].u = Pte.u;
93
94	/* next */
95	cbPages -= PAGE_SIZE;
96	if (!cbPages)
97	break;
98	GCPtr += PAGE_SIZE;
99	Pte.u += PAGE_SIZE;
100	}
101
102	return VINF_SUCCESS;
103	}
104
105	/* next */
106	pCur = pCur->CTX_SUFF(pNext);
107	}
108
109	AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
110	return VERR_INVALID_PARAMETER;
111	}
112
113
114	/**
115	* Sets (replaces) the page flags for a range of pages in a mapping.
116	*
117	* @returns VBox status.
118	* @param pVM VM handle.
119	* @param GCPtr Virtual address of the first page in the range.
120	* @param cb Size (in bytes) of the range to apply the modification to.
121	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
122	*/
123	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
124	{
125	return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
126	}
127
128
129	/**
130	* Modify page flags for a range of pages in a mapping.
131	*
132	* The existing flags are ANDed with the fMask and ORed with the fFlags.
133	*
134	* @returns VBox status code.
135	* @param pVM VM handle.
136	* @param GCPtr Virtual address of the first page in the range.
137	* @param cb Size (in bytes) of the range to apply the modification to.
138	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
139	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
140	*/
141	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
142	{
143	/*
144	* Validate input.
145	*/
146	AssertMsg(!(fFlags & X86_PTE_PAE_PG_MASK), ("fFlags=%#x\n", fFlags));
147	Assert(cb);
148
149	/*
150	* Align the input.
151	*/
152	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
153	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
154	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
155
156	/*
157	* Find the mapping.
158	*/
159	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
160	while (pCur)
161	{
162	RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
163	if (off < pCur->cb)
164	{
165	AssertMsgReturn(off + cb <= pCur->cb,
166	("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
167	GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
168	VERR_INVALID_PARAMETER);
169
170	/*
171	* Perform the requested operation.
172	*/
173	while (cb > 0)
174	{
175	unsigned iPT = off >> X86_PD_SHIFT;
176	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
177	while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
178	{
179	/* 32-Bit */
180	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask \| X86_PTE_PG_MASK;
181	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u \|= fFlags & ~X86_PTE_PG_MASK;
182
183	/* PAE */
184	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u &= fMask \| X86_PTE_PAE_PG_MASK;
185	pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512].u \|= fFlags & ~X86_PTE_PAE_PG_MASK;
186
187	/* invalidate tls */
188	PGM_INVL_PG(VMMGetCpu(pVM), (RTGCUINTPTR)pCur->GCPtr + off);
189
190	/* next */
191	iPTE++;
192	cb -= PAGE_SIZE;
193	off += PAGE_SIZE;
194	}
195	}
196
197	return VINF_SUCCESS;
198	}
199	/* next */
200	pCur = pCur->CTX_SUFF(pNext);
201	}
202
203	AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
204	return VERR_INVALID_PARAMETER;
205	}
206
207
208	#ifndef IN_RING0
209	/**
210	* Sets all PDEs involved with the mapping in the shadow page table.
211	*
212	* @param pVM The VM handle.
213	* @param pMap Pointer to the mapping in question.
214	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
215	*/
216	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
217	{
218	Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(&pVM->pgm.s)));
219
220	if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s)
221	\|\| pVM->cCpus > 1)
222	return;
223
224	/* This only applies to raw mode where we only support 1 VCPU. */
225	PVMCPU pVCpu = VMMGetCpu0(pVM);
226	if (!pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
227	return; /* too early */
228
229	PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
230	Assert(enmShadowMode <= PGMMODE_PAE_NX);
231
232	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
233
234	/*
235	* Insert the page tables into the shadow page directories.
236	*/
237	unsigned i = pMap->cPTs;
238	iNewPDE += i;
239	while (i-- > 0)
240	{
241	iNewPDE--;
242
243	switch (enmShadowMode)
244	{
245	case PGMMODE_32_BIT:
246	{
247	PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
248	AssertFatal(pShw32BitPd);
249	#ifdef IN_RC /* Lock mapping to prevent it from being reused during pgmPoolFree. */
250	PGMDynLockHCPage(pVM, (uint8_t *)pShw32BitPd);
251	#endif
252	/* Free any previous user, unless it's us. */
253	Assert( (pShw32BitPd->a[iNewPDE].u & (X86_PDE_P \| PGM_PDFLAGS_MAPPING)) != (X86_PDE_P \| PGM_PDFLAGS_MAPPING)
254	\|\| (pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK) == pMap->aPTs[i].HCPhysPT);
255	if ( pShw32BitPd->a[iNewPDE].n.u1Present
256	&& !(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING))
257	pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
258
259	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags. */
260	pShw32BitPd->a[iNewPDE].u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US
261	\| (uint32_t)pMap->aPTs[i].HCPhysPT;
262	#ifdef IN_RC
263	/* Unlock dynamic mappings again. */
264	PGMDynUnlockHCPage(pVM, (uint8_t *)pShw32BitPd);
265	#endif
266	break;
267	}
268
269	case PGMMODE_PAE:
270	case PGMMODE_PAE_NX:
271	{
272	const uint32_t iPdPt = iNewPDE / 256;
273	unsigned iPaePde = iNewPDE * 2 % 512;
274	PX86PDPT pShwPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
275	Assert(pShwPdpt);
276	#ifdef IN_RC /* Lock mapping to prevent it from being reused during pgmShwSyncPaePDPtr. */
277	PGMDynLockHCPage(pVM, (uint8_t *)pShwPdpt);
278	#endif
279
280	/*
281	* Get the shadow PD.
282	* If no PD, sync it (PAE guest) or fake (not present or 32-bit guest).
283	* Note! The RW, US and A bits are reserved for PAE PDPTEs. Setting the
284	* accessed bit causes invalid VT-x guest state errors.
285	*/
286	PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(&pVCpu->pgm.s, iPdPt << X86_PDPT_SHIFT);
287	if (!pShwPaePd)
288	{
289	X86PDPE GstPdpe;
290	if (PGMGetGuestMode(pVCpu) < PGMMODE_PAE)
291	GstPdpe.u = X86_PDPE_P;
292	else
293	{
294	PX86PDPE pGstPdpe = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, iPdPt << X86_PDPT_SHIFT);
295	if (pGstPdpe)
296	GstPdpe = *pGstPdpe;
297	else
298	GstPdpe.u = X86_PDPE_P;
299	}
300	int rc = pgmShwSyncPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT, &GstPdpe, &pShwPaePd);
301	AssertFatalRC(rc);
302	}
303	Assert(pShwPaePd);
304	#ifdef IN_RC /* Lock mapping to prevent it from being reused during pgmPoolFree. */
305	PGMDynLockHCPage(pVM, (uint8_t *)pShwPaePd);
306	#endif
307
308	/*
309	* Mark the page as locked; disallow flushing.
310	*/
311	PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
312	AssertFatal(pPoolPagePd);
313	if (!pgmPoolIsPageLocked(&pVM->pgm.s, pPoolPagePd))
314	pgmPoolLockPage(pPool, pPoolPagePd);
315	#ifdef VBOX_STRICT
316	else if (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING)
317	{
318	Assert(PGMGetGuestMode(pVCpu) >= PGMMODE_PAE); /** @todo We may hit this during reset, will fix later. */
319	AssertFatalMsg( (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0
320	\|\| !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
321	("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT0));
322	Assert(pShwPaePd->a[iPaePde+1].u & PGM_PDFLAGS_MAPPING);
323	AssertFatalMsg( (pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1
324	\|\| !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
325	("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT1));
326	}
327	#endif
328
329	/*
330	* Insert our first PT, freeing anything we might be replacing unless it's a mapping (i.e. us).
331	*/
332	Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P \| PGM_PDFLAGS_MAPPING)) != (X86_PDE_P \| PGM_PDFLAGS_MAPPING)
333	\|\| (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0);
334	if ( pShwPaePd->a[iPaePde].n.u1Present
335	&& !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
336	{
337	Assert(!(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
338	pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK, pPoolPagePd->idx, iPaePde);
339	}
340	pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US
341	\| pMap->aPTs[i].HCPhysPaePT0;
342
343	/* 2nd 2 MB PDE of the 4 MB region, same as above. */
344	iPaePde++;
345	AssertFatal(iPaePde < 512);
346	Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P \| PGM_PDFLAGS_MAPPING)) != (X86_PDE_P \| PGM_PDFLAGS_MAPPING)
347	\|\| (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1);
348	if ( pShwPaePd->a[iPaePde].n.u1Present
349	&& !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
350	pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iPaePde);
351	pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US
352	\| pMap->aPTs[i].HCPhysPaePT1;
353
354	/*
355	* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode)
356	*/
357	pShwPdpt->a[iPdPt].u \|= PGM_PLXFLAGS_MAPPING;
358
359	#ifdef IN_RC
360	/* Unlock dynamic mappings again. */
361	PGMDynUnlockHCPage(pVM, (uint8_t *)pShwPaePd);
362	PGMDynUnlockHCPage(pVM, (uint8_t *)pShwPdpt);
363	#endif
364	break;
365	}
366
367	default:
368	AssertFailed();
369	break;
370	}
371	}
372	}
373
374
375	/**
376	* Clears all PDEs involved with the mapping in the shadow page table.
377	*
378	* @param pVM The VM handle.
379	* @param pShwPageCR3 CR3 root page
380	* @param pMap Pointer to the mapping in question.
381	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
382	* @param fDeactivateCR3 Set if it's pgmMapDeactivateCR3 calling.
383	*/
384	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3)
385	{
386	Log(("pgmMapClearShadowPDEs: old pde %x (cPTs=%x) (mappings enabled %d) fDeactivateCR3=%RTbool\n", iOldPDE, pMap->cPTs, pgmMapAreMappingsEnabled(&pVM->pgm.s), fDeactivateCR3));
387
388	/*
389	* Skip this if disabled or if it doesn't apply.
390	*/
391	if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s)
392	\|\| pVM->cCpus > 1)
393	return;
394
395	Assert(pShwPageCR3);
396
397	/* This only applies to raw mode where we only support 1 VCPU. */
398	PVMCPU pVCpu = VMMGetCpu0(pVM);
399	# ifdef IN_RC
400	Assert(pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
401	# endif
402
403	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
404
405	PX86PDPT pCurrentShwPdpt = NULL;
406	if ( PGMGetGuestMode(pVCpu) >= PGMMODE_PAE
407	&& pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
408	{
409	pCurrentShwPdpt = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
410	#ifdef IN_RC /* Lock mapping to prevent it from being reused (currently not possible). */
411	if (pCurrentShwPdpt)
412	PGMDynLockHCPage(pVM, (uint8_t *)pCurrentShwPdpt);
413	#endif
414	}
415
416	unsigned i = pMap->cPTs;
417	PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
418
419	iOldPDE += i;
420	while (i-- > 0)
421	{
422	iOldPDE--;
423
424	switch(enmShadowMode)
425	{
426	case PGMMODE_32_BIT:
427	{
428	PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
429	AssertFatal(pShw32BitPd);
430
431	Assert(!pShw32BitPd->a[iOldPDE].n.u1Present \|\| (pShw32BitPd->a[iOldPDE].u & PGM_PDFLAGS_MAPPING));
432	pShw32BitPd->a[iOldPDE].u = 0;
433	break;
434	}
435
436	case PGMMODE_PAE:
437	case PGMMODE_PAE_NX:
438	{
439	const unsigned iPdpt = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
440	unsigned iPaePde = iOldPDE * 2 % 512;
441	PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
442	PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(&pVCpu->pgm.s, pShwPdpt, (iPdpt << X86_PDPT_SHIFT));
443
444	/*
445	* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode)
446	*/
447	if (fDeactivateCR3)
448	pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
449	else if (pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING)
450	{
451	/* See if there are any other mappings here. This is suboptimal code. */
452	pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
453	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
454	if ( pCur != pMap
455	&& ( (pCur->GCPtr >> X86_PDPT_SHIFT) == iPdpt
456	\|\| (pCur->GCPtrLast >> X86_PDPT_SHIFT) == iPdpt))
457	{
458	pShwPdpt->a[iPdpt].u \|= PGM_PLXFLAGS_MAPPING;
459	break;
460	}
461	}
462
463	/*
464	* If the page directory of the old CR3 is reused in the new one, then don't
465	* clear the hypervisor mappings.
466	*/
467	if ( pCurrentShwPdpt
468	&& (pCurrentShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) == (pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) )
469	{
470	LogFlow(("pgmMapClearShadowPDEs: Pdpe %d reused -> don't clear hypervisor mappings!\n", iPdpt));
471	break;
472	}
473
474	/*
475	* Clear the mappings in the PD.
476	*/
477	AssertFatal(pShwPaePd);
478	Assert(!pShwPaePd->a[iPaePde].n.u1Present \|\| (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
479	pShwPaePd->a[iPaePde].u = 0;
480
481	iPaePde++;
482	AssertFatal(iPaePde < 512);
483	Assert(!pShwPaePd->a[iPaePde].n.u1Present \|\| (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
484	pShwPaePd->a[iPaePde].u = 0;
485
486	/*
487	* Unlock the shadow pool PD page if the PDPTE no longer holds any mappings.
488	*/
489	if ( fDeactivateCR3
490	\|\| !(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
491	{
492	PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
493	AssertFatal(pPoolPagePd);
494	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPoolPagePd))
495	pgmPoolUnlockPage(pPool, pPoolPagePd);
496	}
497	break;
498	}
499
500	default:
501	AssertFailed();
502	break;
503	}
504	}
505	#ifdef IN_RC
506	/* Unlock dynamic mappings again. */
507	if (pCurrentShwPdpt)
508	PGMDynUnlockHCPage(pVM, (uint8_t *)pCurrentShwPdpt);
509	#endif
510	}
511	#endif /* !IN_RING0 */
512
513	#if defined(VBOX_STRICT) && !defined(IN_RING0)
514	/**
515	* Clears all PDEs involved with the mapping in the shadow page table.
516	*
517	* @param pVM The VM handle.
518	* @param pVCpu The VMCPU handle.
519	* @param pShwPageCR3 CR3 root page
520	* @param pMap Pointer to the mapping in question.
521	* @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
522	*/
523	static void pgmMapCheckShadowPDEs(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
524	{
525	Assert(pShwPageCR3);
526
527	uint32_t i = pMap->cPTs;
528	PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
529	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
530
531	iPDE += i;
532	while (i-- > 0)
533	{
534	iPDE--;
535
536	switch (enmShadowMode)
537	{
538	case PGMMODE_32_BIT:
539	{
540	PCX86PD pShw32BitPd = (PCX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
541	AssertFatal(pShw32BitPd);
542
543	AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT),
544	("Expected %x vs %x; iPDE=%#x %RGv %s\n",
545	pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT),
546	iPDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
547	break;
548	}
549
550	case PGMMODE_PAE:
551	case PGMMODE_PAE_NX:
552	{
553	const unsigned iPdpt = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
554	unsigned iPaePDE = iPDE * 2 % 512;
555	PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPageCR3);
556	PCX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(&pVCpu->pgm.s, pShwPdpt, iPdpt << X86_PDPT_SHIFT);
557	AssertFatal(pShwPaePd);
558
559	AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0),
560	("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
561	pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0),
562	iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
563
564	iPaePDE++;
565	AssertFatal(iPaePDE < 512);
566
567	AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1),
568	("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
569	pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1),
570	iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
571
572	AssertMsg(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING,
573	("%RX64; iPdpt=%#x iPDE=%#x iPaePDE=%#x %RGv %s\n",
574	pShwPdpt->a[iPdpt].u,
575	iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
576
577	PCPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
578	AssertFatal(pPoolPagePd);
579	AssertMsg(pPoolPagePd->cLocked, (".idx=%d .type=%d\n", pPoolPagePd->idx, pPoolPagePd->enmKind));
580	break;
581	}
582
583	default:
584	AssertFailed();
585	break;
586	}
587	}
588	}
589
590
591	/**
592	* Check the hypervisor mappings in the active CR3.
593	*
594	* @param pVM The virtual machine.
595	*/
596	VMMDECL(void) PGMMapCheck(PVM pVM)
597	{
598	/*
599	* Can skip this if mappings are disabled.
600	*/
601	if (!pgmMapAreMappingsEnabled(&pVM->pgm.s))
602	return;
603
604	/* This only applies to raw mode where we only support 1 VCPU. */
605	Assert(pVM->cCpus == 1);
606	PVMCPU pVCpu = VMMGetCpu0(pVM);
607	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
608
609	/*
610	* Iterate mappings.
611	*/
612	pgmLock(pVM); /* to avoid assertions */
613	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
614	{
615	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
616	pgmMapCheckShadowPDEs(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
617	}
618	pgmUnlock(pVM);
619	}
620	#endif /* defined(VBOX_STRICT) && !defined(IN_RING0) */
621
622	#ifndef IN_RING0
623
624	/**
625	* Apply the hypervisor mappings to the active CR3.
626	*
627	* @returns VBox status.
628	* @param pVM The virtual machine.
629	* @param pShwPageCR3 CR3 root page
630	*/
631	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
632	{
633	/*
634	* Skip this if disabled or if it doesn't apply.
635	*/
636	if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s)
637	\|\| pVM->cCpus > 1)
638	return VINF_SUCCESS;
639
640	/* Note! This might not be logged successfully in RC because we usually
641	cannot flush the log at this point. */
642	Log4(("pgmMapActivateCR3: fixed mappings=%RTbool idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
643
644	#ifdef VBOX_STRICT
645	PVMCPU pVCpu = VMMGetCpu0(pVM);
646	Assert(pShwPageCR3 && pShwPageCR3 == pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
647	#endif
648
649	/*
650	* Iterate mappings.
651	*/
652	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
653	{
654	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
655	pgmMapSetShadowPDEs(pVM, pCur, iPDE);
656	}
657	return VINF_SUCCESS;
658	}
659
660
661	/**
662	* Remove the hypervisor mappings from the specified CR3
663	*
664	* @returns VBox status.
665	* @param pVM The virtual machine.
666	* @param pShwPageCR3 CR3 root page
667	*/
668	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
669	{
670	/*
671	* Skip this if disabled or if it doesn't apply.
672	*/
673	if ( !pgmMapAreMappingsEnabled(&pVM->pgm.s)
674	\|\| pVM->cCpus > 1)
675	return VINF_SUCCESS;
676
677	Assert(pShwPageCR3);
678	Log4(("pgmMapDeactivateCR3: fixed mappings=%d idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
679
680	/*
681	* Iterate mappings.
682	*/
683	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
684	{
685	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
686	pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE, true /fDeactivateCR3/);
687	}
688	return VINF_SUCCESS;
689	}
690
691
692	/**
693	* Checks guest PD for conflicts with VMM GC mappings.
694	*
695	* @returns true if conflict detected.
696	* @returns false if not.
697	* @param pVM The virtual machine.
698	*/
699	VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
700	{
701	/*
702	* Can skip this if mappings are safely fixed.
703	*/
704	if (!pgmMapAreMappingsFloating(&pVM->pgm.s))
705	return false;
706
707	Assert(pVM->cCpus == 1);
708
709	/* This only applies to raw mode where we only support 1 VCPU. */
710	PVMCPU pVCpu = &pVM->aCpus[0];
711
712	PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
713	Assert(enmGuestMode <= PGMMODE_PAE_NX);
714
715	/*
716	* Iterate mappings.
717	*/
718	if (enmGuestMode == PGMMODE_32_BIT)
719	{
720	/*
721	* Resolve the page directory.
722	*/
723	PX86PD pPD = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
724	Assert(pPD);
725
726	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
727	{
728	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
729	unsigned iPT = pCur->cPTs;
730	while (iPT-- > 0)
731	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
732	&& (pVM->fRawR0Enabled \|\| pPD->a[iPDE + iPT].n.u1User))
733	{
734	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
735
736	#ifdef IN_RING3
737	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
738	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
739	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
740	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
741	#else
742	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
743	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
744	(iPT + iPDE) << X86_PD_SHIFT,
745	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
746	#endif
747	return true;
748	}
749	}
750	}
751	else if ( enmGuestMode == PGMMODE_PAE
752	\|\| enmGuestMode == PGMMODE_PAE_NX)
753	{
754	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
755	{
756	RTGCPTR GCPtr = pCur->GCPtr;
757
758	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
759	while (iPT-- > 0)
760	{
761	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
762
763	if ( Pde.n.u1Present
764	&& (pVM->fRawR0Enabled \|\| Pde.n.u1User))
765	{
766	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
767	#ifdef IN_RING3
768	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
769	" PDE=%016RX64.\n",
770	GCPtr, pCur->pszDesc, Pde.u));
771	#else
772	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
773	" PDE=%016RX64.\n",
774	GCPtr, Pde.u));
775	#endif
776	return true;
777	}
778	GCPtr += (1 << X86_PD_PAE_SHIFT);
779	}
780	}
781	}
782	else
783	AssertFailed();
784
785	return false;
786	}
787
788
789	/**
790	* Checks and resolves (ring 3 only) guest conflicts with the guest mappings.
791	*
792	* @returns VBox status.
793	* @param pVM The virtual machine.
794	*/
795	int pgmMapResolveConflicts(PVM pVM)
796	{
797	/* The caller is expected to check these two conditions. */
798	Assert(!pVM->pgm.s.fMappingsFixed);
799	Assert(!pVM->pgm.s.fMappingsDisabled);
800
801	/* This only applies to raw mode where we only support 1 VCPU. */
802	Assert(pVM->cCpus == 1);
803	PVMCPU pVCpu = &pVM->aCpus[0];
804	PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
805	Assert(enmGuestMode <= PGMMODE_PAE_NX);
806
807	if (enmGuestMode == PGMMODE_32_BIT)
808	{
809	/*
810	* Resolve the page directory.
811	*/
812	PX86PD pPD = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
813	Assert(pPD);
814
815	/*
816	* Iterate mappings.
817	*/
818	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; )
819	{
820	PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
821	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
822	unsigned iPT = pCur->cPTs;
823	while (iPT-- > 0)
824	{
825	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
826	&& ( pVM->fRawR0Enabled
827	\|\| pPD->a[iPDE + iPT].n.u1User))
828	{
829	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
830
831	#ifdef IN_RING3
832	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
833	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
834	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
835	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
836	int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
837	AssertRCReturn(rc, rc);
838	break;
839	#else
840	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
841	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
842	(iPT + iPDE) << X86_PD_SHIFT,
843	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
844	return VINF_PGM_SYNC_CR3;
845	#endif
846	}
847	}
848	pCur = pNext;
849	}
850	}
851	else if ( enmGuestMode == PGMMODE_PAE
852	\|\| enmGuestMode == PGMMODE_PAE_NX)
853	{
854	/*
855	* Iterate mappings.
856	*/
857	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur;)
858	{
859	PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
860	RTGCPTR GCPtr = pCur->GCPtr;
861	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
862	while (iPT-- > 0)
863	{
864	X86PDEPAE Pde = pgmGstGetPaePDE(&pVCpu->pgm.s, GCPtr);
865
866	if ( Pde.n.u1Present
867	&& (pVM->fRawR0Enabled \|\| Pde.n.u1User))
868	{
869	STAM_COUNTER_INC(&pVM->pgm.s.StatR3DetectedConflicts);
870	#ifdef IN_RING3
871	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
872	" PDE=%016RX64.\n",
873	GCPtr, pCur->pszDesc, Pde.u));
874	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, pCur->GCPtr);
875	AssertRCReturn(rc, rc);
876	break;
877	#else
878	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
879	" PDE=%016RX64.\n",
880	GCPtr, Pde.u));
881	return VINF_PGM_SYNC_CR3;
882	#endif
883	}
884	GCPtr += (1 << X86_PD_PAE_SHIFT);
885	}
886	pCur = pNext;
887	}
888	}
889	else
890	AssertFailed();
891
892	Assert(!PGMMapHasConflicts(pVM));
893	return VINF_SUCCESS;
894	}
895
896	#endif /* IN_RING0 */
897

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp@ 30164

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