PGMAllMap.cpp@ 78402

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1	/* $Id: PGMAllMap.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/em.h>
25	#include "PGMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "PGMInline.h"
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/assert.h>
31
32
33	/**
34	* Maps a range of physical pages at a given virtual address
35	* in the guest context.
36	*
37	* The GC virtual address range must be within an existing mapping.
38	*
39	* @returns VBox status code.
40	* @param pVM The cross context VM structure.
41	* @param GCPtr Where to map the page(s). Must be page aligned.
42	* @param HCPhys Start of the range of physical pages. Must be page aligned.
43	* @param cbPages Number of bytes to map. Must be page aligned.
44	* @param fFlags Page flags (X86_PTE_*).
45	*/
46	VMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
47	{
48	AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
49
50	/*
51	* Validate input.
52	*/
53	AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
54	AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
55	AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
56
57	/* hypervisor defaults */
58	if (!fFlags)
59	fFlags = X86_PTE_P \| X86_PTE_A \| X86_PTE_D;
60
61	/*
62	* Find the mapping.
63	*/
64	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
65	while (pCur)
66	{
67	if (GCPtr - pCur->GCPtr < pCur->cb)
68	{
69	if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
70	{
71	AssertMsgFailed(("Invalid range!!\n"));
72	return VERR_INVALID_PARAMETER;
73	}
74
75	/*
76	* Setup PTE.
77	*/
78	X86PTEPAE Pte;
79	Pte.u = fFlags \| (HCPhys & X86_PTE_PAE_PG_MASK);
80
81	/*
82	* Update the page tables.
83	*/
84	for (;;)
85	{
86	RTGCUINTPTR off = GCPtr - pCur->GCPtr;
87	const unsigned iPT = off >> X86_PD_SHIFT;
88	const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
89
90	/* 32-bit */
91	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
92
93	/* pae */
94	PGMSHWPTEPAE_SET(pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512], Pte.u);
95
96	/* next */
97	cbPages -= PAGE_SIZE;
98	if (!cbPages)
99	break;
100	GCPtr += PAGE_SIZE;
101	Pte.u += PAGE_SIZE;
102	}
103
104	return VINF_SUCCESS;
105	}
106
107	/* next */
108	pCur = pCur->CTX_SUFF(pNext);
109	}
110
111	AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
112	return VERR_INVALID_PARAMETER;
113	}
114
115
116	/**
117	* Sets (replaces) the page flags for a range of pages in a mapping.
118	*
119	* @returns VBox status code.
120	* @param pVM The cross context VM structure.
121	* @param GCPtr Virtual address of the first page in the range.
122	* @param cb Size (in bytes) of the range to apply the modification to.
123	* @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
124	*/
125	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
126	{
127	return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
128	}
129
130
131	/**
132	* Modify page flags for a range of pages in a mapping.
133	*
134	* The existing flags are ANDed with the fMask and ORed with the fFlags.
135	*
136	* @returns VBox status code.
137	* @param pVM The cross context VM structure.
138	* @param GCPtr Virtual address of the first page in the range.
139	* @param cb Size (in bytes) of the range to apply the modification to.
140	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
141	* @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
142	*/
143	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
144	{
145	/*
146	* Validate input.
147	*/
148	AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK \| X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags));
149	Assert(cb);
150
151	/*
152	* Align the input.
153	*/
154	cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
155	cb = RT_ALIGN_Z(cb, PAGE_SIZE);
156	GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
157
158	/*
159	* Find the mapping.
160	*/
161	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
162	while (pCur)
163	{
164	RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
165	if (off < pCur->cb)
166	{
167	AssertMsgReturn(off + cb <= pCur->cb,
168	("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
169	GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
170	VERR_INVALID_PARAMETER);
171
172	/*
173	* Perform the requested operation.
174	*/
175	while (cb > 0)
176	{
177	unsigned iPT = off >> X86_PD_SHIFT;
178	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
179	while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
180	{
181	/* 32-Bit */
182	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask \| X86_PTE_PG_MASK;
183	pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u \|= fFlags & ~X86_PTE_PG_MASK;
184
185	/* PAE */
186	PPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
187	PGMSHWPTEPAE_SET(*pPtePae,
188	( PGMSHWPTEPAE_GET_U(*pPtePae)
189	& (fMask \| X86_PTE_PAE_PG_MASK))
190	\| (fFlags & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_PAE_MBZ_MASK_NX)));
191
192	/* invalidate tls */
193	PGM_INVL_PG(VMMGetCpu(pVM), (RTGCUINTPTR)pCur->GCPtr + off);
194
195	/* next */
196	iPTE++;
197	cb -= PAGE_SIZE;
198	off += PAGE_SIZE;
199	}
200	}
201
202	return VINF_SUCCESS;
203	}
204	/* next */
205	pCur = pCur->CTX_SUFF(pNext);
206	}
207
208	AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
209	return VERR_INVALID_PARAMETER;
210	}
211
212
213	/**
214	* Get information about a page in a mapping.
215	*
216	* This differs from PGMShwGetPage and PGMGstGetPage in that it only consults
217	* the page table to calculate the flags.
218	*
219	* @returns VINF_SUCCESS, VERR_PAGE_NOT_PRESENT or VERR_NOT_FOUND.
220	* @param pVM The cross context VM structure.
221	* @param GCPtr The page address.
222	* @param pfFlags Where to return the flags. Optional.
223	* @param pHCPhys Where to return the address. Optional.
224	*/
225	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
226	{
227	/*
228	* Find the mapping.
229	*/
230	GCPtr &= PAGE_BASE_GC_MASK;
231	PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
232	while (pCur)
233	{
234	RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
235	if (off < pCur->cb)
236	{
237	/*
238	* Dig out the information.
239	*/
240	int rc = VINF_SUCCESS;
241	unsigned iPT = off >> X86_PD_SHIFT;
242	unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
243	PCPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
244	if (PGMSHWPTEPAE_IS_P(*pPtePae))
245	{
246	if (pfFlags)
247	pfFlags = PGMSHWPTEPAE_GET_U(pPtePae) & ~X86_PTE_PAE_PG_MASK;
248	if (pHCPhys)
249	pHCPhys = PGMSHWPTEPAE_GET_HCPHYS(pPtePae);
250	}
251	else
252	rc = VERR_PAGE_NOT_PRESENT;
253	return rc;
254	}
255	/* next */
256	pCur = pCur->CTX_SUFF(pNext);
257	}
258
259	return VERR_NOT_FOUND;
260	}
261
262	#ifndef PGM_WITHOUT_MAPPINGS
263
264	/**
265	* Sets all PDEs involved with the mapping in the shadow page table.
266	*
267	* Ignored if mappings are disabled (i.e. if HM is enabled).
268	*
269	* @param pVM The cross context VM structure.
270	* @param pMap Pointer to the mapping in question.
271	* @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
272	*/
273	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
274	{
275	Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(pVM)));
276
277	if (!pgmMapAreMappingsEnabled(pVM))
278	return;
279
280	/* This only applies to raw mode where we only support 1 VCPU. */
281	PVMCPU pVCpu = VMMGetCpu0(pVM);
282	if (!pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
283	return; /* too early */
284
285	PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
286	Assert(enmShadowMode <= PGMMODE_PAE_NX);
287
288	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
289
290	/*
291	* Insert the page tables into the shadow page directories.
292	*/
293	unsigned i = pMap->cPTs;
294	iNewPDE += i;
295	while (i-- > 0)
296	{
297	iNewPDE--;
298
299	switch (enmShadowMode)
300	{
301	case PGMMODE_32_BIT:
302	{
303	PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(pVCpu);
304	AssertFatal(pShw32BitPd);
305
306	/* Free any previous user, unless it's us. */
307	Assert( (pShw32BitPd->a[iNewPDE].u & (X86_PDE_P \| PGM_PDFLAGS_MAPPING)) != (X86_PDE_P \| PGM_PDFLAGS_MAPPING)
308	\|\| (pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK) == pMap->aPTs[i].HCPhysPT);
309	if ( pShw32BitPd->a[iNewPDE].n.u1Present
310	&& !(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING))
311	pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
312
313	/* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags. */
314	pShw32BitPd->a[iNewPDE].u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US
315	\| (uint32_t)pMap->aPTs[i].HCPhysPT;
316	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShw32BitPd);
317	break;
318	}
319
320	case PGMMODE_PAE:
321	case PGMMODE_PAE_NX:
322	{
323	const uint32_t iPdPt = iNewPDE / 256;
324	unsigned iPaePde = iNewPDE * 2 % 512;
325	PX86PDPT pShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
326	Assert(pShwPdpt);
327
328	/*
329	* Get the shadow PD.
330	* If no PD, sync it (PAE guest) or fake (not present or 32-bit guest).
331	* Note! The RW, US and A bits are reserved for PAE PDPTEs. Setting the
332	* accessed bit causes invalid VT-x guest state errors.
333	*/
334	PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
335	if (!pShwPaePd)
336	{
337	X86PDPE GstPdpe;
338	if (PGMGetGuestMode(pVCpu) < PGMMODE_PAE)
339	GstPdpe.u = X86_PDPE_P;
340	else
341	{
342	PX86PDPE pGstPdpe = pgmGstGetPaePDPEPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
343	if (pGstPdpe)
344	GstPdpe = *pGstPdpe;
345	else
346	GstPdpe.u = X86_PDPE_P;
347	}
348	int rc = pgmShwSyncPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT, GstPdpe.u, &pShwPaePd);
349	AssertFatalRC(rc);
350	}
351	Assert(pShwPaePd);
352
353	/*
354	* Mark the page as locked; disallow flushing.
355	*/
356	PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
357	AssertFatal(pPoolPagePd);
358	if (!pgmPoolIsPageLocked(pPoolPagePd))
359	pgmPoolLockPage(pPool, pPoolPagePd);
360	# ifdef VBOX_STRICT
361	else if (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING)
362	{
363	Assert(PGMGetGuestMode(pVCpu) >= PGMMODE_PAE); /** @todo We may hit this during reset, will fix later. */
364	AssertFatalMsg( (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0
365	\|\| !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
366	("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT0));
367	Assert(pShwPaePd->a[iPaePde+1].u & PGM_PDFLAGS_MAPPING);
368	AssertFatalMsg( (pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1
369	\|\| !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
370	("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT1));
371	}
372	# endif
373
374	/*
375	* Insert our first PT, freeing anything we might be replacing unless it's a mapping (i.e. us).
376	*/
377	Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P \| PGM_PDFLAGS_MAPPING)) != (X86_PDE_P \| PGM_PDFLAGS_MAPPING)
378	\|\| (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0);
379	if ( pShwPaePd->a[iPaePde].n.u1Present
380	&& !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
381	{
382	Assert(!(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
383	pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK, pPoolPagePd->idx, iPaePde);
384	}
385	pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US
386	\| pMap->aPTs[i].HCPhysPaePT0;
387
388	/* 2nd 2 MB PDE of the 4 MB region, same as above. */
389	iPaePde++;
390	AssertFatal(iPaePde < 512);
391	Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P \| PGM_PDFLAGS_MAPPING)) != (X86_PDE_P \| PGM_PDFLAGS_MAPPING)
392	\|\| (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1);
393	if ( pShwPaePd->a[iPaePde].n.u1Present
394	&& !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
395	pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iPaePde);
396	pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US
397	\| pMap->aPTs[i].HCPhysPaePT1;
398
399	/*
400	* Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode)
401	*/
402	pShwPdpt->a[iPdPt].u \|= PGM_PLXFLAGS_MAPPING;
403
404	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPaePd);
405	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPdpt);
406	break;
407	}
408
409	default:
410	AssertFailed();
411	break;
412	}
413	}
414	}
415
416
417	/**
418	* Clears all PDEs involved with the mapping in the shadow page table.
419	*
420	* Ignored if mappings are disabled (i.e. if HM is enabled).
421	*
422	* @param pVM The cross context VM structure.
423	* @param pShwPageCR3 CR3 root page
424	* @param pMap Pointer to the mapping in question.
425	* @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
426	* @param fDeactivateCR3 Set if it's pgmMapDeactivateCR3 calling.
427	*/
428	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3)
429	{
430	Log(("pgmMapClearShadowPDEs: old pde %x (cPTs=%x) (mappings enabled %d) fDeactivateCR3=%RTbool\n", iOldPDE, pMap->cPTs, pgmMapAreMappingsEnabled(pVM), fDeactivateCR3));
431
432	/*
433	* Skip this if it doesn't apply.
434	*/
435	if (!pgmMapAreMappingsEnabled(pVM))
436	return;
437
438	Assert(pShwPageCR3);
439
440	/* This only applies to raw mode where we only support 1 VCPU. */
441	PVMCPU pVCpu = VMMGetCpu0(pVM);
442	# ifdef IN_RC
443	Assert(pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
444	# endif
445
446	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
447
448	PX86PDPT pCurrentShwPdpt = NULL;
449	if ( PGMGetGuestMode(pVCpu) >= PGMMODE_PAE
450	&& pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
451	pCurrentShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
452
453	unsigned i = pMap->cPTs;
454	PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
455
456	iOldPDE += i;
457	while (i-- > 0)
458	{
459	iOldPDE--;
460
461	switch(enmShadowMode)
462	{
463	case PGMMODE_32_BIT:
464	{
465	PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
466	AssertFatal(pShw32BitPd);
467
468	Assert(!pShw32BitPd->a[iOldPDE].n.u1Present \|\| (pShw32BitPd->a[iOldPDE].u & PGM_PDFLAGS_MAPPING));
469	pShw32BitPd->a[iOldPDE].u = 0;
470	break;
471	}
472
473	case PGMMODE_PAE:
474	case PGMMODE_PAE_NX:
475	{
476	const unsigned iPdpt = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
477	unsigned iPaePde = iOldPDE * 2 % 512;
478	PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
479	PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, pShwPdpt, (iPdpt << X86_PDPT_SHIFT));
480
481	/*
482	* Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode)
483	*/
484	if (fDeactivateCR3)
485	pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
486	else if (pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING)
487	{
488	/* See if there are any other mappings here. This is suboptimal code. */
489	pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
490	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
491	if ( pCur != pMap
492	&& ( (pCur->GCPtr >> X86_PDPT_SHIFT) == iPdpt
493	\|\| (pCur->GCPtrLast >> X86_PDPT_SHIFT) == iPdpt))
494	{
495	pShwPdpt->a[iPdpt].u \|= PGM_PLXFLAGS_MAPPING;
496	break;
497	}
498	}
499
500	/*
501	* If the page directory of the old CR3 is reused in the new one, then don't
502	* clear the hypervisor mappings.
503	*/
504	if ( pCurrentShwPdpt
505	&& (pCurrentShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) == (pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) )
506	{
507	LogFlow(("pgmMapClearShadowPDEs: Pdpe %d reused -> don't clear hypervisor mappings!\n", iPdpt));
508	break;
509	}
510
511	/*
512	* Clear the mappings in the PD.
513	*/
514	AssertFatal(pShwPaePd);
515	Assert(!pShwPaePd->a[iPaePde].n.u1Present \|\| (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
516	pShwPaePd->a[iPaePde].u = 0;
517
518	iPaePde++;
519	AssertFatal(iPaePde < 512);
520	Assert(!pShwPaePd->a[iPaePde].n.u1Present \|\| (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
521	pShwPaePd->a[iPaePde].u = 0;
522
523	/*
524	* Unlock the shadow pool PD page if the PDPTE no longer holds any mappings.
525	*/
526	if ( fDeactivateCR3
527	\|\| !(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
528	{
529	PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
530	AssertFatal(pPoolPagePd);
531	if (pgmPoolIsPageLocked(pPoolPagePd))
532	pgmPoolUnlockPage(pPool, pPoolPagePd);
533	}
534	break;
535	}
536
537	default:
538	AssertFailed();
539	break;
540	}
541	}
542
543	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pCurrentShwPdpt);
544	}
545
546	#endif /* PGM_WITHOUT_MAPPINGS */
547	#if defined(VBOX_STRICT) && !defined(IN_RING0)
548
549	/**
550	* Clears all PDEs involved with the mapping in the shadow page table.
551	*
552	* @param pVM The cross context VM structure.
553	* @param pVCpu The cross context virtual CPU structure.
554	* @param pShwPageCR3 CR3 root page
555	* @param pMap Pointer to the mapping in question.
556	* @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
557	*/
558	static void pgmMapCheckShadowPDEs(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
559	{
560	Assert(pShwPageCR3);
561
562	uint32_t i = pMap->cPTs;
563	PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
564	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
565
566	iPDE += i;
567	while (i-- > 0)
568	{
569	iPDE--;
570
571	switch (enmShadowMode)
572	{
573	case PGMMODE_32_BIT:
574	{
575	PCX86PD pShw32BitPd = (PCX86PD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
576	AssertFatal(pShw32BitPd);
577
578	AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT),
579	("Expected %x vs %x; iPDE=%#x %RGv %s\n",
580	pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| (uint32_t)pMap->aPTs[i].HCPhysPT),
581	iPDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
582	break;
583	}
584
585	case PGMMODE_PAE:
586	case PGMMODE_PAE_NX:
587	{
588	const unsigned iPdpt = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
589	unsigned iPaePDE = iPDE * 2 % 512;
590	PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
591	PCX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, pShwPdpt, iPdpt << X86_PDPT_SHIFT);
592	AssertFatal(pShwPaePd);
593
594	AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0),
595	("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
596	pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT0),
597	iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
598
599	iPaePDE++;
600	AssertFatal(iPaePDE < 512);
601
602	AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1),
603	("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
604	pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING \| X86_PDE_P \| X86_PDE_A \| X86_PDE_RW \| X86_PDE_US \| pMap->aPTs[i].HCPhysPaePT1),
605	iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
606
607	AssertMsg(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING,
608	("%RX64; iPdpt=%#x iPDE=%#x iPaePDE=%#x %RGv %s\n",
609	pShwPdpt->a[iPdpt].u,
610	iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
611
612	PCPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
613	AssertFatal(pPoolPagePd);
614	AssertMsg(pPoolPagePd->cLocked, (".idx=%d .type=%d\n", pPoolPagePd->idx, pPoolPagePd->enmKind));
615	break;
616	}
617
618	default:
619	AssertFailed();
620	break;
621	}
622	}
623	}
624
625
626	/**
627	* Check the hypervisor mappings in the active CR3.
628	*
629	* Ignored if mappings are disabled (i.e. if HM is enabled).
630	*
631	* @param pVM The cross context VM structure.
632	*/
633	VMMDECL(void) PGMMapCheck(PVM pVM)
634	{
635	/*
636	* Can skip this if mappings are disabled.
637	*/
638	if (!pgmMapAreMappingsEnabled(pVM))
639	return;
640
641	/* This only applies to raw mode where we only support 1 VCPU. */
642	Assert(pVM->cCpus == 1);
643	PVMCPU pVCpu = VMMGetCpu0(pVM);
644	Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
645
646	/*
647	* Iterate mappings.
648	*/
649	pgmLock(pVM); /* to avoid assertions */
650	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
651	{
652	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
653	pgmMapCheckShadowPDEs(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
654	}
655	pgmUnlock(pVM);
656	}
657
658	#endif /* defined(VBOX_STRICT) && !defined(IN_RING0) */
659	#ifndef PGM_WITHOUT_MAPPINGS
660
661	/**
662	* Apply the hypervisor mappings to the active CR3.
663	*
664	* Ignored if mappings are disabled (i.e. if HM is enabled).
665	*
666	* @returns VBox status code.
667	* @param pVM The cross context VM structure.
668	* @param pShwPageCR3 CR3 root page
669	*/
670	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
671	{
672	RT_NOREF_PV(pShwPageCR3);
673
674	/*
675	* Skip this if it doesn't apply.
676	*/
677	if (!pgmMapAreMappingsEnabled(pVM))
678	return VINF_SUCCESS;
679
680	/* Note! This might not be logged successfully in RC because we usually
681	cannot flush the log at this point. */
682	Log4(("pgmMapActivateCR3: fixed mappings=%RTbool idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
683
684	#ifdef VBOX_STRICT
685	PVMCPU pVCpu = VMMGetCpu0(pVM);
686	Assert(pShwPageCR3 && pShwPageCR3 == pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
687	#endif
688
689	/*
690	* Iterate mappings.
691	*/
692	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
693	{
694	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
695	pgmMapSetShadowPDEs(pVM, pCur, iPDE);
696	}
697	return VINF_SUCCESS;
698	}
699
700
701	/**
702	* Remove the hypervisor mappings from the specified CR3
703	*
704	* Ignored if mappings are disabled (i.e. if HM is enabled).
705	*
706	* @returns VBox status code.
707	* @param pVM The cross context VM structure.
708	* @param pShwPageCR3 CR3 root page
709	*/
710	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
711	{
712	/*
713	* Skip this if it doesn't apply.
714	*/
715	if (!pgmMapAreMappingsEnabled(pVM))
716	return VINF_SUCCESS;
717
718	Assert(pShwPageCR3);
719	Log4(("pgmMapDeactivateCR3: fixed mappings=%d idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
720
721	/*
722	* Iterate mappings.
723	*/
724	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
725	{
726	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
727	pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE, true /fDeactivateCR3/);
728	}
729	return VINF_SUCCESS;
730	}
731
732
733	/**
734	* Checks guest PD for conflicts with VMM GC mappings.
735	*
736	* @returns true if conflict detected.
737	* @returns false if not.
738	* @param pVM The cross context VM structure.
739	*/
740	VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
741	{
742	/*
743	* Can skip this if mappings are safely fixed.
744	*/
745	if (!pgmMapAreMappingsFloating(pVM))
746	return false;
747	AssertReturn(pgmMapAreMappingsEnabled(pVM), false);
748
749	/* This only applies to raw mode where we only support 1 VCPU. */
750	PVMCPU pVCpu = &pVM->aCpus[0];
751
752	PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
753	Assert(enmGuestMode <= PGMMODE_PAE_NX);
754
755	/*
756	* Iterate mappings.
757	*/
758	if (enmGuestMode == PGMMODE_32_BIT)
759	{
760	/*
761	* Resolve the page directory.
762	*/
763	PX86PD pPD = pgmGstGet32bitPDPtr(pVCpu);
764	Assert(pPD);
765
766	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
767	{
768	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
769	unsigned iPT = pCur->cPTs;
770	while (iPT-- > 0)
771	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
772	&& (EMIsRawRing0Enabled(pVM) \|\| pPD->a[iPDE + iPT].n.u1User))
773	{
774	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
775
776	# ifdef IN_RING3
777	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
778	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
779	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
780	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
781	# else
782	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
783	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
784	(iPT + iPDE) << X86_PD_SHIFT,
785	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
786	# endif
787	return true;
788	}
789	}
790	}
791	else if ( enmGuestMode == PGMMODE_PAE
792	\|\| enmGuestMode == PGMMODE_PAE_NX)
793	{
794	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
795	{
796	RTGCPTR GCPtr = pCur->GCPtr;
797
798	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
799	while (iPT-- > 0)
800	{
801	X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
802
803	if ( Pde.n.u1Present
804	&& (EMIsRawRing0Enabled(pVM) \|\| Pde.n.u1User))
805	{
806	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
807	# ifdef IN_RING3
808	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
809	" PDE=%016RX64.\n",
810	GCPtr, pCur->pszDesc, Pde.u));
811	# else
812	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
813	" PDE=%016RX64.\n",
814	GCPtr, Pde.u));
815	# endif
816	return true;
817	}
818	GCPtr += (1 << X86_PD_PAE_SHIFT);
819	}
820	}
821	}
822	else
823	AssertFailed();
824
825	return false;
826	}
827
828
829	/**
830	* Checks and resolves (ring 3 only) guest conflicts with the guest mappings.
831	*
832	* @returns VBox status code.
833	* @param pVM The cross context VM structure.
834	*/
835	int pgmMapResolveConflicts(PVM pVM)
836	{
837	/* The caller is expected to check these two conditions. */
838	Assert(!pVM->pgm.s.fMappingsFixed);
839	Assert(pgmMapAreMappingsEnabled(pVM));
840
841	/* This only applies to raw mode where we only support 1 VCPU. */
842	Assert(pVM->cCpus == 1);
843	PVMCPU pVCpu = &pVM->aCpus[0];
844	PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
845	Assert(enmGuestMode <= PGMMODE_PAE_NX);
846
847	if (enmGuestMode == PGMMODE_32_BIT)
848	{
849	/*
850	* Resolve the page directory.
851	*/
852	PX86PD pPD = pgmGstGet32bitPDPtr(pVCpu);
853	Assert(pPD);
854
855	/*
856	* Iterate mappings.
857	*/
858	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; )
859	{
860	PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
861	unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
862	unsigned iPT = pCur->cPTs;
863	while (iPT-- > 0)
864	{
865	if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
866	&& ( EMIsRawRing0Enabled(pVM)
867	\|\| pPD->a[iPDE + iPT].n.u1User))
868	{
869	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
870
871	# ifdef IN_RING3
872	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
873	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
874	(iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
875	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
876	int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
877	AssertRCReturn(rc, rc);
878	break;
879	# else
880	Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
881	" iPDE=%#x iPT=%#x PDE=%RGp.\n",
882	(iPT + iPDE) << X86_PD_SHIFT,
883	iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
884	return VINF_PGM_SYNC_CR3;
885	# endif
886	}
887	}
888	pCur = pNext;
889	}
890	}
891	else if ( enmGuestMode == PGMMODE_PAE
892	\|\| enmGuestMode == PGMMODE_PAE_NX)
893	{
894	/*
895	* Iterate mappings.
896	*/
897	for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur;)
898	{
899	PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
900	RTGCPTR GCPtr = pCur->GCPtr;
901	unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
902	while (iPT-- > 0)
903	{
904	X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
905
906	if ( Pde.n.u1Present
907	&& (EMIsRawRing0Enabled(pVM) \|\| Pde.n.u1User))
908	{
909	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
910	#ifdef IN_RING3
911	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
912	" PDE=%016RX64.\n",
913	GCPtr, pCur->pszDesc, Pde.u));
914	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, pCur->GCPtr);
915	AssertRCReturn(rc, rc);
916	break;
917	#else
918	Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
919	" PDE=%016RX64.\n",
920	GCPtr, Pde.u));
921	return VINF_PGM_SYNC_CR3;
922	#endif
923	}
924	GCPtr += (1 << X86_PD_PAE_SHIFT);
925	}
926	pCur = pNext;
927	}
928	}
929	else
930	AssertFailed();
931
932	Assert(!PGMMapHasConflicts(pVM));
933	return VINF_SUCCESS;
934	}
935
936	#endif /* PGM_WITHOUT_MAPPINGS */
937

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp@ 78402

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