PGMAllPhys.cpp@ 4592

Last change on this file since 4592 was 4591, checked in by vboxsync, 18 years ago
PGMPhysGCPhys2CCPtr + PGMPhysGCPhys2CCPtrRelease. Started on the NEW_PHYS_CODE.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 86.4 KB

Line
1	/* $Id: PGMAllPhys.cpp 4591 2007-09-07 01:26:43Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, Physical Memory Addressing.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @def PGM_IGNORE_RAM_FLAGS_RESERVED
19	* Don't respect the MM_RAM_FLAGS_RESERVED flag when converting to HC addresses.
20	*
21	* Since this flag is currently incorrectly kept set for ROM regions we will
22	* have to ignore it for now so we don't break stuff.
23	*
24	* @todo this has been fixed now I believe, remove this hack.
25	*/
26	#define PGM_IGNORE_RAM_FLAGS_RESERVED
27
28
29	/*******************************************************************************
30	* Header Files *
31	*******************************************************************************/
32	#define LOG_GROUP LOG_GROUP_PGM_PHYS
33	#include <VBox/pgm.h>
34	#include <VBox/trpm.h>
35	#include <VBox/vmm.h>
36	#include <VBox/iom.h>
37	#include "PGMInternal.h"
38	#include <VBox/vm.h>
39	#include <VBox/param.h>
40	#include <VBox/err.h>
41	#include <iprt/assert.h>
42	#include <iprt/string.h>
43	#include <iprt/asm.h>
44	#include <VBox/log.h>
45	#ifdef IN_RING3
46	# include <iprt/thread.h>
47	#endif
48
49
50
51	/**
52	* Checks if Address Gate 20 is enabled or not.
53	*
54	* @returns true if enabled.
55	* @returns false if disabled.
56	* @param pVM VM handle.
57	*/
58	PGMDECL(bool) PGMPhysIsA20Enabled(PVM pVM)
59	{
60	LogFlow(("PGMPhysIsA20Enabled %d\n", pVM->pgm.s.fA20Enabled));
61	return !!pVM->pgm.s.fA20Enabled ; /* stupid MS compiler doesn't trust me. */
62	}
63
64
65	/**
66	* Validates a GC physical address.
67	*
68	* @returns true if valid.
69	* @returns false if invalid.
70	* @param pVM The VM handle.
71	* @param GCPhys The physical address to validate.
72	*/
73	PGMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys)
74	{
75	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
76	pRam;
77	pRam = CTXSUFF(pRam->pNext))
78	{
79	RTGCPHYS off = GCPhys - pRam->GCPhys;
80	if (off < pRam->cb)
81	return true;
82	}
83	return false;
84	}
85
86
87	/**
88	* Checks if a GC physical address is a normal page,
89	* i.e. not ROM, MMIO or reserved.
90	*
91	* @returns true if normal.
92	* @returns false if invalid, ROM, MMIO or reserved page.
93	* @param pVM The VM handle.
94	* @param GCPhys The physical address to check.
95	*/
96	PGMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys)
97	{
98	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
99	pRam;
100	pRam = CTXSUFF(pRam->pNext))
101	{
102	RTGCPHYS off = GCPhys - pRam->GCPhys;
103	if (off < pRam->cb)
104	return !(pRam->aHCPhys[off >> PAGE_SHIFT] & (MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO2));
105	}
106	return false;
107	}
108
109
110	/**
111	* Converts a GC physical address to a HC physical address.
112	*
113	* @returns VINF_SUCCESS on success.
114	* @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
115	* page but has no physical backing.
116	* @returns VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid
117	* GC physical address.
118	* @param pVM The VM handle.
119	* @param GCPhys The GC physical address to convert.
120	* @param pHCPhys Where to store the HC physical address on success.
121	*/
122	PGMDECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
123	{
124	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
125	pRam;
126	pRam = CTXSUFF(pRam->pNext))
127	{
128	RTGCPHYS off = GCPhys - pRam->GCPhys;
129	if (off < pRam->cb)
130	{
131	if ( pRam->pvHC
132	\|\| (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
133	{
134	unsigned iPage = off >> PAGE_SHIFT;
135	if (RT_UNLIKELY(!(pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK)))
136	{
137	#ifdef IN_RING3
138	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
139	#else
140	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
141	#endif
142	if (rc != VINF_SUCCESS)
143	return rc;
144	}
145
146	RTHCPHYS HCPhys = pRam->aHCPhys[off >> PAGE_SHIFT];
147	#ifndef PGM_IGNORE_RAM_FLAGS_RESERVED
148	if (!(HCPhys & MM_RAM_FLAGS_RESERVED))
149	#endif
150	{
151	*pHCPhys = (HCPhys & X86_PTE_PAE_PG_MASK)
152	\| (off & PAGE_OFFSET_MASK);
153	return VINF_SUCCESS;
154	}
155	}
156	return VERR_PGM_PHYS_PAGE_RESERVED;
157	}
158	}
159	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
160	}
161
162
163	#ifdef NEW_PHYS_CODE
164
165
166	/**
167	* Replace a zero or shared page with new page that we can write to.
168	*
169	* @returns VBox status.
170	* @todo Define the return values and propagate them up the call tree..
171	*
172	* @param pVM The VM address.
173	* @param pPage The physical page tracking structure.
174	* @param GCPhys The address of the page.
175	*
176	* @remarks Called from within the PGM critical section.
177	*/
178	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
179	{
180	return VERR_NOT_IMPLEMENTED;
181	}
182
183
184	/**
185	* Deal with pages that are not writable, i.e. not in the ALLOCATED state.
186	*
187	* @returns VBox status code.
188	* @retval VINF_SUCCESS on success.
189	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
190	*
191	* @param pVM The VM address.
192	* @param pPage The physical page tracking structure.
193	* @param GCPhys The address of the page.
194	*
195	* @remarks Called from within the PGM critical section.
196	*/
197	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys)
198	{
199	switch (pPage->u2State)
200	{
201	case PGM_PAGE_STATE_WRITE_MONITORED:
202	pPage->fWrittenTo = true;
203	pPage->u2State = PGM_PAGE_STATE_WRITE_ALLOCATED;
204	/* fall thru */
205	case PGM_PAGE_STATE_ALLOCATED:
206	return VINF_SUCCESS;
207
208	/*
209	* Zero pages can be dummy pages for MMIO or reserved memory,
210	* so we need to check the flags before joining cause with
211	* shared page replacement.
212	*/
213	case PGM_PAGE_STATE_ZERO:
214	if ( PGM_PAGE_IS_MMIO(pPage)
215	\|\| PGM_PAGE_IS_RESERVED(pPage))
216	return VERR_PGM_PHYS_PAGE_RESERVED;
217	/* fall thru */
218	case PGM_PAGE_STATE_SHARED:
219	return pgmPhysAllocPage(pVM, pPage, GCPhys);
220	}
221	}
222
223
224	#ifdef IN_RING3
225
226	/**
227	* Tree enumeration callback for dealing with age rollover.
228	* It will perform a simple compression of the current age.
229	*/
230	static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
231	{
232	/* ASSMES iNow = 4 */
233	PPGMCHUNKR3MAPPING pChunk = (PPGMCHUNKR3MAPPING)pNode;
234	if (pChunk->iAge >= UINT32_C(0xffffff00))
235	pChunk->iAge = 3;
236	else if (pChunk->iAge >= UINT32_C(0xfffff000))
237	pChunk->iAge = 2;
238	else if (pChunk->iAge)
239	pChunk->iAge = 1;
240	return 0;
241	}
242
243
244	/**
245	* Tree enumeration callback that updates the chunks that have
246	* been used since the last
247	*/
248	static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
249	{
250	PPGMCHUNKR3MAPPING pChunk = (PPGMCHUNKR3MAPPING)pNode;
251	if (!pChunk->iAge)
252	{
253	PVM pVM = (PVM)pvUser;
254	RTAvllU32Remove(&pVM->pgm.s.R3ChunkTlb.pAgeTree, pChunk->AgeCore.Key);
255	pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.R3ChunkTlb.iNow;
256	RTAvllU32Insert(&pVM->pgm.s.R3ChunkTlb.pAgeTree, &pChunk->AgeCore);
257	}
258
259	return 0;
260	}
261
262
263	/**
264	* Performs ageing of the ring-3 chunk mappings.
265	*
266	* @param pVM The VM handle.
267	*/
268	PGMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
269	{
270	pVM->pgm.s.R3ChunkMap.AgeingCountdown = RT_MIN(pVM->pgm.s.R3ChunkMap.cMax / 4, 1024);
271	pVM->pgm.s.R3ChunkMap.iNow++;
272	if (pVM->pgm.s.R3ChunkMap.iNow == 0)
273	{
274	pVM->pgm.s.R3ChunkMap.iNow = 20;
275	RTAvlU32DoWithAll(&pVM->pgm.s.R3ChunkMap.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingRolloverCallback, NULL);
276	}
277	RTAvlU32DoWithAll(&pVM->pgm.s.R3ChunkMap.pTree, true /fFromLeft/, pgmR3PhysChunkAgeingCallback, pVM);
278	}
279
280
281	/**
282	* The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
283	*/
284	typedef struct PGMR3PHYSCHUNKUNMAPCB
285	{
286	PVM pVM; /*< The VM handle. /
287	PPGMR3CHUNKMAP pChunk; /*< The chunk to unmap. /
288	} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
289
290
291	/**
292	* Callback used to find the mapping that's been unused for
293	* the longest time.
294	*/
295	static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
296	{
297	do
298	{
299	PPGMR3CHUNKMAP pChunk = (PPGMR3CHUNKMAP)((uint8_t *)pNode - RT_OFFSETOF(PGMR3CHUNKMAP, AgeCore));
300	if ( pChunk->iAge
301	&& !pChunk->cRefs)
302	{
303	/*
304	* Check that it's not in any of the TLBs.
305	*/
306	PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
307	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.R3ChunkTlb->aEntries); i++)
308	if (pVM->pgm.s.R3ChunkTlb->aEntries[i].pChunk == pChunk)
309	{
310	pChunk = NULL;
311	break;
312	}
313	if (pChunk)
314	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.CTXSUFF(PhysTlb)->aEntries); i++)
315	if (pVM->pgm.s.CTXSUFF(PhysTlb)->aEntries[i].pChunk == pChunk)
316	{
317	pChunk = NULL;
318	break;
319	}
320	if (pChunk)
321	{
322	((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
323	return 1; /* done */
324	}
325	}
326
327	/* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
328	pNode = pNode->pList;
329	} while (pNode);
330	return 0;
331	}
332
333
334	/**
335	* Finds a good candidate for unmapping when the ring-3 mapping cache is full.
336	*
337	* The candidate will not be part of any TLBs, so no need to flush
338	* anything afterwards.
339	*
340	* @returns Chunk id.
341	* @param pVM The VM handle.
342	*/
343	int pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
344	{
345	/*
346	* Do tree ageing first?
347	*/
348	if (pVM->pgm.s.R3ChunkMap.AgeingCountdown-- == 0)
349	pgmR3PhysChunkAgeing(pVM);
350
351	/*
352	* Enumerate the age tree starting with the left most node.
353	*/
354	PGMR3PHYSCHUNKUNMAPCB Args;
355	Args.pVM = pVM;
356	Args.pChunk = NULL;
357	if (RTAvlU32DoWithAll(&pVM->pgm.s.R3ChunkMap.pAgeTree, true /fFromLeft/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
358	return Args.pChunk->idChunk;
359	return INT32_MAX;
360	}
361
362
363	/**
364	* Maps the given chunk into the ring-3 mapping cache.
365	*
366	* This will call ring-0.
367	*
368	* @returns VBox status code.
369	* @param pVM The VM handle.
370	* @param idChunk The chunk in question.
371	* @param ppChunk Where to store the chunk tracking structure.
372	*
373	* @remarks Called from within the PGM critical section.
374	*/
375	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAPPING ppChunk)
376	{
377	/*
378	* Allocate a new tracking structure first.
379	*/
380	#if 0 /* for later when we've got a separate mapping method for ring-0. */
381	PPGMCHUNKR3MAPPING pChunk = (PPGMCHUNKR3MAPPING)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
382	#else
383	PPGMCHUNKR3MAPPING pChunk = (PPGMCHUNKR3MAPPING)MMHyperAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
384	#endif
385	AssertReturn(pChunk, VERR_NO_MEMORY);
386	pChunk->Core.Key = idChunk;
387	pChunk->pv = NULL;
388	pChunk->cRefs = 0;
389	pChunk->iAge = 0;
390
391	/*
392	* Request the ring-0 part to map the chunk in question and if
393	* necessary unmap another one to make space in the mapping cache.
394	*/
395	PGMMAPCHUNKREQ Req;
396	Req.pvR3 = NULL;
397	Req.idChunkMap = idChunck;
398	Req.idChunkUnmap = INT32_MAX;
399	if (pVM->pgm.R3ChunkMap.c >= pVM->pgm.R3ChunkMap.cMax)
400	Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
401	/** @todo SUPCallVMMR0Ex needs to support in+out or similar. */
402	int rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_PGM_MAP_CHUNK, &Req, sizeof(Req));
403	if (VBOX_SUCCESS(rc))
404	{
405	/*
406	* Update the tree.
407	*/
408	/* insert the new one. */
409	AssertPtr(Req.pvR3);
410	pChunk->pv = Req.pvR3;
411	bool fRc = RTAvlU32Insert(&pVM->pgm.s.R3ChunkMap.Tree, &pChunk->Core);
412	AssertRelease(fRc);
413	pVM->pgm.s.R3ChunkMap.c++;
414
415	/* remove the unmapped one. */
416	if (Req.idChunkUnmap != INT32_MAX)
417	{
418	PPGMCHUNKR3MAPPING pUnmappedChunk = (PPGMCHUNKR3MAPPING)RTAvlU32Remove(&pVM->pgm.s.R3ChunkMap.Tree, Req.idChunkUnmap);
419	AssertRelease(pUnmappedChunk);
420	pUnmappedChunk->pv = NULL;
421	pUnmappedChunk->Key = INT32_MAX;
422	#if 0 /* for later when we've got a separate mapping method for ring-0. */
423	MMR3HeapFree(pUnmappedChunk);
424	#else
425	MMHyperFree(pVM, pUnmappedChunk);
426	#endif
427	pVM->pgm.R3ChunkMap.c--;
428	}
429	}
430	else
431	{
432	AssertRC(rc);
433	#if 0 /* for later when we've got a separate mapping method for ring-0. */
434	MMR3HeapFree(pChunk);
435	#else
436	MMHyperFree(pVM, pChunk);
437	#endif
438	pChunk = NULL;
439	}
440
441	*ppChunk = pChunk;
442	return rc;
443	}
444	#endif /* IN_RING3 */
445
446
447	/**
448	* Maps a page into the current virtual address space so it can be accessed.
449	*
450	* @returns VBox status code.
451	* @retval VINF_SUCCESS on success.
452	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
453	*
454	* @param pVM The VM address.
455	* @param pPage The physical page tracking structure.
456	* @param GCPhys The address of the page.
457	* @param ppMap Where to store the address of the mapping tracking structure.
458	* @param ppv Where to store the mapping address of the page. The page
459	* offset is masked off!
460	*
461	* @remarks Called from within the PGM critical section.
462	*/
463	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv)
464	{
465	#ifdef IN_GC
466	/*
467	* Just some sketchy GC code.
468	*/
469	*ppMap = NULL;
470	RTHCPHYS HCPhys = pPage->HCPhys & PGM_HCPHYS_PAGE_MASK;
471	Assert(HCPhys != pVM->pgm.s.HCPhysZeroPg)
472	return PGMGCDynMapHCPage(pVM, HCPhys, ppv);
473
474	#else /* IN_RING3 \|\| IN_RING0 */
475
476	/**
477	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
478	* @returns Chunk TLB index.
479	* @param idChunk The Chunk ID.
480	*/
481	#define PGM_R3CHUNKTLB_IDX(idChunk) ( (idChunk) & (PGM_R3CHUNKTLB_ENTRIES - 1) )
482
483	/*
484	* Find/make Chunk TLB entry for the mapping chunk.
485	*/
486	PPGMR3CHUNK pChunk;
487	const uint32_t idChunk = PGM_PAGE_GET_PAGEID(pPage) >> XXX_CHUNKID_SHIFT;
488	PGMR3CHUNKTLBE pTlbe = &pVM->pgm.s.R3ChunkTlb.aEntries[PGM_R3CHUNKTLB_IDX(idChunk)];
489	if (pTlbe->idChunk == idChunk)
490	{
491	STAM_COUNTER_INC(&pVM->pgm.s.StatR3ChunkTlbHits);
492	pChunk = pTlbe->pChunk;
493	}
494	else
495	{
496	STAM_COUNTER_INC(&pVM->pgm.s.StatR3ChunkTlbMisses);
497
498	/*
499	* Find the chunk, map it if necessary.
500	*/
501	pChunk = (PPGMR3CHUNK)RTAvlU32Get(&pVM->pgm.s.R3ChunkMap.Tree, idChunk);
502	if (!pChunk)
503	{
504	#ifdef IN_RING0
505	int rc = VMMR0CallHost(pVM, VMMCALLHOST_PGM_MAP_CHUNK, idChunk);
506	AssertRCReturn(rc, rc);
507	pChunk = (PPGMR3CHUNK)RTAvlU32Get(&pVM->pgm.s.R3ChunkMap.Tree, idChunk);
508	Assert(pChunk);
509	#else
510	int rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
511	if (VBOX_FAILURE(rc))
512	return rc;
513	#endif
514	}
515
516	/*
517	* Enter it into the Chunk TLB.
518	*/
519	pTlbe->idChunk = idChunk;
520	pTlbe->pChunk = pChunk;
521	pChunk->iAge = 0;
522	}
523
524	ppv = (uint8_t )pMap->pv + (iPage << PAGE_SHIFT);
525	*ppMap = pChunk;
526	return VINF_SUCCESS;
527	#endif /* IN_RING3 */
528	}
529
530
531	/**
532	* Calculates the index of a guest page in the Physical TLB.
533	* @returns Physical TLB index.
534	* @param GCPhys The guest physical address.
535	*/
536	#define PGM_R3PHYSTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_R3PHYSTLB_ENTRIES - 1) )
537
538	#if defined(IN_RING3) \|\| defined(IN_RING0)
539	# define PGM_PHYSTLB_IDX(GCPhys) PGM_R3PHYSTLB_IDX(GCPhys)
540	# define PGMPHYSTLBE PGMR3PHYSTLBE
541	#else /* IN_GC */
542	# define PGM_PHYSTLB_IDX(GCPhys) PGM_GCPHYSTLB_IDX(GCPhys)
543	# define PGMPHYSTLBE PGMGCPHYSTLBE
544	#endif
545
546
547	/**
548	* Load a guest page into the ring-3 physical TLB.
549	*
550	* @returns VBox status code.
551	* @retval VINF_SUCCESS on success
552	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
553	* @param pPGM The PGM instance pointer.
554	* @param GCPhys The guest physical address in question.
555	*/
556	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys)
557	{
558	STAM_COUNTER_INC(&pPGM->StatR3PhysTlbMisses);
559
560	/*
561	* Find the ram range.
562	* 99.8% of requests are expected to be in the first range.
563	*/
564	PPGMRAMRANGE pRam = CTXSUFF(pPGM->pRamRanges);
565	RTGCPHYS off = GCPhys - pRam->GCPhys;
566	if (RT_UNLIKELY(off >= pRam->cb))
567	{
568	do
569	{
570	pRam = CTXSUFF(pRam->pNext);
571	if (!pRam)
572	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
573	off = GCPhys - pRam->GCPhys;
574	} while (off >= pRam->cb);
575	}
576
577	/*
578	* Map the page.
579	* Make a special case for the zero page as it is kind of special.
580	*/
581	PPGMPAGE pPage = &pRam->aPages[off >> PAGE_SHIFT];
582	PPGMR3PHYSTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PHYSTLB_IDX(GCPhys)];
583	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ZERO)
584	{
585	void *pv;
586	PPGMPAGEMAP pMap;
587	int rc = pgmPhysPageMap(pVM, pPage, GCPhys, &pMap, &pv);
588	if (VBOX_FAILURE(rc))
589	return rc;
590	pTlbe->pMap = pMap;
591	pTlbe->pv = pv;
592	}
593	else
594	{
595	Assert(PGM_PAGE_GET_HCPHYS(pPage) == pPGM->HCPhysZeroPg);
596	pTlbe->pMap = NULL;
597	pTlbe->pv = pPGM->pvZeroPgR3;
598	}
599	pTlbe->pPage = pPage;
600	return VINF_SUCCESS;
601	}
602
603
604	/**
605	* Queries the Physical TLB entry for a physical guest page,
606	* attemting to load the TLB entry if necessary.
607	*
608	* @returns VBox status code.
609	* @retval VINF_SUCCESS on success
610	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
611	* @param pPgm The PGM instance handle.
612	* @param GCPhys The address of the guest page.
613	* @param ppTlbe Where to store the pointer to the TLB entry.
614	*/
615	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPgm, RTGCPHYS GCPhys, PPPGMPHYSTLBE ppTlbe)
616	{
617	int rc;
618	PGMPHYSTLBE pTlbe = &pPgm->CTXSUFF(PhysTlb).aEntries[PGM_PHYSTLB_IDX(GCPhys)];
619	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
620	{
621	STAM_COUNTER_INC(&pPgm->StatR3PhysTlbHits);
622	rc = VINF_SUCCESS;
623	}
624	else
625	rc = pgmPhysPageLoadIntoTlb(pVM, GCPhys);
626	*ppTlbe = pTlbe;
627	return rc;
628	}
629
630
631	#endif /* NEW_PHYS_CODE */
632
633
634	/**
635	* Requests the mapping of a guest page into the current context.
636	*
637	* This API should only be used for very short term, as it will consume
638	* scarse resources (R0 and GC) in the mapping cache. When you're done
639	* with the page, call PGMPhysGCPhys2CCPtrRelease() ASAP to release it.
640	*
641	* @returns VBox status code.
642	* @retval VINF_SUCCESS on success.
643	* @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical backing.
644	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
645	*
646	* @param pVM The VM handle.
647	* @param GCPhys The guest physical address of the page that should be mapped.
648	* @param ppv Where to store the address corresponding to GCPhys.
649	*
650	* @remark Avoid calling this API from within critical sections (other than
651	* the PGM one) because of the deadlock risk.
652	*/
653	PGMDECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv)
654	{
655	# ifdef NEW_PHYS_CODE
656	int rc = pgmLock(pVM);
657	AssertRCReturn(rc);
658
659	#ifdef IN_GC
660	/* Until a physical TLB is implemented for GC, let PGMGCDynMapGCPageEx handle it. */
661	return PGMGCDynMapGCPageEx(pVM, GCPhys, ppv);
662
663	#else
664	/*
665	* Query the Physical TLB entry for the page (may fail).
666	*/
667	PGMPHYSTLBE pTlbe;
668	int rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
669	if (RT_SUCCESS(rc))
670	{
671	/*
672	* If the page is shared, the zero page, or being write monitored
673	* it must be converted to an page that's writable if possible.
674	*/
675	PPGMPAGE pPage = pTlbe->pPage;
676	if (RT_UNLIKELY(pPage->u2State != PGM_PAGE_STATE_ALLOCATED))
677	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
678	if (RT_SUCCESS(rc))
679	{
680	/*
681	* Now, just perform the locking and calculate the return address.
682	*/
683	PPGMPAGEMAP pMap = pTlbe->pMap;
684	pMap->cRefs++;
685	if (RT_LIKELY(pPage->cLocks != PGM_PAGE_MAX_LOCKS))
686	if (RT_UNLIKELY(++pPage->cLocks == PGM_PAGE_MAX_LOCKS))
687	{
688	AssertMsgFailed(("%VGp is entering permanent locked state!\n", GCPhys));
689	pMap->cRefs++; /* Extra ref to prevent it from going away. */
690	}
691
692	ppv = (void )((uintptr_t)pTlbe->pv \| (GCPhys & PAGE_OFFSET_MASK));
693	}
694	}
695
696	pgmUnlock(pVM);
697	return rc;
698
699	#endif /* IN_RING3 \|\| IN_RING0 */
700
701	#else
702	/*
703	* Temporary fallback code.
704	*/
705	# ifdef IN_GC
706	return PGMGCDynMapGCPageEx(pVM, GCPhys, ppv);
707	# else
708	return PGMPhysGCPhys2HCPtr(pVM, GCPhys, 1, ppv);
709	# endif
710	#endif
711	}
712
713
714	/**
715	* Release the mapping of a guest page.
716	*
717	* This is the counterpart to the PGMPhysGCPhys2CCPtr.
718	*
719	* @param pVM The VM handle.
720	* @param GCPhys The address that was mapped using PGMPhysGCPhys2CCPtr.
721	* @param pv The address that PGMPhysGCPhys2CCPtr returned.
722	*/
723	PGMDECL(void) PGMPhysGCPhys2CCPtrRelease(PVM pVM, RTGCPHYS GCPhys, void *pv)
724	{
725	#ifdef NEW_PHYS_CODE
726	#ifdef IN_GC
727	/* currently nothing to do here. */
728	/* --- postponed
729	#elif defined(IN_RING0)
730	*/
731
732	#else /* IN_RING3 */
733	pgmLock(pVM);
734
735	/*
736	* Try the Physical TLB cache.
737	* There's a high likely hood that this will work out since it's a short-term lock.
738	*/
739	PPGMR3PHYSTLBE pTlbe = &pVM->pgm.s.R3PhysTlb.aEntries[PGM_R3PHYSTLB_IDX(GCPhys)];
740	if (RT_LIKELY(pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK)))
741	{
742	PPGMPAGE pPage = pTlbe->pPage;
743	Assert(PGM_PAGE_IS_NORMAL(pPage));
744	Assert(pPage->cLocks >= 1);
745	if (pPage->cLocks != PGM_PAGE_MAX_LOCKS)
746	pPage->cLocks--;
747
748	PPGMR3CHUNK pChunk = pTlbe->pChunk;
749	Assert(pChunk->cRefs >= 1);
750	pChunk->cRefs--;
751	pChunk->iAge = 0;
752	}
753	else
754	{
755	/*
756	* Find the page and unlock it.
757	*/
758	PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
759	RTGCPHYS off = GCPhys - pRam->GCPhys;
760	if (RT_UNLIKELY(off >= pRam->cb))
761	{
762	do
763	{
764	pRam = CTXSUFF(pRam->pNext);
765	AssertMsgRelease(pRam, ("GCPhys=%RGp\n", GCPhys));
766	off = GCPhys - pRam->GCPhys;
767	} while (off >= pRam->cb);
768	}
769	PPGMPAGE pPage = &pRam->aPages[off >> PAGE_SHIFT];
770	Assert(PGM_PAGE_IS_NORMAL(pTlbe->pPage));
771	Assert(pPage->cLocks >= 1);
772	if (pPage->cLocks != PGM_PAGE_MAX_LOCKS)
773	pPage->cLocks--;
774
775	/*
776	* Now find the chunk mapping and unlock it.
777	*/
778	PPGMR3CHUNK pChunk;
779	const uint32_t idChunk = PGM_PAGE_GET_PAGEID(pPage) >> XXX_CHUNKID_SHIFT;
780	PGMR3CHUNKTLBE pTlbe = &pVM->pgm.s.R3ChunkTlb.aEntries[PGM_R3CHUNKTLB_IDX(idChunk)];
781	if (pTlbe->idChunk == idChunk)
782	pChunk = pTlbe->pChunk;
783	else
784	{
785	pChunk = (PPGMR3CHUNK)RTAvlU32Get(&pVM->pgm.s.R3ChunkMap.Tree, idChunk);
786	AssertMsgRelease(pChunk, ("GCPhys=%RGp\n", GCPhys));
787	pChunk->iAge = 0;
788	}
789	Assert(pChunk->cRefs >= 1);
790	pChunk->cRefs--;
791	}
792
793	pgmUnlock(pVM);
794	#endif /* IN_RING3 */
795	#else
796	NOREF(pVM);
797	NOREF(GCPhys);
798	NOREF(pv);
799	#endif
800	}
801
802
803	/**
804	* Converts a GC physical address to a HC pointer.
805	*
806	* @returns VINF_SUCCESS on success.
807	* @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
808	* page but has no physical backing.
809	* @returns VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid
810	* GC physical address.
811	* @returns VERR_PGM_GCPHYS_RANGE_CROSSES_BOUNDARY if the range crosses
812	* a dynamic ram chunk boundary
813	* @param pVM The VM handle.
814	* @param GCPhys The GC physical address to convert.
815	* @param cbRange Physical range
816	* @param pHCPtr Where to store the HC pointer on success.
817	*/
818	PGMDECL(int) PGMPhysGCPhys2HCPtr(PVM pVM, RTGCPHYS GCPhys, RTUINT cbRange, PRTHCPTR pHCPtr)
819	{
820	#ifdef PGM_DYNAMIC_RAM_ALLOC
821	if ((GCPhys & PGM_DYNAMIC_CHUNK_BASE_MASK) != ((GCPhys+cbRange-1) & PGM_DYNAMIC_CHUNK_BASE_MASK))
822	{
823	AssertMsgFailed(("PGMPhysGCPhys2HCPtr %VGp - %VGp crosses a chunk boundary!!\n", GCPhys, GCPhys+cbRange));
824	LogRel(("PGMPhysGCPhys2HCPtr %VGp - %VGp crosses a chunk boundary!!\n", GCPhys, GCPhys+cbRange));
825	return VERR_PGM_GCPHYS_RANGE_CROSSES_BOUNDARY;
826	}
827	#endif
828
829	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
830	pRam;
831	pRam = CTXSUFF(pRam->pNext))
832	{
833	RTGCPHYS off = GCPhys - pRam->GCPhys;
834	if (off < pRam->cb)
835	{
836	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
837	{
838	unsigned iPage = off >> PAGE_SHIFT;
839	if (RT_UNLIKELY(!(pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK)))
840	{
841	#ifdef IN_RING3
842	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
843	#else
844	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
845	#endif
846	if (rc != VINF_SUCCESS)
847	return rc;
848	}
849	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
850	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
851	return VINF_SUCCESS;
852	}
853	if (pRam->pvHC)
854	{
855	#ifndef PGM_IGNORE_RAM_FLAGS_RESERVED
856	if (!(pRam->aHCPhys[off >> PAGE_SHIFT] & MM_RAM_FLAGS_RESERVED))
857	#endif
858	{
859	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + off);
860	return VINF_SUCCESS;
861	}
862	}
863	return VERR_PGM_PHYS_PAGE_RESERVED;
864	}
865	}
866	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
867	}
868
869
870	/**
871	* Validates a HC pointer.
872	*
873	* @returns true if valid.
874	* @returns false if invalid.
875	* @param pVM The VM handle.
876	* @param HCPtr The pointer to validate.
877	*/
878	PGMDECL(bool) PGMPhysIsHCPtrValid(PVM pVM, RTHCPTR HCPtr)
879	{
880	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
881	pRam;
882	pRam = CTXSUFF(pRam->pNext))
883	{
884	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
885	{
886	/** @note this is quite slow */
887	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
888	{
889	if (CTXSUFF(pRam->pavHCChunk)[iChunk])
890	{
891	RTHCUINTPTR off = (RTHCUINTPTR)HCPtr - (RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk];
892	if (off < PGM_DYNAMIC_CHUNK_SIZE)
893	return true;
894	}
895	}
896	}
897	else if (pRam->pvHC)
898	{
899	RTHCUINTPTR off = (RTHCUINTPTR)HCPtr - (RTHCUINTPTR)pRam->pvHC;
900
901	if (off < pRam->cb)
902	return true;
903	}
904	}
905	return false;
906	}
907
908
909	/**
910	* Converts a HC pointer to a GC physical address.
911	*
912	* @returns VINF_SUCCESS on success.
913	* @returns VERR_INVALID_POINTER if the pointer is not within the
914	* GC physical memory.
915	* @param pVM The VM handle.
916	* @param HCPtr The HC pointer to convert.
917	* @param pGCPhys Where to store the GC physical address on success.
918	*/
919	PGMDECL(int) PGMPhysHCPtr2GCPhys(PVM pVM, RTHCPTR HCPtr, PRTGCPHYS pGCPhys)
920	{
921	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
922	pRam;
923	pRam = CTXSUFF(pRam->pNext))
924	{
925	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
926	{
927	/** @note this is quite slow */
928	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
929	{
930	if (CTXSUFF(pRam->pavHCChunk)[iChunk])
931	{
932	RTHCUINTPTR off = (RTHCUINTPTR)HCPtr - (RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk];
933	if (off < PGM_DYNAMIC_CHUNK_SIZE)
934	{
935	pGCPhys = pRam->GCPhys + iChunkPGM_DYNAMIC_CHUNK_SIZE + off;
936	return VINF_SUCCESS;
937	}
938	}
939	}
940	}
941	else if (pRam->pvHC)
942	{
943	RTHCUINTPTR off = (RTHCUINTPTR)HCPtr - (RTHCUINTPTR)pRam->pvHC;
944	if (off < pRam->cb)
945	{
946	*pGCPhys = pRam->GCPhys + off;
947	return VINF_SUCCESS;
948	}
949	}
950	}
951	return VERR_INVALID_POINTER;
952	}
953
954
955	/**
956	* Converts a HC pointer to a GC physical address.
957	*
958	* @returns VINF_SUCCESS on success.
959	* @returns VERR_PGM_PHYS_PAGE_RESERVED it it's a valid GC physical
960	* page but has no physical backing.
961	* @returns VERR_INVALID_POINTER if the pointer is not within the
962	* GC physical memory.
963	* @param pVM The VM handle.
964	* @param HCPtr The HC pointer to convert.
965	* @param pHCPhys Where to store the HC physical address on success.
966	*/
967	PGMDECL(int) PGMPhysHCPtr2HCPhys(PVM pVM, RTHCPTR HCPtr, PRTHCPHYS pHCPhys)
968	{
969	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
970	pRam;
971	pRam = CTXSUFF(pRam->pNext))
972	{
973	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
974	{
975	/** @note this is quite slow */
976	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
977	{
978	if (CTXSUFF(pRam->pavHCChunk)[iChunk])
979	{
980	RTHCUINTPTR off = (RTHCUINTPTR)HCPtr - (RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[iChunk];
981	if (off < PGM_DYNAMIC_CHUNK_SIZE)
982	{
983	RTHCPHYS HCPhys = pRam->aHCPhys[off >> PAGE_SHIFT];
984	#ifndef PGM_IGNORE_RAM_FLAGS_RESERVED
985	if (!(HCPhys & MM_RAM_FLAGS_RESERVED))
986	#endif
987	{
988	*pHCPhys = (HCPhys & X86_PTE_PAE_PG_MASK)
989	\| (off & PAGE_OFFSET_MASK);
990	return VINF_SUCCESS;
991	}
992	return VERR_PGM_PHYS_PAGE_RESERVED;
993	}
994	}
995	}
996	}
997	else if (pRam->pvHC)
998	{
999	RTHCUINTPTR off = (RTHCUINTPTR)HCPtr - (RTHCUINTPTR)pRam->pvHC;
1000	if (off < pRam->cb)
1001	{
1002	RTHCPHYS HCPhys = pRam->aHCPhys[off >> PAGE_SHIFT];
1003	#ifndef PGM_IGNORE_RAM_FLAGS_RESERVED
1004	if (!(HCPhys & MM_RAM_FLAGS_RESERVED))
1005	#endif
1006	{
1007	*pHCPhys = (HCPhys & X86_PTE_PAE_PG_MASK)
1008	\| (off & PAGE_OFFSET_MASK);
1009	return VINF_SUCCESS;
1010	}
1011	return VERR_PGM_PHYS_PAGE_RESERVED;
1012	}
1013	}
1014	}
1015	return VERR_INVALID_POINTER;
1016	}
1017
1018
1019	/**
1020	* Validates a HC Physical address.
1021	*
1022	* This is an extremely slow API, don't use it!
1023	*
1024	* @returns true if valid.
1025	* @returns false if invalid.
1026	* @param pVM The VM handle.
1027	* @param HCPhys The physical address to validate.
1028	*/
1029	PGMDECL(bool) PGMPhysIsHCPhysValid(PVM pVM, RTHCPHYS HCPhys)
1030	{
1031	RTGCPHYS GCPhys;
1032	int rc = PGMPhysHCPhys2GCPhys(pVM, HCPhys, &GCPhys);
1033	return VBOX_SUCCESS(rc);
1034	}
1035
1036
1037	/**
1038	* Converts a HC physical address to a GC physical address.
1039	*
1040	* This is an extremely slow API, don't use it!
1041	*
1042	* @returns VINF_SUCCESS on success.
1043	* @returns VERR_INVALID_POINTER if the HC physical address is
1044	* not within the GC physical memory.
1045	* @param pVM The VM handle.
1046	* @param HCPhys The HC physical address to convert.
1047	* @param pGCPhys Where to store the GC physical address on success.
1048	*/
1049	PGMDECL(int) PGMPhysHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys)
1050	{
1051	unsigned off = HCPhys & PAGE_OFFSET_MASK;
1052	HCPhys &= X86_PTE_PAE_PG_MASK;
1053	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
1054	pRam;
1055	pRam = CTXSUFF(pRam->pNext))
1056	{
1057	if ( pRam->pvHC
1058	\|\| (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
1059	{
1060	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1061	while (iPage-- > 0)
1062	#ifndef PGM_IGNORE_RAM_FLAGS_RESERVED
1063	if ((pRam->aHCPhys[iPage] & (X86_PTE_PAE_PG_MASK \| MM_RAM_FLAGS_RESERVED)) == HCPhys)
1064	#else
1065	if ((pRam->aHCPhys[iPage] & (X86_PTE_PAE_PG_MASK)) == HCPhys)
1066	#endif
1067	{
1068	*pGCPhys = pRam->GCPhys + (iPage << PAGE_SHIFT) + off;
1069	return VINF_SUCCESS;
1070	}
1071	}
1072	}
1073	return VERR_INVALID_POINTER;
1074	}
1075
1076
1077	/**
1078	* Converts a HC physical address to a HC pointer.
1079	*
1080	* This is an extremely slow API, don't use it!
1081	*
1082	* @returns VINF_SUCCESS on success.
1083	* @returns VERR_INVALID_POINTER if the HC physical address is
1084	* not within the GC physical memory.
1085	* @param pVM The VM handle.
1086	* @param HCPhys The HC physical address to convert.
1087	* @param pHCPtr Where to store the HC pointer on success.
1088	*/
1089	PGMDECL(int) PGMPhysHCPhys2HCPtr(PVM pVM, RTHCPHYS HCPhys, PRTHCPTR pHCPtr)
1090	{
1091	unsigned off = HCPhys & PAGE_OFFSET_MASK;
1092	HCPhys &= X86_PTE_PAE_PG_MASK;
1093	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
1094	pRam;
1095	pRam = CTXSUFF(pRam->pNext))
1096	{
1097	if ( pRam->pvHC
1098	\|\| (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC))
1099	{
1100	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1101	while (iPage-- > 0)
1102	#ifndef PGM_IGNORE_RAM_FLAGS_RESERVED
1103	if ((pRam->aHCPhys[iPage] & (X86_PTE_PAE_PG_MASK \| MM_RAM_FLAGS_RESERVED)) == HCPhys)
1104	#else
1105	if ((pRam->aHCPhys[iPage] & (X86_PTE_PAE_PG_MASK)) == HCPhys)
1106	#endif
1107	{
1108	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1109	{
1110	unsigned idx = (iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT));
1111
1112	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)CTXSUFF(pRam->pavHCChunk)[idx] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK) + off);
1113	}
1114	else
1115	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvHC + (iPage << PAGE_SHIFT) + off);
1116
1117	return VINF_SUCCESS;
1118	}
1119	}
1120	}
1121	return VERR_INVALID_POINTER;
1122	}
1123
1124
1125	/**
1126	* Converts a guest pointer to a GC physical address.
1127	*
1128	* This uses the current CR3/CR0/CR4 of the guest.
1129	*
1130	* @returns VBox status code.
1131	* @param pVM The VM Handle
1132	* @param GCPtr The guest pointer to convert.
1133	* @param pGCPhys Where to store the HC physical address.
1134	*/
1135	PGMDECL(int) PGMPhysGCPtr2GCPhys(PVM pVM, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
1136	{
1137	return PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, NULL, pGCPhys);
1138	}
1139
1140
1141	/**
1142	* Converts a guest pointer to a HC physical address.
1143	*
1144	* This uses the current CR3/CR0/CR4 of the guest.
1145	*
1146	* @returns VBox status code.
1147	* @param pVM The VM Handle
1148	* @param GCPtr The guest pointer to convert.
1149	* @param pHCPhys Where to store the HC physical address.
1150	*/
1151	PGMDECL(int) PGMPhysGCPtr2HCPhys(PVM pVM, RTGCPTR GCPtr, PRTHCPHYS pHCPhys)
1152	{
1153	RTGCPHYS GCPhys;
1154	int rc = PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, NULL, &GCPhys);
1155	if (VBOX_SUCCESS(rc))
1156	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhys \| ((RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK), pHCPhys);
1157	return rc;
1158	}
1159
1160
1161	/**
1162	* Converts a guest pointer to a HC pointer.
1163	*
1164	* This uses the current CR3/CR0/CR4 of the guest.
1165	*
1166	* @returns VBox status code.
1167	* @param pVM The VM Handle
1168	* @param GCPtr The guest pointer to convert.
1169	* @param pHCPtr Where to store the HC virtual address.
1170	*/
1171	PGMDECL(int) PGMPhysGCPtr2HCPtr(PVM pVM, RTGCPTR GCPtr, PRTHCPTR pHCPtr)
1172	{
1173	RTGCPHYS GCPhys;
1174	int rc = PGM_GST_PFN(GetPage,pVM)(pVM, (RTGCUINTPTR)GCPtr, NULL, &GCPhys);
1175	if (VBOX_SUCCESS(rc))
1176	rc = PGMPhysGCPhys2HCPtr(pVM, GCPhys \| ((RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
1177	return rc;
1178	}
1179
1180
1181	/**
1182	* Converts a guest virtual address to a HC pointer by specfied CR3 and flags.
1183	*
1184	* @returns VBox status code.
1185	* @param pVM The VM Handle
1186	* @param GCPtr The guest pointer to convert.
1187	* @param cr3 The guest CR3.
1188	* @param fFlags Flags used for interpreting the PD correctly: X86_CR4_PSE and X86_CR4_PAE
1189	* @param pHCPtr Where to store the HC pointer.
1190	*
1191	* @remark This function is used by the REM at a time where PGM could
1192	* potentially not be in sync. It could also be used by a
1193	* future DBGF API to cpu state independent conversions.
1194	*/
1195	PGMDECL(int) PGMPhysGCPtr2HCPtrByGstCR3(PVM pVM, RTGCPTR GCPtr, uint32_t cr3, unsigned fFlags, PRTHCPTR pHCPtr)
1196	{
1197	/*
1198	* PAE or 32-bit?
1199	*/
1200	int rc;
1201	if (!(fFlags & X86_CR4_PAE))
1202	{
1203	PX86PD pPD;
1204	rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
1205	if (VBOX_SUCCESS(rc))
1206	{
1207	VBOXPDE Pde = pPD->a[(RTGCUINTPTR)GCPtr >> X86_PD_SHIFT];
1208	if (Pde.n.u1Present)
1209	{
1210	if ((fFlags & X86_CR4_PSE) && Pde.b.u1Size)
1211	{ /* (big page) */
1212	rc = PGMPhysGCPhys2HCPtr(pVM, (Pde.u & X86_PDE4M_PG_MASK) \| ((RTGCUINTPTR)GCPtr & X86_PAGE_4M_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
1213	}
1214	else
1215	{ /* (normal page) */
1216	PVBOXPT pPT;
1217	rc = PGM_GCPHYS_2_PTR(pVM, Pde.u & X86_PDE_PG_MASK, &pPT);
1218	if (VBOX_SUCCESS(rc))
1219	{
1220	VBOXPTE Pte = pPT->a[((RTGCUINTPTR)GCPtr >> X86_PT_SHIFT) & X86_PT_MASK];
1221	if (Pte.n.u1Present)
1222	return PGMPhysGCPhys2HCPtr(pVM, (Pte.u & X86_PTE_PG_MASK) \| ((RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
1223	rc = VERR_PAGE_NOT_PRESENT;
1224	}
1225	}
1226	}
1227	else
1228	rc = VERR_PAGE_TABLE_NOT_PRESENT;
1229	}
1230	}
1231	else
1232	{
1233	/** @todo long mode! */
1234	PX86PDPTR pPdptr;
1235	rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, &pPdptr);
1236	if (VBOX_SUCCESS(rc))
1237	{
1238	X86PDPE Pdpe = pPdptr->a[((RTGCUINTPTR)GCPtr >> X86_PDPTR_SHIFT) & X86_PDPTR_MASK];
1239	if (Pdpe.n.u1Present)
1240	{
1241	PX86PDPAE pPD;
1242	rc = PGM_GCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPD);
1243	if (VBOX_SUCCESS(rc))
1244	{
1245	X86PDEPAE Pde = pPD->a[((RTGCUINTPTR)GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK];
1246	if (Pde.n.u1Present)
1247	{
1248	if ((fFlags & X86_CR4_PSE) && Pde.b.u1Size)
1249	{ /* (big page) */
1250	rc = PGMPhysGCPhys2HCPtr(pVM, (Pde.u & X86_PDE4M_PAE_PG_MASK) \| ((RTGCUINTPTR)GCPtr & X86_PAGE_4M_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
1251	}
1252	else
1253	{ /* (normal page) */
1254	PX86PTPAE pPT;
1255	rc = PGM_GCPHYS_2_PTR(pVM, (Pde.u & X86_PDE_PAE_PG_MASK), &pPT);
1256	if (VBOX_SUCCESS(rc))
1257	{
1258	X86PTEPAE Pte = pPT->a[((RTGCUINTPTR)GCPtr >> X86_PT_PAE_SHIFT) & X86_PT_PAE_MASK];
1259	if (Pte.n.u1Present)
1260	return PGMPhysGCPhys2HCPtr(pVM, (Pte.u & X86_PTE_PAE_PG_MASK) \| ((RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
1261	rc = VERR_PAGE_NOT_PRESENT;
1262	}
1263	}
1264	}
1265	else
1266	rc = VERR_PAGE_TABLE_NOT_PRESENT;
1267	}
1268	}
1269	else
1270	rc = VERR_PAGE_TABLE_NOT_PRESENT;
1271	}
1272	}
1273	return rc;
1274	}
1275
1276
1277	#undef LOG_GROUP
1278	#define LOG_GROUP LOG_GROUP_PGM_PHYS_ACCESS
1279
1280
1281	#ifdef IN_RING3
1282	/**
1283	* Cache PGMPhys memory access
1284	*
1285	* @param pVM VM Handle.
1286	* @param pCache Cache structure pointer
1287	* @param GCPhys GC physical address
1288	* @param pbHC HC pointer corresponding to physical page
1289	*/
1290	static void pgmPhysCacheAdd(PVM pVM, PGMPHYSCACHE pCache, RTGCPHYS GCPhys, uint8_t pbHC)
1291	{
1292	uint32_t iCacheIndex;
1293
1294	GCPhys = PAGE_ADDRESS(GCPhys);
1295	pbHC = (uint8_t *)PAGE_ADDRESS(pbHC);
1296
1297	iCacheIndex = ((GCPhys >> PAGE_SHIFT) & PGM_MAX_PHYSCACHE_ENTRIES_MASK);
1298
1299	ASMBitSet(&pCache->aEntries, iCacheIndex);
1300
1301	pCache->Entry[iCacheIndex].GCPhys = GCPhys;
1302	pCache->Entry[iCacheIndex].pbHC = pbHC;
1303	}
1304	#endif
1305
1306	/**
1307	* Read physical memory.
1308	*
1309	* This API respects access handlers and MMIO. Use PGMPhysReadGCPhys() if you
1310	* want to ignore those.
1311	*
1312	* @param pVM VM Handle.
1313	* @param GCPhys Physical address start reading from.
1314	* @param pvBuf Where to put the read bits.
1315	* @param cbRead How many bytes to read.
1316	*/
1317	PGMDECL(void) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
1318	{
1319	#ifdef IN_RING3
1320	bool fGrabbedLock = false;
1321	#endif
1322
1323	AssertMsg(cbRead > 0, ("don't even think about reading zero bytes!\n"));
1324	if (cbRead == 0)
1325	return;
1326
1327	LogFlow(("PGMPhysRead: %VGp %d\n", GCPhys, cbRead));
1328
1329	#ifdef IN_RING3
1330	if (!VM_IS_EMT(pVM))
1331	{
1332	pgmLock(pVM);
1333	fGrabbedLock = true;
1334	}
1335	#endif
1336
1337	/*
1338	* Copy loop on ram ranges.
1339	*/
1340	PPGMRAMRANGE pCur = CTXSUFF(pVM->pgm.s.pRamRanges);
1341	for (;;)
1342	{
1343	/* Find range. */
1344	while (pCur && GCPhys > pCur->GCPhysLast)
1345	pCur = CTXSUFF(pCur->pNext);
1346	/* Inside range or not? */
1347	if (pCur && GCPhys >= pCur->GCPhys)
1348	{
1349	/*
1350	* Must work our way thru this page by page.
1351	*/
1352	RTGCPHYS off = GCPhys - pCur->GCPhys;
1353	while (off < pCur->cb)
1354	{
1355	unsigned iPage = off >> PAGE_SHIFT;
1356	size_t cb;
1357
1358	/* Physical chunk in dynamically allocated range not present? */
1359	if (RT_UNLIKELY(!(pCur->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK)))
1360	{
1361	/* Treat it as reserved; return zeros */
1362	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1363	if (cb >= cbRead)
1364	{
1365	memset(pvBuf, 0, cbRead);
1366	goto end;
1367	}
1368	memset(pvBuf, 0, cb);
1369	}
1370	else
1371	{
1372	RTHCPHYS HCPhys = pCur->aHCPhys[iPage];
1373	switch (HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_ROM))
1374	{
1375	/*
1376	* Normal memory or ROM.
1377	*/
1378	case 0:
1379	case MM_RAM_FLAGS_ROM:
1380	case MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_RESERVED:
1381	//case MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2: /* = shadow */ - //MMIO2 isn't in the mask.
1382	case MM_RAM_FLAGS_PHYSICAL_WRITE:
1383	case MM_RAM_FLAGS_MMIO2 \| MM_RAM_FLAGS_PHYSICAL_WRITE: // MMIO2 isn't in the mask.
1384	case MM_RAM_FLAGS_VIRTUAL_WRITE:
1385	{
1386	#ifdef IN_GC
1387	void *pvSrc = NULL;
1388	PGMGCDynMapHCPage(pVM, HCPhys & X86_PTE_PAE_PG_MASK, &pvSrc);
1389	pvSrc = (char *)pvSrc + (off & PAGE_OFFSET_MASK);
1390	#else
1391	void *pvSrc = PGMRAMRANGE_GETHCPTR(pCur, off)
1392	#endif
1393	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1394	if (cb >= cbRead)
1395	{
1396	#if defined(IN_RING3) && defined(PGM_PHYSMEMACCESS_CACHING)
1397	if (cbRead <= 4)
1398	pgmPhysCacheAdd(pVM, &pVM->pgm.s.pgmphysreadcache, GCPhys, (uint8_t*)pvSrc);
1399	#endif /* IN_RING3 && PGM_PHYSMEMACCESS_CACHING */
1400	memcpy(pvBuf, pvSrc, cbRead);
1401	goto end;
1402	}
1403	memcpy(pvBuf, pvSrc, cb);
1404	break;
1405	}
1406
1407	/*
1408	* All reserved, nothing there.
1409	*/
1410	case MM_RAM_FLAGS_RESERVED:
1411	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1412	if (cb >= cbRead)
1413	{
1414	memset(pvBuf, 0, cbRead);
1415	goto end;
1416	}
1417	memset(pvBuf, 0, cb);
1418	break;
1419
1420	/*
1421	* Physical handler.
1422	*/
1423	case MM_RAM_FLAGS_PHYSICAL_ALL:
1424	case MM_RAM_FLAGS_MMIO2 \| MM_RAM_FLAGS_PHYSICAL_ALL: /** r=bird: MMIO2 isn't in the mask! */
1425	{
1426	int rc = VINF_PGM_HANDLER_DO_DEFAULT;
1427	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1428	#ifdef IN_RING3 /** @todo deal with this in GC and R0! */
1429
1430	/* find and call the handler */
1431	PPGMPHYSHANDLER pNode = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.pTreesHC->PhysHandlers, GCPhys);
1432	if (pNode && pNode->pfnHandlerR3)
1433	{
1434	size_t cbRange = pNode->Core.KeyLast - GCPhys + 1;
1435	if (cbRange < cb)
1436	cb = cbRange;
1437	if (cb > cbRead)
1438	cb = cbRead;
1439
1440	void *pvSrc = PGMRAMRANGE_GETHCPTR(pCur, off)
1441
1442	/** @note Dangerous assumption that HC handlers don't do anything that really requires an EMT lock! */
1443	rc = pNode->pfnHandlerR3(pVM, GCPhys, pvSrc, pvBuf, cb, PGMACCESSTYPE_READ, pNode->pvUserR3);
1444	}
1445	#endif /* IN_RING3 */
1446	if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
1447	{
1448	#ifdef IN_GC
1449	void *pvSrc = NULL;
1450	PGMGCDynMapHCPage(pVM, HCPhys & X86_PTE_PAE_PG_MASK, &pvSrc);
1451	pvSrc = (char *)pvSrc + (off & PAGE_OFFSET_MASK);
1452	#else
1453	void *pvSrc = PGMRAMRANGE_GETHCPTR(pCur, off)
1454	#endif
1455
1456	if (cb >= cbRead)
1457	{
1458	memcpy(pvBuf, pvSrc, cbRead);
1459	goto end;
1460	}
1461	memcpy(pvBuf, pvSrc, cb);
1462	}
1463	else if (cb >= cbRead)
1464	goto end;
1465	break;
1466	}
1467
1468	case MM_RAM_FLAGS_VIRTUAL_ALL:
1469	{
1470	int rc = VINF_PGM_HANDLER_DO_DEFAULT;
1471	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1472	#ifdef IN_RING3 /** @todo deal with this in GC and R0! */
1473	/* Search the whole tree for matching physical addresses (rather expensive!) */
1474	PPGMVIRTHANDLER pNode;
1475	unsigned iPage;
1476	int rc2 = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &pNode, &iPage);
1477	if (VBOX_SUCCESS(rc2) && pNode->pfnHandlerHC)
1478	{
1479	size_t cbRange = pNode->Core.KeyLast - GCPhys + 1;
1480	if (cbRange < cb)
1481	cb = cbRange;
1482	if (cb > cbRead)
1483	cb = cbRead;
1484	RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pNode->GCPtr & PAGE_BASE_GC_MASK)
1485	+ (iPage << PAGE_SHIFT) + (off & PAGE_OFFSET_MASK);
1486
1487	void *pvSrc = PGMRAMRANGE_GETHCPTR(pCur, off)
1488
1489	/** @note Dangerous assumption that HC handlers don't do anything that really requires an EMT lock! */
1490	rc = pNode->pfnHandlerHC(pVM, (RTGCPTR)GCPtr, pvSrc, pvBuf, cb, PGMACCESSTYPE_READ, 0);
1491	}
1492	#endif /* IN_RING3 */
1493	if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
1494	{
1495	#ifdef IN_GC
1496	void *pvSrc = NULL;
1497	PGMGCDynMapHCPage(pVM, HCPhys & X86_PTE_PAE_PG_MASK, &pvSrc);
1498	pvSrc = (char *)pvSrc + (off & PAGE_OFFSET_MASK);
1499	#else
1500	void *pvSrc = PGMRAMRANGE_GETHCPTR(pCur, off)
1501	#endif
1502	if (cb >= cbRead)
1503	{
1504	memcpy(pvBuf, pvSrc, cbRead);
1505	goto end;
1506	}
1507	memcpy(pvBuf, pvSrc, cb);
1508	}
1509	else if (cb >= cbRead)
1510	goto end;
1511	break;
1512	}
1513
1514	/*
1515	* The rest needs to be taken more carefully.
1516	*/
1517	default:
1518	#if 1 /** @todo r=bird: Can you do this properly please. */
1519	/** @todo Try MMIO; quick hack */
1520	if (cbRead <= 4 && IOMMMIORead(pVM, GCPhys, (uint32_t *)pvBuf, cbRead) == VINF_SUCCESS)
1521	goto end;
1522	#endif
1523
1524	/** @todo fix me later. */
1525	AssertReleaseMsgFailed(("Unknown read at %VGp size %d implement the complex physical reading case %x\n",
1526	GCPhys, cbRead,
1527	HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_ROM)));
1528	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1529	break;
1530	}
1531	}
1532	cbRead -= cb;
1533	off += cb;
1534	pvBuf = (char *)pvBuf + cb;
1535	}
1536
1537	GCPhys = pCur->GCPhysLast + 1;
1538	}
1539	else
1540	{
1541	LogFlow(("PGMPhysRead: Unassigned %VGp size=%d\n", GCPhys, cbRead));
1542
1543	/*
1544	* Unassigned address space.
1545	*/
1546	size_t cb;
1547	if ( !pCur
1548	\|\| (cb = pCur->GCPhys - GCPhys) >= cbRead)
1549	{
1550	memset(pvBuf, 0, cbRead);
1551	goto end;
1552	}
1553
1554	memset(pvBuf, 0, cb);
1555	cbRead -= cb;
1556	pvBuf = (char *)pvBuf + cb;
1557	GCPhys += cb;
1558	}
1559	}
1560	end:
1561	#ifdef IN_RING3
1562	if (fGrabbedLock)
1563	pgmUnlock(pVM);
1564	#endif
1565	return;
1566	}
1567
1568	/**
1569	* Write to physical memory.
1570	*
1571	* This API respects access handlers and MMIO. Use PGMPhysReadGCPhys() if you
1572	* want to ignore those.
1573	*
1574	* @param pVM VM Handle.
1575	* @param GCPhys Physical address to write to.
1576	* @param pvBuf What to write.
1577	* @param cbWrite How many bytes to write.
1578	*/
1579	PGMDECL(void) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
1580	{
1581	#ifdef IN_RING3
1582	bool fGrabbedLock = false;
1583	#endif
1584
1585	AssertMsg(!pVM->pgm.s.fNoMorePhysWrites, ("Calling PGMPhysWrite after pgmR3Save()!\n"));
1586	AssertMsg(cbWrite > 0, ("don't even think about writing zero bytes!\n"));
1587	if (cbWrite == 0)
1588	return;
1589
1590	LogFlow(("PGMPhysWrite: %VGp %d\n", GCPhys, cbWrite));
1591
1592	#ifdef IN_RING3
1593	if (!VM_IS_EMT(pVM))
1594	{
1595	pgmLock(pVM);
1596	fGrabbedLock = true;
1597	}
1598	#endif
1599	/*
1600	* Copy loop on ram ranges.
1601	*/
1602	PPGMRAMRANGE pCur = CTXSUFF(pVM->pgm.s.pRamRanges);
1603	for (;;)
1604	{
1605	/* Find range. */
1606	while (pCur && GCPhys > pCur->GCPhysLast)
1607	pCur = CTXSUFF(pCur->pNext);
1608	/* Inside range or not? */
1609	if (pCur && GCPhys >= pCur->GCPhys)
1610	{
1611	/*
1612	* Must work our way thru this page by page.
1613	*/
1614	unsigned off = GCPhys - pCur->GCPhys;
1615	while (off < pCur->cb)
1616	{
1617	unsigned iPage = off >> PAGE_SHIFT;
1618
1619	/* Physical chunk in dynamically allocated range not present? */
1620	if (RT_UNLIKELY(!(pCur->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK)))
1621	{
1622	int rc;
1623	#ifdef IN_RING3
1624	if (fGrabbedLock)
1625	{
1626	pgmUnlock(pVM);
1627	rc = pgmr3PhysGrowRange(pVM, GCPhys);
1628	if (rc == VINF_SUCCESS)
1629	PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite); /* try again; can't assume pCur is still valid (paranoia) */
1630	return;
1631	}
1632	rc = pgmr3PhysGrowRange(pVM, GCPhys);
1633	#else
1634	rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
1635	#endif
1636	if (rc != VINF_SUCCESS)
1637	goto end;
1638	}
1639
1640	size_t cb;
1641	RTHCPHYS HCPhys = pCur->aHCPhys[iPage];
1642	/** @todo r=bird: missing MM_RAM_FLAGS_ROM here, we shall not allow anyone to overwrite the ROM! */
1643	switch (HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2 \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE))
1644	{
1645	/*
1646	* Normal memory, MMIO2 or writable shadow ROM.
1647	*/
1648	case 0:
1649	case MM_RAM_FLAGS_MMIO2:
1650	case MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2: /* shadow rom */
1651	{
1652	#ifdef IN_GC
1653	void *pvDst = NULL;
1654	PGMGCDynMapHCPage(pVM, HCPhys & X86_PTE_PAE_PG_MASK, &pvDst);
1655	pvDst = (char *)pvDst + (off & PAGE_OFFSET_MASK);
1656	#else
1657	void *pvDst = PGMRAMRANGE_GETHCPTR(pCur, off)
1658	#endif
1659	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1660	if (cb >= cbWrite)
1661	{
1662	#if defined(IN_RING3) && defined(PGM_PHYSMEMACCESS_CACHING)
1663	if (cbWrite <= 4)
1664	pgmPhysCacheAdd(pVM, &pVM->pgm.s.pgmphyswritecache, GCPhys, (uint8_t*)pvDst);
1665	#endif /* IN_RING3 && PGM_PHYSMEMACCESS_CACHING */
1666	memcpy(pvDst, pvBuf, cbWrite);
1667	goto end;
1668	}
1669	memcpy(pvDst, pvBuf, cb);
1670	break;
1671	}
1672
1673	/*
1674	* All reserved, nothing there.
1675	*/
1676	case MM_RAM_FLAGS_RESERVED:
1677	case MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO2:
1678	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1679	if (cb >= cbWrite)
1680	goto end;
1681	break;
1682
1683	/*
1684	* Physical handler.
1685	*/
1686	case MM_RAM_FLAGS_PHYSICAL_ALL:
1687	case MM_RAM_FLAGS_PHYSICAL_WRITE:
1688	case MM_RAM_FLAGS_MMIO2 \| MM_RAM_FLAGS_PHYSICAL_ALL:
1689	case MM_RAM_FLAGS_MMIO2 \| MM_RAM_FLAGS_PHYSICAL_WRITE:
1690	{
1691	int rc = VINF_PGM_HANDLER_DO_DEFAULT;
1692	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1693	#ifdef IN_RING3 /** @todo deal with this in GC and R0! */
1694	/* find and call the handler */
1695	PPGMPHYSHANDLER pNode = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.pTreesHC->PhysHandlers, GCPhys);
1696	if (pNode && pNode->pfnHandlerR3)
1697	{
1698	size_t cbRange = pNode->Core.KeyLast - GCPhys + 1;
1699	if (cbRange < cb)
1700	cb = cbRange;
1701	if (cb > cbWrite)
1702	cb = cbWrite;
1703
1704	void *pvDst = PGMRAMRANGE_GETHCPTR(pCur, off)
1705
1706	/** @note Dangerous assumption that HC handlers don't do anything that really requires an EMT lock! */
1707	rc = pNode->pfnHandlerR3(pVM, GCPhys, pvDst, (void *)pvBuf, cb, PGMACCESSTYPE_WRITE, pNode->pvUserR3);
1708	}
1709	#endif /* IN_RING3 */
1710	if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
1711	{
1712	#ifdef IN_GC
1713	void *pvDst = NULL;
1714	PGMGCDynMapHCPage(pVM, HCPhys & X86_PTE_PAE_PG_MASK, &pvDst);
1715	pvDst = (char *)pvDst + (off & PAGE_OFFSET_MASK);
1716	#else
1717	void *pvDst = PGMRAMRANGE_GETHCPTR(pCur, off)
1718	#endif
1719	if (cb >= cbWrite)
1720	{
1721	memcpy(pvDst, pvBuf, cbWrite);
1722	goto end;
1723	}
1724	memcpy(pvDst, pvBuf, cb);
1725	}
1726	else if (cb >= cbWrite)
1727	goto end;
1728	break;
1729	}
1730
1731	case MM_RAM_FLAGS_VIRTUAL_ALL:
1732	case MM_RAM_FLAGS_VIRTUAL_WRITE:
1733	{
1734	int rc = VINF_PGM_HANDLER_DO_DEFAULT;
1735	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1736	#ifdef IN_RING3
1737	/** @todo deal with this in GC and R0! */
1738	/* Search the whole tree for matching physical addresses (rather expensive!) */
1739	PPGMVIRTHANDLER pNode;
1740	unsigned iPage;
1741	int rc2 = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &pNode, &iPage);
1742	if (VBOX_SUCCESS(rc2) && pNode->pfnHandlerHC)
1743	{
1744	size_t cbRange = pNode->Core.KeyLast - GCPhys + 1;
1745	if (cbRange < cb)
1746	cb = cbRange;
1747	if (cb > cbWrite)
1748	cb = cbWrite;
1749	RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pNode->GCPtr & PAGE_BASE_GC_MASK)
1750	+ (iPage << PAGE_SHIFT) + (off & PAGE_OFFSET_MASK);
1751
1752	void *pvDst = PGMRAMRANGE_GETHCPTR(pCur, off)
1753
1754	/** @note Dangerous assumption that HC handlers don't do anything that really requires an EMT lock! */
1755	rc = pNode->pfnHandlerHC(pVM, (RTGCPTR)GCPtr, pvDst, (void *)pvBuf, cb, PGMACCESSTYPE_WRITE, 0);
1756	}
1757	#endif /* IN_RING3 */
1758	if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
1759	{
1760	#ifdef IN_GC
1761	void *pvDst = NULL;
1762	PGMGCDynMapHCPage(pVM, HCPhys & X86_PTE_PAE_PG_MASK, &pvDst);
1763	pvDst = (char *)pvDst + (off & PAGE_OFFSET_MASK);
1764	#else
1765	void *pvDst = PGMRAMRANGE_GETHCPTR(pCur, off)
1766	#endif
1767	if (cb >= cbWrite)
1768	{
1769	memcpy(pvDst, pvBuf, cbWrite);
1770	goto end;
1771	}
1772	memcpy(pvDst, pvBuf, cb);
1773	}
1774	else if (cb >= cbWrite)
1775	goto end;
1776	break;
1777	}
1778
1779	/*
1780	* Physical write handler + virtual write handler.
1781	* Consider this a quick workaround for the CSAM + shadow caching problem.
1782	*
1783	* We hand it to the shadow caching first since it requires the unchanged
1784	* data. CSAM will have to put up with it already being changed.
1785	*/
1786	case MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE:
1787	{
1788	int rc = VINF_PGM_HANDLER_DO_DEFAULT;
1789	cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
1790	#ifdef IN_RING3 /** @todo deal with this in GC and R0! */
1791	/* 1. The physical handler */
1792	PPGMPHYSHANDLER pPhysNode = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.pTreesHC->PhysHandlers, GCPhys);
1793	if (pPhysNode && pPhysNode->pfnHandlerR3)
1794	{
1795	size_t cbRange = pPhysNode->Core.KeyLast - GCPhys + 1;
1796	if (cbRange < cb)
1797	cb = cbRange;
1798	if (cb > cbWrite)
1799	cb = cbWrite;
1800
1801	void *pvDst = PGMRAMRANGE_GETHCPTR(pCur, off)
1802
1803	/** @note Dangerous assumption that HC handlers don't do anything that really requires an EMT lock! */
1804	rc = pPhysNode->pfnHandlerR3(pVM, GCPhys, pvDst, (void *)pvBuf, cb, PGMACCESSTYPE_WRITE, pPhysNode->pvUserR3);
1805	}
1806
1807	/* 2. The virtual handler (will see incorrect data) */
1808	PPGMVIRTHANDLER pVirtNode;
1809	unsigned iPage;
1810	int rc2 = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys, &pVirtNode, &iPage);
1811	if (VBOX_SUCCESS(rc2) && pVirtNode->pfnHandlerHC)
1812	{
1813	size_t cbRange = pVirtNode->Core.KeyLast - GCPhys + 1;
1814	if (cbRange < cb)
1815	cb = cbRange;
1816	if (cb > cbWrite)
1817	cb = cbWrite;
1818	RTGCUINTPTR GCPtr = ((RTGCUINTPTR)pVirtNode->GCPtr & PAGE_BASE_GC_MASK)
1819	+ (iPage << PAGE_SHIFT) + (off & PAGE_OFFSET_MASK);
1820
1821	void *pvDst = PGMRAMRANGE_GETHCPTR(pCur, off)
1822
1823	/** @note Dangerous assumption that HC handlers don't do anything that really requires an EMT lock! */
1824	rc2 = pVirtNode->pfnHandlerHC(pVM, (RTGCPTR)GCPtr, pvDst, (void *)pvBuf, cb, PGMACCESSTYPE_WRITE, 0);
1825	if ( ( rc2 != VINF_PGM_HANDLER_DO_DEFAULT
1826	&& rc == VINF_PGM_HANDLER_DO_DEFAULT)
1827	\|\| ( VBOX_FAILURE(rc2)
1828	&& VBOX_SUCCESS(rc)))
1829	rc = rc2;
1830	}
1831	#endif /* IN_RING3 */
1832	if (rc == VINF_PGM_HANDLER_DO_DEFAULT)
1833	{
1834	#ifdef IN_GC
1835	void *pvDst = NULL;
1836	PGMGCDynMapHCPage(pVM, HCPhys & X86_PTE_PAE_PG_MASK, &pvDst);
1837	pvDst = (char *)pvDst + (off & PAGE_OFFSET_MASK);
1838	#else
1839	void *pvDst = PGMRAMRANGE_GETHCPTR(pCur, off)
1840	#endif
1841	if (cb >= cbWrite)
1842	{
1843	memcpy(pvDst, pvBuf, cbWrite);
1844	goto end;
1845	}
1846	memcpy(pvDst, pvBuf, cb);
1847	}
1848	else if (cb >= cbWrite)
1849	goto end;
1850	break;
1851	}
1852
1853
1854	/*
1855	* The rest needs to be taken more carefully.
1856	*/
1857	default:
1858	#if 1 /** @todo r=bird: Can you do this properly please. */
1859	/** @todo Try MMIO; quick hack */
1860	if (cbWrite <= 4 && IOMMMIOWrite(pVM, GCPhys, (uint32_t )pvBuf, cbWrite) == VINF_SUCCESS)
1861	goto end;
1862	#endif
1863
1864	/** @todo fix me later. */
1865	AssertReleaseMsgFailed(("Unknown write at %VGp size %d implement the complex physical writing case %x\n",
1866	GCPhys, cbWrite,
1867	(HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2 \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE))));
1868	/* skip the write */
1869	cb = cbWrite;
1870	break;
1871	}
1872
1873	cbWrite -= cb;
1874	off += cb;
1875	pvBuf = (const char *)pvBuf + cb;
1876	}
1877
1878	GCPhys = pCur->GCPhysLast + 1;
1879	}
1880	else
1881	{
1882	/*
1883	* Unassigned address space.
1884	*/
1885	size_t cb;
1886	if ( !pCur
1887	\|\| (cb = pCur->GCPhys - GCPhys) >= cbWrite)
1888	goto end;
1889
1890	cbWrite -= cb;
1891	pvBuf = (const char *)pvBuf + cb;
1892	GCPhys += cb;
1893	}
1894	}
1895	end:
1896	#ifdef IN_RING3
1897	if (fGrabbedLock)
1898	pgmUnlock(pVM);
1899	#endif
1900	return;
1901	}
1902
1903	#ifndef IN_GC /* Ring 0 & 3 only */
1904
1905	/**
1906	* Read from guest physical memory by GC physical address, bypassing
1907	* MMIO and access handlers.
1908	*
1909	* @returns VBox status.
1910	* @param pVM VM handle.
1911	* @param pvDst The destination address.
1912	* @param GCPhysSrc The source address (GC physical address).
1913	* @param cb The number of bytes to read.
1914	*/
1915	PGMDECL(int) PGMPhysReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb)
1916	{
1917	/*
1918	* Anything to be done?
1919	*/
1920	if (!cb)
1921	return VINF_SUCCESS;
1922
1923	/*
1924	* Loop ram ranges.
1925	*/
1926	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
1927	pRam;
1928	pRam = pRam->CTXSUFF(pNext))
1929	{
1930	RTGCPHYS off = GCPhysSrc - pRam->GCPhys;
1931	if (off < pRam->cb)
1932	{
1933	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1934	{
1935	/* Copy page by page as we're not dealing with a linear HC range. */
1936	for (;;)
1937	{
1938	/* convert */
1939	void *pvSrc;
1940	int rc = PGMRamGCPhys2HCPtr(pVM, pRam, GCPhysSrc, &pvSrc);
1941	if (VBOX_FAILURE(rc))
1942	return rc;
1943
1944	/* copy */
1945	size_t cbRead = PAGE_SIZE - ((RTGCUINTPTR)GCPhysSrc & PAGE_OFFSET_MASK);
1946	if (cbRead >= cb)
1947	{
1948	memcpy(pvDst, pvSrc, cb);
1949	return VINF_SUCCESS;
1950	}
1951	memcpy(pvDst, pvSrc, cbRead);
1952
1953	/* next */
1954	cb -= cbRead;
1955	pvDst = (uint8_t *)pvDst + cbRead;
1956	GCPhysSrc += cbRead;
1957	}
1958	}
1959	else if (pRam->pvHC)
1960	{
1961	/* read */
1962	size_t cbRead = pRam->cb - off;
1963	if (cbRead >= cb)
1964	{
1965	memcpy(pvDst, (uint8_t *)pRam->pvHC + off, cb);
1966	return VINF_SUCCESS;
1967	}
1968	memcpy(pvDst, (uint8_t *)pRam->pvHC + off, cbRead);
1969
1970	/* next */
1971	cb -= cbRead;
1972	pvDst = (uint8_t *)pvDst + cbRead;
1973	GCPhysSrc += cbRead;
1974	}
1975	else
1976	return VERR_PGM_PHYS_PAGE_RESERVED;
1977	}
1978	else if (GCPhysSrc < pRam->GCPhysLast)
1979	break;
1980	}
1981	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
1982	}
1983
1984
1985	/**
1986	* Write to guest physical memory referenced by GC pointer.
1987	* Write memory to GC physical address in guest physical memory.
1988	*
1989	* This will bypass MMIO and access handlers.
1990	*
1991	* @returns VBox status.
1992	* @param pVM VM handle.
1993	* @param GCPhysDst The GC physical address of the destination.
1994	* @param pvSrc The source buffer.
1995	* @param cb The number of bytes to write.
1996	*/
1997	PGMDECL(int) PGMPhysWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb)
1998	{
1999	/*
2000	* Anything to be done?
2001	*/
2002	if (!cb)
2003	return VINF_SUCCESS;
2004
2005	LogFlow(("PGMPhysWriteGCPhys: %VGp %d\n", GCPhysDst, cb));
2006
2007	/*
2008	* Loop ram ranges.
2009	*/
2010	for (PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
2011	pRam;
2012	pRam = pRam->CTXSUFF(pNext))
2013	{
2014	RTGCPHYS off = GCPhysDst - pRam->GCPhys;
2015	if (off < pRam->cb)
2016	{
2017	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2018	{
2019	/* Copy page by page as we're not dealing with a linear HC range. */
2020	for (;;)
2021	{
2022	/* convert */
2023	void *pvDst;
2024	int rc = PGMRamGCPhys2HCPtr(pVM, pRam, GCPhysDst, &pvDst);
2025	if (VBOX_FAILURE(rc))
2026	return rc;
2027
2028	/* copy */
2029	size_t cbWrite = PAGE_SIZE - ((RTGCUINTPTR)GCPhysDst & PAGE_OFFSET_MASK);
2030	if (cbWrite >= cb)
2031	{
2032	memcpy(pvDst, pvSrc, cb);
2033	return VINF_SUCCESS;
2034	}
2035	memcpy(pvDst, pvSrc, cbWrite);
2036
2037	/* next */
2038	cb -= cbWrite;
2039	pvSrc = (uint8_t *)pvSrc + cbWrite;
2040	GCPhysDst += cbWrite;
2041	}
2042	}
2043	else if (pRam->pvHC)
2044	{
2045	/* write */
2046	size_t cbWrite = pRam->cb - off;
2047	if (cbWrite >= cb)
2048	{
2049	memcpy((uint8_t *)pRam->pvHC + off, pvSrc, cb);
2050	return VINF_SUCCESS;
2051	}
2052	memcpy((uint8_t *)pRam->pvHC + off, pvSrc, cbWrite);
2053
2054	/* next */
2055	cb -= cbWrite;
2056	GCPhysDst += cbWrite;
2057	pvSrc = (uint8_t *)pvSrc + cbWrite;
2058	}
2059	else
2060	return VERR_PGM_PHYS_PAGE_RESERVED;
2061	}
2062	else if (GCPhysDst < pRam->GCPhysLast)
2063	break;
2064	}
2065	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
2066	}
2067
2068
2069	/**
2070	* Read from guest physical memory referenced by GC pointer.
2071	*
2072	* This function uses the current CR3/CR0/CR4 of the guest and will
2073	* bypass access handlers and not set any accessed bits.
2074	*
2075	* @returns VBox status.
2076	* @param pVM VM handle.
2077	* @param pvDst The destination address.
2078	* @param GCPtrSrc The source address (GC pointer).
2079	* @param cb The number of bytes to read.
2080	*/
2081	PGMDECL(int) PGMPhysReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
2082	{
2083	/*
2084	* Anything to do?
2085	*/
2086	if (!cb)
2087	return VINF_SUCCESS;
2088
2089	/*
2090	* Optimize reads within a single page.
2091	*/
2092	if (((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
2093	{
2094	void *pvSrc;
2095	int rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrSrc, &pvSrc);
2096	if (VBOX_FAILURE(rc))
2097	return rc;
2098	memcpy(pvDst, pvSrc, cb);
2099	return VINF_SUCCESS;
2100	}
2101
2102	/*
2103	* Page by page.
2104	*/
2105	for (;;)
2106	{
2107	/* convert */
2108	void *pvSrc;
2109	int rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrSrc, &pvSrc);
2110	if (VBOX_FAILURE(rc))
2111	return rc;
2112
2113	/* copy */
2114	size_t cbRead = PAGE_SIZE - ((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK);
2115	if (cbRead >= cb)
2116	{
2117	memcpy(pvDst, pvSrc, cb);
2118	return VINF_SUCCESS;
2119	}
2120	memcpy(pvDst, pvSrc, cbRead);
2121
2122	/* next */
2123	cb -= cbRead;
2124	pvDst = (uint8_t *)pvDst + cbRead;
2125	GCPtrSrc += cbRead;
2126	}
2127	}
2128
2129
2130	/**
2131	* Write to guest physical memory referenced by GC pointer.
2132	*
2133	* This function uses the current CR3/CR0/CR4 of the guest and will
2134	* bypass access handlers and not set dirty or accessed bits.
2135	*
2136	* @returns VBox status.
2137	* @param pVM VM handle.
2138	* @param GCPtrDst The destination address (GC pointer).
2139	* @param pvSrc The source address.
2140	* @param cb The number of bytes to write.
2141	*/
2142	PGMDECL(int) PGMPhysWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
2143	{
2144	/*
2145	* Anything to do?
2146	*/
2147	if (!cb)
2148	return VINF_SUCCESS;
2149
2150	LogFlow(("PGMPhysWriteGCPtr: %VGv %d\n", GCPtrDst, cb));
2151
2152	/*
2153	* Optimize writes within a single page.
2154	*/
2155	if (((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
2156	{
2157	void *pvDst;
2158	int rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrDst, &pvDst);
2159	if (VBOX_FAILURE(rc))
2160	return rc;
2161	memcpy(pvDst, pvSrc, cb);
2162	return VINF_SUCCESS;
2163	}
2164
2165	/*
2166	* Page by page.
2167	*/
2168	for (;;)
2169	{
2170	/* convert */
2171	void *pvDst;
2172	int rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrDst, &pvDst);
2173	if (VBOX_FAILURE(rc))
2174	return rc;
2175
2176	/* copy */
2177	size_t cbWrite = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
2178	if (cbWrite >= cb)
2179	{
2180	memcpy(pvDst, pvSrc, cb);
2181	return VINF_SUCCESS;
2182	}
2183	memcpy(pvDst, pvSrc, cbWrite);
2184
2185	/* next */
2186	cb -= cbWrite;
2187	pvSrc = (uint8_t *)pvSrc + cbWrite;
2188	GCPtrDst += cbWrite;
2189	}
2190	}
2191
2192	/**
2193	* Read from guest physical memory referenced by GC pointer.
2194	*
2195	* This function uses the current CR3/CR0/CR4 of the guest and will
2196	* respect access handlers and set accessed bits.
2197	*
2198	* @returns VBox status.
2199	* @param pVM VM handle.
2200	* @param pvDst The destination address.
2201	* @param GCPtrSrc The source address (GC pointer).
2202	* @param cb The number of bytes to read.
2203	*/
2204	/** @todo use the PGMPhysReadGCPtr name and rename the unsafe one to something appropriate */
2205	PGMDECL(int) PGMPhysReadGCPtrSafe(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb)
2206	{
2207	RTGCPHYS GCPhys;
2208	RTGCUINTPTR offset;
2209	int rc;
2210
2211	/*
2212	* Anything to do?
2213	*/
2214	if (!cb)
2215	return VINF_SUCCESS;
2216
2217	LogFlow(("PGMPhysReadGCPtrSafe: %VGv %d\n", GCPtrSrc, cb));
2218
2219	/*
2220	* Optimize reads within a single page.
2221	*/
2222	if (((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
2223	{
2224	/* Convert virtual to physical address */
2225	offset = GCPtrSrc & PAGE_OFFSET_MASK;
2226	rc = PGMPhysGCPtr2GCPhys(pVM, GCPtrSrc, &GCPhys);
2227	AssertRCReturn(rc, rc);
2228
2229	/* mark the guest page as accessed. */
2230	rc = PGMGstModifyPage(pVM, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)(X86_PTE_A));
2231	AssertRC(rc);
2232
2233	PGMPhysRead(pVM, GCPhys + offset, pvDst, cb);
2234	return VINF_SUCCESS;
2235	}
2236
2237	/*
2238	* Page by page.
2239	*/
2240	for (;;)
2241	{
2242	/* Convert virtual to physical address */
2243	offset = GCPtrSrc & PAGE_OFFSET_MASK;
2244	rc = PGMPhysGCPtr2GCPhys(pVM, GCPtrSrc, &GCPhys);
2245	AssertRCReturn(rc, rc);
2246
2247	/* mark the guest page as accessed. */
2248	int rc = PGMGstModifyPage(pVM, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)(X86_PTE_A));
2249	AssertRC(rc);
2250
2251	/* copy */
2252	size_t cbRead = PAGE_SIZE - ((RTGCUINTPTR)GCPtrSrc & PAGE_OFFSET_MASK);
2253	if (cbRead >= cb)
2254	{
2255	PGMPhysRead(pVM, GCPhys + offset, pvDst, cb);
2256	return VINF_SUCCESS;
2257	}
2258	PGMPhysRead(pVM, GCPhys + offset, pvDst, cbRead);
2259
2260	/* next */
2261	cb -= cbRead;
2262	pvDst = (uint8_t *)pvDst + cbRead;
2263	GCPtrSrc += cbRead;
2264	}
2265	}
2266
2267
2268	/**
2269	* Write to guest physical memory referenced by GC pointer.
2270	*
2271	* This function uses the current CR3/CR0/CR4 of the guest and will
2272	* respect access handlers and set dirty and accessed bits.
2273	*
2274	* @returns VBox status.
2275	* @param pVM VM handle.
2276	* @param GCPtrDst The destination address (GC pointer).
2277	* @param pvSrc The source address.
2278	* @param cb The number of bytes to write.
2279	*/
2280	/** @todo use the PGMPhysWriteGCPtr name and rename the unsafe one to something appropriate */
2281	PGMDECL(int) PGMPhysWriteGCPtrSafe(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
2282	{
2283	RTGCPHYS GCPhys;
2284	RTGCUINTPTR offset;
2285	int rc;
2286
2287	/*
2288	* Anything to do?
2289	*/
2290	if (!cb)
2291	return VINF_SUCCESS;
2292
2293	LogFlow(("PGMPhysWriteGCPtrSafe: %VGv %d\n", GCPtrDst, cb));
2294
2295	/*
2296	* Optimize writes within a single page.
2297	*/
2298	if (((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
2299	{
2300	/* Convert virtual to physical address */
2301	offset = GCPtrDst & PAGE_OFFSET_MASK;
2302	rc = PGMPhysGCPtr2GCPhys(pVM, GCPtrDst, &GCPhys);
2303	AssertRCReturn(rc, rc);
2304
2305	/* mark the guest page as accessed and dirty. */
2306	rc = PGMGstModifyPage(pVM, GCPtrDst, 1, X86_PTE_A \| X86_PTE_D, ~(uint64_t)(X86_PTE_A \| X86_PTE_D));
2307	AssertRC(rc);
2308
2309	PGMPhysWrite(pVM, GCPhys + offset, pvSrc, cb);
2310	return VINF_SUCCESS;
2311	}
2312
2313	/*
2314	* Page by page.
2315	*/
2316	for (;;)
2317	{
2318	/* Convert virtual to physical address */
2319	offset = GCPtrDst & PAGE_OFFSET_MASK;
2320	rc = PGMPhysGCPtr2GCPhys(pVM, GCPtrDst, &GCPhys);
2321	AssertRCReturn(rc, rc);
2322
2323	/* mark the guest page as accessed and dirty. */
2324	rc = PGMGstModifyPage(pVM, GCPtrDst, 1, X86_PTE_A \| X86_PTE_D, ~(uint64_t)(X86_PTE_A \| X86_PTE_D));
2325	AssertRC(rc);
2326
2327	/* copy */
2328	size_t cbWrite = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
2329	if (cbWrite >= cb)
2330	{
2331	PGMPhysWrite(pVM, GCPhys + offset, pvSrc, cb);
2332	return VINF_SUCCESS;
2333	}
2334	PGMPhysWrite(pVM, GCPhys + offset, pvSrc, cbWrite);
2335
2336	/* next */
2337	cb -= cbWrite;
2338	pvSrc = (uint8_t *)pvSrc + cbWrite;
2339	GCPtrDst += cbWrite;
2340	}
2341	}
2342
2343	/**
2344	* Write to guest physical memory referenced by GC pointer and update the PTE.
2345	*
2346	* This function uses the current CR3/CR0/CR4 of the guest and will
2347	* bypass access handlers and set any dirty and accessed bits in the PTE.
2348	*
2349	* If you don't want to set the dirty bit, use PGMPhysWriteGCPtr().
2350	*
2351	* @returns VBox status.
2352	* @param pVM VM handle.
2353	* @param GCPtrDst The destination address (GC pointer).
2354	* @param pvSrc The source address.
2355	* @param cb The number of bytes to write.
2356	*/
2357	PGMDECL(int) PGMPhysWriteGCPtrDirty(PVM pVM, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
2358	{
2359	/*
2360	* Anything to do?
2361	*/
2362	if (!cb)
2363	return VINF_SUCCESS;
2364
2365	/*
2366	* Optimize writes within a single page.
2367	*/
2368	if (((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK) + cb <= PAGE_SIZE)
2369	{
2370	void *pvDst;
2371	int rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrDst, &pvDst);
2372	if (VBOX_FAILURE(rc))
2373	return rc;
2374	memcpy(pvDst, pvSrc, cb);
2375	rc = PGMGstModifyPage(pVM, GCPtrDst, cb, X86_PTE_A \| X86_PTE_D, ~(uint64_t)(X86_PTE_A \| X86_PTE_D));
2376	AssertRC(rc);
2377	return VINF_SUCCESS;
2378	}
2379
2380	/*
2381	* Page by page.
2382	*/
2383	for (;;)
2384	{
2385	/* convert */
2386	void *pvDst;
2387	int rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrDst, &pvDst);
2388	if (VBOX_FAILURE(rc))
2389	return rc;
2390
2391	/* mark the guest page as accessed and dirty. */
2392	rc = PGMGstModifyPage(pVM, GCPtrDst, 1, X86_PTE_A \| X86_PTE_D, ~(uint64_t)(X86_PTE_A \| X86_PTE_D));
2393	AssertRC(rc);
2394
2395	/* copy */
2396	size_t cbWrite = PAGE_SIZE - ((RTGCUINTPTR)GCPtrDst & PAGE_OFFSET_MASK);
2397	if (cbWrite >= cb)
2398	{
2399	memcpy(pvDst, pvSrc, cb);
2400	return VINF_SUCCESS;
2401	}
2402	memcpy(pvDst, pvSrc, cbWrite);
2403
2404	/* next */
2405	cb -= cbWrite;
2406	GCPtrDst += cbWrite;
2407	pvSrc = (char *)pvSrc + cbWrite;
2408	}
2409	}
2410
2411	#endif /* !IN_GC */
2412
2413
2414
2415	/**
2416	* Performs a read of guest virtual memory for instruction emulation.
2417	*
2418	* This will check permissions, raise exceptions and update the access bits.
2419	*
2420	* The current implementation will bypass all access handlers. It may later be
2421	* changed to at least respect MMIO.
2422	*
2423	*
2424	* @returns VBox status code suitable to scheduling.
2425	* @retval VINF_SUCCESS if the read was performed successfully.
2426	* @retval VINF_EM_RAW_GUEST_TRAP if an exception was raised but not dispatched yet.
2427	* @retval VINF_TRPM_XCPT_DISPATCHED if an exception was raised and dispatched.
2428	*
2429	* @param pVM The VM handle.
2430	* @param pCtxCore The context core.
2431	* @param pvDst Where to put the bytes we've read.
2432	* @param GCPtrSrc The source address.
2433	* @param cb The number of bytes to read. Not more than a page.
2434	*
2435	* @remark This function will dynamically map physical pages in GC. This may unmap
2436	* mappings done by the caller. Be careful!
2437	*/
2438	PGMDECL(int) PGMPhysInterpretedRead(PVM pVM, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb)
2439	{
2440	Assert(cb <= PAGE_SIZE);
2441
2442	/** @todo r=bird: This isn't perfect!
2443	* -# It's not checking for reserved bits being 1.
2444	* -# It's not correctly dealing with the access bit.
2445	* -# It's not respecting MMIO memory or any other access handlers.
2446	*/
2447	/*
2448	* 1. Translate virtual to physical. This may fault.
2449	* 2. Map the physical address.
2450	* 3. Do the read operation.
2451	* 4. Set access bits if required.
2452	*/
2453	int rc;
2454	unsigned cb1 = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
2455	if (cb <= cb1)
2456	{
2457	/*
2458	* Not crossing pages.
2459	*/
2460	RTGCPHYS GCPhys;
2461	uint64_t fFlags;
2462	rc = PGM_GST_PFN(GetPage,pVM)(pVM, GCPtrSrc, &fFlags, &GCPhys);
2463	if (VBOX_SUCCESS(rc))
2464	{
2465	/** @todo we should check reserved bits ... */
2466	void *pvSrc;
2467	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pvSrc);
2468	switch (rc)
2469	{
2470	case VINF_SUCCESS:
2471	Log(("PGMPhysInterpretedRead: pvDst=%p pvSrc=%p cb=%d\n", pvDst, (uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb));
2472	memcpy(pvDst, (uint8_t *)pvSrc + (GCPtrSrc & PAGE_OFFSET_MASK), cb);
2473	break;
2474	case VERR_PGM_PHYS_PAGE_RESERVED:
2475	case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
2476	memset(pvDst, 0, cb);
2477	break;
2478	default:
2479	return rc;
2480	}
2481
2482	/** @todo access bit emulation isn't 100% correct. */
2483	if (!(fFlags & X86_PTE_A))
2484	{
2485	rc = PGM_GST_PFN(ModifyPage,pVM)(pVM, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
2486	AssertRC(rc);
2487	}
2488	return VINF_SUCCESS;
2489	}
2490	}
2491	else
2492	{
2493	/*
2494	* Crosses pages.
2495	*/
2496	unsigned cb2 = cb - cb1;
2497	uint64_t fFlags1;
2498	RTGCPHYS GCPhys1;
2499	uint64_t fFlags2;
2500	RTGCPHYS GCPhys2;
2501	rc = PGM_GST_PFN(GetPage,pVM)(pVM, GCPtrSrc, &fFlags1, &GCPhys1);
2502	if (VBOX_SUCCESS(rc))
2503	rc = PGM_GST_PFN(GetPage,pVM)(pVM, GCPtrSrc + cb1, &fFlags2, &GCPhys2);
2504	if (VBOX_SUCCESS(rc))
2505	{
2506	/** @todo we should check reserved bits ... */
2507	AssertMsgFailed(("cb=%d cb1=%d cb2=%d GCPtrSrc=%VGv\n", cb, cb1, cb2, GCPtrSrc));
2508	void *pvSrc1;
2509	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys1, &pvSrc1);
2510	switch (rc)
2511	{
2512	case VINF_SUCCESS:
2513	memcpy(pvDst, (uint8_t *)pvSrc1 + (GCPtrSrc & PAGE_OFFSET_MASK), cb1);
2514	break;
2515	case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
2516	memset(pvDst, 0, cb1);
2517	break;
2518	default:
2519	return rc;
2520	}
2521
2522	void *pvSrc2;
2523	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys2, &pvSrc2);
2524	switch (rc)
2525	{
2526	case VINF_SUCCESS:
2527	memcpy((uint8_t *)pvDst + cb2, pvSrc2, cb2);
2528	break;
2529	case VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS:
2530	memset((uint8_t *)pvDst + cb2, 0, cb2);
2531	break;
2532	default:
2533	return rc;
2534	}
2535
2536	if (!(fFlags1 & X86_PTE_A))
2537	{
2538	rc = PGM_GST_PFN(ModifyPage,pVM)(pVM, GCPtrSrc, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
2539	AssertRC(rc);
2540	}
2541	if (!(fFlags2 & X86_PTE_A))
2542	{
2543	rc = PGM_GST_PFN(ModifyPage,pVM)(pVM, GCPtrSrc + cb1, 1, X86_PTE_A, ~(uint64_t)X86_PTE_A);
2544	AssertRC(rc);
2545	}
2546	return VINF_SUCCESS;
2547	}
2548	}
2549
2550	/*
2551	* Raise a #PF.
2552	*/
2553	uint32_t uErr;
2554
2555	/* Get the current privilege level. */
2556	uint32_t cpl = CPUMGetGuestCPL(pVM, pCtxCore);
2557	switch (rc)
2558	{
2559	case VINF_SUCCESS:
2560	uErr = (cpl >= 2) ? X86_TRAP_PF_RSVD \| X86_TRAP_PF_US : X86_TRAP_PF_RSVD;
2561	break;
2562
2563	case VERR_PAGE_NOT_PRESENT:
2564	case VERR_PAGE_TABLE_NOT_PRESENT:
2565	uErr = (cpl >= 2) ? X86_TRAP_PF_US : 0;
2566	break;
2567
2568	default:
2569	AssertMsgFailed(("rc=%Vrc GCPtrSrc=%VGv cb=%#x\n", rc, GCPtrSrc, cb));
2570	return rc;
2571	}
2572	Log(("PGMPhysInterpretedRead: GCPtrSrc=%VGv cb=%#x -> #PF(%#x)\n", GCPtrSrc, cb, uErr));
2573	return TRPMRaiseXcptErrCR2(pVM, pCtxCore, X86_XCPT_PF, uErr, GCPtrSrc);
2574	}
2575
2576	/// @todo PGMDECL(int) PGMPhysInterpretedWrite(PVM pVM, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb)
2577

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp@ 4592

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