PGMAllPool.cpp@ 19503

Last change on this file since 19503 was 19503, checked in by vboxsync, 16 years ago
Fixed r47022 regression
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 159.4 KB

Line
1	/* $Id: PGMAllPool.cpp 19503 2009-05-07 19:37:11Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	__BEGIN_DECLS
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	__END_DECLS
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pCpu The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
249	{
250	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	uShw.pPT->a[iShw].u = 0;
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	uShw.pPTPae->a[iShw].u = 0;
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	uShw.pPDPae->a[iShw+i].u = 0;
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pCpu
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	uShw.pPDPae->a[iShw2].u = 0;
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	uShw.pPTPae->a[iShw].u = 0;
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pCpu
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	uShw.pPTPae->a[iShw2].u = 0;
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	uShw.pPD->a[iShw].u = 0;
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pCpu
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	uShw.pPD->a[iShw2].u = 0;
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	uShw.pPD->a[iShw].u = 0;
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	uShw.pPDPae->a[iShw].u = 0;
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pCpu
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	uShw.pPDPae->a[iShw2].u = 0;
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	uShw.pPDPT->a[iShw].u = 0;
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pCpu
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	uShw.pPDPT->a[iShw2].u = 0;
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	uShw.pPDPae->a[iShw].u = 0;
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pCpu
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	uShw.pPDPae->a[iShw2].u = 0;
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	uShw.pPDPT->a[iShw].u = 0;
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pCpu
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	uShw.pPDPT->a[iShw2].u = 0;
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	uShw.pPML4->a[iShw].u = 0;
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pCpu
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	uShw.pPML4->a[iShw2].u = 0;
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pCpu The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pCpu->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pPage The page in question.
823	* @param pRegFrame Trap register frame.
824	* @param pCpu The disassembly info for the faulting instruction.
825	* @param pvFault The fault address.
826	*
827	* @remark The REP prefix check is left to the caller because of STOSD/W.
828	*/
829	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PPGMPOOLPAGE pPage, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
830	{
831	#ifndef IN_RC
832	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
833	if ( HWACCMHasPendingIrq(pVM)
834	&& (pRegFrame->rsp - pvFault) < 32)
835	{
836	/* Fault caused by stack writes while trying to inject an interrupt event. */
837	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
838	return true;
839	}
840	#else
841	NOREF(pVM); NOREF(pvFault);
842	#endif
843
844	switch (pCpu->pCurInstr->opcode)
845	{
846	/* call implies the actual push of the return address faulted */
847	case OP_CALL:
848	Log4(("pgmPoolMonitorIsReused: CALL\n"));
849	return true;
850	case OP_PUSH:
851	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
852	return true;
853	case OP_PUSHF:
854	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
855	return true;
856	case OP_PUSHA:
857	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
858	return true;
859	case OP_FXSAVE:
860	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
861	return true;
862	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
863	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
864	return true;
865	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
866	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
867	return true;
868	case OP_MOVSWD:
869	case OP_STOSWD:
870	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
871	&& pRegFrame->rcx >= 0x40
872	)
873	{
874	Assert(pCpu->mode == CPUMODE_64BIT);
875
876	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
877	return true;
878	}
879	return false;
880	}
881	if ( (pCpu->param1.flags & USE_REG_GEN32)
882	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
883	{
884	Log4(("pgmPoolMonitorIsReused: ESP\n"));
885	return true;
886	}
887
888	//if (pPage->fCR3Mix)
889	// return false;
890	return false;
891	}
892
893
894	/**
895	* Flushes the page being accessed.
896	*
897	* @returns VBox status code suitable for scheduling.
898	* @param pVM The VM handle.
899	* @param pVCpu The VMCPU handle.
900	* @param pPool The pool.
901	* @param pPage The pool page (head).
902	* @param pCpu The disassembly of the write instruction.
903	* @param pRegFrame The trap register frame.
904	* @param GCPhysFault The fault address as guest physical address.
905	* @param pvFault The fault address.
906	*/
907	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
908	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
909	{
910	/*
911	* First, do the flushing.
912	*/
913	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
914
915	/*
916	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
917	*/
918	uint32_t cbWritten;
919	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
920	if (RT_SUCCESS(rc2))
921	pRegFrame->rip += pCpu->opsize;
922	else if (rc2 == VERR_EM_INTERPRETER)
923	{
924	#ifdef IN_RC
925	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
926	{
927	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
928	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
929	rc = VINF_SUCCESS;
930	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
931	}
932	else
933	#endif
934	{
935	rc = VINF_EM_RAW_EMULATE_INSTR;
936	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
937	}
938	}
939	else
940	rc = rc2;
941
942	/* See use in pgmPoolAccessHandlerSimple(). */
943	PGM_INVL_GUEST_TLBS();
944
945	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
946	return rc;
947
948	}
949
950
951	/**
952	* Handles the STOSD write accesses.
953	*
954	* @returns VBox status code suitable for scheduling.
955	* @param pVM The VM handle.
956	* @param pPool The pool.
957	* @param pPage The pool page (head).
958	* @param pCpu The disassembly of the write instruction.
959	* @param pRegFrame The trap register frame.
960	* @param GCPhysFault The fault address as guest physical address.
961	* @param pvFault The fault address.
962	*/
963	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
964	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
965	{
966	Assert(pCpu->mode == CPUMODE_32BIT);
967
968	Log3(("pgmPoolAccessHandlerSTOSD\n"));
969
970	/*
971	* Increment the modification counter and insert it into the list
972	* of modified pages the first time.
973	*/
974	if (!pPage->cModifications++)
975	pgmPoolMonitorModifiedInsert(pPool, pPage);
976
977	/*
978	* Execute REP STOSD.
979	*
980	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
981	* write situation, meaning that it's safe to write here.
982	*/
983	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
984	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
985	while (pRegFrame->ecx)
986	{
987	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
988	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
989	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
990	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
991	#else
992	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
993	#endif
994	#ifdef IN_RC
995	(uint32_t )pu32 = pRegFrame->eax;
996	#else
997	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
998	#endif
999	pu32 += 4;
1000	GCPhysFault += 4;
1001	pRegFrame->edi += 4;
1002	pRegFrame->ecx--;
1003	}
1004	pRegFrame->rip += pCpu->opsize;
1005
1006	#ifdef IN_RC
1007	/* See use in pgmPoolAccessHandlerSimple(). */
1008	PGM_INVL_GUEST_TLBS();
1009	#endif
1010
1011	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1012	return VINF_SUCCESS;
1013	}
1014
1015
1016	/**
1017	* Handles the simple write accesses.
1018	*
1019	* @returns VBox status code suitable for scheduling.
1020	* @param pVM The VM handle.
1021	* @param pVCpu The VMCPU handle.
1022	* @param pPool The pool.
1023	* @param pPage The pool page (head).
1024	* @param pCpu The disassembly of the write instruction.
1025	* @param pRegFrame The trap register frame.
1026	* @param GCPhysFault The fault address as guest physical address.
1027	* @param pvFault The fault address.
1028	*/
1029	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
1030	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1031	{
1032	Log3(("pgmPoolAccessHandlerSimple\n"));
1033	/*
1034	* Increment the modification counter and insert it into the list
1035	* of modified pages the first time.
1036	*/
1037	if (!pPage->cModifications++)
1038	pgmPoolMonitorModifiedInsert(pPool, pPage);
1039
1040	/*
1041	* Clear all the pages. ASSUMES that pvFault is readable.
1042	*/
1043	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1044	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1045	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1046	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1047	#else
1048	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1049	#endif
1050
1051	/*
1052	* Interpret the instruction.
1053	*/
1054	uint32_t cb;
1055	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
1056	if (RT_SUCCESS(rc))
1057	pRegFrame->rip += pCpu->opsize;
1058	else if (rc == VERR_EM_INTERPRETER)
1059	{
1060	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1061	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
1062	rc = VINF_EM_RAW_EMULATE_INSTR;
1063	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1064	}
1065
1066	#ifdef IN_RC
1067	/*
1068	* Quick hack, with logging enabled we're getting stale
1069	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1070	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1071	* have to be fixed to support this. But that'll have to wait till next week.
1072	*
1073	* An alternative is to keep track of the changed PTEs together with the
1074	* GCPhys from the guest PT. This may proove expensive though.
1075	*
1076	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1077	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1078	*/
1079	PGM_INVL_GUEST_TLBS();
1080	#endif
1081
1082	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1083	return rc;
1084	}
1085
1086	/**
1087	* \#PF Handler callback for PT write accesses.
1088	*
1089	* @returns VBox status code (appropriate for GC return).
1090	* @param pVM VM Handle.
1091	* @param uErrorCode CPU Error code.
1092	* @param pRegFrame Trap register frame.
1093	* NULL on DMA and other non CPU access.
1094	* @param pvFault The fault address (cr2).
1095	* @param GCPhysFault The GC physical address corresponding to pvFault.
1096	* @param pvUser User argument.
1097	*/
1098	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1099	{
1100	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1101	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1102	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1103	PVMCPU pVCpu = VMMGetCpu(pVM);
1104
1105	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1106
1107	/*
1108	* We should ALWAYS have the list head as user parameter. This
1109	* is because we use that page to record the changes.
1110	*/
1111	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1112
1113	/*
1114	* Disassemble the faulting instruction.
1115	*/
1116	DISCPUSTATE Cpu;
1117	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
1118	AssertRCReturn(rc, rc);
1119
1120	/*
1121	* Check if it's worth dealing with.
1122	*/
1123	bool fReused = false;
1124	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1125	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1126	)
1127	&& !(fReused = pgmPoolMonitorIsReused(pVM, pPage, pRegFrame, &Cpu, pvFault))
1128	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1129	{
1130	/*
1131	* Simple instructions, no REP prefix.
1132	*/
1133	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1134	{
1135	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1136	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1137	return rc;
1138	}
1139
1140	/*
1141	* Windows is frequently doing small memset() operations (netio test 4k+).
1142	* We have to deal with these or we'll kill the cache and performance.
1143	*/
1144	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1145	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1146	&& pRegFrame->ecx <= 0x20
1147	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1148	&& !((uintptr_t)pvFault & 3)
1149	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1150	&& Cpu.mode == CPUMODE_32BIT
1151	&& Cpu.opmode == CPUMODE_32BIT
1152	&& Cpu.addrmode == CPUMODE_32BIT
1153	&& Cpu.prefix == PREFIX_REP
1154	&& !pRegFrame->eflags.Bits.u1DF
1155	)
1156	{
1157	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1158	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1159	return rc;
1160	}
1161
1162	/* REP prefix, don't bother. */
1163	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1164	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1165	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1166	}
1167
1168	/*
1169	* Not worth it, so flush it.
1170	*
1171	* If we considered it to be reused, don't to back to ring-3
1172	* to emulate failed instructions since we usually cannot
1173	* interpret then. This may be a bit risky, in which case
1174	* the reuse detection must be fixed.
1175	*/
1176	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1177	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1178	rc = VINF_SUCCESS;
1179	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1180	return rc;
1181	}
1182
1183	# endif /* !IN_RING3 */
1184	#endif /* PGMPOOL_WITH_MONITORING */
1185
1186	#ifdef PGMPOOL_WITH_CACHE
1187
1188	/**
1189	* Inserts a page into the GCPhys hash table.
1190	*
1191	* @param pPool The pool.
1192	* @param pPage The page.
1193	*/
1194	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1195	{
1196	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1197	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1198	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1199	pPage->iNext = pPool->aiHash[iHash];
1200	pPool->aiHash[iHash] = pPage->idx;
1201	}
1202
1203
1204	/**
1205	* Removes a page from the GCPhys hash table.
1206	*
1207	* @param pPool The pool.
1208	* @param pPage The page.
1209	*/
1210	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1211	{
1212	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1213	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1214	if (pPool->aiHash[iHash] == pPage->idx)
1215	pPool->aiHash[iHash] = pPage->iNext;
1216	else
1217	{
1218	uint16_t iPrev = pPool->aiHash[iHash];
1219	for (;;)
1220	{
1221	const int16_t i = pPool->aPages[iPrev].iNext;
1222	if (i == pPage->idx)
1223	{
1224	pPool->aPages[iPrev].iNext = pPage->iNext;
1225	break;
1226	}
1227	if (i == NIL_PGMPOOL_IDX)
1228	{
1229	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1230	break;
1231	}
1232	iPrev = i;
1233	}
1234	}
1235	pPage->iNext = NIL_PGMPOOL_IDX;
1236	}
1237
1238
1239	/**
1240	* Frees up one cache page.
1241	*
1242	* @returns VBox status code.
1243	* @retval VINF_SUCCESS on success.
1244	* @param pPool The pool.
1245	* @param iUser The user index.
1246	*/
1247	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1248	{
1249	#ifndef IN_RC
1250	const PVM pVM = pPool->CTX_SUFF(pVM);
1251	#endif
1252	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1253	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1254
1255	/*
1256	* Select one page from the tail of the age list.
1257	*/
1258	PPGMPOOLPAGE pPage;
1259	for (unsigned iLoop = 0; ; iLoop++)
1260	{
1261	uint16_t iToFree = pPool->iAgeTail;
1262	if (iToFree == iUser)
1263	iToFree = pPool->aPages[iToFree].iAgePrev;
1264	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1265	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1266	{
1267	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1268	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1269	{
1270	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1271	continue;
1272	iToFree = i;
1273	break;
1274	}
1275	}
1276	*/
1277	Assert(iToFree != iUser);
1278	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1279	pPage = &pPool->aPages[iToFree];
1280
1281	/*
1282	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1283	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1284	*/
1285	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1286	break;
1287	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1288	pgmPoolCacheUsed(pPool, pPage);
1289	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1290	}
1291
1292	/*
1293	* Found a usable page, flush it and return.
1294	*/
1295	int rc = pgmPoolFlushPage(pPool, pPage);
1296	if (rc == VINF_SUCCESS)
1297	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1298	return rc;
1299	}
1300
1301
1302	/**
1303	* Checks if a kind mismatch is really a page being reused
1304	* or if it's just normal remappings.
1305	*
1306	* @returns true if reused and the cached page (enmKind1) should be flushed
1307	* @returns false if not reused.
1308	* @param enmKind1 The kind of the cached page.
1309	* @param enmKind2 The kind of the requested page.
1310	*/
1311	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1312	{
1313	switch (enmKind1)
1314	{
1315	/*
1316	* Never reuse them. There is no remapping in non-paging mode.
1317	*/
1318	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1319	case PGMPOOLKIND_32BIT_PD_PHYS:
1320	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1321	case PGMPOOLKIND_PAE_PD_PHYS:
1322	case PGMPOOLKIND_PAE_PDPT_PHYS:
1323	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1324	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1325	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1326	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1327	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1328	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1329	return false;
1330
1331	/*
1332	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1333	*/
1334	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1335	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1336	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1337	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1338	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1339	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1340	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1341	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1342	case PGMPOOLKIND_32BIT_PD:
1343	case PGMPOOLKIND_PAE_PDPT:
1344	switch (enmKind2)
1345	{
1346	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1347	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1348	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1349	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1350	case PGMPOOLKIND_64BIT_PML4:
1351	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1352	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1353	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1354	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1355	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1356	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1357	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1358	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1359	return true;
1360	default:
1361	return false;
1362	}
1363
1364	/*
1365	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1366	*/
1367	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1368	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1369	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1370	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1371	case PGMPOOLKIND_64BIT_PML4:
1372	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1373	switch (enmKind2)
1374	{
1375	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1376	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1377	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1378	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1379	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1380	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1381	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1382	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1383	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1384	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1385	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1386	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1387	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1388	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1389	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1390	return true;
1391	default:
1392	return false;
1393	}
1394
1395	/*
1396	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1397	*/
1398	case PGMPOOLKIND_ROOT_NESTED:
1399	return false;
1400
1401	default:
1402	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1403	}
1404	}
1405
1406
1407	/**
1408	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1409	*
1410	* @returns VBox status code.
1411	* @retval VINF_PGM_CACHED_PAGE on success.
1412	* @retval VERR_FILE_NOT_FOUND if not found.
1413	* @param pPool The pool.
1414	* @param GCPhys The GC physical address of the page we're gonna shadow.
1415	* @param enmKind The kind of mapping.
1416	* @param iUser The shadow page pool index of the user table.
1417	* @param iUserTable The index into the user table (shadowed).
1418	* @param ppPage Where to store the pointer to the page.
1419	*/
1420	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1421	{
1422	#ifndef IN_RC
1423	const PVM pVM = pPool->CTX_SUFF(pVM);
1424	#endif
1425	/*
1426	* Look up the GCPhys in the hash.
1427	*/
1428	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1429	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1430	if (i != NIL_PGMPOOL_IDX)
1431	{
1432	do
1433	{
1434	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1435	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1436	if (pPage->GCPhys == GCPhys)
1437	{
1438	if ((PGMPOOLKIND)pPage->enmKind == enmKind)
1439	{
1440	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1441	* doesn't flush it in case there are no more free use records.
1442	*/
1443	pgmPoolCacheUsed(pPool, pPage);
1444
1445	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1446	if (RT_SUCCESS(rc))
1447	{
1448	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1449	*ppPage = pPage;
1450	STAM_COUNTER_INC(&pPool->StatCacheHits);
1451	return VINF_PGM_CACHED_PAGE;
1452	}
1453	return rc;
1454	}
1455
1456	/*
1457	* The kind is different. In some cases we should now flush the page
1458	* as it has been reused, but in most cases this is normal remapping
1459	* of PDs as PT or big pages using the GCPhys field in a slightly
1460	* different way than the other kinds.
1461	*/
1462	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1463	{
1464	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1465	pgmPoolFlushPage(pPool, pPage);
1466	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1467	break;
1468	}
1469	}
1470
1471	/* next */
1472	i = pPage->iNext;
1473	} while (i != NIL_PGMPOOL_IDX);
1474	}
1475
1476	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1477	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1478	return VERR_FILE_NOT_FOUND;
1479	}
1480
1481
1482	/**
1483	* Inserts a page into the cache.
1484	*
1485	* @param pPool The pool.
1486	* @param pPage The cached page.
1487	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1488	*/
1489	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1490	{
1491	/*
1492	* Insert into the GCPhys hash if the page is fit for that.
1493	*/
1494	Assert(!pPage->fCached);
1495	if (fCanBeCached)
1496	{
1497	pPage->fCached = true;
1498	pgmPoolHashInsert(pPool, pPage);
1499	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1500	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1501	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1502	}
1503	else
1504	{
1505	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1506	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1507	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1508	}
1509
1510	/*
1511	* Insert at the head of the age list.
1512	*/
1513	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1514	pPage->iAgeNext = pPool->iAgeHead;
1515	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1516	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1517	else
1518	pPool->iAgeTail = pPage->idx;
1519	pPool->iAgeHead = pPage->idx;
1520	}
1521
1522
1523	/**
1524	* Flushes a cached page.
1525	*
1526	* @param pPool The pool.
1527	* @param pPage The cached page.
1528	*/
1529	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1530	{
1531	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1532
1533	/*
1534	* Remove the page from the hash.
1535	*/
1536	if (pPage->fCached)
1537	{
1538	pPage->fCached = false;
1539	pgmPoolHashRemove(pPool, pPage);
1540	}
1541	else
1542	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1543
1544	/*
1545	* Remove it from the age list.
1546	*/
1547	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1548	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1549	else
1550	pPool->iAgeTail = pPage->iAgePrev;
1551	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1552	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1553	else
1554	pPool->iAgeHead = pPage->iAgeNext;
1555	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1556	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1557	}
1558
1559	#endif /* PGMPOOL_WITH_CACHE */
1560	#ifdef PGMPOOL_WITH_MONITORING
1561
1562	/**
1563	* Looks for pages sharing the monitor.
1564	*
1565	* @returns Pointer to the head page.
1566	* @returns NULL if not found.
1567	* @param pPool The Pool
1568	* @param pNewPage The page which is going to be monitored.
1569	*/
1570	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1571	{
1572	#ifdef PGMPOOL_WITH_CACHE
1573	/*
1574	* Look up the GCPhys in the hash.
1575	*/
1576	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1577	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1578	if (i == NIL_PGMPOOL_IDX)
1579	return NULL;
1580	do
1581	{
1582	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1583	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1584	&& pPage != pNewPage)
1585	{
1586	switch (pPage->enmKind)
1587	{
1588	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1589	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1590	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1591	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1592	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1593	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1594	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1595	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1596	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1597	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1598	case PGMPOOLKIND_64BIT_PML4:
1599	case PGMPOOLKIND_32BIT_PD:
1600	case PGMPOOLKIND_PAE_PDPT:
1601	{
1602	/* find the head */
1603	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1604	{
1605	Assert(pPage->iMonitoredPrev != pPage->idx);
1606	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1607	}
1608	return pPage;
1609	}
1610
1611	/* ignore, no monitoring. */
1612	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1613	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1614	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1615	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1616	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1617	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1618	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1619	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1620	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1621	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1622	case PGMPOOLKIND_ROOT_NESTED:
1623	case PGMPOOLKIND_PAE_PD_PHYS:
1624	case PGMPOOLKIND_PAE_PDPT_PHYS:
1625	case PGMPOOLKIND_32BIT_PD_PHYS:
1626	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1627	break;
1628	default:
1629	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1630	}
1631	}
1632
1633	/* next */
1634	i = pPage->iNext;
1635	} while (i != NIL_PGMPOOL_IDX);
1636	#endif
1637	return NULL;
1638	}
1639
1640
1641	/**
1642	* Enabled write monitoring of a guest page.
1643	*
1644	* @returns VBox status code.
1645	* @retval VINF_SUCCESS on success.
1646	* @param pPool The pool.
1647	* @param pPage The cached page.
1648	*/
1649	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1650	{
1651	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1652
1653	/*
1654	* Filter out the relevant kinds.
1655	*/
1656	switch (pPage->enmKind)
1657	{
1658	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1659	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1660	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1661	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1662	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1663	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1664	case PGMPOOLKIND_64BIT_PML4:
1665	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1666	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1667	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1668	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1669	case PGMPOOLKIND_32BIT_PD:
1670	case PGMPOOLKIND_PAE_PDPT:
1671	break;
1672
1673	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1674	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1675	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1676	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1677	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1678	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1679	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1680	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1681	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1682	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1683	case PGMPOOLKIND_ROOT_NESTED:
1684	/* Nothing to monitor here. */
1685	return VINF_SUCCESS;
1686
1687	case PGMPOOLKIND_32BIT_PD_PHYS:
1688	case PGMPOOLKIND_PAE_PDPT_PHYS:
1689	case PGMPOOLKIND_PAE_PD_PHYS:
1690	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1691	/* Nothing to monitor here. */
1692	return VINF_SUCCESS;
1693	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1694	break;
1695	#else
1696	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1697	#endif
1698	default:
1699	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1700	}
1701
1702	/*
1703	* Install handler.
1704	*/
1705	int rc;
1706	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1707	if (pPageHead)
1708	{
1709	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1710	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1711	pPage->iMonitoredPrev = pPageHead->idx;
1712	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1713	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1714	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1715	pPageHead->iMonitoredNext = pPage->idx;
1716	rc = VINF_SUCCESS;
1717	}
1718	else
1719	{
1720	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1721	PVM pVM = pPool->CTX_SUFF(pVM);
1722	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1723	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1724	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1725	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1726	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1727	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1728	pPool->pszAccessHandler);
1729	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1730	* the heap size should suffice. */
1731	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1732	Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1733	}
1734	pPage->fMonitored = true;
1735	return rc;
1736	}
1737
1738
1739	/**
1740	* Disables write monitoring of a guest page.
1741	*
1742	* @returns VBox status code.
1743	* @retval VINF_SUCCESS on success.
1744	* @param pPool The pool.
1745	* @param pPage The cached page.
1746	*/
1747	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1748	{
1749	/*
1750	* Filter out the relevant kinds.
1751	*/
1752	switch (pPage->enmKind)
1753	{
1754	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1755	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1756	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1757	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1758	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1759	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1760	case PGMPOOLKIND_64BIT_PML4:
1761	case PGMPOOLKIND_32BIT_PD:
1762	case PGMPOOLKIND_PAE_PDPT:
1763	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1764	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1765	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1766	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1767	break;
1768
1769	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1770	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1771	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1772	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1773	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1774	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1775	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1776	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1777	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1778	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1779	case PGMPOOLKIND_ROOT_NESTED:
1780	case PGMPOOLKIND_PAE_PD_PHYS:
1781	case PGMPOOLKIND_PAE_PDPT_PHYS:
1782	case PGMPOOLKIND_32BIT_PD_PHYS:
1783	/* Nothing to monitor here. */
1784	return VINF_SUCCESS;
1785
1786	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1787	break;
1788	#endif
1789	default:
1790	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1791	}
1792
1793	/*
1794	* Remove the page from the monitored list or uninstall it if last.
1795	*/
1796	const PVM pVM = pPool->CTX_SUFF(pVM);
1797	int rc;
1798	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1799	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1800	{
1801	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1802	{
1803	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1804	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1805	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1806	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1807	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1808	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1809	pPool->pszAccessHandler);
1810	AssertFatalRCSuccess(rc);
1811	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1812	}
1813	else
1814	{
1815	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1816	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1817	{
1818	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1819	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1820	}
1821	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1822	rc = VINF_SUCCESS;
1823	}
1824	}
1825	else
1826	{
1827	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1828	AssertFatalRC(rc);
1829	AssertMsg(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3),
1830	("%#x %#x\n", pVM->pgm.s.fGlobalSyncFlags, pVM->fGlobalForcedActions));
1831	}
1832	pPage->fMonitored = false;
1833
1834	/*
1835	* Remove it from the list of modified pages (if in it).
1836	*/
1837	pgmPoolMonitorModifiedRemove(pPool, pPage);
1838
1839	return rc;
1840	}
1841
1842
1843	/**
1844	* Inserts the page into the list of modified pages.
1845	*
1846	* @param pPool The pool.
1847	* @param pPage The page.
1848	*/
1849	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1850	{
1851	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1852	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1853	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1854	&& pPool->iModifiedHead != pPage->idx,
1855	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1856	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1857	pPool->iModifiedHead, pPool->cModifiedPages));
1858
1859	pPage->iModifiedNext = pPool->iModifiedHead;
1860	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1861	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1862	pPool->iModifiedHead = pPage->idx;
1863	pPool->cModifiedPages++;
1864	#ifdef VBOX_WITH_STATISTICS
1865	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1866	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1867	#endif
1868	}
1869
1870
1871	/**
1872	* Removes the page from the list of modified pages and resets the
1873	* moficiation counter.
1874	*
1875	* @param pPool The pool.
1876	* @param pPage The page which is believed to be in the list of modified pages.
1877	*/
1878	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1879	{
1880	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1881	if (pPool->iModifiedHead == pPage->idx)
1882	{
1883	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1884	pPool->iModifiedHead = pPage->iModifiedNext;
1885	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1886	{
1887	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1888	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1889	}
1890	pPool->cModifiedPages--;
1891	}
1892	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1893	{
1894	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1895	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1896	{
1897	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1898	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1899	}
1900	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1901	pPool->cModifiedPages--;
1902	}
1903	else
1904	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1905	pPage->cModifications = 0;
1906	}
1907
1908
1909	/**
1910	* Zaps the list of modified pages, resetting their modification counters in the process.
1911	*
1912	* @param pVM The VM handle.
1913	*/
1914	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1915	{
1916	pgmLock(pVM);
1917	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1918	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1919
1920	unsigned cPages = 0; NOREF(cPages);
1921	uint16_t idx = pPool->iModifiedHead;
1922	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1923	while (idx != NIL_PGMPOOL_IDX)
1924	{
1925	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1926	idx = pPage->iModifiedNext;
1927	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1928	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1929	pPage->cModifications = 0;
1930	Assert(++cPages);
1931	}
1932	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1933	pPool->cModifiedPages = 0;
1934	pgmUnlock(pVM);
1935	}
1936
1937
1938	#ifdef IN_RING3
1939	/**
1940	* Clear all shadow pages and clear all modification counters.
1941	*
1942	* @param pVM The VM handle.
1943	* @remark Should only be used when monitoring is available, thus placed in
1944	* the PGMPOOL_WITH_MONITORING #ifdef.
1945	*/
1946	void pgmPoolClearAll(PVM pVM)
1947	{
1948	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1949	STAM_PROFILE_START(&pPool->StatClearAll, c);
1950	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1951
1952	/*
1953	* Iterate all the pages until we've encountered all that in use.
1954	* This is simple but not quite optimal solution.
1955	*/
1956	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1957	unsigned cLeft = pPool->cUsedPages;
1958	unsigned iPage = pPool->cCurPages;
1959	while (--iPage >= PGMPOOL_IDX_FIRST)
1960	{
1961	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1962	if (pPage->GCPhys != NIL_RTGCPHYS)
1963	{
1964	switch (pPage->enmKind)
1965	{
1966	/*
1967	* We only care about shadow page tables.
1968	*/
1969	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1970	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1971	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1972	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1973	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1974	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1975	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1976	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1977	{
1978	#ifdef PGMPOOL_WITH_USER_TRACKING
1979	if (pPage->cPresent)
1980	#endif
1981	{
1982	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1983	STAM_PROFILE_START(&pPool->StatZeroPage, z);
1984	ASMMemZeroPage(pvShw);
1985	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
1986	#ifdef PGMPOOL_WITH_USER_TRACKING
1987	pPage->cPresent = 0;
1988	pPage->iFirstPresent = ~0;
1989	#endif
1990	}
1991	}
1992	/* fall thru */
1993
1994	default:
1995	Assert(!pPage->cModifications \|\| ++cModifiedPages);
1996	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
1997	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
1998	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1999	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2000	pPage->cModifications = 0;
2001	break;
2002
2003	}
2004	if (!--cLeft)
2005	break;
2006	}
2007	}
2008
2009	/* swipe the special pages too. */
2010	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2011	{
2012	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2013	if (pPage->GCPhys != NIL_RTGCPHYS)
2014	{
2015	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2016	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2017	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2018	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2019	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2020	pPage->cModifications = 0;
2021	}
2022	}
2023
2024	#ifndef DEBUG_michael
2025	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2026	#endif
2027	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2028	pPool->cModifiedPages = 0;
2029
2030	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2031	/*
2032	* Clear all the GCPhys links and rebuild the phys ext free list.
2033	*/
2034	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2035	pRam;
2036	pRam = pRam->CTX_SUFF(pNext))
2037	{
2038	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2039	while (iPage-- > 0)
2040	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2041	}
2042
2043	pPool->iPhysExtFreeHead = 0;
2044	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2045	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2046	for (unsigned i = 0; i < cMaxPhysExts; i++)
2047	{
2048	paPhysExts[i].iNext = i + 1;
2049	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2050	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2051	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2052	}
2053	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2054	#endif
2055
2056
2057	pPool->cPresent = 0;
2058	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2059	}
2060	#endif /* IN_RING3 */
2061
2062
2063	/**
2064	* Handle SyncCR3 pool tasks
2065	*
2066	* @returns VBox status code.
2067	* @retval VINF_SUCCESS if successfully added.
2068	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2069	* @param pVM The VM handle.
2070	* @remark Should only be used when monitoring is available, thus placed in
2071	* the PGMPOOL_WITH_MONITORING #ifdef.
2072	*/
2073	int pgmPoolSyncCR3(PVM pVM)
2074	{
2075	LogFlow(("pgmPoolSyncCR3\n"));
2076	/*
2077	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2078	* Occasionally we will have to clear all the shadow page tables because we wanted
2079	* to monitor a page which was mapped by too many shadowed page tables. This operation
2080	* sometimes refered to as a 'lightweight flush'.
2081	*/
2082	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2083	if (ASMBitTestAndClear(&pVM->pgm.s.fGlobalSyncFlags, PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT))
2084	{
2085	/** @todo SMP support! */
2086	Assert(pVM->cCPUs == 1);
2087	pgmPoolClearAll(pVM);
2088	# else /* !IN_RING3 */
2089	if (pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)
2090	{
2091	LogFlow(("SyncCR3: PGM_GLOBAL_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2092	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2093	return VINF_PGM_SYNC_CR3;
2094	# endif /* !IN_RING3 */
2095	}
2096	else
2097	pgmPoolMonitorModifiedClearAll(pVM);
2098
2099	return VINF_SUCCESS;
2100	}
2101
2102	#endif /* PGMPOOL_WITH_MONITORING */
2103	#ifdef PGMPOOL_WITH_USER_TRACKING
2104
2105	/**
2106	* Frees up at least one user entry.
2107	*
2108	* @returns VBox status code.
2109	* @retval VINF_SUCCESS if successfully added.
2110	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2111	* @param pPool The pool.
2112	* @param iUser The user index.
2113	*/
2114	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2115	{
2116	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2117	#ifdef PGMPOOL_WITH_CACHE
2118	/*
2119	* Just free cached pages in a braindead fashion.
2120	*/
2121	/** @todo walk the age list backwards and free the first with usage. */
2122	int rc = VINF_SUCCESS;
2123	do
2124	{
2125	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2126	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2127	rc = rc2;
2128	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2129	return rc;
2130	#else
2131	/*
2132	* Lazy approach.
2133	*/
2134	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2135	AssertCompileFailed();
2136	Assert(!CPUMIsGuestInLongMode(pVM));
2137	pgmPoolFlushAllInt(pPool);
2138	return VERR_PGM_POOL_FLUSHED;
2139	#endif
2140	}
2141
2142
2143	/**
2144	* Inserts a page into the cache.
2145	*
2146	* This will create user node for the page, insert it into the GCPhys
2147	* hash, and insert it into the age list.
2148	*
2149	* @returns VBox status code.
2150	* @retval VINF_SUCCESS if successfully added.
2151	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2152	* @param pPool The pool.
2153	* @param pPage The cached page.
2154	* @param GCPhys The GC physical address of the page we're gonna shadow.
2155	* @param iUser The user index.
2156	* @param iUserTable The user table index.
2157	*/
2158	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2159	{
2160	int rc = VINF_SUCCESS;
2161	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2162
2163	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2164
2165	#ifdef VBOX_STRICT
2166	/*
2167	* Check that the entry doesn't already exists.
2168	*/
2169	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2170	{
2171	uint16_t i = pPage->iUserHead;
2172	do
2173	{
2174	Assert(i < pPool->cMaxUsers);
2175	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2176	i = paUsers[i].iNext;
2177	} while (i != NIL_PGMPOOL_USER_INDEX);
2178	}
2179	#endif
2180
2181	/*
2182	* Find free a user node.
2183	*/
2184	uint16_t i = pPool->iUserFreeHead;
2185	if (i == NIL_PGMPOOL_USER_INDEX)
2186	{
2187	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2188	if (RT_FAILURE(rc))
2189	return rc;
2190	i = pPool->iUserFreeHead;
2191	}
2192
2193	/*
2194	* Unlink the user node from the free list,
2195	* initialize and insert it into the user list.
2196	*/
2197	pPool->iUserFreeHead = paUsers[i].iNext;
2198	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2199	paUsers[i].iUser = iUser;
2200	paUsers[i].iUserTable = iUserTable;
2201	pPage->iUserHead = i;
2202
2203	/*
2204	* Insert into cache and enable monitoring of the guest page if enabled.
2205	*
2206	* Until we implement caching of all levels, including the CR3 one, we'll
2207	* have to make sure we don't try monitor & cache any recursive reuse of
2208	* a monitored CR3 page. Because all windows versions are doing this we'll
2209	* have to be able to do combined access monitoring, CR3 + PT and
2210	* PD + PT (guest PAE).
2211	*
2212	* Update:
2213	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2214	*/
2215	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2216	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2217	const bool fCanBeMonitored = true;
2218	# else
2219	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2220	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2221	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2222	# endif
2223	# ifdef PGMPOOL_WITH_CACHE
2224	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2225	# endif
2226	if (fCanBeMonitored)
2227	{
2228	# ifdef PGMPOOL_WITH_MONITORING
2229	rc = pgmPoolMonitorInsert(pPool, pPage);
2230	AssertRC(rc);
2231	}
2232	# endif
2233	#endif /* PGMPOOL_WITH_MONITORING */
2234	return rc;
2235	}
2236
2237
2238	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2239	/**
2240	* Adds a user reference to a page.
2241	*
2242	* This will move the page to the head of the
2243	*
2244	* @returns VBox status code.
2245	* @retval VINF_SUCCESS if successfully added.
2246	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2247	* @param pPool The pool.
2248	* @param pPage The cached page.
2249	* @param iUser The user index.
2250	* @param iUserTable The user table.
2251	*/
2252	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2253	{
2254	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2255
2256	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2257	# ifdef VBOX_STRICT
2258	/*
2259	* Check that the entry doesn't already exists.
2260	*/
2261	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2262	{
2263	uint16_t i = pPage->iUserHead;
2264	do
2265	{
2266	Assert(i < pPool->cMaxUsers);
2267	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2268	i = paUsers[i].iNext;
2269	} while (i != NIL_PGMPOOL_USER_INDEX);
2270	}
2271	# endif
2272
2273	/*
2274	* Allocate a user node.
2275	*/
2276	uint16_t i = pPool->iUserFreeHead;
2277	if (i == NIL_PGMPOOL_USER_INDEX)
2278	{
2279	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2280	if (RT_FAILURE(rc))
2281	return rc;
2282	i = pPool->iUserFreeHead;
2283	}
2284	pPool->iUserFreeHead = paUsers[i].iNext;
2285
2286	/*
2287	* Initialize the user node and insert it.
2288	*/
2289	paUsers[i].iNext = pPage->iUserHead;
2290	paUsers[i].iUser = iUser;
2291	paUsers[i].iUserTable = iUserTable;
2292	pPage->iUserHead = i;
2293
2294	# ifdef PGMPOOL_WITH_CACHE
2295	/*
2296	* Tell the cache to update its replacement stats for this page.
2297	*/
2298	pgmPoolCacheUsed(pPool, pPage);
2299	# endif
2300	return VINF_SUCCESS;
2301	}
2302	# endif /* PGMPOOL_WITH_CACHE */
2303
2304
2305	/**
2306	* Frees a user record associated with a page.
2307	*
2308	* This does not clear the entry in the user table, it simply replaces the
2309	* user record to the chain of free records.
2310	*
2311	* @param pPool The pool.
2312	* @param HCPhys The HC physical address of the shadow page.
2313	* @param iUser The shadow page pool index of the user table.
2314	* @param iUserTable The index into the user table (shadowed).
2315	*/
2316	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2317	{
2318	/*
2319	* Unlink and free the specified user entry.
2320	*/
2321	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2322
2323	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2324	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2325	uint16_t i = pPage->iUserHead;
2326	if ( i != NIL_PGMPOOL_USER_INDEX
2327	&& paUsers[i].iUser == iUser
2328	&& paUsers[i].iUserTable == iUserTable)
2329	{
2330	pPage->iUserHead = paUsers[i].iNext;
2331
2332	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2333	paUsers[i].iNext = pPool->iUserFreeHead;
2334	pPool->iUserFreeHead = i;
2335	return;
2336	}
2337
2338	/* General: Linear search. */
2339	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2340	while (i != NIL_PGMPOOL_USER_INDEX)
2341	{
2342	if ( paUsers[i].iUser == iUser
2343	&& paUsers[i].iUserTable == iUserTable)
2344	{
2345	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2346	paUsers[iPrev].iNext = paUsers[i].iNext;
2347	else
2348	pPage->iUserHead = paUsers[i].iNext;
2349
2350	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2351	paUsers[i].iNext = pPool->iUserFreeHead;
2352	pPool->iUserFreeHead = i;
2353	return;
2354	}
2355	iPrev = i;
2356	i = paUsers[i].iNext;
2357	}
2358
2359	/* Fatal: didn't find it */
2360	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2361	iUser, iUserTable, pPage->GCPhys));
2362	}
2363
2364
2365	/**
2366	* Gets the entry size of a shadow table.
2367	*
2368	* @param enmKind The kind of page.
2369	*
2370	* @returns The size of the entry in bytes. That is, 4 or 8.
2371	* @returns If the kind is not for a table, an assertion is raised and 0 is
2372	* returned.
2373	*/
2374	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2375	{
2376	switch (enmKind)
2377	{
2378	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2379	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2380	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2381	case PGMPOOLKIND_32BIT_PD:
2382	case PGMPOOLKIND_32BIT_PD_PHYS:
2383	return 4;
2384
2385	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2386	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2387	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2388	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2389	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2390	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2391	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2392	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2393	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2394	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2395	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2396	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2397	case PGMPOOLKIND_64BIT_PML4:
2398	case PGMPOOLKIND_PAE_PDPT:
2399	case PGMPOOLKIND_ROOT_NESTED:
2400	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2401	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2402	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2403	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2404	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2405	case PGMPOOLKIND_PAE_PD_PHYS:
2406	case PGMPOOLKIND_PAE_PDPT_PHYS:
2407	return 8;
2408
2409	default:
2410	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2411	}
2412	}
2413
2414
2415	/**
2416	* Gets the entry size of a guest table.
2417	*
2418	* @param enmKind The kind of page.
2419	*
2420	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2421	* @returns If the kind is not for a table, an assertion is raised and 0 is
2422	* returned.
2423	*/
2424	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2425	{
2426	switch (enmKind)
2427	{
2428	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2429	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2430	case PGMPOOLKIND_32BIT_PD:
2431	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2432	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2433	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2434	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2435	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2436	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2437	return 4;
2438
2439	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2440	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2441	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2442	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2443	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2444	case PGMPOOLKIND_64BIT_PML4:
2445	case PGMPOOLKIND_PAE_PDPT:
2446	return 8;
2447
2448	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2449	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2450	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2451	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2452	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2453	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2454	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2455	case PGMPOOLKIND_ROOT_NESTED:
2456	case PGMPOOLKIND_PAE_PD_PHYS:
2457	case PGMPOOLKIND_PAE_PDPT_PHYS:
2458	case PGMPOOLKIND_32BIT_PD_PHYS:
2459	/** @todo can we return 0? (nobody is calling this...) */
2460	AssertFailed();
2461	return 0;
2462
2463	default:
2464	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2465	}
2466	}
2467
2468	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2469
2470	/**
2471	* Scans one shadow page table for mappings of a physical page.
2472	*
2473	* @param pVM The VM handle.
2474	* @param pPhysPage The guest page in question.
2475	* @param iShw The shadow page table.
2476	* @param cRefs The number of references made in that PT.
2477	*/
2478	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2479	{
2480	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2481	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2482
2483	/*
2484	* Assert sanity.
2485	*/
2486	Assert(cRefs == 1);
2487	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2488	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2489
2490	/*
2491	* Then, clear the actual mappings to the page in the shadow PT.
2492	*/
2493	switch (pPage->enmKind)
2494	{
2495	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2496	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2497	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2498	{
2499	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2500	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2501	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2502	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2503	{
2504	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2505	pPT->a[i].u = 0;
2506	cRefs--;
2507	if (!cRefs)
2508	return;
2509	}
2510	#ifdef LOG_ENABLED
2511	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2512	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2513	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2514	{
2515	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2516	pPT->a[i].u = 0;
2517	}
2518	#endif
2519	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2520	break;
2521	}
2522
2523	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2524	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2525	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2526	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2527	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2528	{
2529	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2530	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2531	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2532	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2533	{
2534	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2535	pPT->a[i].u = 0;
2536	cRefs--;
2537	if (!cRefs)
2538	return;
2539	}
2540	#ifdef LOG_ENABLED
2541	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2542	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2543	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2544	{
2545	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2546	pPT->a[i].u = 0;
2547	}
2548	#endif
2549	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2550	break;
2551	}
2552
2553	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2554	{
2555	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2556	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2557	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2558	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2559	{
2560	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2561	pPT->a[i].u = 0;
2562	cRefs--;
2563	if (!cRefs)
2564	return;
2565	}
2566	#ifdef LOG_ENABLED
2567	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2568	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2569	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2570	{
2571	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2572	pPT->a[i].u = 0;
2573	}
2574	#endif
2575	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2576	break;
2577	}
2578
2579	default:
2580	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2581	}
2582	}
2583
2584
2585	/**
2586	* Scans one shadow page table for mappings of a physical page.
2587	*
2588	* @param pVM The VM handle.
2589	* @param pPhysPage The guest page in question.
2590	* @param iShw The shadow page table.
2591	* @param cRefs The number of references made in that PT.
2592	*/
2593	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2594	{
2595	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2596	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2597	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2598	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2599	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2600	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2601	}
2602
2603
2604	/**
2605	* Flushes a list of shadow page tables mapping the same physical page.
2606	*
2607	* @param pVM The VM handle.
2608	* @param pPhysPage The guest page in question.
2609	* @param iPhysExt The physical cross reference extent list to flush.
2610	*/
2611	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2612	{
2613	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2614	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2615	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2616
2617	const uint16_t iPhysExtStart = iPhysExt;
2618	PPGMPOOLPHYSEXT pPhysExt;
2619	do
2620	{
2621	Assert(iPhysExt < pPool->cMaxPhysExts);
2622	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2623	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2624	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2625	{
2626	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2627	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2628	}
2629
2630	/* next */
2631	iPhysExt = pPhysExt->iNext;
2632	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2633
2634	/* insert the list into the free list and clear the ram range entry. */
2635	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2636	pPool->iPhysExtFreeHead = iPhysExtStart;
2637	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2638
2639	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2640	}
2641
2642	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2643
2644	/**
2645	* Flushes all shadow page table mappings of the given guest page.
2646	*
2647	* This is typically called when the host page backing the guest one has been
2648	* replaced or when the page protection was changed due to an access handler.
2649	*
2650	* @returns VBox status code.
2651	* @retval VINF_SUCCESS if all references has been successfully cleared.
2652	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2653	* pool cleaning. FF and sync flags are set.
2654	*
2655	* @param pVM The VM handle.
2656	* @param pPhysPage The guest page in question.
2657	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2658	* flushed, it is NOT touched if this isn't necessary.
2659	* The caller MUST initialized this to @a false.
2660	*/
2661	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2662	{
2663	int rc = VINF_SUCCESS;
2664	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2665	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2666	if (u16)
2667	{
2668	/*
2669	* The zero page is currently screwing up the tracking and we'll
2670	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2671	* is defined, zero pages won't normally be mapped. Some kind of solution
2672	* will be needed for this problem of course, but it will have to wait...
2673	*/
2674	if (PGM_PAGE_IS_ZERO(pPhysPage))
2675	rc = VINF_PGM_GCPHYS_ALIASED;
2676	else
2677	{
2678	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2679	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2680	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2681	PVMCPU pVCpu = VMMGetCpu(pVM);
2682	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2683	# endif
2684
2685	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2686	pgmPoolTrackFlushGCPhysPT(pVM,
2687	pPhysPage,
2688	PGMPOOL_TD_GET_IDX(u16),
2689	PGMPOOL_TD_GET_CREFS(u16));
2690	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2691	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2692	else
2693	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2694	*pfFlushTLBs = true;
2695
2696	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2697	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2698	# endif
2699	}
2700	}
2701
2702	#elif defined(PGMPOOL_WITH_CACHE)
2703	if (PGM_PAGE_IS_ZERO(pPhysPage))
2704	rc = VINF_PGM_GCPHYS_ALIASED;
2705	else
2706	{
2707	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2708	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2709	PVMCPU pVCpu = VMMGetCpu(pVM);
2710	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2711	# endif
2712	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2713	if (rc == VINF_SUCCESS)
2714	*pfFlushTLBs = true;
2715	}
2716
2717	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2718	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2719	# endif
2720
2721	#else
2722	rc = VINF_PGM_GCPHYS_ALIASED;
2723	#endif
2724
2725	if (rc == VINF_PGM_GCPHYS_ALIASED)
2726	{
2727	Assert(pVM->cCPUs == 1); /* @todo check */
2728	pVM->pgm.s.fGlobalSyncFlags \|= PGM_GLOBAL_SYNC_CLEAR_PGM_POOL;
2729	for (unsigned i=0;i<pVM->cCPUs;i++)
2730	{
2731	PVMCPU pVCpu = &pVM->aCpus[i];
2732	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2733	}
2734	rc = VINF_PGM_SYNC_CR3;
2735	}
2736
2737	return rc;
2738	}
2739
2740
2741	/**
2742	* Scans all shadow page tables for mappings of a physical page.
2743	*
2744	* This may be slow, but it's most likely more efficient than cleaning
2745	* out the entire page pool / cache.
2746	*
2747	* @returns VBox status code.
2748	* @retval VINF_SUCCESS if all references has been successfully cleared.
2749	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2750	* a page pool cleaning.
2751	*
2752	* @param pVM The VM handle.
2753	* @param pPhysPage The guest page in question.
2754	*/
2755	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2756	{
2757	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2758	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2759	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2760	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2761
2762	#if 1
2763	/*
2764	* There is a limit to what makes sense.
2765	*/
2766	if (pPool->cPresent > 1024)
2767	{
2768	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2769	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2770	return VINF_PGM_GCPHYS_ALIASED;
2771	}
2772	#endif
2773
2774	/*
2775	* Iterate all the pages until we've encountered all that in use.
2776	* This is simple but not quite optimal solution.
2777	*/
2778	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2779	const uint32_t u32 = u64;
2780	unsigned cLeft = pPool->cUsedPages;
2781	unsigned iPage = pPool->cCurPages;
2782	while (--iPage >= PGMPOOL_IDX_FIRST)
2783	{
2784	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2785	if (pPage->GCPhys != NIL_RTGCPHYS)
2786	{
2787	switch (pPage->enmKind)
2788	{
2789	/*
2790	* We only care about shadow page tables.
2791	*/
2792	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2793	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2794	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2795	{
2796	unsigned cPresent = pPage->cPresent;
2797	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2798	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2799	if (pPT->a[i].n.u1Present)
2800	{
2801	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2802	{
2803	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2804	pPT->a[i].u = 0;
2805	}
2806	if (!--cPresent)
2807	break;
2808	}
2809	break;
2810	}
2811
2812	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2813	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2814	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2815	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2816	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2817	{
2818	unsigned cPresent = pPage->cPresent;
2819	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2820	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2821	if (pPT->a[i].n.u1Present)
2822	{
2823	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2824	{
2825	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2826	pPT->a[i].u = 0;
2827	}
2828	if (!--cPresent)
2829	break;
2830	}
2831	break;
2832	}
2833	}
2834	if (!--cLeft)
2835	break;
2836	}
2837	}
2838
2839	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2840	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2841	return VINF_SUCCESS;
2842	}
2843
2844
2845	/**
2846	* Clears the user entry in a user table.
2847	*
2848	* This is used to remove all references to a page when flushing it.
2849	*/
2850	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2851	{
2852	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2853	Assert(pUser->iUser < pPool->cCurPages);
2854	uint32_t iUserTable = pUser->iUserTable;
2855
2856	/*
2857	* Map the user page.
2858	*/
2859	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2860	union
2861	{
2862	uint64_t *pau64;
2863	uint32_t *pau32;
2864	} u;
2865	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2866
2867	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2868
2869	/* Safety precaution in case we change the paging for other modes too in the future. */
2870	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2871
2872	#ifdef VBOX_STRICT
2873	/*
2874	* Some sanity checks.
2875	*/
2876	switch (pUserPage->enmKind)
2877	{
2878	case PGMPOOLKIND_32BIT_PD:
2879	case PGMPOOLKIND_32BIT_PD_PHYS:
2880	Assert(iUserTable < X86_PG_ENTRIES);
2881	break;
2882	case PGMPOOLKIND_PAE_PDPT:
2883	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2884	case PGMPOOLKIND_PAE_PDPT_PHYS:
2885	Assert(iUserTable < 4);
2886	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2887	break;
2888	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2889	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2890	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2891	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2892	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2893	case PGMPOOLKIND_PAE_PD_PHYS:
2894	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2895	break;
2896	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2897	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2898	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2899	break;
2900	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2901	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2902	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2903	break;
2904	case PGMPOOLKIND_64BIT_PML4:
2905	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2906	/* GCPhys >> PAGE_SHIFT is the index here */
2907	break;
2908	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2909	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2910	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2911	break;
2912
2913	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2914	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2915	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2916	break;
2917
2918	case PGMPOOLKIND_ROOT_NESTED:
2919	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2920	break;
2921
2922	default:
2923	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2924	break;
2925	}
2926	#endif /* VBOX_STRICT */
2927
2928	/*
2929	* Clear the entry in the user page.
2930	*/
2931	switch (pUserPage->enmKind)
2932	{
2933	/* 32-bit entries */
2934	case PGMPOOLKIND_32BIT_PD:
2935	case PGMPOOLKIND_32BIT_PD_PHYS:
2936	u.pau32[iUserTable] = 0;
2937	break;
2938
2939	/* 64-bit entries */
2940	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2941	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2942	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2943	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2944	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2945	#if defined(IN_RC)
2946	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
2947	* non-present PDPT will continue to cause page faults.
2948	*/
2949	ASMReloadCR3();
2950	#endif
2951	/* no break */
2952	case PGMPOOLKIND_PAE_PD_PHYS:
2953	case PGMPOOLKIND_PAE_PDPT_PHYS:
2954	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2955	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2956	case PGMPOOLKIND_64BIT_PML4:
2957	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2958	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2959	case PGMPOOLKIND_PAE_PDPT:
2960	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2961	case PGMPOOLKIND_ROOT_NESTED:
2962	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2963	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2964	u.pau64[iUserTable] = 0;
2965	break;
2966
2967	default:
2968	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2969	}
2970	}
2971
2972
2973	/**
2974	* Clears all users of a page.
2975	*/
2976	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2977	{
2978	/*
2979	* Free all the user records.
2980	*/
2981	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
2982
2983	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2984	uint16_t i = pPage->iUserHead;
2985	while (i != NIL_PGMPOOL_USER_INDEX)
2986	{
2987	/* Clear enter in user table. */
2988	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
2989
2990	/* Free it. */
2991	const uint16_t iNext = paUsers[i].iNext;
2992	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2993	paUsers[i].iNext = pPool->iUserFreeHead;
2994	pPool->iUserFreeHead = i;
2995
2996	/* Next. */
2997	i = iNext;
2998	}
2999	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3000	}
3001
3002	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3003
3004	/**
3005	* Allocates a new physical cross reference extent.
3006	*
3007	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3008	* @param pVM The VM handle.
3009	* @param piPhysExt Where to store the phys ext index.
3010	*/
3011	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3012	{
3013	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3014	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3015	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3016	{
3017	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3018	return NULL;
3019	}
3020	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3021	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3022	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3023	*piPhysExt = iPhysExt;
3024	return pPhysExt;
3025	}
3026
3027
3028	/**
3029	* Frees a physical cross reference extent.
3030	*
3031	* @param pVM The VM handle.
3032	* @param iPhysExt The extent to free.
3033	*/
3034	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3035	{
3036	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3037	Assert(iPhysExt < pPool->cMaxPhysExts);
3038	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3039	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3040	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3041	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3042	pPool->iPhysExtFreeHead = iPhysExt;
3043	}
3044
3045
3046	/**
3047	* Frees a physical cross reference extent.
3048	*
3049	* @param pVM The VM handle.
3050	* @param iPhysExt The extent to free.
3051	*/
3052	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3053	{
3054	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3055
3056	const uint16_t iPhysExtStart = iPhysExt;
3057	PPGMPOOLPHYSEXT pPhysExt;
3058	do
3059	{
3060	Assert(iPhysExt < pPool->cMaxPhysExts);
3061	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3062	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3063	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3064
3065	/* next */
3066	iPhysExt = pPhysExt->iNext;
3067	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3068
3069	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3070	pPool->iPhysExtFreeHead = iPhysExtStart;
3071	}
3072
3073
3074	/**
3075	* Insert a reference into a list of physical cross reference extents.
3076	*
3077	* @returns The new tracking data for PGMPAGE.
3078	*
3079	* @param pVM The VM handle.
3080	* @param iPhysExt The physical extent index of the list head.
3081	* @param iShwPT The shadow page table index.
3082	*
3083	*/
3084	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3085	{
3086	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3087	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3088
3089	/* special common case. */
3090	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3091	{
3092	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3093	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3094	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
3095	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3096	}
3097
3098	/* general treatment. */
3099	const uint16_t iPhysExtStart = iPhysExt;
3100	unsigned cMax = 15;
3101	for (;;)
3102	{
3103	Assert(iPhysExt < pPool->cMaxPhysExts);
3104	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3105	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3106	{
3107	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3108	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3109	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3110	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3111	}
3112	if (!--cMax)
3113	{
3114	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3115	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3116	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
3117	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3118	}
3119	}
3120
3121	/* add another extent to the list. */
3122	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3123	if (!pNew)
3124	{
3125	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3126	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3127	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3128	}
3129	pNew->iNext = iPhysExtStart;
3130	pNew->aidx[0] = iShwPT;
3131	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3132	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3133	}
3134
3135
3136	/**
3137	* Add a reference to guest physical page where extents are in use.
3138	*
3139	* @returns The new tracking data for PGMPAGE.
3140	*
3141	* @param pVM The VM handle.
3142	* @param u16 The ram range flags (top 16-bits).
3143	* @param iShwPT The shadow page table index.
3144	*/
3145	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3146	{
3147	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3148	{
3149	/*
3150	* Convert to extent list.
3151	*/
3152	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3153	uint16_t iPhysExt;
3154	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3155	if (pPhysExt)
3156	{
3157	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3158	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3159	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3160	pPhysExt->aidx[1] = iShwPT;
3161	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3162	}
3163	else
3164	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3165	}
3166	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3167	{
3168	/*
3169	* Insert into the extent list.
3170	*/
3171	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3172	}
3173	else
3174	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3175	return u16;
3176	}
3177
3178
3179	/**
3180	* Clear references to guest physical memory.
3181	*
3182	* @param pPool The pool.
3183	* @param pPage The page.
3184	* @param pPhysPage Pointer to the aPages entry in the ram range.
3185	*/
3186	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3187	{
3188	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3189	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3190
3191	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3192	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3193	{
3194	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3195	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3196	do
3197	{
3198	Assert(iPhysExt < pPool->cMaxPhysExts);
3199
3200	/*
3201	* Look for the shadow page and check if it's all freed.
3202	*/
3203	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3204	{
3205	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3206	{
3207	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3208
3209	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3210	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3211	{
3212	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3213	return;
3214	}
3215
3216	/* we can free the node. */
3217	PVM pVM = pPool->CTX_SUFF(pVM);
3218	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3219	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3220	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3221	{
3222	/* lonely node */
3223	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3224	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3225	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3226	}
3227	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3228	{
3229	/* head */
3230	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3231	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3232	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3233	}
3234	else
3235	{
3236	/* in list */
3237	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3238	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3239	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3240	}
3241	iPhysExt = iPhysExtNext;
3242	return;
3243	}
3244	}
3245
3246	/* next */
3247	iPhysExtPrev = iPhysExt;
3248	iPhysExt = paPhysExts[iPhysExt].iNext;
3249	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3250
3251	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3252	}
3253	else /* nothing to do */
3254	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3255	}
3256
3257
3258	/**
3259	* Clear references to guest physical memory.
3260	*
3261	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3262	* is assumed to be correct, so the linear search can be skipped and we can assert
3263	* at an earlier point.
3264	*
3265	* @param pPool The pool.
3266	* @param pPage The page.
3267	* @param HCPhys The host physical address corresponding to the guest page.
3268	* @param GCPhys The guest physical address corresponding to HCPhys.
3269	*/
3270	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3271	{
3272	/*
3273	* Walk range list.
3274	*/
3275	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3276	while (pRam)
3277	{
3278	RTGCPHYS off = GCPhys - pRam->GCPhys;
3279	if (off < pRam->cb)
3280	{
3281	/* does it match? */
3282	const unsigned iPage = off >> PAGE_SHIFT;
3283	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3284	#ifdef LOG_ENABLED
3285	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3286	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3287	#endif
3288	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3289	{
3290	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3291	return;
3292	}
3293	break;
3294	}
3295	pRam = pRam->CTX_SUFF(pNext);
3296	}
3297	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3298	}
3299
3300
3301	/**
3302	* Clear references to guest physical memory.
3303	*
3304	* @param pPool The pool.
3305	* @param pPage The page.
3306	* @param HCPhys The host physical address corresponding to the guest page.
3307	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3308	*/
3309	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3310	{
3311	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3312
3313	/*
3314	* Walk range list.
3315	*/
3316	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3317	while (pRam)
3318	{
3319	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3320	if (off < pRam->cb)
3321	{
3322	/* does it match? */
3323	const unsigned iPage = off >> PAGE_SHIFT;
3324	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3325	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3326	{
3327	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3328	return;
3329	}
3330	break;
3331	}
3332	pRam = pRam->CTX_SUFF(pNext);
3333	}
3334
3335	/*
3336	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3337	*/
3338	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3339	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3340	while (pRam)
3341	{
3342	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3343	while (iPage-- > 0)
3344	{
3345	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3346	{
3347	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3348	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3349	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3350	return;
3351	}
3352	}
3353	pRam = pRam->CTX_SUFF(pNext);
3354	}
3355
3356	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3357	}
3358
3359
3360	/**
3361	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3362	*
3363	* @param pPool The pool.
3364	* @param pPage The page.
3365	* @param pShwPT The shadow page table (mapping of the page).
3366	* @param pGstPT The guest page table.
3367	*/
3368	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3369	{
3370	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3371	if (pShwPT->a[i].n.u1Present)
3372	{
3373	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3374	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3375	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3376	if (!--pPage->cPresent)
3377	break;
3378	}
3379	}
3380
3381
3382	/**
3383	* Clear references to guest physical memory in a PAE / 32-bit page table.
3384	*
3385	* @param pPool The pool.
3386	* @param pPage The page.
3387	* @param pShwPT The shadow page table (mapping of the page).
3388	* @param pGstPT The guest page table (just a half one).
3389	*/
3390	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3391	{
3392	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3393	if (pShwPT->a[i].n.u1Present)
3394	{
3395	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3396	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3397	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3398	}
3399	}
3400
3401
3402	/**
3403	* Clear references to guest physical memory in a PAE / PAE page table.
3404	*
3405	* @param pPool The pool.
3406	* @param pPage The page.
3407	* @param pShwPT The shadow page table (mapping of the page).
3408	* @param pGstPT The guest page table.
3409	*/
3410	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3411	{
3412	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3413	if (pShwPT->a[i].n.u1Present)
3414	{
3415	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3416	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3417	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3418	}
3419	}
3420
3421
3422	/**
3423	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3424	*
3425	* @param pPool The pool.
3426	* @param pPage The page.
3427	* @param pShwPT The shadow page table (mapping of the page).
3428	*/
3429	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3430	{
3431	RTGCPHYS GCPhys = pPage->GCPhys;
3432	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3433	if (pShwPT->a[i].n.u1Present)
3434	{
3435	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3436	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3437	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3438	}
3439	}
3440
3441
3442	/**
3443	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3444	*
3445	* @param pPool The pool.
3446	* @param pPage The page.
3447	* @param pShwPT The shadow page table (mapping of the page).
3448	*/
3449	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3450	{
3451	RTGCPHYS GCPhys = pPage->GCPhys;
3452	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3453	if (pShwPT->a[i].n.u1Present)
3454	{
3455	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3456	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3457	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3458	}
3459	}
3460
3461	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3462
3463
3464	/**
3465	* Clear references to shadowed pages in a 32 bits page directory.
3466	*
3467	* @param pPool The pool.
3468	* @param pPage The page.
3469	* @param pShwPD The shadow page directory (mapping of the page).
3470	*/
3471	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3472	{
3473	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3474	{
3475	if ( pShwPD->a[i].n.u1Present
3476	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3477	)
3478	{
3479	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3480	if (pSubPage)
3481	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3482	else
3483	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3484	}
3485	}
3486	}
3487
3488	/**
3489	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3490	*
3491	* @param pPool The pool.
3492	* @param pPage The page.
3493	* @param pShwPD The shadow page directory (mapping of the page).
3494	*/
3495	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3496	{
3497	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3498	{
3499	if ( pShwPD->a[i].n.u1Present
3500	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3501	)
3502	{
3503	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3504	if (pSubPage)
3505	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3506	else
3507	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3508	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3509	}
3510	}
3511	}
3512
3513	/**
3514	* Clear references to shadowed pages in a PAE page directory pointer table.
3515	*
3516	* @param pPool The pool.
3517	* @param pPage The page.
3518	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3519	*/
3520	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3521	{
3522	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3523	{
3524	if ( pShwPDPT->a[i].n.u1Present
3525	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3526	)
3527	{
3528	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3529	if (pSubPage)
3530	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3531	else
3532	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3533	}
3534	}
3535	}
3536
3537
3538	/**
3539	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3540	*
3541	* @param pPool The pool.
3542	* @param pPage The page.
3543	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3544	*/
3545	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3546	{
3547	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3548	{
3549	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3550	if (pShwPDPT->a[i].n.u1Present)
3551	{
3552	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3553	if (pSubPage)
3554	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3555	else
3556	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3557	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3558	}
3559	}
3560	}
3561
3562
3563	/**
3564	* Clear references to shadowed pages in a 64-bit level 4 page table.
3565	*
3566	* @param pPool The pool.
3567	* @param pPage The page.
3568	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3569	*/
3570	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3571	{
3572	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3573	{
3574	if (pShwPML4->a[i].n.u1Present)
3575	{
3576	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3577	if (pSubPage)
3578	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3579	else
3580	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3581	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3582	}
3583	}
3584	}
3585
3586
3587	/**
3588	* Clear references to shadowed pages in an EPT page table.
3589	*
3590	* @param pPool The pool.
3591	* @param pPage The page.
3592	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3593	*/
3594	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3595	{
3596	RTGCPHYS GCPhys = pPage->GCPhys;
3597	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3598	if (pShwPT->a[i].n.u1Present)
3599	{
3600	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3601	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3602	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3603	}
3604	}
3605
3606
3607	/**
3608	* Clear references to shadowed pages in an EPT page directory.
3609	*
3610	* @param pPool The pool.
3611	* @param pPage The page.
3612	* @param pShwPD The shadow page directory (mapping of the page).
3613	*/
3614	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3615	{
3616	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3617	{
3618	if (pShwPD->a[i].n.u1Present)
3619	{
3620	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3621	if (pSubPage)
3622	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3623	else
3624	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3625	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3626	}
3627	}
3628	}
3629
3630
3631	/**
3632	* Clear references to shadowed pages in an EPT page directory pointer table.
3633	*
3634	* @param pPool The pool.
3635	* @param pPage The page.
3636	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3637	*/
3638	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3639	{
3640	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3641	{
3642	if (pShwPDPT->a[i].n.u1Present)
3643	{
3644	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3645	if (pSubPage)
3646	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3647	else
3648	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3649	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3650	}
3651	}
3652	}
3653
3654
3655	/**
3656	* Clears all references made by this page.
3657	*
3658	* This includes other shadow pages and GC physical addresses.
3659	*
3660	* @param pPool The pool.
3661	* @param pPage The page.
3662	*/
3663	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3664	{
3665	/*
3666	* Map the shadow page and take action according to the page kind.
3667	*/
3668	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3669	switch (pPage->enmKind)
3670	{
3671	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3672	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3673	{
3674	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3675	void *pvGst;
3676	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3677	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3678	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3679	break;
3680	}
3681
3682	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3683	{
3684	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3685	void *pvGst;
3686	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3687	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3688	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3689	break;
3690	}
3691
3692	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3693	{
3694	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3695	void *pvGst;
3696	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3697	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3698	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3699	break;
3700	}
3701
3702	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3703	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3704	{
3705	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3706	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3707	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3708	break;
3709	}
3710
3711	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3712	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3713	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3714	{
3715	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3716	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3717	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3718	break;
3719	}
3720
3721	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3722	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3723	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3724	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3725	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3726	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3727	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3728	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3729	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3730	break;
3731	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3732
3733	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3734	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3735	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3736	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3737	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3738	case PGMPOOLKIND_PAE_PD_PHYS:
3739	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3740	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3741	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3742	break;
3743
3744	case PGMPOOLKIND_32BIT_PD_PHYS:
3745	case PGMPOOLKIND_32BIT_PD:
3746	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3747	break;
3748
3749	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3750	case PGMPOOLKIND_PAE_PDPT:
3751	case PGMPOOLKIND_PAE_PDPT_PHYS:
3752	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3753	break;
3754
3755	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3756	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3757	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3758	break;
3759
3760	case PGMPOOLKIND_64BIT_PML4:
3761	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3762	break;
3763
3764	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3765	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3766	break;
3767
3768	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3769	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3770	break;
3771
3772	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3773	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3774	break;
3775
3776	default:
3777	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3778	}
3779
3780	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3781	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3782	ASMMemZeroPage(pvShw);
3783	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3784	pPage->fZeroed = true;
3785	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3786	}
3787
3788	#endif /* PGMPOOL_WITH_USER_TRACKING */
3789	#ifdef IN_RING3
3790	/**
3791	* Flushes the entire cache.
3792	*
3793	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
3794	* and execute this CR3 flush.
3795	*
3796	* @param pPool The pool.
3797	*
3798	* @remark Only used during reset now, we might want to rename and/or move it.
3799	*/
3800	static void pgmPoolFlushAllInt(PPGMPOOL pPool)
3801	{
3802	PVM pVM = pPool->CTX_SUFF(pVM);
3803
3804	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
3805	LogFlow(("pgmPoolFlushAllInt:\n"));
3806
3807	/*
3808	* If there are no pages in the pool, there is nothing to do.
3809	*/
3810	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
3811	{
3812	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3813	return;
3814	}
3815
3816	/*
3817	* Exit the shadow mode since we're going to clear everything,
3818	* including the root page.
3819	*/
3820	/** @todo Need to synchronize this across all VCPUs! */
3821	Assert(pVM->cCPUs == 1);
3822	for (unsigned i=0;i<pVM->cCPUs;i++)
3823	{
3824	PVMCPU pVCpu = &pVM->aCpus[i];
3825	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
3826	}
3827
3828	/*
3829	* Nuke the free list and reinsert all pages into it.
3830	*/
3831	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
3832	{
3833	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3834
3835	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
3836	#ifdef PGMPOOL_WITH_MONITORING
3837	if (pPage->fMonitored)
3838	pgmPoolMonitorFlush(pPool, pPage);
3839	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3840	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3841	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3842	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3843	pPage->cModifications = 0;
3844	#endif
3845	pPage->GCPhys = NIL_RTGCPHYS;
3846	pPage->enmKind = PGMPOOLKIND_FREE;
3847	Assert(pPage->idx == i);
3848	pPage->iNext = i + 1;
3849	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
3850	pPage->fSeenNonGlobal = false;
3851	pPage->fMonitored= false;
3852	pPage->fCached = false;
3853	pPage->fReusedFlushPending = false;
3854	#ifdef PGMPOOL_WITH_USER_TRACKING
3855	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3856	#else
3857	pPage->fCR3Mix = false;
3858	#endif
3859	#ifdef PGMPOOL_WITH_CACHE
3860	pPage->iAgeNext = NIL_PGMPOOL_IDX;
3861	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3862	#endif
3863	pPage->fLocked = false;
3864	}
3865	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
3866	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
3867	pPool->cUsedPages = 0;
3868
3869	#ifdef PGMPOOL_WITH_USER_TRACKING
3870	/*
3871	* Zap and reinitialize the user records.
3872	*/
3873	pPool->cPresent = 0;
3874	pPool->iUserFreeHead = 0;
3875	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3876	const unsigned cMaxUsers = pPool->cMaxUsers;
3877	for (unsigned i = 0; i < cMaxUsers; i++)
3878	{
3879	paUsers[i].iNext = i + 1;
3880	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3881	paUsers[i].iUserTable = 0xfffffffe;
3882	}
3883	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
3884	#endif
3885
3886	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3887	/*
3888	* Clear all the GCPhys links and rebuild the phys ext free list.
3889	*/
3890	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
3891	pRam;
3892	pRam = pRam->CTX_SUFF(pNext))
3893	{
3894	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3895	while (iPage-- > 0)
3896	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
3897	}
3898
3899	pPool->iPhysExtFreeHead = 0;
3900	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3901	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
3902	for (unsigned i = 0; i < cMaxPhysExts; i++)
3903	{
3904	paPhysExts[i].iNext = i + 1;
3905	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
3906	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
3907	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
3908	}
3909	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3910	#endif
3911
3912	#ifdef PGMPOOL_WITH_MONITORING
3913	/*
3914	* Just zap the modified list.
3915	*/
3916	pPool->cModifiedPages = 0;
3917	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
3918	#endif
3919
3920	#ifdef PGMPOOL_WITH_CACHE
3921	/*
3922	* Clear the GCPhys hash and the age list.
3923	*/
3924	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
3925	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
3926	pPool->iAgeHead = NIL_PGMPOOL_IDX;
3927	pPool->iAgeTail = NIL_PGMPOOL_IDX;
3928	#endif
3929
3930	/*
3931	* Reinsert active pages into the hash and ensure monitoring chains are correct.
3932	*/
3933	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
3934	{
3935	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3936	pPage->iNext = NIL_PGMPOOL_IDX;
3937	#ifdef PGMPOOL_WITH_MONITORING
3938	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3939	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3940	pPage->cModifications = 0;
3941	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
3942	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3943	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3944	if (pPage->fMonitored)
3945	{
3946	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
3947	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
3948	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
3949	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
3950	pPool->pszAccessHandler);
3951	AssertFatalRCSuccess(rc);
3952	# ifdef PGMPOOL_WITH_CACHE
3953	pgmPoolHashInsert(pPool, pPage);
3954	# endif
3955	}
3956	#endif
3957	#ifdef PGMPOOL_WITH_USER_TRACKING
3958	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
3959	#endif
3960	#ifdef PGMPOOL_WITH_CACHE
3961	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
3962	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
3963	#endif
3964	}
3965
3966	for (unsigned i=0;i<pVM->cCPUs;i++)
3967	{
3968	PVMCPU pVCpu = &pVM->aCpus[i];
3969	/*
3970	* Re-enter the shadowing mode and assert Sync CR3 FF.
3971	*/
3972	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
3973	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3974	}
3975
3976	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3977	}
3978
3979	#endif /* IN_RING3 */
3980
3981	/**
3982	* Flushes a pool page.
3983	*
3984	* This moves the page to the free list after removing all user references to it.
3985	* In GC this will cause a CR3 reload if the page is traced back to an active root page.
3986	*
3987	* @returns VBox status code.
3988	* @retval VINF_SUCCESS on success.
3989	* @param pPool The pool.
3990	* @param HCPhys The HC physical address of the shadow page.
3991	*/
3992	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3993	{
3994	PVM pVM = pPool->CTX_SUFF(pVM);
3995
3996	int rc = VINF_SUCCESS;
3997	STAM_PROFILE_START(&pPool->StatFlushPage, f);
3998	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
3999	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4000
4001	/*
4002	* Quietly reject any attempts at flushing any of the special root pages.
4003	*/
4004	if (pPage->idx < PGMPOOL_IDX_FIRST)
4005	{
4006	AssertFailed(); /* can no longer happen */
4007	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4008	return VINF_SUCCESS;
4009	}
4010
4011	pgmLock(pVM);
4012
4013	/*
4014	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4015	*/
4016	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4017	{
4018	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4019	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4020	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4021	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4022	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4023	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4024	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4025	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4026	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4027	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4028	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4029	pgmUnlock(pVM);
4030	return VINF_SUCCESS;
4031	}
4032
4033	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4034	/* Start a subset so we won't run out of mapping space. */
4035	PVMCPU pVCpu = VMMGetCpu(pVM);
4036	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4037	#endif
4038
4039	/*
4040	* Mark the page as being in need of a ASMMemZeroPage().
4041	*/
4042	pPage->fZeroed = false;
4043
4044	#ifdef PGMPOOL_WITH_USER_TRACKING
4045	/*
4046	* Clear the page.
4047	*/
4048	pgmPoolTrackClearPageUsers(pPool, pPage);
4049	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4050	pgmPoolTrackDeref(pPool, pPage);
4051	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4052	#endif
4053
4054	#ifdef PGMPOOL_WITH_CACHE
4055	/*
4056	* Flush it from the cache.
4057	*/
4058	pgmPoolCacheFlushPage(pPool, pPage);
4059	#endif /* PGMPOOL_WITH_CACHE */
4060
4061	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4062	/* Heavy stuff done. */
4063	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4064	#endif
4065
4066	#ifdef PGMPOOL_WITH_MONITORING
4067	/*
4068	* Deregistering the monitoring.
4069	*/
4070	if (pPage->fMonitored)
4071	rc = pgmPoolMonitorFlush(pPool, pPage);
4072	#endif
4073
4074	/*
4075	* Free the page.
4076	*/
4077	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4078	pPage->iNext = pPool->iFreeHead;
4079	pPool->iFreeHead = pPage->idx;
4080	pPage->enmKind = PGMPOOLKIND_FREE;
4081	pPage->GCPhys = NIL_RTGCPHYS;
4082	pPage->fReusedFlushPending = false;
4083
4084	pPool->cUsedPages--;
4085	pgmUnlock(pVM);
4086	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4087	return rc;
4088	}
4089
4090
4091	/**
4092	* Frees a usage of a pool page.
4093	*
4094	* The caller is responsible to updating the user table so that it no longer
4095	* references the shadow page.
4096	*
4097	* @param pPool The pool.
4098	* @param HCPhys The HC physical address of the shadow page.
4099	* @param iUser The shadow page pool index of the user table.
4100	* @param iUserTable The index into the user table (shadowed).
4101	*/
4102	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4103	{
4104	PVM pVM = pPool->CTX_SUFF(pVM);
4105
4106	STAM_PROFILE_START(&pPool->StatFree, a);
4107	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4108	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4109	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4110	pgmLock(pVM);
4111	#ifdef PGMPOOL_WITH_USER_TRACKING
4112	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4113	#endif
4114	#ifdef PGMPOOL_WITH_CACHE
4115	if (!pPage->fCached)
4116	#endif
4117	pgmPoolFlushPage(pPool, pPage);
4118	pgmUnlock(pVM);
4119	STAM_PROFILE_STOP(&pPool->StatFree, a);
4120	}
4121
4122
4123	/**
4124	* Makes one or more free page free.
4125	*
4126	* @returns VBox status code.
4127	* @retval VINF_SUCCESS on success.
4128	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4129	*
4130	* @param pPool The pool.
4131	* @param enmKind Page table kind
4132	* @param iUser The user of the page.
4133	*/
4134	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4135	{
4136	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4137
4138	/*
4139	* If the pool isn't full grown yet, expand it.
4140	*/
4141	if ( pPool->cCurPages < pPool->cMaxPages
4142	#if defined(IN_RC)
4143	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4144	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4145	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4146	#endif
4147	)
4148	{
4149	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4150	#ifdef IN_RING3
4151	int rc = PGMR3PoolGrow(pPool->pVMR3);
4152	#else
4153	int rc = CTXALLMID(VMM, CallHost)(pPool->CTX_SUFF(pVM), VMMCALLHOST_PGM_POOL_GROW, 0);
4154	#endif
4155	if (RT_FAILURE(rc))
4156	return rc;
4157	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4158	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4159	return VINF_SUCCESS;
4160	}
4161
4162	#ifdef PGMPOOL_WITH_CACHE
4163	/*
4164	* Free one cached page.
4165	*/
4166	return pgmPoolCacheFreeOne(pPool, iUser);
4167	#else
4168	/*
4169	* Flush the pool.
4170	*
4171	* If we have tracking enabled, it should be possible to come up with
4172	* a cheap replacement strategy...
4173	*/
4174	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4175	AssertCompileFailed();
4176	Assert(!CPUMIsGuestInLongMode(pVM));
4177	pgmPoolFlushAllInt(pPool);
4178	return VERR_PGM_POOL_FLUSHED;
4179	#endif
4180	}
4181
4182
4183	/**
4184	* Allocates a page from the pool.
4185	*
4186	* This page may actually be a cached page and not in need of any processing
4187	* on the callers part.
4188	*
4189	* @returns VBox status code.
4190	* @retval VINF_SUCCESS if a NEW page was allocated.
4191	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4192	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4193	* @param pVM The VM handle.
4194	* @param GCPhys The GC physical address of the page we're gonna shadow.
4195	* For 4MB and 2MB PD entries, it's the first address the
4196	* shadow PT is covering.
4197	* @param enmKind The kind of mapping.
4198	* @param iUser The shadow page pool index of the user table.
4199	* @param iUserTable The index into the user table (shadowed).
4200	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4201	*/
4202	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
4203	{
4204	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4205	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4206	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4207	*ppPage = NULL;
4208	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4209	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4210	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)); */
4211
4212	#ifdef PGMPOOL_WITH_CACHE
4213	if (pPool->fCacheEnabled)
4214	{
4215	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, iUser, iUserTable, ppPage);
4216	if (RT_SUCCESS(rc2))
4217	{
4218	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4219	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4220	return rc2;
4221	}
4222	}
4223	#endif
4224
4225	/*
4226	* Allocate a new one.
4227	*/
4228	int rc = VINF_SUCCESS;
4229	uint16_t iNew = pPool->iFreeHead;
4230	if (iNew == NIL_PGMPOOL_IDX)
4231	{
4232	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4233	if (RT_FAILURE(rc))
4234	{
4235	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4236	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4237	return rc;
4238	}
4239	iNew = pPool->iFreeHead;
4240	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4241	}
4242
4243	/* unlink the free head */
4244	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4245	pPool->iFreeHead = pPage->iNext;
4246	pPage->iNext = NIL_PGMPOOL_IDX;
4247
4248	/*
4249	* Initialize it.
4250	*/
4251	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4252	pPage->enmKind = enmKind;
4253	pPage->GCPhys = GCPhys;
4254	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4255	pPage->fMonitored = false;
4256	pPage->fCached = false;
4257	pPage->fReusedFlushPending = false;
4258	#ifdef PGMPOOL_WITH_MONITORING
4259	pPage->cModifications = 0;
4260	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4261	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4262	#else
4263	pPage->fCR3Mix = false;
4264	#endif
4265	#ifdef PGMPOOL_WITH_USER_TRACKING
4266	pPage->cPresent = 0;
4267	pPage->iFirstPresent = ~0;
4268
4269	/*
4270	* Insert into the tracking and cache. If this fails, free the page.
4271	*/
4272	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4273	if (RT_FAILURE(rc3))
4274	{
4275	pPool->cUsedPages--;
4276	pPage->enmKind = PGMPOOLKIND_FREE;
4277	pPage->GCPhys = NIL_RTGCPHYS;
4278	pPage->iNext = pPool->iFreeHead;
4279	pPool->iFreeHead = pPage->idx;
4280	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4281	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4282	return rc3;
4283	}
4284	#endif /* PGMPOOL_WITH_USER_TRACKING */
4285
4286	/*
4287	* Commit the allocation, clear the page and return.
4288	*/
4289	#ifdef VBOX_WITH_STATISTICS
4290	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4291	pPool->cUsedPagesHigh = pPool->cUsedPages;
4292	#endif
4293
4294	if (!pPage->fZeroed)
4295	{
4296	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4297	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4298	ASMMemZeroPage(pv);
4299	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4300	}
4301
4302	*ppPage = pPage;
4303	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4304	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4305	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4306	return rc;
4307	}
4308
4309
4310	/**
4311	* Frees a usage of a pool page.
4312	*
4313	* @param pVM The VM handle.
4314	* @param HCPhys The HC physical address of the shadow page.
4315	* @param iUser The shadow page pool index of the user table.
4316	* @param iUserTable The index into the user table (shadowed).
4317	*/
4318	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4319	{
4320	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4321	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4322	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4323	}
4324
4325
4326	#ifdef IN_RING3
4327	/**
4328	* Flushes the entire cache.
4329	*
4330	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4331	* and execute this CR3 flush.
4332	*
4333	* @param pPool The pool.
4334	*/
4335	void pgmPoolFlushAll(PVM pVM)
4336	{
4337	LogFlow(("pgmPoolFlushAll:\n"));
4338	pgmPoolFlushAllInt(pVM->pgm.s.CTX_SUFF(pPool));
4339	}
4340	#endif /* IN_RING3 */
4341
4342	#ifdef LOG_ENABLED
4343	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4344	{
4345	switch(enmKind)
4346	{
4347	case PGMPOOLKIND_INVALID:
4348	return "PGMPOOLKIND_INVALID";
4349	case PGMPOOLKIND_FREE:
4350	return "PGMPOOLKIND_FREE";
4351	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4352	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4353	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4354	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4355	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4356	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4357	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4358	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4359	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4360	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4361	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4362	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4363	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4364	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4365	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4366	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4367	case PGMPOOLKIND_32BIT_PD:
4368	return "PGMPOOLKIND_32BIT_PD";
4369	case PGMPOOLKIND_32BIT_PD_PHYS:
4370	return "PGMPOOLKIND_32BIT_PD_PHYS";
4371	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4372	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4373	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4374	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4375	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4376	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4377	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4378	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4379	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4380	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4381	case PGMPOOLKIND_PAE_PD_PHYS:
4382	return "PGMPOOLKIND_PAE_PD_PHYS";
4383	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4384	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4385	case PGMPOOLKIND_PAE_PDPT:
4386	return "PGMPOOLKIND_PAE_PDPT";
4387	case PGMPOOLKIND_PAE_PDPT_PHYS:
4388	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4389	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4390	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4391	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4392	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4393	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4394	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4395	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4396	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4397	case PGMPOOLKIND_64BIT_PML4:
4398	return "PGMPOOLKIND_64BIT_PML4";
4399	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4400	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4401	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4402	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4403	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4404	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4405	case PGMPOOLKIND_ROOT_NESTED:
4406	return "PGMPOOLKIND_ROOT_NESTED";
4407	}
4408	return "Unknown kind!";
4409	}
4410	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 19503

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