VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 22766

Last change on this file since 22766 was 22766, checked in by vboxsync, 16 years ago

pgmPoolFlushPageByGCPhys is currently only used in ring 3; save some space in the R0 & GC modules.
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1/* $Id: PGMAllPool.cpp 22766 2009-09-04 09:05:20Z vboxsync $ */
2/** @file
3 * PGM Shadow Page Pool.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_POOL
27#include <VBox/pgm.h>
28#include <VBox/mm.h>
29#include <VBox/em.h>
30#include <VBox/cpum.h>
31#ifdef IN_RC
32# include <VBox/patm.h>
33#endif
34#include "PGMInternal.h"
35#include <VBox/vm.h>
36#include <VBox/disopcode.h>
37#include <VBox/hwacc_vmx.h>
38
39#include <VBox/log.h>
40#include <VBox/err.h>
41#include <iprt/asm.h>
42#include <iprt/string.h>
43
44
45/*******************************************************************************
46* Internal Functions *
47*******************************************************************************/
48RT_C_DECLS_BEGIN
49static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50#ifdef PGMPOOL_WITH_USER_TRACKING
51DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54#endif
55#ifdef PGMPOOL_WITH_CACHE
56static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
57#endif
58#ifdef PGMPOOL_WITH_MONITORING
59static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
60#endif
61#ifndef IN_RING3
62DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
63#endif
64#ifdef LOG_ENABLED
65static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
66#endif
67
68void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
69void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
70int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
71PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
72void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
73void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
74
75RT_C_DECLS_END
76
77
78/**
79 * Checks if the specified page pool kind is for a 4MB or 2MB guest page.
80 *
81 * @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
82 * @param enmKind The page kind.
83 */
84DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
85{
86 switch (enmKind)
87 {
88 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
89 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
90 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
91 return true;
92 default:
93 return false;
94 }
95}
96
97/** @def PGMPOOL_PAGE_2_LOCKED_PTR
98 * Maps a pool page pool into the current context and lock it (RC only).
99 *
100 * @returns VBox status code.
101 * @param pVM The VM handle.
102 * @param pPage The pool page.
103 *
104 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
105 * small page window employeed by that function. Be careful.
106 * @remark There is no need to assert on the result.
107 */
108#if defined(IN_RC)
109DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
110{
111 void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
112
113 /* Make sure the dynamic mapping will not be reused. */
114 if (pv)
115 PGMDynLockHCPage(pVM, (uint8_t *)pv);
116
117 return pv;
118}
119#else
120# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
121#endif
122
123/** @def PGMPOOL_UNLOCK_PTR
124 * Unlock a previously locked dynamic caching (RC only).
125 *
126 * @returns VBox status code.
127 * @param pVM The VM handle.
128 * @param pPage The pool page.
129 *
130 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
131 * small page window employeed by that function. Be careful.
132 * @remark There is no need to assert on the result.
133 */
134#if defined(IN_RC)
135DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
136{
137 if (pvPage)
138 PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
139}
140#else
141# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
142#endif
143
144
145#ifdef PGMPOOL_WITH_MONITORING
146/**
147 * Determin the size of a write instruction.
148 * @returns number of bytes written.
149 * @param pDis The disassembler state.
150 */
151static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
152{
153 /*
154 * This is very crude and possibly wrong for some opcodes,
155 * but since it's not really supposed to be called we can
156 * probably live with that.
157 */
158 return DISGetParamSize(pDis, &pDis->param1);
159}
160
161
162/**
163 * Flushes a chain of pages sharing the same access monitor.
164 *
165 * @returns VBox status code suitable for scheduling.
166 * @param pPool The pool.
167 * @param pPage A page in the chain.
168 */
169int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
170{
171 LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
172
173 /*
174 * Find the list head.
175 */
176 uint16_t idx = pPage->idx;
177 if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
178 {
179 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
180 {
181 idx = pPage->iMonitoredPrev;
182 Assert(idx != pPage->idx);
183 pPage = &pPool->aPages[idx];
184 }
185 }
186
187 /*
188 * Iterate the list flushing each shadow page.
189 */
190 int rc = VINF_SUCCESS;
191 for (;;)
192 {
193 idx = pPage->iMonitoredNext;
194 Assert(idx != pPage->idx);
195 if (pPage->idx >= PGMPOOL_IDX_FIRST)
196 {
197 int rc2 = pgmPoolFlushPage(pPool, pPage);
198 AssertRC(rc2);
199 }
200 /* next */
201 if (idx == NIL_PGMPOOL_IDX)
202 break;
203 pPage = &pPool->aPages[idx];
204 }
205 return rc;
206}
207
208
209/**
210 * Wrapper for getting the current context pointer to the entry being modified.
211 *
212 * @returns VBox status code suitable for scheduling.
213 * @param pVM VM Handle.
214 * @param pvDst Destination address
215 * @param pvSrc Source guest virtual address.
216 * @param GCPhysSrc The source guest physical address.
217 * @param cb Size of data to read
218 */
219DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
220{
221#if defined(IN_RING3)
222 memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
223 return VINF_SUCCESS;
224#else
225 /* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
226 return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
227#endif
228}
229
230/**
231 * Process shadow entries before they are changed by the guest.
232 *
233 * For PT entries we will clear them. For PD entries, we'll simply check
234 * for mapping conflicts and set the SyncCR3 FF if found.
235 *
236 * @param pVCpu VMCPU handle
237 * @param pPool The pool.
238 * @param pPage The head page.
239 * @param GCPhysFault The guest physical fault address.
240 * @param uAddress In R0 and GC this is the guest context fault address (flat).
241 * In R3 this is the host context 'fault' address.
242 * @param pDis The disassembler state for figuring out the write size.
243 * This need not be specified if the caller knows we won't do cross entry accesses.
244 */
245void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pDis)
246{
247 AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%#x (idx=%#x)\n", pPage->iMonitoredPrev, pPage->idx));
248 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
249 const unsigned cbWrite = pDis ? pgmPoolDisasWriteSize(pDis) : 0;
250 PVM pVM = pPool->CTX_SUFF(pVM);
251
252 LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, cbWrite));
253
254 for (;;)
255 {
256 union
257 {
258 void *pv;
259 PX86PT pPT;
260 PX86PTPAE pPTPae;
261 PX86PD pPD;
262 PX86PDPAE pPDPae;
263 PX86PDPT pPDPT;
264 PX86PML4 pPML4;
265 } uShw;
266
267 LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
268
269 uShw.pv = NULL;
270 switch (pPage->enmKind)
271 {
272 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273 {
274 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275 const unsigned iShw = off / sizeof(X86PTE);
276 LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277 if (uShw.pPT->a[iShw].n.u1Present)
278 {
279# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280 X86PTE GstPte;
281
282 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283 AssertRC(rc);
284 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285 pgmPoolTracDerefGCPhysHint(pPool, pPage,
286 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287 GstPte.u & X86_PTE_PG_MASK);
288# endif
289 ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
290 }
291 break;
292 }
293
294 /* page/2 sized */
295 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296 {
297 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298 if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299 {
300 const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301 LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302 if (uShw.pPTPae->a[iShw].n.u1Present)
303 {
304# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305 X86PTE GstPte;
306 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307 AssertRC(rc);
308
309 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310 pgmPoolTracDerefGCPhysHint(pPool, pPage,
311 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312 GstPte.u & X86_PTE_PG_MASK);
313# endif
314 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
315 }
316 }
317 break;
318 }
319
320 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324 {
325 unsigned iGst = off / sizeof(X86PDE);
326 unsigned iShwPdpt = iGst / 256;
327 unsigned iShw = (iGst % 256) * 2;
328 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330 LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331 if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332 {
333 for (unsigned i = 0; i < 2; i++)
334 {
335# ifndef IN_RING0
336 if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
337 {
338 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341 break;
342 }
343 else
344# endif /* !IN_RING0 */
345 if (uShw.pPDPae->a[iShw+i].n.u1Present)
346 {
347 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348 pgmPoolFree(pVM,
349 uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350 pPage->idx,
351 iShw + i);
352 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
353 }
354
355 /* paranoia / a bit assumptive. */
356 if ( pDis
357 && (off & 3)
358 && (off & 3) + cbWrite > 4)
359 {
360 const unsigned iShw2 = iShw + 2 + i;
361 if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362 {
363# ifndef IN_RING0
364 if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
365 {
366 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369 break;
370 }
371 else
372# endif /* !IN_RING0 */
373 if (uShw.pPDPae->a[iShw2].n.u1Present)
374 {
375 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376 pgmPoolFree(pVM,
377 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378 pPage->idx,
379 iShw2);
380 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
381 }
382 }
383 }
384 }
385 }
386 break;
387 }
388
389 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390 {
391 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392 const unsigned iShw = off / sizeof(X86PTEPAE);
393 if (uShw.pPTPae->a[iShw].n.u1Present)
394 {
395# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396 X86PTEPAE GstPte;
397 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398 AssertRC(rc);
399
400 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401 pgmPoolTracDerefGCPhysHint(pPool, pPage,
402 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403 GstPte.u & X86_PTE_PAE_PG_MASK);
404# endif
405 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
406 }
407
408 /* paranoia / a bit assumptive. */
409 if ( pDis
410 && (off & 7)
411 && (off & 7) + cbWrite > sizeof(X86PTEPAE))
412 {
413 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416 if (uShw.pPTPae->a[iShw2].n.u1Present)
417 {
418# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419 X86PTEPAE GstPte;
420# ifdef IN_RING3
421 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422# else
423 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424# endif
425 AssertRC(rc);
426 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427 pgmPoolTracDerefGCPhysHint(pPool, pPage,
428 uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429 GstPte.u & X86_PTE_PAE_PG_MASK);
430# endif
431 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
432 }
433 }
434 break;
435 }
436
437 case PGMPOOLKIND_32BIT_PD:
438 {
439 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440 const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442 LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443# ifndef IN_RING0
444 if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445 {
446 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450 break;
451 }
452# endif /* !IN_RING0 */
453# ifndef IN_RING0
454 else
455# endif /* !IN_RING0 */
456 {
457 if (uShw.pPD->a[iShw].n.u1Present)
458 {
459 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460 pgmPoolFree(pVM,
461 uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462 pPage->idx,
463 iShw);
464 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
465 }
466 }
467 /* paranoia / a bit assumptive. */
468 if ( pDis
469 && (off & 3)
470 && (off & 3) + cbWrite > sizeof(X86PTE))
471 {
472 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473 if ( iShw2 != iShw
474 && iShw2 < RT_ELEMENTS(uShw.pPD->a))
475 {
476# ifndef IN_RING0
477 if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478 {
479 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483 break;
484 }
485# endif /* !IN_RING0 */
486# ifndef IN_RING0
487 else
488# endif /* !IN_RING0 */
489 {
490 if (uShw.pPD->a[iShw2].n.u1Present)
491 {
492 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493 pgmPoolFree(pVM,
494 uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495 pPage->idx,
496 iShw2);
497 ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
498 }
499 }
500 }
501 }
502#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503 if ( uShw.pPD->a[iShw].n.u1Present
504 && !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505 {
506 LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508 ASMProbeReadByte(pvAddress);
509# endif
510 pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
512 }
513#endif
514 break;
515 }
516
517 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518 {
519 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520 const unsigned iShw = off / sizeof(X86PDEPAE);
521#ifndef IN_RING0
522 if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523 {
524 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528 break;
529 }
530#endif /* !IN_RING0 */
531 /*
532 * Causes trouble when the guest uses a PDE to refer to the whole page table level
533 * structure. (Invalidate here; faults later on when it tries to change the page
534 * table entries -> recheck; probably only applies to the RC case.)
535 */
536# ifndef IN_RING0
537 else
538# endif /* !IN_RING0 */
539 {
540 if (uShw.pPDPae->a[iShw].n.u1Present)
541 {
542 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543 pgmPoolFree(pVM,
544 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545 pPage->idx,
546 iShw);
547 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
548 }
549 }
550 /* paranoia / a bit assumptive. */
551 if ( pDis
552 && (off & 7)
553 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
554 {
555 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558#ifndef IN_RING0
559 if ( iShw2 != iShw
560 && uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561 {
562 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566 break;
567 }
568#endif /* !IN_RING0 */
569# ifndef IN_RING0
570 else
571# endif /* !IN_RING0 */
572 if (uShw.pPDPae->a[iShw2].n.u1Present)
573 {
574 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575 pgmPoolFree(pVM,
576 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577 pPage->idx,
578 iShw2);
579 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
580 }
581 }
582 break;
583 }
584
585 case PGMPOOLKIND_PAE_PDPT:
586 {
587 /*
588 * Hopefully this doesn't happen very often:
589 * - touching unused parts of the page
590 * - messing with the bits of pd pointers without changing the physical address
591 */
592 /* PDPT roots are not page aligned; 32 byte only! */
593 const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596 const unsigned iShw = offPdpt / sizeof(X86PDPE);
597 if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598 {
599# ifndef IN_RING0
600 if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601 {
602 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605 LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606 break;
607 }
608# endif /* !IN_RING0 */
609# ifndef IN_RING0
610 else
611# endif /* !IN_RING0 */
612 if (uShw.pPDPT->a[iShw].n.u1Present)
613 {
614 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615 pgmPoolFree(pVM,
616 uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617 pPage->idx,
618 iShw);
619 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
620 }
621
622 /* paranoia / a bit assumptive. */
623 if ( pDis
624 && (offPdpt & 7)
625 && (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626 {
627 const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628 if ( iShw2 != iShw
629 && iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630 {
631# ifndef IN_RING0
632 if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633 {
634 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638 break;
639 }
640# endif /* !IN_RING0 */
641# ifndef IN_RING0
642 else
643# endif /* !IN_RING0 */
644 if (uShw.pPDPT->a[iShw2].n.u1Present)
645 {
646 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647 pgmPoolFree(pVM,
648 uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649 pPage->idx,
650 iShw2);
651 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
652 }
653 }
654 }
655 }
656 break;
657 }
658
659#ifndef IN_RC
660 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661 {
662 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663 const unsigned iShw = off / sizeof(X86PDEPAE);
664 Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665 if (uShw.pPDPae->a[iShw].n.u1Present)
666 {
667 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668 pgmPoolFree(pVM,
669 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670 pPage->idx,
671 iShw);
672 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
673 }
674 /* paranoia / a bit assumptive. */
675 if ( pDis
676 && (off & 7)
677 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
678 {
679 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682 Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683 if (uShw.pPDPae->a[iShw2].n.u1Present)
684 {
685 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686 pgmPoolFree(pVM,
687 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688 pPage->idx,
689 iShw2);
690 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
691 }
692 }
693 break;
694 }
695
696 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697 {
698 /*
699 * Hopefully this doesn't happen very often:
700 * - messing with the bits of pd pointers without changing the physical address
701 */
702 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703 {
704 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705 const unsigned iShw = off / sizeof(X86PDPE);
706 if (uShw.pPDPT->a[iShw].n.u1Present)
707 {
708 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709 pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
711 }
712 /* paranoia / a bit assumptive. */
713 if ( pDis
714 && (off & 7)
715 && (off & 7) + cbWrite > sizeof(X86PDPE))
716 {
717 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718 if (uShw.pPDPT->a[iShw2].n.u1Present)
719 {
720 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721 pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
723 }
724 }
725 }
726 break;
727 }
728
729 case PGMPOOLKIND_64BIT_PML4:
730 {
731 /*
732 * Hopefully this doesn't happen very often:
733 * - messing with the bits of pd pointers without changing the physical address
734 */
735 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736 {
737 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738 const unsigned iShw = off / sizeof(X86PDPE);
739 if (uShw.pPML4->a[iShw].n.u1Present)
740 {
741 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742 pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743 ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
744 }
745 /* paranoia / a bit assumptive. */
746 if ( pDis
747 && (off & 7)
748 && (off & 7) + cbWrite > sizeof(X86PDPE))
749 {
750 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751 if (uShw.pPML4->a[iShw2].n.u1Present)
752 {
753 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754 pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755 ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
756 }
757 }
758 }
759 break;
760 }
761#endif /* IN_RING0 */
762
763 default:
764 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765 }
766 PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768 /* next */
769 if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770 return;
771 pPage = &pPool->aPages[pPage->iMonitoredNext];
772 }
773}
774
775# ifndef IN_RING3
776/**
777 * Checks if a access could be a fork operation in progress.
778 *
779 * Meaning, that the guest is setting up the parent process for Copy-On-Write.
780 *
781 * @returns true if it's likly that we're forking, otherwise false.
782 * @param pPool The pool.
783 * @param pDis The disassembled instruction.
784 * @param offFault The access offset.
785 */
786DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
787{
788 /*
789 * i386 linux is using btr to clear X86_PTE_RW.
790 * The functions involved are (2.6.16 source inspection):
791 * clear_bit
792 * ptep_set_wrprotect
793 * copy_one_pte
794 * copy_pte_range
795 * copy_pmd_range
796 * copy_pud_range
797 * copy_page_range
798 * dup_mmap
799 * dup_mm
800 * copy_mm
801 * copy_process
802 * do_fork
803 */
804 if ( pDis->pCurInstr->opcode == OP_BTR
805 && !(offFault & 4)
806 /** @todo Validate that the bit index is X86_PTE_RW. */
807 )
808 {
809 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810 return true;
811 }
812 return false;
813}
814
815
816/**
817 * Determine whether the page is likely to have been reused.
818 *
819 * @returns true if we consider the page as being reused for a different purpose.
820 * @returns false if we consider it to still be a paging page.
821 * @param pVM VM Handle.
822 * @param pVCpu VMCPU Handle.
823 * @param pRegFrame Trap register frame.
824 * @param pDis The disassembly info for the faulting instruction.
825 * @param pvFault The fault address.
826 *
827 * @remark The REP prefix check is left to the caller because of STOSD/W.
828 */
829DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
830{
831#ifndef IN_RC
832 /** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
833 if ( HWACCMHasPendingIrq(pVM)
834 && (pRegFrame->rsp - pvFault) < 32)
835 {
836 /* Fault caused by stack writes while trying to inject an interrupt event. */
837 Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
838 return true;
839 }
840#else
841 NOREF(pVM); NOREF(pvFault);
842#endif
843
844 LogFlow(("Reused instr %RGv %d at %RGv param1.flags=%x param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.flags, pDis->param1.base.reg_gen));
845
846 /* Non-supervisor mode write means it's used for something else. */
847 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
848 return true;
849
850 switch (pDis->pCurInstr->opcode)
851 {
852 /* call implies the actual push of the return address faulted */
853 case OP_CALL:
854 Log4(("pgmPoolMonitorIsReused: CALL\n"));
855 return true;
856 case OP_PUSH:
857 Log4(("pgmPoolMonitorIsReused: PUSH\n"));
858 return true;
859 case OP_PUSHF:
860 Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
861 return true;
862 case OP_PUSHA:
863 Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
864 return true;
865 case OP_FXSAVE:
866 Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
867 return true;
868 case OP_MOVNTI: /* solaris - block_zero_no_xmm */
869 Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
870 return true;
871 case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
872 Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
873 return true;
874 case OP_MOVSWD:
875 case OP_STOSWD:
876 if ( pDis->prefix == (PREFIX_REP|PREFIX_REX)
877 && pRegFrame->rcx >= 0x40
878 )
879 {
880 Assert(pDis->mode == CPUMODE_64BIT);
881
882 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
883 return true;
884 }
885 return false;
886 }
887 if ( ( (pDis->param1.flags & USE_REG_GEN32)
888 || (pDis->param1.flags & USE_REG_GEN64))
889 && (pDis->param1.base.reg_gen == USE_REG_ESP))
890 {
891 Log4(("pgmPoolMonitorIsReused: ESP\n"));
892 return true;
893 }
894
895 return false;
896}
897
898
899/**
900 * Handles the STOSD write accesses.
901 *
902 * @returns VBox status code suitable for scheduling.
903 * @param pVM The VM handle.
904 * @param pPool The pool.
905 * @param pPage The pool page (head).
906 * @param pDis The disassembly of the write instruction.
907 * @param pRegFrame The trap register frame.
908 * @param GCPhysFault The fault address as guest physical address.
909 * @param pvFault The fault address.
910 */
911DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
912 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
913{
914 unsigned uIncrement = pDis->param1.size;
915
916 Assert(pDis->mode == CPUMODE_32BIT || pDis->mode == CPUMODE_64BIT);
917 Assert(pRegFrame->rcx <= 0x20);
918
919#ifdef VBOX_STRICT
920 if (pDis->opmode == CPUMODE_32BIT)
921 Assert(uIncrement == 4);
922 else
923 Assert(uIncrement == 8);
924#endif
925
926 Log3(("pgmPoolAccessHandlerSTOSD\n"));
927
928 /*
929 * Increment the modification counter and insert it into the list
930 * of modified pages the first time.
931 */
932 if (!pPage->cModifications++)
933 pgmPoolMonitorModifiedInsert(pPool, pPage);
934
935 /*
936 * Execute REP STOSD.
937 *
938 * This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
939 * write situation, meaning that it's safe to write here.
940 */
941 PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
942 RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
943 while (pRegFrame->rcx)
944 {
945#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
946 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
947 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
948 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
949#else
950 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
951#endif
952#ifdef IN_RC
953 *(uint32_t *)pu32 = pRegFrame->eax;
954#else
955 PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
956#endif
957 pu32 += uIncrement;
958 GCPhysFault += uIncrement;
959 pRegFrame->rdi += uIncrement;
960 pRegFrame->rcx--;
961 }
962 pRegFrame->rip += pDis->opsize;
963
964#ifdef IN_RC
965 /* See use in pgmPoolAccessHandlerSimple(). */
966 PGM_INVL_VCPU_TLBS(pVCpu);
967#endif
968
969 LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
970 return VINF_SUCCESS;
971}
972
973
974/**
975 * Handles the simple write accesses.
976 *
977 * @returns VBox status code suitable for scheduling.
978 * @param pVM The VM handle.
979 * @param pVCpu The VMCPU handle.
980 * @param pPool The pool.
981 * @param pPage The pool page (head).
982 * @param pDis The disassembly of the write instruction.
983 * @param pRegFrame The trap register frame.
984 * @param GCPhysFault The fault address as guest physical address.
985 * @param pvFault The fault address.
986 * @param pfReused Reused state (out)
987 */
988DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
989 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
990{
991 Log3(("pgmPoolAccessHandlerSimple\n"));
992 /*
993 * Increment the modification counter and insert it into the list
994 * of modified pages the first time.
995 */
996 if (!pPage->cModifications++)
997 pgmPoolMonitorModifiedInsert(pPool, pPage);
998
999 /*
1000 * Clear all the pages. ASSUMES that pvFault is readable.
1001 */
1002#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1003 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1004 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1005 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1006#else
1007 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1008#endif
1009
1010 /*
1011 * Interpret the instruction.
1012 */
1013 uint32_t cb;
1014 int rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb);
1015 if (RT_SUCCESS(rc))
1016 pRegFrame->rip += pDis->opsize;
1017 else if (rc == VERR_EM_INTERPRETER)
1018 {
1019 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1020 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
1021 rc = VINF_EM_RAW_EMULATE_INSTR;
1022 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1023 }
1024
1025 if (rc == VINF_SUCCESS)
1026 {
1027 switch (pPage->enmKind)
1028 {
1029 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1030 {
1031 X86PTEPAE GstPte;
1032 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1033 AssertRC(rc);
1034
1035 /* Check the new value written by the guest. If present and with a bogus physical address, then
1036 * it's fairly safe to assume the guest is reusing the PT.
1037 */
1038 if (GstPte.n.u1Present)
1039 {
1040 RTHCPHYS HCPhys = -1;
1041 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1042 if (rc != VINF_SUCCESS)
1043 {
1044 *pfReused = true;
1045 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1046 }
1047 }
1048 break;
1049 }
1050 }
1051 }
1052
1053#ifdef IN_RC
1054 /*
1055 * Quick hack, with logging enabled we're getting stale
1056 * code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1057 * Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1058 * have to be fixed to support this. But that'll have to wait till next week.
1059 *
1060 * An alternative is to keep track of the changed PTEs together with the
1061 * GCPhys from the guest PT. This may proove expensive though.
1062 *
1063 * At the moment, it's VITAL that it's done AFTER the instruction interpreting
1064 * because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1065 */
1066 PGM_INVL_VCPU_TLBS(pVCpu);
1067#endif
1068
1069 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1070 return rc;
1071}
1072
1073/**
1074 * \#PF Handler callback for PT write accesses.
1075 *
1076 * @returns VBox status code (appropriate for GC return).
1077 * @param pVM VM Handle.
1078 * @param uErrorCode CPU Error code.
1079 * @param pRegFrame Trap register frame.
1080 * NULL on DMA and other non CPU access.
1081 * @param pvFault The fault address (cr2).
1082 * @param GCPhysFault The GC physical address corresponding to pvFault.
1083 * @param pvUser User argument.
1084 */
1085DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1086{
1087 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1088 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1089 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1090 PVMCPU pVCpu = VMMGetCpu(pVM);
1091 unsigned cMaxModifications;
1092 bool fForcedFlush = false;
1093
1094 LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1095
1096 pgmLock(pVM);
1097 if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1098 {
1099 /* Pool page changed while we were waiting for the lock; ignore. */
1100 Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1101 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1102 pgmUnlock(pVM);
1103 return VINF_SUCCESS;
1104 }
1105
1106 /*
1107 * Disassemble the faulting instruction.
1108 */
1109 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1110 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1111 AssertReturnStmt(rc == VINF_SUCCESS, pgmUnlock(pVM), rc);
1112
1113 Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1114
1115 /*
1116 * We should ALWAYS have the list head as user parameter. This
1117 * is because we use that page to record the changes.
1118 */
1119 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1120#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1121 Assert(!pPage->fDirty);
1122#endif
1123
1124 /* Maximum nr of modifications depends on the guest mode. */
1125 if (pDis->mode == CPUMODE_32BIT)
1126 cMaxModifications = 48;
1127 else
1128 cMaxModifications = 24;
1129
1130 /*
1131 * Incremental page table updates should weight more than random ones.
1132 * (Only applies when started from offset 0)
1133 */
1134 pVCpu->pgm.s.cPoolAccessHandler++;
1135 if ( pPage->pvLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1136 && pPage->pvLastAccessHandlerRip < pRegFrame->rip + 0x40
1137 && pvFault == (pPage->pvLastAccessHandlerFault + pDis->param1.size)
1138 && pVCpu->pgm.s.cPoolAccessHandler == (pPage->cLastAccessHandlerCount + 1))
1139 {
1140 Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1141 pPage->cModifications = pPage->cModifications * 2;
1142 pPage->pvLastAccessHandlerFault = pvFault;
1143 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1144 if (pPage->cModifications >= cMaxModifications)
1145 {
1146 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1147 fForcedFlush = true;
1148 }
1149 }
1150
1151 if (pPage->cModifications >= cMaxModifications)
1152 Log(("Mod overflow %VGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1153
1154 /*
1155 * Check if it's worth dealing with.
1156 */
1157 bool fReused = false;
1158 bool fNotReusedNotForking = false;
1159 if ( ( pPage->cModifications < cMaxModifications /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
1160 || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1161 )
1162 && !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1163 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1164 {
1165 /*
1166 * Simple instructions, no REP prefix.
1167 */
1168 if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE)))
1169 {
1170 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1171 if (fReused)
1172 goto flushPage;
1173
1174 /* A mov instruction to change the first page table entry will be remembered so we can detect
1175 * full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1176 */
1177 if ( rc == VINF_SUCCESS
1178 && pDis->pCurInstr->opcode == OP_MOV
1179 && (pvFault & PAGE_OFFSET_MASK) == 0)
1180 {
1181 pPage->pvLastAccessHandlerFault = pvFault;
1182 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1183 pPage->pvLastAccessHandlerRip = pRegFrame->rip;
1184 /* Make sure we don't kick out a page too quickly. */
1185 if (pPage->cModifications > 8)
1186 pPage->cModifications = 2;
1187 }
1188 else
1189 if (pPage->pvLastAccessHandlerFault == pvFault)
1190 {
1191 /* ignore the 2nd write to this page table entry. */
1192 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1193 }
1194 else
1195 {
1196 pPage->pvLastAccessHandlerFault = 0;
1197 pPage->pvLastAccessHandlerRip = 0;
1198 }
1199
1200 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1201 pgmUnlock(pVM);
1202 return rc;
1203 }
1204
1205 /*
1206 * Windows is frequently doing small memset() operations (netio test 4k+).
1207 * We have to deal with these or we'll kill the cache and performance.
1208 */
1209 if ( pDis->pCurInstr->opcode == OP_STOSWD
1210 && !pRegFrame->eflags.Bits.u1DF
1211 && pDis->opmode == pDis->mode
1212 && pDis->addrmode == pDis->mode)
1213 {
1214 bool fValidStosd = false;
1215
1216 if ( pDis->mode == CPUMODE_32BIT
1217 && pDis->prefix == PREFIX_REP
1218 && pRegFrame->ecx <= 0x20
1219 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1220 && !((uintptr_t)pvFault & 3)
1221 && (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */
1222 )
1223 {
1224 fValidStosd = true;
1225 pRegFrame->rcx &= 0xffffffff; /* paranoia */
1226 }
1227 else
1228 if ( pDis->mode == CPUMODE_64BIT
1229 && pDis->prefix == (PREFIX_REP | PREFIX_REX)
1230 && pRegFrame->rcx <= 0x20
1231 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1232 && !((uintptr_t)pvFault & 7)
1233 && (pRegFrame->rax == 0 || pRegFrame->rax == 0x80) /* the two values observed. */
1234 )
1235 {
1236 fValidStosd = true;
1237 }
1238
1239 if (fValidStosd)
1240 {
1241 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1242 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1243 pgmUnlock(pVM);
1244 return rc;
1245 }
1246 }
1247
1248 /* REP prefix, don't bother. */
1249 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1250 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1251 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1252 fNotReusedNotForking = true;
1253 }
1254
1255#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1256 /* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1257 * leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1258 */
1259 if ( pPage->cModifications >= cMaxModifications
1260 && !fForcedFlush
1261 && pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1262 && ( fNotReusedNotForking
1263 || ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1264 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1265 )
1266 )
1267 {
1268 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
1269 Assert(pPage->fDirty == false);
1270
1271 /* Flush any monitored duplicates as we will disable write protection. */
1272 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1273 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1274 {
1275 PPGMPOOLPAGE pPageHead = pPage;
1276
1277 /* Find the monitor head. */
1278 while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1279 pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1280
1281 while (pPageHead)
1282 {
1283 unsigned idxNext = pPageHead->iMonitoredNext;
1284
1285 if (pPageHead != pPage)
1286 {
1287 STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1288 Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1289 int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1290 AssertRC(rc2);
1291 }
1292
1293 if (idxNext == NIL_PGMPOOL_IDX)
1294 break;
1295
1296 pPageHead = &pPool->aPages[idxNext];
1297 }
1298 }
1299
1300 /* The flushing above might fail for locked pages, so double check. */
1301 if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1302 && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1303 {
1304 /* Temporarily allow write access to the page table again. */
1305 rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys, pPage->GCPhys);
1306 if (rc == VINF_SUCCESS)
1307 {
1308 rc = PGMShwModifyPage(pVCpu, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
1309 AssertMsg(rc == VINF_SUCCESS
1310 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1311 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1312 || rc == VERR_PAGE_NOT_PRESENT,
1313 ("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1314
1315 pgmPoolAddDirtyPage(pVM, pPool, pPage);
1316 pPage->pvDirtyFault = pvFault;
1317
1318 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1319 pgmUnlock(pVM);
1320 return rc;
1321 }
1322 }
1323 }
1324#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1325
1326 /*
1327 * Not worth it, so flush it.
1328 */
1329flushPage:
1330 rc = pgmPoolMonitorChainFlush(pPool, pPage);
1331 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1332 pgmUnlock(pVM);
1333 return rc;
1334}
1335
1336# endif /* !IN_RING3 */
1337
1338# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1339
1340# ifdef VBOX_STRICT
1341/**
1342 * Check references to guest physical memory in a PAE / PAE page table.
1343 *
1344 * @param pPool The pool.
1345 * @param pPage The page.
1346 * @param pShwPT The shadow page table (mapping of the page).
1347 * @param pGstPT The guest page table.
1348 */
1349DECLINLINE(void) pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
1350{
1351 unsigned cErrors = 0;
1352#ifdef VBOX_STRICT
1353 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1354 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1355#endif
1356 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1357 {
1358 if (pShwPT->a[i].n.u1Present)
1359 {
1360 RTHCPHYS HCPhys = -1;
1361 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1362 if ( rc != VINF_SUCCESS
1363 || (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys)
1364 {
1365 RTHCPHYS HCPhysPT = -1;
1366 Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1367 cErrors++;
1368
1369 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pPage->GCPhys, &HCPhysPT);
1370 AssertRC(rc);
1371
1372 for (unsigned i = 0; i < pPool->cCurPages; i++)
1373 {
1374 PPGMPOOLPAGE pTempPage = &pPool->aPages[i];
1375
1376 if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1377 {
1378 PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pTempPage);
1379
1380 for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1381 {
1382 if ( pShwPT2->a[j].n.u1Present
1383 && pShwPT2->a[j].n.u1Write
1384 && ((pShwPT2->a[j].u & X86_PTE_PAE_PG_MASK) == HCPhysPT))
1385 {
1386 Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, pShwPT->a[j].u, pShwPT2->a[j].u));
1387 }
1388 }
1389 }
1390 }
1391 }
1392 }
1393 }
1394 Assert(!cErrors);
1395}
1396# endif /* VBOX_STRICT */
1397
1398/**
1399 * Clear references to guest physical memory in a PAE / PAE page table.
1400 *
1401 * @returns nr of changed PTEs
1402 * @param pPool The pool.
1403 * @param pPage The page.
1404 * @param pShwPT The shadow page table (mapping of the page).
1405 * @param pGstPT The guest page table.
1406 * @param pOldGstPT The old cached guest page table.
1407 */
1408DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT, PCX86PTPAE pOldGstPT)
1409{
1410 unsigned cChanged = 0;
1411
1412#ifdef VBOX_STRICT
1413 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1414 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1415#endif
1416 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1417 {
1418 if (pShwPT->a[i].n.u1Present)
1419 {
1420 /* The the old cached PTE is identical, then there's no need to flush the shadow copy. */
1421 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1422 {
1423#ifdef VBOX_STRICT
1424 RTHCPHYS HCPhys = -1;
1425 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1426 AssertMsg(rc == VINF_SUCCESS && (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1427#endif
1428 uint64_t uHostAttr = pShwPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1429 bool fHostRW = !!(pShwPT->a[i].u & X86_PTE_RW);
1430 uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1431 bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1432
1433 if ( uHostAttr == uGuestAttr
1434 && fHostRW <= fGuestRW)
1435 continue;
1436 }
1437 cChanged++;
1438 /* Something was changed, so flush it. */
1439 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1440 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1441 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
1442 ASMAtomicWriteSize(&pShwPT->a[i].u, 0);
1443 }
1444 }
1445 return cChanged;
1446}
1447
1448
1449/**
1450 * Flush a dirty page
1451 *
1452 * @param pVM VM Handle.
1453 * @param pPool The pool.
1454 * @param idxSlot Dirty array slot index
1455 * @param fForceRemoval Force removal from the dirty page list
1456 */
1457static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fForceRemoval = false)
1458{
1459 PPGMPOOLPAGE pPage;
1460 unsigned idxPage;
1461
1462 Assert(idxSlot < RT_ELEMENTS(pPool->aIdxDirtyPages));
1463 if (pPool->aIdxDirtyPages[idxSlot] == NIL_PGMPOOL_IDX)
1464 return;
1465
1466 idxPage = pPool->aIdxDirtyPages[idxSlot];
1467 AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1468 pPage = &pPool->aPages[idxPage];
1469 Assert(pPage->idx == idxPage);
1470 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1471
1472 AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1473 Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1474
1475 /* Flush those PTEs that have changed. */
1476 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1477 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1478 void *pvGst;
1479 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1480 unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst, (PCX86PTPAE)&pPool->aDirtyPages[idxSlot][0]);
1481 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1482
1483 /** Note: we might want to consider keeping the dirty page active in case there were many changes. */
1484
1485 /* Write protect the page again to catch all write accesses. */
1486 rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys);
1487 Assert(rc == VINF_SUCCESS);
1488 pPage->fDirty = false;
1489
1490#ifdef VBOX_STRICT
1491 uint64_t fFlags = 0;
1492 RTHCPHYS HCPhys;
1493 rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys);
1494 AssertMsg( ( rc == VINF_SUCCESS
1495 && (!(fFlags & X86_PTE_RW) || HCPhys != pPage->Core.Key))
1496 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1497 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1498 || rc == VERR_PAGE_NOT_PRESENT,
1499 ("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags));
1500#endif
1501
1502 /* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1503 Assert(pPage->cModifications);
1504 if (cChanges < 4)
1505 pPage->cModifications = 1; /* must use > 0 here */
1506 else
1507 pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1508
1509 STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1510 if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages))
1511 pPool->idxFreeDirtyPage = idxSlot;
1512
1513 pPool->cDirtyPages--;
1514 pPool->aIdxDirtyPages[idxSlot] = NIL_PGMPOOL_IDX;
1515 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1516 Log(("Removed dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1517}
1518
1519# ifndef IN_RING3
1520/**
1521 * Add a new dirty page
1522 *
1523 * @param pVM VM Handle.
1524 * @param pPool The pool.
1525 * @param pPage The page.
1526 */
1527void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1528{
1529 unsigned idxFree;
1530
1531 Assert(PGMIsLocked(pVM));
1532 AssertCompile(RT_ELEMENTS(pPool->aIdxDirtyPages) == 8 || RT_ELEMENTS(pPool->aIdxDirtyPages) == 16);
1533 Assert(!pPage->fDirty);
1534
1535 idxFree = pPool->idxFreeDirtyPage;
1536 Assert(idxFree < RT_ELEMENTS(pPool->aIdxDirtyPages));
1537 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1538
1539 if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aIdxDirtyPages))
1540 pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* force removal */);
1541 Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages));
1542 AssertMsg(pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1543
1544 Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1545
1546 /* Make a copy of the guest page table as we require valid GCPhys addresses when removing
1547 * references to physical pages. (the HCPhys linear lookup is *extremely* expensive!)
1548 */
1549 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1550 void *pvGst;
1551 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1552 memcpy(&pPool->aDirtyPages[idxFree][0], pvGst, PAGE_SIZE);
1553#ifdef VBOX_STRICT
1554 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1555#endif
1556
1557 STAM_COUNTER_INC(&pPool->StatDirtyPage);
1558 pPage->fDirty = true;
1559 pPage->idxDirty = idxFree;
1560 pPool->aIdxDirtyPages[idxFree] = pPage->idx;
1561 pPool->cDirtyPages++;
1562
1563 pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1564 if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages)
1565 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1566 {
1567 unsigned i;
1568 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1569 {
1570 idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1571 if (pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX)
1572 {
1573 pPool->idxFreeDirtyPage = idxFree;
1574 break;
1575 }
1576 }
1577 Assert(i != RT_ELEMENTS(pPool->aIdxDirtyPages));
1578 }
1579
1580 Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages) || pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX);
1581 return;
1582}
1583# endif /* !IN_RING3 */
1584
1585/**
1586 * Check if the specified page is dirty (not write monitored)
1587 *
1588 * @return dirty or not
1589 * @param pVM VM Handle.
1590 * @param GCPhys Guest physical address
1591 */
1592bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1593{
1594 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1595 Assert(PGMIsLocked(pVM));
1596 if (!pPool->cDirtyPages)
1597 return false;
1598
1599 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1600
1601 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1602 {
1603 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1604 {
1605 PPGMPOOLPAGE pPage;
1606 unsigned idxPage = pPool->aIdxDirtyPages[i];
1607
1608 pPage = &pPool->aPages[idxPage];
1609 if (pPage->GCPhys == GCPhys)
1610 return true;
1611 }
1612 }
1613 return false;
1614}
1615
1616/**
1617 * Reset all dirty pages by reinstating page monitoring.
1618 *
1619 * @param pVM VM Handle.
1620 * @param fForceRemoval Force removal of all dirty pages
1621 */
1622void pgmPoolResetDirtyPages(PVM pVM, bool fForceRemoval)
1623{
1624 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1625 Assert(PGMIsLocked(pVM));
1626 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1627
1628 if (!pPool->cDirtyPages)
1629 return;
1630
1631 Log(("pgmPoolResetDirtyPages\n"));
1632 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1633 pgmPoolFlushDirtyPage(pVM, pPool, i, fForceRemoval);
1634
1635 pPool->idxFreeDirtyPage = 0;
1636 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1637 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1638 {
1639 unsigned i;
1640 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1641 {
1642 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1643 {
1644 pPool->idxFreeDirtyPage = i;
1645 break;
1646 }
1647 }
1648 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1649 }
1650
1651 Assert(pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX || pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages));
1652 return;
1653}
1654# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1655#endif /* PGMPOOL_WITH_MONITORING */
1656
1657#ifdef PGMPOOL_WITH_CACHE
1658
1659/**
1660 * Inserts a page into the GCPhys hash table.
1661 *
1662 * @param pPool The pool.
1663 * @param pPage The page.
1664 */
1665DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1666{
1667 Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1668 Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1669 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1670 pPage->iNext = pPool->aiHash[iHash];
1671 pPool->aiHash[iHash] = pPage->idx;
1672}
1673
1674
1675/**
1676 * Removes a page from the GCPhys hash table.
1677 *
1678 * @param pPool The pool.
1679 * @param pPage The page.
1680 */
1681DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1682{
1683 Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1684 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1685 if (pPool->aiHash[iHash] == pPage->idx)
1686 pPool->aiHash[iHash] = pPage->iNext;
1687 else
1688 {
1689 uint16_t iPrev = pPool->aiHash[iHash];
1690 for (;;)
1691 {
1692 const int16_t i = pPool->aPages[iPrev].iNext;
1693 if (i == pPage->idx)
1694 {
1695 pPool->aPages[iPrev].iNext = pPage->iNext;
1696 break;
1697 }
1698 if (i == NIL_PGMPOOL_IDX)
1699 {
1700 AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1701 break;
1702 }
1703 iPrev = i;
1704 }
1705 }
1706 pPage->iNext = NIL_PGMPOOL_IDX;
1707}
1708
1709
1710/**
1711 * Frees up one cache page.
1712 *
1713 * @returns VBox status code.
1714 * @retval VINF_SUCCESS on success.
1715 * @param pPool The pool.
1716 * @param iUser The user index.
1717 */
1718static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1719{
1720#ifndef IN_RC
1721 const PVM pVM = pPool->CTX_SUFF(pVM);
1722#endif
1723 Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1724 STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1725
1726 /*
1727 * Select one page from the tail of the age list.
1728 */
1729 PPGMPOOLPAGE pPage;
1730 for (unsigned iLoop = 0; ; iLoop++)
1731 {
1732 uint16_t iToFree = pPool->iAgeTail;
1733 if (iToFree == iUser)
1734 iToFree = pPool->aPages[iToFree].iAgePrev;
1735/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1736 if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1737 {
1738 uint16_t i = pPool->aPages[iToFree].iAgePrev;
1739 for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1740 {
1741 if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1742 continue;
1743 iToFree = i;
1744 break;
1745 }
1746 }
1747*/
1748 Assert(iToFree != iUser);
1749 AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1750 pPage = &pPool->aPages[iToFree];
1751
1752 /*
1753 * Reject any attempts at flushing the currently active shadow CR3 mapping.
1754 * Call pgmPoolCacheUsed to move the page to the head of the age list.
1755 */
1756 if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1757 break;
1758 LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1759 pgmPoolCacheUsed(pPool, pPage);
1760 AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1761 }
1762
1763 /*
1764 * Found a usable page, flush it and return.
1765 */
1766 return pgmPoolFlushPage(pPool, pPage);
1767}
1768
1769
1770/**
1771 * Checks if a kind mismatch is really a page being reused
1772 * or if it's just normal remappings.
1773 *
1774 * @returns true if reused and the cached page (enmKind1) should be flushed
1775 * @returns false if not reused.
1776 * @param enmKind1 The kind of the cached page.
1777 * @param enmKind2 The kind of the requested page.
1778 */
1779static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1780{
1781 switch (enmKind1)
1782 {
1783 /*
1784 * Never reuse them. There is no remapping in non-paging mode.
1785 */
1786 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1787 case PGMPOOLKIND_32BIT_PD_PHYS:
1788 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1789 case PGMPOOLKIND_PAE_PD_PHYS:
1790 case PGMPOOLKIND_PAE_PDPT_PHYS:
1791 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1792 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1793 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1794 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1795 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1796 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1797 return false;
1798
1799 /*
1800 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1801 */
1802 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1803 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1804 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1805 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1806 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1807 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1808 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1809 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1810 case PGMPOOLKIND_32BIT_PD:
1811 case PGMPOOLKIND_PAE_PDPT:
1812 switch (enmKind2)
1813 {
1814 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1815 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1816 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1817 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1818 case PGMPOOLKIND_64BIT_PML4:
1819 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1820 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1821 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1822 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1823 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1824 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1825 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1826 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1827 return true;
1828 default:
1829 return false;
1830 }
1831
1832 /*
1833 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1834 */
1835 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1836 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1837 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1838 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1839 case PGMPOOLKIND_64BIT_PML4:
1840 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1841 switch (enmKind2)
1842 {
1843 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1844 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1845 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1846 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1847 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1848 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1849 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1850 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1851 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1852 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1853 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1854 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1855 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1856 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1857 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1858 return true;
1859 default:
1860 return false;
1861 }
1862
1863 /*
1864 * These cannot be flushed, and it's common to reuse the PDs as PTs.
1865 */
1866 case PGMPOOLKIND_ROOT_NESTED:
1867 return false;
1868
1869 default:
1870 AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1871 }
1872}
1873
1874
1875/**
1876 * Attempts to satisfy a pgmPoolAlloc request from the cache.
1877 *
1878 * @returns VBox status code.
1879 * @retval VINF_PGM_CACHED_PAGE on success.
1880 * @retval VERR_FILE_NOT_FOUND if not found.
1881 * @param pPool The pool.
1882 * @param GCPhys The GC physical address of the page we're gonna shadow.
1883 * @param enmKind The kind of mapping.
1884 * @param enmAccess Access type for the mapping (only relevant for big pages)
1885 * @param iUser The shadow page pool index of the user table.
1886 * @param iUserTable The index into the user table (shadowed).
1887 * @param ppPage Where to store the pointer to the page.
1888 */
1889static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1890{
1891#ifndef IN_RC
1892 const PVM pVM = pPool->CTX_SUFF(pVM);
1893#endif
1894 /*
1895 * Look up the GCPhys in the hash.
1896 */
1897 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1898 Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1899 if (i != NIL_PGMPOOL_IDX)
1900 {
1901 do
1902 {
1903 PPGMPOOLPAGE pPage = &pPool->aPages[i];
1904 Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1905 if (pPage->GCPhys == GCPhys)
1906 {
1907 if ( (PGMPOOLKIND)pPage->enmKind == enmKind
1908 && (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
1909 {
1910 /* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1911 * doesn't flush it in case there are no more free use records.
1912 */
1913 pgmPoolCacheUsed(pPool, pPage);
1914
1915 int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1916 if (RT_SUCCESS(rc))
1917 {
1918 Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1919 *ppPage = pPage;
1920 if (pPage->cModifications)
1921 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
1922 STAM_COUNTER_INC(&pPool->StatCacheHits);
1923 return VINF_PGM_CACHED_PAGE;
1924 }
1925 return rc;
1926 }
1927
1928 if ((PGMPOOLKIND)pPage->enmKind != enmKind)
1929 {
1930 /*
1931 * The kind is different. In some cases we should now flush the page
1932 * as it has been reused, but in most cases this is normal remapping
1933 * of PDs as PT or big pages using the GCPhys field in a slightly
1934 * different way than the other kinds.
1935 */
1936 if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1937 {
1938 STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1939 pgmPoolFlushPage(pPool, pPage);
1940 break;
1941 }
1942 }
1943 }
1944
1945 /* next */
1946 i = pPage->iNext;
1947 } while (i != NIL_PGMPOOL_IDX);
1948 }
1949
1950 Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1951 STAM_COUNTER_INC(&pPool->StatCacheMisses);
1952 return VERR_FILE_NOT_FOUND;
1953}
1954
1955
1956/**
1957 * Inserts a page into the cache.
1958 *
1959 * @param pPool The pool.
1960 * @param pPage The cached page.
1961 * @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1962 */
1963static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1964{
1965 /*
1966 * Insert into the GCPhys hash if the page is fit for that.
1967 */
1968 Assert(!pPage->fCached);
1969 if (fCanBeCached)
1970 {
1971 pPage->fCached = true;
1972 pgmPoolHashInsert(pPool, pPage);
1973 Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1974 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1975 STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1976 }
1977 else
1978 {
1979 Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1980 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1981 STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1982 }
1983
1984 /*
1985 * Insert at the head of the age list.
1986 */
1987 pPage->iAgePrev = NIL_PGMPOOL_IDX;
1988 pPage->iAgeNext = pPool->iAgeHead;
1989 if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1990 pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1991 else
1992 pPool->iAgeTail = pPage->idx;
1993 pPool->iAgeHead = pPage->idx;
1994}
1995
1996
1997/**
1998 * Flushes a cached page.
1999 *
2000 * @param pPool The pool.
2001 * @param pPage The cached page.
2002 */
2003static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2004{
2005 Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2006
2007 /*
2008 * Remove the page from the hash.
2009 */
2010 if (pPage->fCached)
2011 {
2012 pPage->fCached = false;
2013 pgmPoolHashRemove(pPool, pPage);
2014 }
2015 else
2016 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2017
2018 /*
2019 * Remove it from the age list.
2020 */
2021 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2022 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2023 else
2024 pPool->iAgeTail = pPage->iAgePrev;
2025 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2026 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2027 else
2028 pPool->iAgeHead = pPage->iAgeNext;
2029 pPage->iAgeNext = NIL_PGMPOOL_IDX;
2030 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2031}
2032
2033#endif /* PGMPOOL_WITH_CACHE */
2034#ifdef PGMPOOL_WITH_MONITORING
2035
2036/**
2037 * Looks for pages sharing the monitor.
2038 *
2039 * @returns Pointer to the head page.
2040 * @returns NULL if not found.
2041 * @param pPool The Pool
2042 * @param pNewPage The page which is going to be monitored.
2043 */
2044static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2045{
2046#ifdef PGMPOOL_WITH_CACHE
2047 /*
2048 * Look up the GCPhys in the hash.
2049 */
2050 RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2051 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2052 if (i == NIL_PGMPOOL_IDX)
2053 return NULL;
2054 do
2055 {
2056 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2057 if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2058 && pPage != pNewPage)
2059 {
2060 switch (pPage->enmKind)
2061 {
2062 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2063 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2064 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2065 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2066 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2067 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2068 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2069 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2070 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2071 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2072 case PGMPOOLKIND_64BIT_PML4:
2073 case PGMPOOLKIND_32BIT_PD:
2074 case PGMPOOLKIND_PAE_PDPT:
2075 {
2076 /* find the head */
2077 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2078 {
2079 Assert(pPage->iMonitoredPrev != pPage->idx);
2080 pPage = &pPool->aPages[pPage->iMonitoredPrev];
2081 }
2082 return pPage;
2083 }
2084
2085 /* ignore, no monitoring. */
2086 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2087 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2088 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2089 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2090 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2091 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2092 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2093 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2094 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2095 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2096 case PGMPOOLKIND_ROOT_NESTED:
2097 case PGMPOOLKIND_PAE_PD_PHYS:
2098 case PGMPOOLKIND_PAE_PDPT_PHYS:
2099 case PGMPOOLKIND_32BIT_PD_PHYS:
2100 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2101 break;
2102 default:
2103 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2104 }
2105 }
2106
2107 /* next */
2108 i = pPage->iNext;
2109 } while (i != NIL_PGMPOOL_IDX);
2110#endif
2111 return NULL;
2112}
2113
2114
2115/**
2116 * Enabled write monitoring of a guest page.
2117 *
2118 * @returns VBox status code.
2119 * @retval VINF_SUCCESS on success.
2120 * @param pPool The pool.
2121 * @param pPage The cached page.
2122 */
2123static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2124{
2125 LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
2126
2127 /*
2128 * Filter out the relevant kinds.
2129 */
2130 switch (pPage->enmKind)
2131 {
2132 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2133 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2134 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2135 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2136 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2137 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2138 case PGMPOOLKIND_64BIT_PML4:
2139 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2140 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2141 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2142 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2143 case PGMPOOLKIND_32BIT_PD:
2144 case PGMPOOLKIND_PAE_PDPT:
2145 break;
2146
2147 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2148 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2149 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2150 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2151 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2152 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2153 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2154 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2155 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2156 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2157 case PGMPOOLKIND_ROOT_NESTED:
2158 /* Nothing to monitor here. */
2159 return VINF_SUCCESS;
2160
2161 case PGMPOOLKIND_32BIT_PD_PHYS:
2162 case PGMPOOLKIND_PAE_PDPT_PHYS:
2163 case PGMPOOLKIND_PAE_PD_PHYS:
2164 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2165 /* Nothing to monitor here. */
2166 return VINF_SUCCESS;
2167#ifdef PGMPOOL_WITH_MIXED_PT_CR3
2168 break;
2169#else
2170 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2171#endif
2172 default:
2173 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2174 }
2175
2176 /*
2177 * Install handler.
2178 */
2179 int rc;
2180 PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2181 if (pPageHead)
2182 {
2183 Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2184 Assert(pPageHead->iMonitoredPrev != pPage->idx);
2185
2186#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2187 if (pPageHead->fDirty)
2188 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirty, true /* force removal */);
2189#endif
2190
2191 pPage->iMonitoredPrev = pPageHead->idx;
2192 pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2193 if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2194 pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2195 pPageHead->iMonitoredNext = pPage->idx;
2196 rc = VINF_SUCCESS;
2197 }
2198 else
2199 {
2200 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2201 PVM pVM = pPool->CTX_SUFF(pVM);
2202 const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2203 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2204 GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
2205 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2206 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2207 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2208 pPool->pszAccessHandler);
2209 /** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2210 * the heap size should suffice. */
2211 AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2212 Assert(!(VMMGetCpu(pVM)->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
2213 }
2214 pPage->fMonitored = true;
2215 return rc;
2216}
2217
2218
2219/**
2220 * Disables write monitoring of a guest page.
2221 *
2222 * @returns VBox status code.
2223 * @retval VINF_SUCCESS on success.
2224 * @param pPool The pool.
2225 * @param pPage The cached page.
2226 */
2227static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2228{
2229 /*
2230 * Filter out the relevant kinds.
2231 */
2232 switch (pPage->enmKind)
2233 {
2234 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2235 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2236 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2237 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2238 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2239 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2240 case PGMPOOLKIND_64BIT_PML4:
2241 case PGMPOOLKIND_32BIT_PD:
2242 case PGMPOOLKIND_PAE_PDPT:
2243 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2244 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2245 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2246 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2247 break;
2248
2249 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2250 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2251 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2252 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2253 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2254 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2255 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2256 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2257 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2258 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2259 case PGMPOOLKIND_ROOT_NESTED:
2260 case PGMPOOLKIND_PAE_PD_PHYS:
2261 case PGMPOOLKIND_PAE_PDPT_PHYS:
2262 case PGMPOOLKIND_32BIT_PD_PHYS:
2263 /* Nothing to monitor here. */
2264 return VINF_SUCCESS;
2265
2266#ifdef PGMPOOL_WITH_MIXED_PT_CR3
2267 break;
2268#endif
2269 default:
2270 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2271 }
2272
2273 /*
2274 * Remove the page from the monitored list or uninstall it if last.
2275 */
2276 const PVM pVM = pPool->CTX_SUFF(pVM);
2277 int rc;
2278 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2279 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2280 {
2281 if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2282 {
2283 PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2284 pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2285 rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
2286 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2287 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2288 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2289 pPool->pszAccessHandler);
2290 AssertFatalRCSuccess(rc);
2291 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2292 }
2293 else
2294 {
2295 pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2296 if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2297 {
2298 pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2299 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2300 }
2301 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2302 rc = VINF_SUCCESS;
2303 }
2304 }
2305 else
2306 {
2307 rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
2308 AssertFatalRC(rc);
2309#ifdef VBOX_STRICT
2310 PVMCPU pVCpu = VMMGetCpu(pVM);
2311#endif
2312 AssertMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2313 ("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2314 }
2315 pPage->fMonitored = false;
2316
2317 /*
2318 * Remove it from the list of modified pages (if in it).
2319 */
2320 pgmPoolMonitorModifiedRemove(pPool, pPage);
2321
2322 return rc;
2323}
2324
2325
2326/**
2327 * Inserts the page into the list of modified pages.
2328 *
2329 * @param pPool The pool.
2330 * @param pPage The page.
2331 */
2332void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2333{
2334 Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2335 AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2336 && pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2337 && pPool->iModifiedHead != pPage->idx,
2338 ("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2339 pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2340 pPool->iModifiedHead, pPool->cModifiedPages));
2341
2342 pPage->iModifiedNext = pPool->iModifiedHead;
2343 if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2344 pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2345 pPool->iModifiedHead = pPage->idx;
2346 pPool->cModifiedPages++;
2347#ifdef VBOX_WITH_STATISTICS
2348 if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2349 pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2350#endif
2351}
2352
2353
2354/**
2355 * Removes the page from the list of modified pages and resets the
2356 * moficiation counter.
2357 *
2358 * @param pPool The pool.
2359 * @param pPage The page which is believed to be in the list of modified pages.
2360 */
2361static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2362{
2363 Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2364 if (pPool->iModifiedHead == pPage->idx)
2365 {
2366 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2367 pPool->iModifiedHead = pPage->iModifiedNext;
2368 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2369 {
2370 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2371 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2372 }
2373 pPool->cModifiedPages--;
2374 }
2375 else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2376 {
2377 pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2378 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2379 {
2380 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2381 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2382 }
2383 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2384 pPool->cModifiedPages--;
2385 }
2386 else
2387 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2388 pPage->cModifications = 0;
2389}
2390
2391
2392/**
2393 * Zaps the list of modified pages, resetting their modification counters in the process.
2394 *
2395 * @param pVM The VM handle.
2396 */
2397static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2398{
2399 pgmLock(pVM);
2400 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2401 LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2402
2403 unsigned cPages = 0; NOREF(cPages);
2404
2405#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2406 pgmPoolResetDirtyPages(pVM, true /* force removal. */);
2407#endif
2408
2409 uint16_t idx = pPool->iModifiedHead;
2410 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2411 while (idx != NIL_PGMPOOL_IDX)
2412 {
2413 PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2414 idx = pPage->iModifiedNext;
2415 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2416 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2417 pPage->cModifications = 0;
2418 Assert(++cPages);
2419 }
2420 AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2421 pPool->cModifiedPages = 0;
2422 pgmUnlock(pVM);
2423}
2424
2425
2426#ifdef IN_RING3
2427/**
2428 * Callback to clear all shadow pages and clear all modification counters.
2429 *
2430 * @returns VBox status code.
2431 * @param pVM The VM handle.
2432 * @param pVCpu The VMCPU for the EMT we're being called on. Unused.
2433 * @param pvUser Unused parameter.
2434 *
2435 * @remark Should only be used when monitoring is available, thus placed in
2436 * the PGMPOOL_WITH_MONITORING \#ifdef.
2437 */
2438DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, PVMCPU pVCpu, void *pvUser)
2439{
2440 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2441 STAM_PROFILE_START(&pPool->StatClearAll, c);
2442 LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
2443 NOREF(pvUser); NOREF(pVCpu);
2444
2445 pgmLock(pVM);
2446
2447#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2448 pgmPoolResetDirtyPages(pVM, true /* force removal. */);
2449#endif
2450
2451 /*
2452 * Iterate all the pages until we've encountered all that in use.
2453 * This is simple but not quite optimal solution.
2454 */
2455 unsigned cModifiedPages = 0; NOREF(cModifiedPages);
2456 unsigned cLeft = pPool->cUsedPages;
2457 unsigned iPage = pPool->cCurPages;
2458 while (--iPage >= PGMPOOL_IDX_FIRST)
2459 {
2460 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2461 if (pPage->GCPhys != NIL_RTGCPHYS)
2462 {
2463 switch (pPage->enmKind)
2464 {
2465 /*
2466 * We only care about shadow page tables.
2467 */
2468 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2469 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2470 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2471 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2472 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2473 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2474 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2475 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2476 {
2477#ifdef PGMPOOL_WITH_USER_TRACKING
2478 if (pPage->cPresent)
2479#endif
2480 {
2481 void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
2482 STAM_PROFILE_START(&pPool->StatZeroPage, z);
2483 ASMMemZeroPage(pvShw);
2484 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
2485#ifdef PGMPOOL_WITH_USER_TRACKING
2486 pPage->cPresent = 0;
2487 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
2488#endif
2489 }
2490#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2491 else
2492 Assert(!pPage->fDirty);
2493#endif
2494 }
2495 /* fall thru */
2496
2497 default:
2498#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2499 Assert(!pPage->fDirty);
2500#endif
2501 Assert(!pPage->cModifications || ++cModifiedPages);
2502 Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX || pPage->cModifications);
2503 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX || pPage->cModifications);
2504 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2505 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2506 pPage->cModifications = 0;
2507 break;
2508
2509 }
2510 if (!--cLeft)
2511 break;
2512 }
2513 }
2514
2515 /* swipe the special pages too. */
2516 for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2517 {
2518 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2519 if (pPage->GCPhys != NIL_RTGCPHYS)
2520 {
2521 Assert(!pPage->cModifications || ++cModifiedPages);
2522 Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX || pPage->cModifications);
2523 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX || pPage->cModifications);
2524 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2525 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2526 pPage->cModifications = 0;
2527 }
2528 }
2529
2530#ifndef DEBUG_michael
2531 AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2532#endif
2533 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2534 pPool->cModifiedPages = 0;
2535
2536#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2537 /*
2538 * Clear all the GCPhys links and rebuild the phys ext free list.
2539 */
2540 for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2541 pRam;
2542 pRam = pRam->CTX_SUFF(pNext))
2543 {
2544 unsigned iPage = pRam->cb >> PAGE_SHIFT;
2545 while (iPage-- > 0)
2546 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2547 }
2548
2549 pPool->iPhysExtFreeHead = 0;
2550 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2551 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2552 for (unsigned i = 0; i < cMaxPhysExts; i++)
2553 {
2554 paPhysExts[i].iNext = i + 1;
2555 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2556 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2557 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2558 }
2559 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2560#endif
2561
2562#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2563 /* Clear all dirty pages. */
2564 pPool->idxFreeDirtyPage = 0;
2565 pPool->cDirtyPages = 0;
2566 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
2567 pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
2568#endif
2569
2570 /* Clear the PGM_SYNC_CLEAR_PGM_POOL flag on all VCPUs to prevent redundant flushes. */
2571 for (unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)
2572 {
2573 PVMCPU pVCpu = &pVM->aCpus[idCpu];
2574
2575 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2576 }
2577
2578 pPool->cPresent = 0;
2579 pgmUnlock(pVM);
2580 PGM_INVL_ALL_VCPU_TLBS(pVM);
2581 STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2582 return VINF_SUCCESS;
2583}
2584#endif /* IN_RING3 */
2585
2586
2587/**
2588 * Handle SyncCR3 pool tasks
2589 *
2590 * @returns VBox status code.
2591 * @retval VINF_SUCCESS if successfully added.
2592 * @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2593 * @param pVCpu The VMCPU handle.
2594 * @remark Should only be used when monitoring is available, thus placed in
2595 * the PGMPOOL_WITH_MONITORING #ifdef.
2596 */
2597int pgmPoolSyncCR3(PVMCPU pVCpu)
2598{
2599 PVM pVM = pVCpu->CTX_SUFF(pVM);
2600 LogFlow(("pgmPoolSyncCR3\n"));
2601
2602 /*
2603 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2604 * Occasionally we will have to clear all the shadow page tables because we wanted
2605 * to monitor a page which was mapped by too many shadowed page tables. This operation
2606 * sometimes refered to as a 'lightweight flush'.
2607 */
2608# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2609 if (ASMBitTestAndClear(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_CLEAR_PGM_POOL_BIT))
2610 {
2611 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmPoolClearAll, NULL);
2612 AssertRC(rc);
2613 }
2614# else /* !IN_RING3 */
2615 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2616 {
2617 LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2618 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2619 return VINF_PGM_SYNC_CR3;
2620 }
2621# endif /* !IN_RING3 */
2622 else
2623 pgmPoolMonitorModifiedClearAll(pVM);
2624
2625 return VINF_SUCCESS;
2626}
2627
2628#endif /* PGMPOOL_WITH_MONITORING */
2629#ifdef PGMPOOL_WITH_USER_TRACKING
2630
2631/**
2632 * Frees up at least one user entry.
2633 *
2634 * @returns VBox status code.
2635 * @retval VINF_SUCCESS if successfully added.
2636 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2637 * @param pPool The pool.
2638 * @param iUser The user index.
2639 */
2640static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2641{
2642 STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2643#ifdef PGMPOOL_WITH_CACHE
2644 /*
2645 * Just free cached pages in a braindead fashion.
2646 */
2647 /** @todo walk the age list backwards and free the first with usage. */
2648 int rc = VINF_SUCCESS;
2649 do
2650 {
2651 int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2652 if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2653 rc = rc2;
2654 } while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2655 return rc;
2656#else
2657 /*
2658 * Lazy approach.
2659 */
2660 /* @todo This path no longer works (CR3 root pages will be flushed)!! */
2661 AssertCompileFailed();
2662 Assert(!CPUMIsGuestInLongMode(pVM));
2663 pgmPoolFlushAllInt(pPool);
2664 return VERR_PGM_POOL_FLUSHED;
2665#endif
2666}
2667
2668
2669/**
2670 * Inserts a page into the cache.
2671 *
2672 * This will create user node for the page, insert it into the GCPhys
2673 * hash, and insert it into the age list.
2674 *
2675 * @returns VBox status code.
2676 * @retval VINF_SUCCESS if successfully added.
2677 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2678 * @param pPool The pool.
2679 * @param pPage The cached page.
2680 * @param GCPhys The GC physical address of the page we're gonna shadow.
2681 * @param iUser The user index.
2682 * @param iUserTable The user table index.
2683 */
2684DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2685{
2686 int rc = VINF_SUCCESS;
2687 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2688
2689 LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2690
2691#ifdef VBOX_STRICT
2692 /*
2693 * Check that the entry doesn't already exists.
2694 */
2695 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2696 {
2697 uint16_t i = pPage->iUserHead;
2698 do
2699 {
2700 Assert(i < pPool->cMaxUsers);
2701 AssertMsg(paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2702 i = paUsers[i].iNext;
2703 } while (i != NIL_PGMPOOL_USER_INDEX);
2704 }
2705#endif
2706
2707 /*
2708 * Find free a user node.
2709 */
2710 uint16_t i = pPool->iUserFreeHead;
2711 if (i == NIL_PGMPOOL_USER_INDEX)
2712 {
2713 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2714 if (RT_FAILURE(rc))
2715 return rc;
2716 i = pPool->iUserFreeHead;
2717 }
2718
2719 /*
2720 * Unlink the user node from the free list,
2721 * initialize and insert it into the user list.
2722 */
2723 pPool->iUserFreeHead = paUsers[i].iNext;
2724 paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2725 paUsers[i].iUser = iUser;
2726 paUsers[i].iUserTable = iUserTable;
2727 pPage->iUserHead = i;
2728
2729 /*
2730 * Insert into cache and enable monitoring of the guest page if enabled.
2731 *
2732 * Until we implement caching of all levels, including the CR3 one, we'll
2733 * have to make sure we don't try monitor & cache any recursive reuse of
2734 * a monitored CR3 page. Because all windows versions are doing this we'll
2735 * have to be able to do combined access monitoring, CR3 + PT and
2736 * PD + PT (guest PAE).
2737 *
2738 * Update:
2739 * We're now cooperating with the CR3 monitor if an uncachable page is found.
2740 */
2741#if defined(PGMPOOL_WITH_MONITORING) || defined(PGMPOOL_WITH_CACHE)
2742# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2743 const bool fCanBeMonitored = true;
2744# else
2745 bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2746 || (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2747 || pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2748# endif
2749# ifdef PGMPOOL_WITH_CACHE
2750 pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2751# endif
2752 if (fCanBeMonitored)
2753 {
2754# ifdef PGMPOOL_WITH_MONITORING
2755 rc = pgmPoolMonitorInsert(pPool, pPage);
2756 AssertRC(rc);
2757 }
2758# endif
2759#endif /* PGMPOOL_WITH_MONITORING */
2760 return rc;
2761}
2762
2763
2764# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2765/**
2766 * Adds a user reference to a page.
2767 *
2768 * This will move the page to the head of the
2769 *
2770 * @returns VBox status code.
2771 * @retval VINF_SUCCESS if successfully added.
2772 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2773 * @param pPool The pool.
2774 * @param pPage The cached page.
2775 * @param iUser The user index.
2776 * @param iUserTable The user table.
2777 */
2778static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2779{
2780 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2781
2782 Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2783
2784# ifdef VBOX_STRICT
2785 /*
2786 * Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2787 */
2788 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2789 {
2790 uint16_t i = pPage->iUserHead;
2791 do
2792 {
2793 Assert(i < pPool->cMaxUsers);
2794 AssertMsg(iUser != PGMPOOL_IDX_PD || iUser != PGMPOOL_IDX_PDPT || iUser != PGMPOOL_IDX_NESTED_ROOT || iUser != PGMPOOL_IDX_AMD64_CR3 ||
2795 paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2796 i = paUsers[i].iNext;
2797 } while (i != NIL_PGMPOOL_USER_INDEX);
2798 }
2799# endif
2800
2801 /*
2802 * Allocate a user node.
2803 */
2804 uint16_t i = pPool->iUserFreeHead;
2805 if (i == NIL_PGMPOOL_USER_INDEX)
2806 {
2807 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2808 if (RT_FAILURE(rc))
2809 return rc;
2810 i = pPool->iUserFreeHead;
2811 }
2812 pPool->iUserFreeHead = paUsers[i].iNext;
2813
2814 /*
2815 * Initialize the user node and insert it.
2816 */
2817 paUsers[i].iNext = pPage->iUserHead;
2818 paUsers[i].iUser = iUser;
2819 paUsers[i].iUserTable = iUserTable;
2820 pPage->iUserHead = i;
2821
2822# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2823 if (pPage->fDirty)
2824 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirty, true /* force removal */);
2825# endif
2826
2827# ifdef PGMPOOL_WITH_CACHE
2828 /*
2829 * Tell the cache to update its replacement stats for this page.
2830 */
2831 pgmPoolCacheUsed(pPool, pPage);
2832# endif
2833 return VINF_SUCCESS;
2834}
2835# endif /* PGMPOOL_WITH_CACHE */
2836
2837
2838/**
2839 * Frees a user record associated with a page.
2840 *
2841 * This does not clear the entry in the user table, it simply replaces the
2842 * user record to the chain of free records.
2843 *
2844 * @param pPool The pool.
2845 * @param HCPhys The HC physical address of the shadow page.
2846 * @param iUser The shadow page pool index of the user table.
2847 * @param iUserTable The index into the user table (shadowed).
2848 */
2849static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2850{
2851 /*
2852 * Unlink and free the specified user entry.
2853 */
2854 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2855
2856 Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2857 /* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2858 uint16_t i = pPage->iUserHead;
2859 if ( i != NIL_PGMPOOL_USER_INDEX
2860 && paUsers[i].iUser == iUser
2861 && paUsers[i].iUserTable == iUserTable)
2862 {
2863 pPage->iUserHead = paUsers[i].iNext;
2864
2865 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2866 paUsers[i].iNext = pPool->iUserFreeHead;
2867 pPool->iUserFreeHead = i;
2868 return;
2869 }
2870
2871 /* General: Linear search. */
2872 uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2873 while (i != NIL_PGMPOOL_USER_INDEX)
2874 {
2875 if ( paUsers[i].iUser == iUser
2876 && paUsers[i].iUserTable == iUserTable)
2877 {
2878 if (iPrev != NIL_PGMPOOL_USER_INDEX)
2879 paUsers[iPrev].iNext = paUsers[i].iNext;
2880 else
2881 pPage->iUserHead = paUsers[i].iNext;
2882
2883 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2884 paUsers[i].iNext = pPool->iUserFreeHead;
2885 pPool->iUserFreeHead = i;
2886 return;
2887 }
2888 iPrev = i;
2889 i = paUsers[i].iNext;
2890 }
2891
2892 /* Fatal: didn't find it */
2893 AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2894 iUser, iUserTable, pPage->GCPhys));
2895}
2896
2897
2898/**
2899 * Gets the entry size of a shadow table.
2900 *
2901 * @param enmKind The kind of page.
2902 *
2903 * @returns The size of the entry in bytes. That is, 4 or 8.
2904 * @returns If the kind is not for a table, an assertion is raised and 0 is
2905 * returned.
2906 */
2907DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2908{
2909 switch (enmKind)
2910 {
2911 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2912 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2913 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2914 case PGMPOOLKIND_32BIT_PD:
2915 case PGMPOOLKIND_32BIT_PD_PHYS:
2916 return 4;
2917
2918 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2919 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2920 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2921 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2922 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2923 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2924 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2925 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2926 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2927 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2928 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2929 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2930 case PGMPOOLKIND_64BIT_PML4:
2931 case PGMPOOLKIND_PAE_PDPT:
2932 case PGMPOOLKIND_ROOT_NESTED:
2933 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2934 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2935 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2936 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2937 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2938 case PGMPOOLKIND_PAE_PD_PHYS:
2939 case PGMPOOLKIND_PAE_PDPT_PHYS:
2940 return 8;
2941
2942 default:
2943 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2944 }
2945}
2946
2947
2948/**
2949 * Gets the entry size of a guest table.
2950 *
2951 * @param enmKind The kind of page.
2952 *
2953 * @returns The size of the entry in bytes. That is, 0, 4 or 8.
2954 * @returns If the kind is not for a table, an assertion is raised and 0 is
2955 * returned.
2956 */
2957DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2958{
2959 switch (enmKind)
2960 {
2961 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2962 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2963 case PGMPOOLKIND_32BIT_PD:
2964 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2965 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2966 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2967 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2968 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2969 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2970 return 4;
2971
2972 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2973 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2974 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2975 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2976 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2977 case PGMPOOLKIND_64BIT_PML4:
2978 case PGMPOOLKIND_PAE_PDPT:
2979 return 8;
2980
2981 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2982 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2983 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2984 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2985 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2986 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2987 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2988 case PGMPOOLKIND_ROOT_NESTED:
2989 case PGMPOOLKIND_PAE_PD_PHYS:
2990 case PGMPOOLKIND_PAE_PDPT_PHYS:
2991 case PGMPOOLKIND_32BIT_PD_PHYS:
2992 /** @todo can we return 0? (nobody is calling this...) */
2993 AssertFailed();
2994 return 0;
2995
2996 default:
2997 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2998 }
2999}
3000
3001#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3002
3003/**
3004 * Scans one shadow page table for mappings of a physical page.
3005 *
3006 * @param pVM The VM handle.
3007 * @param pPhysPage The guest page in question.
3008 * @param iShw The shadow page table.
3009 * @param cRefs The number of references made in that PT.
3010 */
3011static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
3012{
3013 LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
3014 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3015
3016 /*
3017 * Assert sanity.
3018 */
3019 Assert(cRefs == 1);
3020 AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
3021 PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
3022
3023 /*
3024 * Then, clear the actual mappings to the page in the shadow PT.
3025 */
3026 switch (pPage->enmKind)
3027 {
3028 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3029 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3030 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3031 {
3032 const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3033 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3034 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3035 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3036 {
3037 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
3038 pPT->a[i].u = 0;
3039 cRefs--;
3040 if (!cRefs)
3041 return;
3042 }
3043#ifdef LOG_ENABLED
3044 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3045 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3046 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3047 {
3048 Log(("i=%d cRefs=%d\n", i, cRefs--));
3049 }
3050#endif
3051 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3052 break;
3053 }
3054
3055 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3056 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3057 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3058 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3059 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3060 {
3061 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3062 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3063 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3064 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3065 {
3066 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3067 pPT->a[i].u = 0;
3068 cRefs--;
3069 if (!cRefs)
3070 return;
3071 }
3072#ifdef LOG_ENABLED
3073 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3074 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3075 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3076 {
3077 Log(("i=%d cRefs=%d\n", i, cRefs--));
3078 }
3079#endif
3080 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
3081 break;
3082 }
3083
3084 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3085 {
3086 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3087 PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3088 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3089 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3090 {
3091 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3092 pPT->a[i].u = 0;
3093 cRefs--;
3094 if (!cRefs)
3095 return;
3096 }
3097#ifdef LOG_ENABLED
3098 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3099 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3100 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3101 {
3102 Log(("i=%d cRefs=%d\n", i, cRefs--));
3103 }
3104#endif
3105 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3106 break;
3107 }
3108
3109 default:
3110 AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3111 }
3112}
3113
3114
3115/**
3116 * Scans one shadow page table for mappings of a physical page.
3117 *
3118 * @param pVM The VM handle.
3119 * @param pPhysPage The guest page in question.
3120 * @param iShw The shadow page table.
3121 * @param cRefs The number of references made in that PT.
3122 */
3123void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
3124{
3125 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3126 LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
3127 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3128 pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
3129 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3130 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3131}
3132
3133
3134/**
3135 * Flushes a list of shadow page tables mapping the same physical page.
3136 *
3137 * @param pVM The VM handle.
3138 * @param pPhysPage The guest page in question.
3139 * @param iPhysExt The physical cross reference extent list to flush.
3140 */
3141void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
3142{
3143 Assert(PGMIsLockOwner(pVM));
3144 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3145 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3146 LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
3147
3148 const uint16_t iPhysExtStart = iPhysExt;
3149 PPGMPOOLPHYSEXT pPhysExt;
3150 do
3151 {
3152 Assert(iPhysExt < pPool->cMaxPhysExts);
3153 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3154 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3155 if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3156 {
3157 pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
3158 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3159 }
3160
3161 /* next */
3162 iPhysExt = pPhysExt->iNext;
3163 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3164
3165 /* insert the list into the free list and clear the ram range entry. */
3166 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3167 pPool->iPhysExtFreeHead = iPhysExtStart;
3168 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3169
3170 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3171}
3172
3173#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3174
3175/**
3176 * Flushes all shadow page table mappings of the given guest page.
3177 *
3178 * This is typically called when the host page backing the guest one has been
3179 * replaced or when the page protection was changed due to an access handler.
3180 *
3181 * @returns VBox status code.
3182 * @retval VINF_SUCCESS if all references has been successfully cleared.
3183 * @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3184 * pool cleaning. FF and sync flags are set.
3185 *
3186 * @param pVM The VM handle.
3187 * @param pPhysPage The guest page in question.
3188 * @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3189 * flushed, it is NOT touched if this isn't necessary.
3190 * The caller MUST initialized this to @a false.
3191 */
3192int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
3193{
3194 PVMCPU pVCpu = VMMGetCpu(pVM);
3195 pgmLock(pVM);
3196 int rc = VINF_SUCCESS;
3197#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3198 const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3199 if (u16)
3200 {
3201 /*
3202 * The zero page is currently screwing up the tracking and we'll
3203 * have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3204 * is defined, zero pages won't normally be mapped. Some kind of solution
3205 * will be needed for this problem of course, but it will have to wait...
3206 */
3207 if (PGM_PAGE_IS_ZERO(pPhysPage))
3208 rc = VINF_PGM_GCPHYS_ALIASED;
3209 else
3210 {
3211# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3212 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3213 pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3214 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3215# endif
3216
3217 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3218 pgmPoolTrackFlushGCPhysPT(pVM,
3219 pPhysPage,
3220 PGMPOOL_TD_GET_IDX(u16),
3221 PGMPOOL_TD_GET_CREFS(u16));
3222 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3223 pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
3224 else
3225 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3226 *pfFlushTLBs = true;
3227
3228# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3229 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3230# endif
3231 }
3232 }
3233
3234#elif defined(PGMPOOL_WITH_CACHE)
3235 if (PGM_PAGE_IS_ZERO(pPhysPage))
3236 rc = VINF_PGM_GCPHYS_ALIASED;
3237 else
3238 {
3239# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3240 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kills the pool otherwise. */
3241 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3242# endif
3243 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3244 if (rc == VINF_SUCCESS)
3245 *pfFlushTLBs = true;
3246 }
3247
3248# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3249 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3250# endif
3251
3252#else
3253 rc = VINF_PGM_GCPHYS_ALIASED;
3254#endif
3255
3256 if (rc == VINF_PGM_GCPHYS_ALIASED)
3257 {
3258 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3259 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3260 rc = VINF_PGM_SYNC_CR3;
3261 }
3262 pgmUnlock(pVM);
3263 return rc;
3264}
3265
3266
3267/**
3268 * Scans all shadow page tables for mappings of a physical page.
3269 *
3270 * This may be slow, but it's most likely more efficient than cleaning
3271 * out the entire page pool / cache.
3272 *
3273 * @returns VBox status code.
3274 * @retval VINF_SUCCESS if all references has been successfully cleared.
3275 * @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3276 * a page pool cleaning.
3277 *
3278 * @param pVM The VM handle.
3279 * @param pPhysPage The guest page in question.
3280 */
3281int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3282{
3283 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3284 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3285 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3286 pPool->cUsedPages, pPool->cPresent, pPhysPage));
3287
3288#if 1
3289 /*
3290 * There is a limit to what makes sense.
3291 */
3292 if (pPool->cPresent > 1024)
3293 {
3294 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3295 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3296 return VINF_PGM_GCPHYS_ALIASED;
3297 }
3298#endif
3299
3300 /*
3301 * Iterate all the pages until we've encountered all that in use.
3302 * This is simple but not quite optimal solution.
3303 */
3304 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3305 const uint32_t u32 = u64;
3306 unsigned cLeft = pPool->cUsedPages;
3307 unsigned iPage = pPool->cCurPages;
3308 while (--iPage >= PGMPOOL_IDX_FIRST)
3309 {
3310 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3311 if (pPage->GCPhys != NIL_RTGCPHYS)
3312 {
3313 switch (pPage->enmKind)
3314 {
3315 /*
3316 * We only care about shadow page tables.
3317 */
3318 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3319 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3320 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3321 {
3322 unsigned cPresent = pPage->cPresent;
3323 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3324 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3325 if (pPT->a[i].n.u1Present)
3326 {
3327 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3328 {
3329 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3330 pPT->a[i].u = 0;
3331 }
3332 if (!--cPresent)
3333 break;
3334 }
3335 break;
3336 }
3337
3338 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3339 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3340 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3341 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3342 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3343 {
3344 unsigned cPresent = pPage->cPresent;
3345 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3346 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3347 if (pPT->a[i].n.u1Present)
3348 {
3349 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3350 {
3351 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3352 pPT->a[i].u = 0;
3353 }
3354 if (!--cPresent)
3355 break;
3356 }
3357 break;
3358 }
3359 }
3360 if (!--cLeft)
3361 break;
3362 }
3363 }
3364
3365 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3366 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3367 return VINF_SUCCESS;
3368}
3369
3370
3371/**
3372 * Clears the user entry in a user table.
3373 *
3374 * This is used to remove all references to a page when flushing it.
3375 */
3376static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3377{
3378 Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3379 Assert(pUser->iUser < pPool->cCurPages);
3380 uint32_t iUserTable = pUser->iUserTable;
3381
3382 /*
3383 * Map the user page.
3384 */
3385 PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3386 union
3387 {
3388 uint64_t *pau64;
3389 uint32_t *pau32;
3390 } u;
3391 u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3392
3393 LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3394
3395 /* Safety precaution in case we change the paging for other modes too in the future. */
3396 Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
3397
3398#ifdef VBOX_STRICT
3399 /*
3400 * Some sanity checks.
3401 */
3402 switch (pUserPage->enmKind)
3403 {
3404 case PGMPOOLKIND_32BIT_PD:
3405 case PGMPOOLKIND_32BIT_PD_PHYS:
3406 Assert(iUserTable < X86_PG_ENTRIES);
3407 break;
3408 case PGMPOOLKIND_PAE_PDPT:
3409 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3410 case PGMPOOLKIND_PAE_PDPT_PHYS:
3411 Assert(iUserTable < 4);
3412 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3413 break;
3414 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3415 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3416 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3417 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3418 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3419 case PGMPOOLKIND_PAE_PD_PHYS:
3420 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3421 break;
3422 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3423 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3424 Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3425 break;
3426 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3427 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3428 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3429 break;
3430 case PGMPOOLKIND_64BIT_PML4:
3431 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3432 /* GCPhys >> PAGE_SHIFT is the index here */
3433 break;
3434 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3435 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3436 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3437 break;
3438
3439 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3440 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3441 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3442 break;
3443
3444 case PGMPOOLKIND_ROOT_NESTED:
3445 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3446 break;
3447
3448 default:
3449 AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3450 break;
3451 }
3452#endif /* VBOX_STRICT */
3453
3454 /*
3455 * Clear the entry in the user page.
3456 */
3457 switch (pUserPage->enmKind)
3458 {
3459 /* 32-bit entries */
3460 case PGMPOOLKIND_32BIT_PD:
3461 case PGMPOOLKIND_32BIT_PD_PHYS:
3462 u.pau32[iUserTable] = 0;
3463 break;
3464
3465 /* 64-bit entries */
3466 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3467 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3468 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3469 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3470 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3471#if defined(IN_RC)
3472 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
3473 * non-present PDPT will continue to cause page faults.
3474 */
3475 ASMReloadCR3();
3476#endif
3477 /* no break */
3478 case PGMPOOLKIND_PAE_PD_PHYS:
3479 case PGMPOOLKIND_PAE_PDPT_PHYS:
3480 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3481 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3482 case PGMPOOLKIND_64BIT_PML4:
3483 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3484 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3485 case PGMPOOLKIND_PAE_PDPT:
3486 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3487 case PGMPOOLKIND_ROOT_NESTED:
3488 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3489 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3490 u.pau64[iUserTable] = 0;
3491 break;
3492
3493 default:
3494 AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3495 }
3496}
3497
3498
3499/**
3500 * Clears all users of a page.
3501 */
3502static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3503{
3504 /*
3505 * Free all the user records.
3506 */
3507 LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3508
3509 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3510 uint16_t i = pPage->iUserHead;
3511 while (i != NIL_PGMPOOL_USER_INDEX)
3512 {
3513 /* Clear enter in user table. */
3514 pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3515
3516 /* Free it. */
3517 const uint16_t iNext = paUsers[i].iNext;
3518 paUsers[i].iUser = NIL_PGMPOOL_IDX;
3519 paUsers[i].iNext = pPool->iUserFreeHead;
3520 pPool->iUserFreeHead = i;
3521
3522 /* Next. */
3523 i = iNext;
3524 }
3525 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3526}
3527
3528#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3529
3530/**
3531 * Allocates a new physical cross reference extent.
3532 *
3533 * @returns Pointer to the allocated extent on success. NULL if we're out of them.
3534 * @param pVM The VM handle.
3535 * @param piPhysExt Where to store the phys ext index.
3536 */
3537PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3538{
3539 Assert(PGMIsLockOwner(pVM));
3540 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3541 uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3542 if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3543 {
3544 STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3545 return NULL;
3546 }
3547 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3548 pPool->iPhysExtFreeHead = pPhysExt->iNext;
3549 pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3550 *piPhysExt = iPhysExt;
3551 return pPhysExt;
3552}
3553
3554
3555/**
3556 * Frees a physical cross reference extent.
3557 *
3558 * @param pVM The VM handle.
3559 * @param iPhysExt The extent to free.
3560 */
3561void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3562{
3563 Assert(PGMIsLockOwner(pVM));
3564 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3565 Assert(iPhysExt < pPool->cMaxPhysExts);
3566 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3567 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3568 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3569 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3570 pPool->iPhysExtFreeHead = iPhysExt;
3571}
3572
3573
3574/**
3575 * Frees a physical cross reference extent.
3576 *
3577 * @param pVM The VM handle.
3578 * @param iPhysExt The extent to free.
3579 */
3580void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3581{
3582 Assert(PGMIsLockOwner(pVM));
3583 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3584
3585 const uint16_t iPhysExtStart = iPhysExt;
3586 PPGMPOOLPHYSEXT pPhysExt;
3587 do
3588 {
3589 Assert(iPhysExt < pPool->cMaxPhysExts);
3590 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3591 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3592 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3593
3594 /* next */
3595 iPhysExt = pPhysExt->iNext;
3596 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3597
3598 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3599 pPool->iPhysExtFreeHead = iPhysExtStart;
3600}
3601
3602
3603/**
3604 * Insert a reference into a list of physical cross reference extents.
3605 *
3606 * @returns The new tracking data for PGMPAGE.
3607 *
3608 * @param pVM The VM handle.
3609 * @param iPhysExt The physical extent index of the list head.
3610 * @param iShwPT The shadow page table index.
3611 *
3612 */
3613static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3614{
3615 Assert(PGMIsLockOwner(pVM));
3616 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3617 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3618
3619 /* special common case. */
3620 if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3621 {
3622 paPhysExts[iPhysExt].aidx[2] = iShwPT;
3623 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3624 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d}\n", iPhysExt, iShwPT));
3625 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3626 }
3627
3628 /* general treatment. */
3629 const uint16_t iPhysExtStart = iPhysExt;
3630 unsigned cMax = 15;
3631 for (;;)
3632 {
3633 Assert(iPhysExt < pPool->cMaxPhysExts);
3634 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3635 if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3636 {
3637 paPhysExts[iPhysExt].aidx[i] = iShwPT;
3638 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3639 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3640 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3641 }
3642 if (!--cMax)
3643 {
3644 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3645 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3646 LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3647 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3648 }
3649 }
3650
3651 /* add another extent to the list. */
3652 PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3653 if (!pNew)
3654 {
3655 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3656 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3657 LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3658 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3659 }
3660 pNew->iNext = iPhysExtStart;
3661 pNew->aidx[0] = iShwPT;
3662 LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3663 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3664}
3665
3666
3667/**
3668 * Add a reference to guest physical page where extents are in use.
3669 *
3670 * @returns The new tracking data for PGMPAGE.
3671 *
3672 * @param pVM The VM handle.
3673 * @param u16 The ram range flags (top 16-bits).
3674 * @param iShwPT The shadow page table index.
3675 */
3676uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3677{
3678 pgmLock(pVM);
3679 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3680 {
3681 /*
3682 * Convert to extent list.
3683 */
3684 Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3685 uint16_t iPhysExt;
3686 PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3687 if (pPhysExt)
3688 {
3689 LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3690 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3691 pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3692 pPhysExt->aidx[1] = iShwPT;
3693 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3694 }
3695 else
3696 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3697 }
3698 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3699 {
3700 /*
3701 * Insert into the extent list.
3702 */
3703 u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3704 }
3705 else
3706 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3707 pgmUnlock(pVM);
3708 return u16;
3709}
3710
3711
3712/**
3713 * Clear references to guest physical memory.
3714 *
3715 * @param pPool The pool.
3716 * @param pPage The page.
3717 * @param pPhysPage Pointer to the aPages entry in the ram range.
3718 */
3719void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3720{
3721 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3722 AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3723
3724 uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3725 if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3726 {
3727 PVM pVM = pPool->CTX_SUFF(pVM);
3728 pgmLock(pVM);
3729
3730 uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3731 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3732 do
3733 {
3734 Assert(iPhysExt < pPool->cMaxPhysExts);
3735
3736 /*
3737 * Look for the shadow page and check if it's all freed.
3738 */
3739 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3740 {
3741 if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3742 {
3743 paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3744
3745 for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3746 if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3747 {
3748 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3749 pgmUnlock(pVM);
3750 return;
3751 }
3752
3753 /* we can free the node. */
3754 const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3755 if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3756 && iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3757 {
3758 /* lonely node */
3759 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3760 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3761 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3762 }
3763 else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3764 {
3765 /* head */
3766 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3767 PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3768 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3769 }
3770 else
3771 {
3772 /* in list */
3773 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3774 paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3775 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3776 }
3777 iPhysExt = iPhysExtNext;
3778 pgmUnlock(pVM);
3779 return;
3780 }
3781 }
3782
3783 /* next */
3784 iPhysExtPrev = iPhysExt;
3785 iPhysExt = paPhysExts[iPhysExt].iNext;
3786 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3787
3788 pgmUnlock(pVM);
3789 AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3790 }
3791 else /* nothing to do */
3792 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3793}
3794
3795
3796/**
3797 * Clear references to guest physical memory.
3798 *
3799 * This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3800 * is assumed to be correct, so the linear search can be skipped and we can assert
3801 * at an earlier point.
3802 *
3803 * @param pPool The pool.
3804 * @param pPage The page.
3805 * @param HCPhys The host physical address corresponding to the guest page.
3806 * @param GCPhys The guest physical address corresponding to HCPhys.
3807 */
3808static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3809{
3810 /*
3811 * Walk range list.
3812 */
3813 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3814 while (pRam)
3815 {
3816 RTGCPHYS off = GCPhys - pRam->GCPhys;
3817 if (off < pRam->cb)
3818 {
3819 /* does it match? */
3820 const unsigned iPage = off >> PAGE_SHIFT;
3821 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3822#ifdef LOG_ENABLED
3823RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3824Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3825#endif
3826 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3827 {
3828 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3829 return;
3830 }
3831 break;
3832 }
3833 pRam = pRam->CTX_SUFF(pNext);
3834 }
3835 AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3836}
3837
3838
3839/**
3840 * Clear references to guest physical memory.
3841 *
3842 * @param pPool The pool.
3843 * @param pPage The page.
3844 * @param HCPhys The host physical address corresponding to the guest page.
3845 * @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3846 */
3847void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3848{
3849 Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3850
3851 /*
3852 * Walk range list.
3853 */
3854 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3855 while (pRam)
3856 {
3857 RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3858 if (off < pRam->cb)
3859 {
3860 /* does it match? */
3861 const unsigned iPage = off >> PAGE_SHIFT;
3862 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3863 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3864 {
3865 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3866 return;
3867 }
3868 break;
3869 }
3870 pRam = pRam->CTX_SUFF(pNext);
3871 }
3872
3873 /*
3874 * Damn, the hint didn't work. We'll have to do an expensive linear search.
3875 */
3876 STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3877 pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3878 while (pRam)
3879 {
3880 unsigned iPage = pRam->cb >> PAGE_SHIFT;
3881 while (iPage-- > 0)
3882 {
3883 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3884 {
3885 Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3886 HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3887 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3888 return;
3889 }
3890 }
3891 pRam = pRam->CTX_SUFF(pNext);
3892 }
3893
3894 AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3895}
3896
3897
3898/**
3899 * Clear references to guest physical memory in a 32-bit / 32-bit page table.
3900 *
3901 * @param pPool The pool.
3902 * @param pPage The page.
3903 * @param pShwPT The shadow page table (mapping of the page).
3904 * @param pGstPT The guest page table.
3905 */
3906DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3907{
3908 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3909 if (pShwPT->a[i].n.u1Present)
3910 {
3911 Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3912 i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3913 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3914 if (!--pPage->cPresent)
3915 break;
3916 }
3917}
3918
3919
3920/**
3921 * Clear references to guest physical memory in a PAE / 32-bit page table.
3922 *
3923 * @param pPool The pool.
3924 * @param pPage The page.
3925 * @param pShwPT The shadow page table (mapping of the page).
3926 * @param pGstPT The guest page table (just a half one).
3927 */
3928DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3929{
3930 for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3931 if (pShwPT->a[i].n.u1Present)
3932 {
3933 Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3934 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3935 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3936 }
3937}
3938
3939
3940/**
3941 * Clear references to guest physical memory in a PAE / PAE page table.
3942 *
3943 * @param pPool The pool.
3944 * @param pPage The page.
3945 * @param pShwPT The shadow page table (mapping of the page).
3946 * @param pGstPT The guest page table.
3947 */
3948DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3949{
3950 for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3951 if (pShwPT->a[i].n.u1Present)
3952 {
3953 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3954 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3955 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3956 }
3957}
3958
3959
3960/**
3961 * Clear references to guest physical memory in a 32-bit / 4MB page table.
3962 *
3963 * @param pPool The pool.
3964 * @param pPage The page.
3965 * @param pShwPT The shadow page table (mapping of the page).
3966 */
3967DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3968{
3969 RTGCPHYS GCPhys = pPage->GCPhys;
3970 for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3971 if (pShwPT->a[i].n.u1Present)
3972 {
3973 Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3974 i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3975 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3976 }
3977}
3978
3979
3980/**
3981 * Clear references to guest physical memory in a PAE / 2/4MB page table.
3982 *
3983 * @param pPool The pool.
3984 * @param pPage The page.
3985 * @param pShwPT The shadow page table (mapping of the page).
3986 */
3987DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3988{
3989 RTGCPHYS GCPhys = pPage->GCPhys;
3990 for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3991 if (pShwPT->a[i].n.u1Present)
3992 {
3993 Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3994 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3995 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3996 }
3997}
3998
3999#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4000
4001
4002/**
4003 * Clear references to shadowed pages in a 32 bits page directory.
4004 *
4005 * @param pPool The pool.
4006 * @param pPage The page.
4007 * @param pShwPD The shadow page directory (mapping of the page).
4008 */
4009DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4010{
4011 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4012 {
4013 if ( pShwPD->a[i].n.u1Present
4014 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4015 )
4016 {
4017 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4018 if (pSubPage)
4019 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4020 else
4021 AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4022 }
4023 }
4024}
4025
4026/**
4027 * Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4028 *
4029 * @param pPool The pool.
4030 * @param pPage The page.
4031 * @param pShwPD The shadow page directory (mapping of the page).
4032 */
4033DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4034{
4035 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4036 {
4037 if ( pShwPD->a[i].n.u1Present
4038 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4039 )
4040 {
4041 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4042 if (pSubPage)
4043 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4044 else
4045 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4046 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4047 }
4048 }
4049}
4050
4051/**
4052 * Clear references to shadowed pages in a PAE page directory pointer table.
4053 *
4054 * @param pPool The pool.
4055 * @param pPage The page.
4056 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4057 */
4058DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4059{
4060 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4061 {
4062 if ( pShwPDPT->a[i].n.u1Present
4063 && !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4064 )
4065 {
4066 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4067 if (pSubPage)
4068 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4069 else
4070 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4071 }
4072 }
4073}
4074
4075
4076/**
4077 * Clear references to shadowed pages in a 64-bit page directory pointer table.
4078 *
4079 * @param pPool The pool.
4080 * @param pPage The page.
4081 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4082 */
4083DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4084{
4085 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4086 {
4087 Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
4088 if (pShwPDPT->a[i].n.u1Present)
4089 {
4090 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4091 if (pSubPage)
4092 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4093 else
4094 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4095 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4096 }
4097 }
4098}
4099
4100
4101/**
4102 * Clear references to shadowed pages in a 64-bit level 4 page table.
4103 *
4104 * @param pPool The pool.
4105 * @param pPage The page.
4106 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4107 */
4108DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4109{
4110 for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4111 {
4112 if (pShwPML4->a[i].n.u1Present)
4113 {
4114 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4115 if (pSubPage)
4116 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4117 else
4118 AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4119 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4120 }
4121 }
4122}
4123
4124
4125/**
4126 * Clear references to shadowed pages in an EPT page table.
4127 *
4128 * @param pPool The pool.
4129 * @param pPage The page.
4130 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4131 */
4132DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4133{
4134 RTGCPHYS GCPhys = pPage->GCPhys;
4135 for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4136 if (pShwPT->a[i].n.u1Present)
4137 {
4138 Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4139 i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4140 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
4141 }
4142}
4143
4144
4145/**
4146 * Clear references to shadowed pages in an EPT page directory.
4147 *
4148 * @param pPool The pool.
4149 * @param pPage The page.
4150 * @param pShwPD The shadow page directory (mapping of the page).
4151 */
4152DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4153{
4154 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4155 {
4156 if (pShwPD->a[i].n.u1Present)
4157 {
4158 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4159 if (pSubPage)
4160 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4161 else
4162 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4163 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4164 }
4165 }
4166}
4167
4168
4169/**
4170 * Clear references to shadowed pages in an EPT page directory pointer table.
4171 *
4172 * @param pPool The pool.
4173 * @param pPage The page.
4174 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4175 */
4176DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4177{
4178 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4179 {
4180 if (pShwPDPT->a[i].n.u1Present)
4181 {
4182 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4183 if (pSubPage)
4184 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4185 else
4186 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4187 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4188 }
4189 }
4190}
4191
4192
4193/**
4194 * Clears all references made by this page.
4195 *
4196 * This includes other shadow pages and GC physical addresses.
4197 *
4198 * @param pPool The pool.
4199 * @param pPage The page.
4200 */
4201static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4202{
4203 /*
4204 * Map the shadow page and take action according to the page kind.
4205 */
4206 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
4207 switch (pPage->enmKind)
4208 {
4209#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4210 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4211 {
4212 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4213 void *pvGst;
4214 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4215 pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4216 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4217 break;
4218 }
4219
4220 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4221 {
4222 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4223 void *pvGst;
4224 int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4225 pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
4226 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4227 break;
4228 }
4229
4230 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4231 {
4232 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4233 void *pvGst;
4234 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4235 pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
4236 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4237 break;
4238 }
4239
4240 case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4241 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4242 {
4243 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4244 pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4245 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4246 break;
4247 }
4248
4249 case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4250 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4251 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4252 {
4253 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4254 pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
4255 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4256 break;
4257 }
4258
4259#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
4260 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4261 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4262 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4263 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4264 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4265 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4266 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4267 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4268 break;
4269#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
4270
4271 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4272 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4273 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4274 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4275 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4276 case PGMPOOLKIND_PAE_PD_PHYS:
4277 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4278 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4279 pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4280 break;
4281
4282 case PGMPOOLKIND_32BIT_PD_PHYS:
4283 case PGMPOOLKIND_32BIT_PD:
4284 pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4285 break;
4286
4287 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4288 case PGMPOOLKIND_PAE_PDPT:
4289 case PGMPOOLKIND_PAE_PDPT_PHYS:
4290 pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4291 break;
4292
4293 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4294 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4295 pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4296 break;
4297
4298 case PGMPOOLKIND_64BIT_PML4:
4299 pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4300 break;
4301
4302 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4303 pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4304 break;
4305
4306 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4307 pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4308 break;
4309
4310 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4311 pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4312 break;
4313
4314 default:
4315 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4316 }
4317
4318 /* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4319 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4320 ASMMemZeroPage(pvShw);
4321 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4322 pPage->fZeroed = true;
4323 PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
4324}
4325#endif /* PGMPOOL_WITH_USER_TRACKING */
4326
4327/**
4328 * Flushes a pool page.
4329 *
4330 * This moves the page to the free list after removing all user references to it.
4331 *
4332 * @returns VBox status code.
4333 * @retval VINF_SUCCESS on success.
4334 * @param pPool The pool.
4335 * @param HCPhys The HC physical address of the shadow page.
4336 */
4337int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4338{
4339 PVM pVM = pPool->CTX_SUFF(pVM);
4340
4341 int rc = VINF_SUCCESS;
4342 STAM_PROFILE_START(&pPool->StatFlushPage, f);
4343 LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4344 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4345
4346 /*
4347 * Quietly reject any attempts at flushing any of the special root pages.
4348 */
4349 if (pPage->idx < PGMPOOL_IDX_FIRST)
4350 {
4351 AssertFailed(); /* can no longer happen */
4352 Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4353 return VINF_SUCCESS;
4354 }
4355
4356 pgmLock(pVM);
4357
4358 /*
4359 * Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4360 */
4361 if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4362 {
4363 AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4364 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4365 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4366 || pPage->enmKind == PGMPOOLKIND_32BIT_PD
4367 || pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4368 || pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4369 || pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4370 || pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4371 || pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4372 ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4373 Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4374 pgmUnlock(pVM);
4375 return VINF_SUCCESS;
4376 }
4377
4378#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4379 /* Start a subset so we won't run out of mapping space. */
4380 PVMCPU pVCpu = VMMGetCpu(pVM);
4381 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4382#endif
4383
4384 /*
4385 * Mark the page as being in need of an ASMMemZeroPage().
4386 */
4387 pPage->fZeroed = false;
4388
4389#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4390 if (pPage->fDirty)
4391 pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirty, true /* force removal */);
4392#endif
4393
4394#ifdef PGMPOOL_WITH_USER_TRACKING
4395 /*
4396 * Clear the page.
4397 */
4398 pgmPoolTrackClearPageUsers(pPool, pPage);
4399 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4400 pgmPoolTrackDeref(pPool, pPage);
4401 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4402#endif
4403
4404#ifdef PGMPOOL_WITH_CACHE
4405 /*
4406 * Flush it from the cache.
4407 */
4408 pgmPoolCacheFlushPage(pPool, pPage);
4409#endif /* PGMPOOL_WITH_CACHE */
4410
4411#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4412 /* Heavy stuff done. */
4413 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4414#endif
4415
4416#ifdef PGMPOOL_WITH_MONITORING
4417 /*
4418 * Deregistering the monitoring.
4419 */
4420 if (pPage->fMonitored)
4421 rc = pgmPoolMonitorFlush(pPool, pPage);
4422#endif
4423
4424 /*
4425 * Free the page.
4426 */
4427 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4428 pPage->iNext = pPool->iFreeHead;
4429 pPool->iFreeHead = pPage->idx;
4430 pPage->enmKind = PGMPOOLKIND_FREE;
4431 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4432 pPage->GCPhys = NIL_RTGCPHYS;
4433 pPage->fReusedFlushPending = false;
4434
4435 pPool->cUsedPages--;
4436 pgmUnlock(pVM);
4437 STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4438 return rc;
4439}
4440
4441
4442/**
4443 * Frees a usage of a pool page.
4444 *
4445 * The caller is responsible to updating the user table so that it no longer
4446 * references the shadow page.
4447 *
4448 * @param pPool The pool.
4449 * @param HCPhys The HC physical address of the shadow page.
4450 * @param iUser The shadow page pool index of the user table.
4451 * @param iUserTable The index into the user table (shadowed).
4452 */
4453void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4454{
4455 PVM pVM = pPool->CTX_SUFF(pVM);
4456
4457 STAM_PROFILE_START(&pPool->StatFree, a);
4458 LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4459 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4460 Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4461 pgmLock(pVM);
4462#ifdef PGMPOOL_WITH_USER_TRACKING
4463 pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4464#endif
4465#ifdef PGMPOOL_WITH_CACHE
4466 if (!pPage->fCached)
4467#endif
4468 pgmPoolFlushPage(pPool, pPage);
4469 pgmUnlock(pVM);
4470 STAM_PROFILE_STOP(&pPool->StatFree, a);
4471}
4472
4473
4474/**
4475 * Makes one or more free page free.
4476 *
4477 * @returns VBox status code.
4478 * @retval VINF_SUCCESS on success.
4479 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4480 *
4481 * @param pPool The pool.
4482 * @param enmKind Page table kind
4483 * @param iUser The user of the page.
4484 */
4485static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4486{
4487 PVM pVM = pPool->CTX_SUFF(pVM);
4488
4489 LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4490
4491 /*
4492 * If the pool isn't full grown yet, expand it.
4493 */
4494 if ( pPool->cCurPages < pPool->cMaxPages
4495#if defined(IN_RC)
4496 /* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4497 && enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4498 && (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD || enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4499#endif
4500 )
4501 {
4502 STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4503#ifdef IN_RING3
4504 int rc = PGMR3PoolGrow(pVM);
4505#else
4506 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4507#endif
4508 if (RT_FAILURE(rc))
4509 return rc;
4510 STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4511 if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4512 return VINF_SUCCESS;
4513 }
4514
4515#ifdef PGMPOOL_WITH_CACHE
4516 /*
4517 * Free one cached page.
4518 */
4519 return pgmPoolCacheFreeOne(pPool, iUser);
4520#else
4521 /*
4522 * Flush the pool.
4523 *
4524 * If we have tracking enabled, it should be possible to come up with
4525 * a cheap replacement strategy...
4526 */
4527 /* @todo This path no longer works (CR3 root pages will be flushed)!! */
4528 AssertCompileFailed();
4529 Assert(!CPUMIsGuestInLongMode(pVM));
4530 pgmPoolFlushAllInt(pPool);
4531 return VERR_PGM_POOL_FLUSHED;
4532#endif
4533}
4534
4535/**
4536 * Allocates a page from the pool.
4537 *
4538 * This page may actually be a cached page and not in need of any processing
4539 * on the callers part.
4540 *
4541 * @returns VBox status code.
4542 * @retval VINF_SUCCESS if a NEW page was allocated.
4543 * @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4544 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4545 * @param pVM The VM handle.
4546 * @param GCPhys The GC physical address of the page we're gonna shadow.
4547 * For 4MB and 2MB PD entries, it's the first address the
4548 * shadow PT is covering.
4549 * @param enmKind The kind of mapping.
4550 * @param enmAccess Access type for the mapping (only relevant for big pages)
4551 * @param iUser The shadow page pool index of the user table.
4552 * @param iUserTable The index into the user table (shadowed).
4553 * @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4554 * @param fLockPage Lock the page
4555 */
4556int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage)
4557{
4558 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4559 STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4560 LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4561 *ppPage = NULL;
4562 /** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4563 * (TRPMR3SyncIDT) because of FF priority. Try fix that?
4564 * Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4565
4566 pgmLock(pVM);
4567
4568#ifdef PGMPOOL_WITH_CACHE
4569 if (pPool->fCacheEnabled)
4570 {
4571 int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4572 if (RT_SUCCESS(rc2))
4573 {
4574 if (fLockPage)
4575 pgmPoolLockPage(pPool, *ppPage);
4576 pgmUnlock(pVM);
4577 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4578 LogFlow(("pgmPoolAlloc: cached returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, *ppPage, (*ppPage)->Core.Key, (*ppPage)->idx));
4579 return rc2;
4580 }
4581 }
4582#endif
4583
4584 /*
4585 * Allocate a new one.
4586 */
4587 int rc = VINF_SUCCESS;
4588 uint16_t iNew = pPool->iFreeHead;
4589 if (iNew == NIL_PGMPOOL_IDX)
4590 {
4591 rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4592 if (RT_FAILURE(rc))
4593 {
4594 pgmUnlock(pVM);
4595 Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4596 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4597 return rc;
4598 }
4599 iNew = pPool->iFreeHead;
4600 AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4601 }
4602
4603 /* unlink the free head */
4604 PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4605 pPool->iFreeHead = pPage->iNext;
4606 pPage->iNext = NIL_PGMPOOL_IDX;
4607
4608 /*
4609 * Initialize it.
4610 */
4611 pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4612 pPage->enmKind = enmKind;
4613 pPage->enmAccess = enmAccess;
4614 pPage->GCPhys = GCPhys;
4615 pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4616 pPage->fMonitored = false;
4617 pPage->fCached = false;
4618#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4619 pPage->fDirty = false;
4620#endif
4621 pPage->fReusedFlushPending = false;
4622#ifdef PGMPOOL_WITH_MONITORING
4623 pPage->cModifications = 0;
4624 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4625 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4626#else
4627 pPage->fCR3Mix = false;
4628#endif
4629#ifdef PGMPOOL_WITH_USER_TRACKING
4630 pPage->cPresent = 0;
4631 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
4632 pPage->pvLastAccessHandlerFault = 0;
4633 pPage->cLastAccessHandlerCount = 0;
4634 pPage->pvLastAccessHandlerRip = 0;
4635
4636 /*
4637 * Insert into the tracking and cache. If this fails, free the page.
4638 */
4639 int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4640 if (RT_FAILURE(rc3))
4641 {
4642 pPool->cUsedPages--;
4643 pPage->enmKind = PGMPOOLKIND_FREE;
4644 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4645 pPage->GCPhys = NIL_RTGCPHYS;
4646 pPage->iNext = pPool->iFreeHead;
4647 pPool->iFreeHead = pPage->idx;
4648 pgmUnlock(pVM);
4649 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4650 Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4651 return rc3;
4652 }
4653#endif /* PGMPOOL_WITH_USER_TRACKING */
4654
4655 /*
4656 * Commit the allocation, clear the page and return.
4657 */
4658#ifdef VBOX_WITH_STATISTICS
4659 if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4660 pPool->cUsedPagesHigh = pPool->cUsedPages;
4661#endif
4662
4663 if (!pPage->fZeroed)
4664 {
4665 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4666 void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4667 ASMMemZeroPage(pv);
4668 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4669 }
4670
4671 *ppPage = pPage;
4672 if (fLockPage)
4673 pgmPoolLockPage(pPool, pPage);
4674 pgmUnlock(pVM);
4675 LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4676 rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4677 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4678 return rc;
4679}
4680
4681
4682/**
4683 * Frees a usage of a pool page.
4684 *
4685 * @param pVM The VM handle.
4686 * @param HCPhys The HC physical address of the shadow page.
4687 * @param iUser The shadow page pool index of the user table.
4688 * @param iUserTable The index into the user table (shadowed).
4689 */
4690void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4691{
4692 LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4693 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4694 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4695}
4696
4697/**
4698 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4699 *
4700 * @returns Pointer to the shadow page structure.
4701 * @param pPool The pool.
4702 * @param HCPhys The HC physical address of the shadow page.
4703 */
4704PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4705{
4706 PVM pVM = pPool->CTX_SUFF(pVM);
4707
4708 Assert(PGMIsLockOwner(pVM));
4709
4710 /*
4711 * Look up the page.
4712 */
4713 pgmLock(pVM);
4714 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4715 pgmUnlock(pVM);
4716
4717 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4718 return pPage;
4719}
4720
4721#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules */
4722/**
4723 * Flush the specified page if present
4724 *
4725 * @param pVM The VM handle.
4726 * @param GCPhys Guest physical address of the page to flush
4727 */
4728void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
4729{
4730#ifdef PGMPOOL_WITH_CACHE
4731 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4732
4733 VM_ASSERT_EMT(pVM);
4734
4735 /*
4736 * Look up the GCPhys in the hash.
4737 */
4738 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
4739 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
4740 if (i == NIL_PGMPOOL_IDX)
4741 return;
4742
4743 do
4744 {
4745 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4746 if (pPage->GCPhys - GCPhys < PAGE_SIZE)
4747 {
4748 switch (pPage->enmKind)
4749 {
4750 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4751 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4752 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4753 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4754 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4755 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4756 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4757 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4758 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4759 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4760 case PGMPOOLKIND_64BIT_PML4:
4761 case PGMPOOLKIND_32BIT_PD:
4762 case PGMPOOLKIND_PAE_PDPT:
4763 {
4764 Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
4765#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4766 if (pPage->fDirty)
4767 STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
4768 else
4769#endif
4770 STAM_COUNTER_INC(&pPool->StatForceFlushPage);
4771 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
4772 pgmPoolMonitorChainFlush(pPool, pPage);
4773 return;
4774 }
4775
4776 /* ignore, no monitoring. */
4777 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4778 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4779 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4780 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4781 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4782 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4783 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4784 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4785 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4786 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4787 case PGMPOOLKIND_ROOT_NESTED:
4788 case PGMPOOLKIND_PAE_PD_PHYS:
4789 case PGMPOOLKIND_PAE_PDPT_PHYS:
4790 case PGMPOOLKIND_32BIT_PD_PHYS:
4791 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4792 break;
4793
4794 default:
4795 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
4796 }
4797 }
4798
4799 /* next */
4800 i = pPage->iNext;
4801 } while (i != NIL_PGMPOOL_IDX);
4802#endif
4803 return;
4804}
4805#endif /* IN_RING3 */
4806
4807#ifdef IN_RING3
4808/**
4809 * Flushes the entire cache.
4810 *
4811 * It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4812 * and execute this CR3 flush.
4813 *
4814 * @param pPool The pool.
4815 */
4816void pgmR3PoolReset(PVM pVM)
4817{
4818 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4819
4820 Assert(PGMIsLockOwner(pVM));
4821 STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
4822 LogFlow(("pgmPoolFlushAllInt:\n"));
4823
4824 /*
4825 * If there are no pages in the pool, there is nothing to do.
4826 */
4827 if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
4828 {
4829 STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4830 return;
4831 }
4832
4833 /*
4834 * Exit the shadow mode since we're going to clear everything,
4835 * including the root page.
4836 */
4837 for (unsigned i=0;i<pVM->cCPUs;i++)
4838 {
4839 PVMCPU pVCpu = &pVM->aCpus[i];
4840 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4841 }
4842
4843 /*
4844 * Nuke the free list and reinsert all pages into it.
4845 */
4846 for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
4847 {
4848 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4849
4850 Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
4851#ifdef PGMPOOL_WITH_MONITORING
4852 if (pPage->fMonitored)
4853 pgmPoolMonitorFlush(pPool, pPage);
4854 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4855 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4856 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4857 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4858 pPage->cModifications = 0;
4859#endif
4860 pPage->GCPhys = NIL_RTGCPHYS;
4861 pPage->enmKind = PGMPOOLKIND_FREE;
4862 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4863 Assert(pPage->idx == i);
4864 pPage->iNext = i + 1;
4865 pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
4866 pPage->fSeenNonGlobal = false;
4867 pPage->fMonitored = false;
4868#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4869 pPage->fDirty = false;
4870#endif
4871 pPage->fCached = false;
4872 pPage->fReusedFlushPending = false;
4873#ifdef PGMPOOL_WITH_USER_TRACKING
4874 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
4875#else
4876 pPage->fCR3Mix = false;
4877#endif
4878#ifdef PGMPOOL_WITH_CACHE
4879 pPage->iAgeNext = NIL_PGMPOOL_IDX;
4880 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4881#endif
4882 pPage->cLocked = 0;
4883 }
4884 pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
4885 pPool->iFreeHead = PGMPOOL_IDX_FIRST;
4886 pPool->cUsedPages = 0;
4887
4888#ifdef PGMPOOL_WITH_USER_TRACKING
4889 /*
4890 * Zap and reinitialize the user records.
4891 */
4892 pPool->cPresent = 0;
4893 pPool->iUserFreeHead = 0;
4894 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
4895 const unsigned cMaxUsers = pPool->cMaxUsers;
4896 for (unsigned i = 0; i < cMaxUsers; i++)
4897 {
4898 paUsers[i].iNext = i + 1;
4899 paUsers[i].iUser = NIL_PGMPOOL_IDX;
4900 paUsers[i].iUserTable = 0xfffffffe;
4901 }
4902 paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
4903#endif
4904
4905#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4906 /*
4907 * Clear all the GCPhys links and rebuild the phys ext free list.
4908 */
4909 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
4910 pRam;
4911 pRam = pRam->CTX_SUFF(pNext))
4912 {
4913 unsigned iPage = pRam->cb >> PAGE_SHIFT;
4914 while (iPage-- > 0)
4915 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
4916 }
4917
4918 pPool->iPhysExtFreeHead = 0;
4919 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4920 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
4921 for (unsigned i = 0; i < cMaxPhysExts; i++)
4922 {
4923 paPhysExts[i].iNext = i + 1;
4924 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
4925 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
4926 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
4927 }
4928 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
4929#endif
4930
4931#ifdef PGMPOOL_WITH_MONITORING
4932 /*
4933 * Just zap the modified list.
4934 */
4935 pPool->cModifiedPages = 0;
4936 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
4937#endif
4938
4939#ifdef PGMPOOL_WITH_CACHE
4940 /*
4941 * Clear the GCPhys hash and the age list.
4942 */
4943 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
4944 pPool->aiHash[i] = NIL_PGMPOOL_IDX;
4945 pPool->iAgeHead = NIL_PGMPOOL_IDX;
4946 pPool->iAgeTail = NIL_PGMPOOL_IDX;
4947#endif
4948
4949#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4950 /* Clear all dirty pages. */
4951 pPool->idxFreeDirtyPage = 0;
4952 pPool->cDirtyPages = 0;
4953 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
4954 pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
4955#endif
4956
4957 /*
4958 * Reinsert active pages into the hash and ensure monitoring chains are correct.
4959 */
4960 for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
4961 {
4962 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4963 pPage->iNext = NIL_PGMPOOL_IDX;
4964#ifdef PGMPOOL_WITH_MONITORING
4965 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4966 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4967 pPage->cModifications = 0;
4968 /* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
4969 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4970 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4971 if (pPage->fMonitored)
4972 {
4973 int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
4974 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
4975 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
4976 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
4977 pPool->pszAccessHandler);
4978 AssertFatalRCSuccess(rc);
4979# ifdef PGMPOOL_WITH_CACHE
4980 pgmPoolHashInsert(pPool, pPage);
4981# endif
4982 }
4983#endif
4984#ifdef PGMPOOL_WITH_USER_TRACKING
4985 Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
4986#endif
4987#ifdef PGMPOOL_WITH_CACHE
4988 Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
4989 Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
4990#endif
4991 }
4992
4993 for (unsigned i=0;i<pVM->cCPUs;i++)
4994 {
4995 PVMCPU pVCpu = &pVM->aCpus[i];
4996 /*
4997 * Re-enter the shadowing mode and assert Sync CR3 FF.
4998 */
4999 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5000 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5001 }
5002
5003 STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
5004}
5005#endif /* IN_RING3 */
5006
5007#ifdef LOG_ENABLED
5008static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5009{
5010 switch(enmKind)
5011 {
5012 case PGMPOOLKIND_INVALID:
5013 return "PGMPOOLKIND_INVALID";
5014 case PGMPOOLKIND_FREE:
5015 return "PGMPOOLKIND_FREE";
5016 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5017 return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5018 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5019 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5020 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5021 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5022 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5023 return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5024 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5025 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5026 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5027 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5028 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5029 return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5030 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5031 return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5032 case PGMPOOLKIND_32BIT_PD:
5033 return "PGMPOOLKIND_32BIT_PD";
5034 case PGMPOOLKIND_32BIT_PD_PHYS:
5035 return "PGMPOOLKIND_32BIT_PD_PHYS";
5036 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5037 return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5038 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5039 return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5040 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5041 return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5042 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5043 return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5044 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5045 return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5046 case PGMPOOLKIND_PAE_PD_PHYS:
5047 return "PGMPOOLKIND_PAE_PD_PHYS";
5048 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5049 return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5050 case PGMPOOLKIND_PAE_PDPT:
5051 return "PGMPOOLKIND_PAE_PDPT";
5052 case PGMPOOLKIND_PAE_PDPT_PHYS:
5053 return "PGMPOOLKIND_PAE_PDPT_PHYS";
5054 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5055 return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5056 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5057 return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5058 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5059 return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5060 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5061 return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5062 case PGMPOOLKIND_64BIT_PML4:
5063 return "PGMPOOLKIND_64BIT_PML4";
5064 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5065 return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5066 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5067 return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5068 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5069 return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5070 case PGMPOOLKIND_ROOT_NESTED:
5071 return "PGMPOOLKIND_ROOT_NESTED";
5072 }
5073 return "Unknown kind!";
5074}
5075#endif /* LOG_ENABLED*/
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