VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 27866

Last change on this file since 27866 was 27775, checked in by vboxsync, 15 years ago

These assertions are actually fatal
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1/* $Id: PGMAllPool.cpp 27775 2010-03-29 11:05:29Z vboxsync $ */
2/** @file
3 * PGM Shadow Page Pool.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_POOL
27#include <VBox/pgm.h>
28#include <VBox/mm.h>
29#include <VBox/em.h>
30#include <VBox/cpum.h>
31#ifdef IN_RC
32# include <VBox/patm.h>
33#endif
34#include "../PGMInternal.h"
35#include <VBox/vm.h>
36#include "../PGMInline.h"
37#include <VBox/disopcode.h>
38#include <VBox/hwacc_vmx.h>
39
40#include <VBox/log.h>
41#include <VBox/err.h>
42#include <iprt/asm.h>
43#include <iprt/string.h>
44
45
46/*******************************************************************************
47* Internal Functions *
48*******************************************************************************/
49RT_C_DECLS_BEGIN
50static void pgmPoolFlushAllInt(PPGMPOOL pPool);
51DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
55static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
56#ifndef IN_RING3
57DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
58#endif
59#ifdef LOG_ENABLED
60static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
61#endif
62#if defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)
63static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT);
64#endif
65
66int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
67PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
68void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
69void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
70
71RT_C_DECLS_END
72
73
74/**
75 * Checks if the specified page pool kind is for a 4MB or 2MB guest page.
76 *
77 * @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
78 * @param enmKind The page kind.
79 */
80DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
81{
82 switch (enmKind)
83 {
84 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
85 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
86 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
87 return true;
88 default:
89 return false;
90 }
91}
92
93/** @def PGMPOOL_PAGE_2_LOCKED_PTR
94 * Maps a pool page pool into the current context and lock it (RC only).
95 *
96 * @returns VBox status code.
97 * @param pVM The VM handle.
98 * @param pPage The pool page.
99 *
100 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
101 * small page window employeed by that function. Be careful.
102 * @remark There is no need to assert on the result.
103 */
104#if defined(IN_RC)
105DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
106{
107 void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
108
109 /* Make sure the dynamic mapping will not be reused. */
110 if (pv)
111 PGMDynLockHCPage(pVM, (uint8_t *)pv);
112
113 return pv;
114}
115#else
116# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
117#endif
118
119/** @def PGMPOOL_UNLOCK_PTR
120 * Unlock a previously locked dynamic caching (RC only).
121 *
122 * @returns VBox status code.
123 * @param pVM The VM handle.
124 * @param pPage The pool page.
125 *
126 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
127 * small page window employeed by that function. Be careful.
128 * @remark There is no need to assert on the result.
129 */
130#if defined(IN_RC)
131DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
132{
133 if (pvPage)
134 PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
135}
136#else
137# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
138#endif
139
140
141/**
142 * Flushes a chain of pages sharing the same access monitor.
143 *
144 * @returns VBox status code suitable for scheduling.
145 * @param pPool The pool.
146 * @param pPage A page in the chain.
147 */
148int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
149{
150 LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
151
152 /*
153 * Find the list head.
154 */
155 uint16_t idx = pPage->idx;
156 if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
157 {
158 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
159 {
160 idx = pPage->iMonitoredPrev;
161 Assert(idx != pPage->idx);
162 pPage = &pPool->aPages[idx];
163 }
164 }
165
166 /*
167 * Iterate the list flushing each shadow page.
168 */
169 int rc = VINF_SUCCESS;
170 for (;;)
171 {
172 idx = pPage->iMonitoredNext;
173 Assert(idx != pPage->idx);
174 if (pPage->idx >= PGMPOOL_IDX_FIRST)
175 {
176 int rc2 = pgmPoolFlushPage(pPool, pPage);
177 AssertRC(rc2);
178 }
179 /* next */
180 if (idx == NIL_PGMPOOL_IDX)
181 break;
182 pPage = &pPool->aPages[idx];
183 }
184 return rc;
185}
186
187
188/**
189 * Wrapper for getting the current context pointer to the entry being modified.
190 *
191 * @returns VBox status code suitable for scheduling.
192 * @param pVM VM Handle.
193 * @param pvDst Destination address
194 * @param pvSrc Source guest virtual address.
195 * @param GCPhysSrc The source guest physical address.
196 * @param cb Size of data to read
197 */
198DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
199{
200#if defined(IN_RING3)
201 memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
202 return VINF_SUCCESS;
203#else
204 /* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
205 return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
206#endif
207}
208
209/**
210 * Process shadow entries before they are changed by the guest.
211 *
212 * For PT entries we will clear them. For PD entries, we'll simply check
213 * for mapping conflicts and set the SyncCR3 FF if found.
214 *
215 * @param pVCpu VMCPU handle
216 * @param pPool The pool.
217 * @param pPage The head page.
218 * @param GCPhysFault The guest physical fault address.
219 * @param uAddress In R0 and GC this is the guest context fault address (flat).
220 * In R3 this is the host context 'fault' address.
221 * @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
222 */
223void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite)
224{
225 AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%#x (idx=%#x)\n", pPage->iMonitoredPrev, pPage->idx));
226 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
227 PVM pVM = pPool->CTX_SUFF(pVM);
228
229 LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))pvAddress, GCPhysFault, cbWrite));
230
231 for (;;)
232 {
233 union
234 {
235 void *pv;
236 PX86PT pPT;
237 PX86PTPAE pPTPae;
238 PX86PD pPD;
239 PX86PDPAE pPDPae;
240 PX86PDPT pPDPT;
241 PX86PML4 pPML4;
242 } uShw;
243
244 LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
245
246 uShw.pv = NULL;
247 switch (pPage->enmKind)
248 {
249 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
250 {
251 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
252 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
253 const unsigned iShw = off / sizeof(X86PTE);
254 LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
255 if (uShw.pPT->a[iShw].n.u1Present)
256 {
257 X86PTE GstPte;
258
259 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
260 AssertRC(rc);
261 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
262 pgmPoolTracDerefGCPhysHint(pPool, pPage,
263 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
264 GstPte.u & X86_PTE_PG_MASK);
265 ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
266 }
267 break;
268 }
269
270 /* page/2 sized */
271 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
272 {
273 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
274 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275 if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
276 {
277 const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
278 LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
279 if (uShw.pPTPae->a[iShw].n.u1Present)
280 {
281 X86PTE GstPte;
282 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283 AssertRC(rc);
284
285 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
286 pgmPoolTracDerefGCPhysHint(pPool, pPage,
287 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
288 GstPte.u & X86_PTE_PG_MASK);
289 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
290 }
291 }
292 break;
293 }
294
295 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
296 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
297 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
298 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
299 {
300 unsigned iGst = off / sizeof(X86PDE);
301 unsigned iShwPdpt = iGst / 256;
302 unsigned iShw = (iGst % 256) * 2;
303 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
304
305 LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
306 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
307 if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
308 {
309 for (unsigned i = 0; i < 2; i++)
310 {
311# ifndef IN_RING0
312 if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
313 {
314 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
315 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
316 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
317 break;
318 }
319 else
320# endif /* !IN_RING0 */
321 if (uShw.pPDPae->a[iShw+i].n.u1Present)
322 {
323 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
324 pgmPoolFree(pVM,
325 uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
326 pPage->idx,
327 iShw + i);
328 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
329 }
330
331 /* paranoia / a bit assumptive. */
332 if ( (off & 3)
333 && (off & 3) + cbWrite > 4)
334 {
335 const unsigned iShw2 = iShw + 2 + i;
336 if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
337 {
338# ifndef IN_RING0
339 if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
340 {
341 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
342 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
343 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
344 break;
345 }
346 else
347# endif /* !IN_RING0 */
348 if (uShw.pPDPae->a[iShw2].n.u1Present)
349 {
350 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
351 pgmPoolFree(pVM,
352 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
353 pPage->idx,
354 iShw2);
355 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
356 }
357 }
358 }
359 }
360 }
361 break;
362 }
363
364 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
365 {
366 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
367 const unsigned iShw = off / sizeof(X86PTEPAE);
368 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
369 if (uShw.pPTPae->a[iShw].n.u1Present)
370 {
371 X86PTEPAE GstPte;
372 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
373 AssertRC(rc);
374
375 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
376 pgmPoolTracDerefGCPhysHint(pPool, pPage,
377 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
378 GstPte.u & X86_PTE_PAE_PG_MASK);
379 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
380 }
381
382 /* paranoia / a bit assumptive. */
383 if ( (off & 7)
384 && (off & 7) + cbWrite > sizeof(X86PTEPAE))
385 {
386 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
387 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
388
389 if (uShw.pPTPae->a[iShw2].n.u1Present)
390 {
391 X86PTEPAE GstPte;
392# ifdef IN_RING3
393 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
394# else
395 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
396# endif
397 AssertRC(rc);
398 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
399 pgmPoolTracDerefGCPhysHint(pPool, pPage,
400 uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
401 GstPte.u & X86_PTE_PAE_PG_MASK);
402 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
403 }
404 }
405 break;
406 }
407
408 case PGMPOOLKIND_32BIT_PD:
409 {
410 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
411 const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
412
413 LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
414 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
415# ifndef IN_RING0
416 if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
417 {
418 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
419 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
420 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
421 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
422 break;
423 }
424# endif /* !IN_RING0 */
425# ifndef IN_RING0
426 else
427# endif /* !IN_RING0 */
428 {
429 if (uShw.pPD->a[iShw].n.u1Present)
430 {
431 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
432 pgmPoolFree(pVM,
433 uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
434 pPage->idx,
435 iShw);
436 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
437 }
438 }
439 /* paranoia / a bit assumptive. */
440 if ( (off & 3)
441 && (off & 3) + cbWrite > sizeof(X86PTE))
442 {
443 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
444 if ( iShw2 != iShw
445 && iShw2 < RT_ELEMENTS(uShw.pPD->a))
446 {
447# ifndef IN_RING0
448 if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
449 {
450 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
451 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
452 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
453 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
454 break;
455 }
456# endif /* !IN_RING0 */
457# ifndef IN_RING0
458 else
459# endif /* !IN_RING0 */
460 {
461 if (uShw.pPD->a[iShw2].n.u1Present)
462 {
463 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
464 pgmPoolFree(pVM,
465 uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
466 pPage->idx,
467 iShw2);
468 ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
469 }
470 }
471 }
472 }
473#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
474 if ( uShw.pPD->a[iShw].n.u1Present
475 && !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
476 {
477 LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
478# ifdef IN_RC /* TLB load - we're pushing things a bit... */
479 ASMProbeReadByte(pvAddress);
480# endif
481 pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
482 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
483 }
484#endif
485 break;
486 }
487
488 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
489 {
490 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
491 const unsigned iShw = off / sizeof(X86PDEPAE);
492 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
493#ifndef IN_RING0
494 if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
495 {
496 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
497 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
498 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
499 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
500 break;
501 }
502#endif /* !IN_RING0 */
503 /*
504 * Causes trouble when the guest uses a PDE to refer to the whole page table level
505 * structure. (Invalidate here; faults later on when it tries to change the page
506 * table entries -> recheck; probably only applies to the RC case.)
507 */
508# ifndef IN_RING0
509 else
510# endif /* !IN_RING0 */
511 {
512 if (uShw.pPDPae->a[iShw].n.u1Present)
513 {
514 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
515 pgmPoolFree(pVM,
516 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
517 pPage->idx,
518 iShw);
519 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
520 }
521 }
522 /* paranoia / a bit assumptive. */
523 if ( (off & 7)
524 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
525 {
526 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
527 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
528
529#ifndef IN_RING0
530 if ( iShw2 != iShw
531 && uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
532 {
533 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
534 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
535 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
536 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
537 break;
538 }
539#endif /* !IN_RING0 */
540# ifndef IN_RING0
541 else
542# endif /* !IN_RING0 */
543 if (uShw.pPDPae->a[iShw2].n.u1Present)
544 {
545 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
546 pgmPoolFree(pVM,
547 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
548 pPage->idx,
549 iShw2);
550 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
551 }
552 }
553 break;
554 }
555
556 case PGMPOOLKIND_PAE_PDPT:
557 {
558 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
559 /*
560 * Hopefully this doesn't happen very often:
561 * - touching unused parts of the page
562 * - messing with the bits of pd pointers without changing the physical address
563 */
564 /* PDPT roots are not page aligned; 32 byte only! */
565 const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
566
567 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
568 const unsigned iShw = offPdpt / sizeof(X86PDPE);
569 if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
570 {
571# ifndef IN_RING0
572 if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
573 {
574 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
575 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
576 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
577 LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
578 break;
579 }
580# endif /* !IN_RING0 */
581# ifndef IN_RING0
582 else
583# endif /* !IN_RING0 */
584 if (uShw.pPDPT->a[iShw].n.u1Present)
585 {
586 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
587 pgmPoolFree(pVM,
588 uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
589 pPage->idx,
590 iShw);
591 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
592 }
593
594 /* paranoia / a bit assumptive. */
595 if ( (offPdpt & 7)
596 && (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
597 {
598 const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
599 if ( iShw2 != iShw
600 && iShw2 < X86_PG_PAE_PDPE_ENTRIES)
601 {
602# ifndef IN_RING0
603 if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
604 {
605 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
606 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
607 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
608 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
609 break;
610 }
611# endif /* !IN_RING0 */
612# ifndef IN_RING0
613 else
614# endif /* !IN_RING0 */
615 if (uShw.pPDPT->a[iShw2].n.u1Present)
616 {
617 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
618 pgmPoolFree(pVM,
619 uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
620 pPage->idx,
621 iShw2);
622 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
623 }
624 }
625 }
626 }
627 break;
628 }
629
630#ifndef IN_RC
631 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
632 {
633 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
634 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
635 const unsigned iShw = off / sizeof(X86PDEPAE);
636 Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
637 if (uShw.pPDPae->a[iShw].n.u1Present)
638 {
639 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
640 pgmPoolFree(pVM,
641 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
642 pPage->idx,
643 iShw);
644 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
645 }
646 /* paranoia / a bit assumptive. */
647 if ( (off & 7)
648 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
649 {
650 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
651 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
652
653 Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
654 if (uShw.pPDPae->a[iShw2].n.u1Present)
655 {
656 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
657 pgmPoolFree(pVM,
658 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
659 pPage->idx,
660 iShw2);
661 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
662 }
663 }
664 break;
665 }
666
667 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
668 {
669 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
670 /*
671 * Hopefully this doesn't happen very often:
672 * - messing with the bits of pd pointers without changing the physical address
673 */
674 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
675 const unsigned iShw = off / sizeof(X86PDPE);
676 if (uShw.pPDPT->a[iShw].n.u1Present)
677 {
678 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
679 pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
680 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
681 }
682 /* paranoia / a bit assumptive. */
683 if ( (off & 7)
684 && (off & 7) + cbWrite > sizeof(X86PDPE))
685 {
686 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
687 if (uShw.pPDPT->a[iShw2].n.u1Present)
688 {
689 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
690 pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
691 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
692 }
693 }
694 break;
695 }
696
697 case PGMPOOLKIND_64BIT_PML4:
698 {
699 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
700 /*
701 * Hopefully this doesn't happen very often:
702 * - messing with the bits of pd pointers without changing the physical address
703 */
704 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705 const unsigned iShw = off / sizeof(X86PDPE);
706 if (uShw.pPML4->a[iShw].n.u1Present)
707 {
708 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
709 pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
710 ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
711 }
712 /* paranoia / a bit assumptive. */
713 if ( (off & 7)
714 && (off & 7) + cbWrite > sizeof(X86PDPE))
715 {
716 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
717 if (uShw.pPML4->a[iShw2].n.u1Present)
718 {
719 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
720 pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
721 ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
722 }
723 }
724 break;
725 }
726#endif /* IN_RING0 */
727
728 default:
729 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
730 }
731 PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
732
733 /* next */
734 if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
735 return;
736 pPage = &pPool->aPages[pPage->iMonitoredNext];
737 }
738}
739
740# ifndef IN_RING3
741/**
742 * Checks if a access could be a fork operation in progress.
743 *
744 * Meaning, that the guest is setting up the parent process for Copy-On-Write.
745 *
746 * @returns true if it's likly that we're forking, otherwise false.
747 * @param pPool The pool.
748 * @param pDis The disassembled instruction.
749 * @param offFault The access offset.
750 */
751DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
752{
753 /*
754 * i386 linux is using btr to clear X86_PTE_RW.
755 * The functions involved are (2.6.16 source inspection):
756 * clear_bit
757 * ptep_set_wrprotect
758 * copy_one_pte
759 * copy_pte_range
760 * copy_pmd_range
761 * copy_pud_range
762 * copy_page_range
763 * dup_mmap
764 * dup_mm
765 * copy_mm
766 * copy_process
767 * do_fork
768 */
769 if ( pDis->pCurInstr->opcode == OP_BTR
770 && !(offFault & 4)
771 /** @todo Validate that the bit index is X86_PTE_RW. */
772 )
773 {
774 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
775 return true;
776 }
777 return false;
778}
779
780
781/**
782 * Determine whether the page is likely to have been reused.
783 *
784 * @returns true if we consider the page as being reused for a different purpose.
785 * @returns false if we consider it to still be a paging page.
786 * @param pVM VM Handle.
787 * @param pVCpu VMCPU Handle.
788 * @param pRegFrame Trap register frame.
789 * @param pDis The disassembly info for the faulting instruction.
790 * @param pvFault The fault address.
791 *
792 * @remark The REP prefix check is left to the caller because of STOSD/W.
793 */
794DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
795{
796#ifndef IN_RC
797 /** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
798 if ( HWACCMHasPendingIrq(pVM)
799 && (pRegFrame->rsp - pvFault) < 32)
800 {
801 /* Fault caused by stack writes while trying to inject an interrupt event. */
802 Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
803 return true;
804 }
805#else
806 NOREF(pVM); NOREF(pvFault);
807#endif
808
809 LogFlow(("Reused instr %RGv %d at %RGv param1.flags=%x param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.flags, pDis->param1.base.reg_gen));
810
811 /* Non-supervisor mode write means it's used for something else. */
812 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
813 return true;
814
815 switch (pDis->pCurInstr->opcode)
816 {
817 /* call implies the actual push of the return address faulted */
818 case OP_CALL:
819 Log4(("pgmPoolMonitorIsReused: CALL\n"));
820 return true;
821 case OP_PUSH:
822 Log4(("pgmPoolMonitorIsReused: PUSH\n"));
823 return true;
824 case OP_PUSHF:
825 Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
826 return true;
827 case OP_PUSHA:
828 Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
829 return true;
830 case OP_FXSAVE:
831 Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
832 return true;
833 case OP_MOVNTI: /* solaris - block_zero_no_xmm */
834 Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
835 return true;
836 case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
837 Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
838 return true;
839 case OP_MOVSWD:
840 case OP_STOSWD:
841 if ( pDis->prefix == (PREFIX_REP|PREFIX_REX)
842 && pRegFrame->rcx >= 0x40
843 )
844 {
845 Assert(pDis->mode == CPUMODE_64BIT);
846
847 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
848 return true;
849 }
850 return false;
851 }
852 if ( ( (pDis->param1.flags & USE_REG_GEN32)
853 || (pDis->param1.flags & USE_REG_GEN64))
854 && (pDis->param1.base.reg_gen == USE_REG_ESP))
855 {
856 Log4(("pgmPoolMonitorIsReused: ESP\n"));
857 return true;
858 }
859
860 return false;
861}
862
863/**
864 * Flushes the page being accessed.
865 *
866 * @returns VBox status code suitable for scheduling.
867 * @param pVM The VM handle.
868 * @param pVCpu The VMCPU handle.
869 * @param pPool The pool.
870 * @param pPage The pool page (head).
871 * @param pDis The disassembly of the write instruction.
872 * @param pRegFrame The trap register frame.
873 * @param GCPhysFault The fault address as guest physical address.
874 * @param pvFault The fault address.
875 */
876static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
877 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
878{
879 /*
880 * First, do the flushing.
881 */
882 int rc = pgmPoolMonitorChainFlush(pPool, pPage);
883
884 /*
885 * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). Must do this in raw mode (!); XP boot will fail otherwise
886 */
887 uint32_t cbWritten;
888 int rc2 = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten, EMCODETYPE_ALL);
889 if (RT_SUCCESS(rc2))
890 pRegFrame->rip += pDis->opsize;
891 else if (rc2 == VERR_EM_INTERPRETER)
892 {
893#ifdef IN_RC
894 if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
895 {
896 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
897 pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
898 rc = VINF_SUCCESS;
899 STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
900 }
901 else
902#endif
903 {
904 rc = VINF_EM_RAW_EMULATE_INSTR;
905 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
906 }
907 }
908 else
909 rc = rc2;
910
911 LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
912 return rc;
913}
914
915/**
916 * Handles the STOSD write accesses.
917 *
918 * @returns VBox status code suitable for scheduling.
919 * @param pVM The VM handle.
920 * @param pPool The pool.
921 * @param pPage The pool page (head).
922 * @param pDis The disassembly of the write instruction.
923 * @param pRegFrame The trap register frame.
924 * @param GCPhysFault The fault address as guest physical address.
925 * @param pvFault The fault address.
926 */
927DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
928 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
929{
930 unsigned uIncrement = pDis->param1.size;
931
932 Assert(pDis->mode == CPUMODE_32BIT || pDis->mode == CPUMODE_64BIT);
933 Assert(pRegFrame->rcx <= 0x20);
934
935#ifdef VBOX_STRICT
936 if (pDis->opmode == CPUMODE_32BIT)
937 Assert(uIncrement == 4);
938 else
939 Assert(uIncrement == 8);
940#endif
941
942 Log3(("pgmPoolAccessHandlerSTOSD\n"));
943
944 /*
945 * Increment the modification counter and insert it into the list
946 * of modified pages the first time.
947 */
948 if (!pPage->cModifications++)
949 pgmPoolMonitorModifiedInsert(pPool, pPage);
950
951 /*
952 * Execute REP STOSD.
953 *
954 * This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
955 * write situation, meaning that it's safe to write here.
956 */
957 PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
958 RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
959 while (pRegFrame->rcx)
960 {
961#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
962 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
963 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
964 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
965#else
966 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
967#endif
968#ifdef IN_RC
969 *(uint32_t *)(uintptr_t)pu32 = pRegFrame->eax;
970#else
971 PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
972#endif
973 pu32 += uIncrement;
974 GCPhysFault += uIncrement;
975 pRegFrame->rdi += uIncrement;
976 pRegFrame->rcx--;
977 }
978 pRegFrame->rip += pDis->opsize;
979
980 LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
981 return VINF_SUCCESS;
982}
983
984
985/**
986 * Handles the simple write accesses.
987 *
988 * @returns VBox status code suitable for scheduling.
989 * @param pVM The VM handle.
990 * @param pVCpu The VMCPU handle.
991 * @param pPool The pool.
992 * @param pPage The pool page (head).
993 * @param pDis The disassembly of the write instruction.
994 * @param pRegFrame The trap register frame.
995 * @param GCPhysFault The fault address as guest physical address.
996 * @param pvFault The fault address.
997 * @param pfReused Reused state (out)
998 */
999DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
1000 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
1001{
1002 Log3(("pgmPoolAccessHandlerSimple\n"));
1003 /*
1004 * Increment the modification counter and insert it into the list
1005 * of modified pages the first time.
1006 */
1007 if (!pPage->cModifications++)
1008 pgmPoolMonitorModifiedInsert(pPool, pPage);
1009
1010 /*
1011 * Clear all the pages. ASSUMES that pvFault is readable.
1012 */
1013#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1014 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1015 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
1016 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1017#else
1018 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
1019#endif
1020
1021 /*
1022 * Interpret the instruction.
1023 */
1024 uint32_t cb;
1025 int rc = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb, EMCODETYPE_ALL);
1026 if (RT_SUCCESS(rc))
1027 pRegFrame->rip += pDis->opsize;
1028 else if (rc == VERR_EM_INTERPRETER)
1029 {
1030 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1031 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
1032 rc = VINF_EM_RAW_EMULATE_INSTR;
1033 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1034 }
1035
1036#if 0 /* experimental code */
1037 if (rc == VINF_SUCCESS)
1038 {
1039 switch (pPage->enmKind)
1040 {
1041 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1042 {
1043 X86PTEPAE GstPte;
1044 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1045 AssertRC(rc);
1046
1047 /* Check the new value written by the guest. If present and with a bogus physical address, then
1048 * it's fairly safe to assume the guest is reusing the PT.
1049 */
1050 if (GstPte.n.u1Present)
1051 {
1052 RTHCPHYS HCPhys = -1;
1053 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1054 if (rc != VINF_SUCCESS)
1055 {
1056 *pfReused = true;
1057 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1058 }
1059 }
1060 break;
1061 }
1062 }
1063 }
1064#endif
1065
1066 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1067 return rc;
1068}
1069
1070/**
1071 * \#PF Handler callback for PT write accesses.
1072 *
1073 * @returns VBox status code (appropriate for GC return).
1074 * @param pVM VM Handle.
1075 * @param uErrorCode CPU Error code.
1076 * @param pRegFrame Trap register frame.
1077 * NULL on DMA and other non CPU access.
1078 * @param pvFault The fault address (cr2).
1079 * @param GCPhysFault The GC physical address corresponding to pvFault.
1080 * @param pvUser User argument.
1081 */
1082DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1083{
1084 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1085 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1086 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1087 PVMCPU pVCpu = VMMGetCpu(pVM);
1088 unsigned cMaxModifications;
1089 bool fForcedFlush = false;
1090
1091 LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1092
1093 pgmLock(pVM);
1094 if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1095 {
1096 /* Pool page changed while we were waiting for the lock; ignore. */
1097 Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1098 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1099 pgmUnlock(pVM);
1100 return VINF_SUCCESS;
1101 }
1102#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1103 if (pPage->fDirty)
1104 {
1105 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH));
1106 pgmUnlock(pVM);
1107 return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1108 }
1109#endif
1110
1111#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1112 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1113 {
1114 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1115 void *pvGst;
1116 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1117 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1118 }
1119#endif
1120
1121 /*
1122 * Disassemble the faulting instruction.
1123 */
1124 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1125 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1126 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1127 {
1128 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1129 pgmUnlock(pVM);
1130 return rc;
1131 }
1132
1133 Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1134
1135 /*
1136 * We should ALWAYS have the list head as user parameter. This
1137 * is because we use that page to record the changes.
1138 */
1139 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1140
1141#ifdef IN_RING0
1142 /* Maximum nr of modifications depends on the page type. */
1143 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1144 cMaxModifications = 4;
1145 else
1146 cMaxModifications = 24;
1147#else
1148 cMaxModifications = 48;
1149#endif
1150
1151 /*
1152 * Incremental page table updates should weight more than random ones.
1153 * (Only applies when started from offset 0)
1154 */
1155 pVCpu->pgm.s.cPoolAccessHandler++;
1156 if ( pPage->pvLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1157 && pPage->pvLastAccessHandlerRip < pRegFrame->rip + 0x40
1158 && pvFault == (pPage->pvLastAccessHandlerFault + pDis->param1.size)
1159 && pVCpu->pgm.s.cPoolAccessHandler == (pPage->cLastAccessHandlerCount + 1))
1160 {
1161 Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1162 pPage->cModifications = pPage->cModifications * 2;
1163 pPage->pvLastAccessHandlerFault = pvFault;
1164 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1165 if (pPage->cModifications >= cMaxModifications)
1166 {
1167 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1168 fForcedFlush = true;
1169 }
1170 }
1171
1172 if (pPage->cModifications >= cMaxModifications)
1173 Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1174
1175 /*
1176 * Check if it's worth dealing with.
1177 */
1178 bool fReused = false;
1179 bool fNotReusedNotForking = false;
1180 if ( ( pPage->cModifications < cMaxModifications /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
1181 || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1182 )
1183 && !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1184 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1185 {
1186 /*
1187 * Simple instructions, no REP prefix.
1188 */
1189 if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE)))
1190 {
1191 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1192 if (fReused)
1193 goto flushPage;
1194
1195 /* A mov instruction to change the first page table entry will be remembered so we can detect
1196 * full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1197 */
1198 if ( rc == VINF_SUCCESS
1199 && pDis->pCurInstr->opcode == OP_MOV
1200 && (pvFault & PAGE_OFFSET_MASK) == 0)
1201 {
1202 pPage->pvLastAccessHandlerFault = pvFault;
1203 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1204 pPage->pvLastAccessHandlerRip = pRegFrame->rip;
1205 /* Make sure we don't kick out a page too quickly. */
1206 if (pPage->cModifications > 8)
1207 pPage->cModifications = 2;
1208 }
1209 else
1210 if (pPage->pvLastAccessHandlerFault == pvFault)
1211 {
1212 /* ignore the 2nd write to this page table entry. */
1213 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1214 }
1215 else
1216 {
1217 pPage->pvLastAccessHandlerFault = 0;
1218 pPage->pvLastAccessHandlerRip = 0;
1219 }
1220
1221 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1222 pgmUnlock(pVM);
1223 return rc;
1224 }
1225
1226 /*
1227 * Windows is frequently doing small memset() operations (netio test 4k+).
1228 * We have to deal with these or we'll kill the cache and performance.
1229 */
1230 if ( pDis->pCurInstr->opcode == OP_STOSWD
1231 && !pRegFrame->eflags.Bits.u1DF
1232 && pDis->opmode == pDis->mode
1233 && pDis->addrmode == pDis->mode)
1234 {
1235 bool fValidStosd = false;
1236
1237 if ( pDis->mode == CPUMODE_32BIT
1238 && pDis->prefix == PREFIX_REP
1239 && pRegFrame->ecx <= 0x20
1240 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1241 && !((uintptr_t)pvFault & 3)
1242 && (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */
1243 )
1244 {
1245 fValidStosd = true;
1246 pRegFrame->rcx &= 0xffffffff; /* paranoia */
1247 }
1248 else
1249 if ( pDis->mode == CPUMODE_64BIT
1250 && pDis->prefix == (PREFIX_REP | PREFIX_REX)
1251 && pRegFrame->rcx <= 0x20
1252 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1253 && !((uintptr_t)pvFault & 7)
1254 && (pRegFrame->rax == 0 || pRegFrame->rax == 0x80) /* the two values observed. */
1255 )
1256 {
1257 fValidStosd = true;
1258 }
1259
1260 if (fValidStosd)
1261 {
1262 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1263 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1264 pgmUnlock(pVM);
1265 return rc;
1266 }
1267 }
1268
1269 /* REP prefix, don't bother. */
1270 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1271 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1272 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1273 fNotReusedNotForking = true;
1274 }
1275
1276#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1277 /* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1278 * leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1279 */
1280 if ( pPage->cModifications >= cMaxModifications
1281 && !fForcedFlush
1282 && pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1283 && ( fNotReusedNotForking
1284 || ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1285 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1286 )
1287 )
1288 {
1289 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
1290 Assert(pPage->fDirty == false);
1291
1292 /* Flush any monitored duplicates as we will disable write protection. */
1293 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1294 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1295 {
1296 PPGMPOOLPAGE pPageHead = pPage;
1297
1298 /* Find the monitor head. */
1299 while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1300 pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1301
1302 while (pPageHead)
1303 {
1304 unsigned idxNext = pPageHead->iMonitoredNext;
1305
1306 if (pPageHead != pPage)
1307 {
1308 STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1309 Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1310 int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1311 AssertRC(rc2);
1312 }
1313
1314 if (idxNext == NIL_PGMPOOL_IDX)
1315 break;
1316
1317 pPageHead = &pPool->aPages[idxNext];
1318 }
1319 }
1320
1321 /* The flushing above might fail for locked pages, so double check. */
1322 if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1323 && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1324 {
1325 pgmPoolAddDirtyPage(pVM, pPool, pPage);
1326
1327 /* Temporarily allow write access to the page table again. */
1328 rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys, pPage->GCPhys);
1329 if (rc == VINF_SUCCESS)
1330 {
1331 rc = PGMShwModifyPage(pVCpu, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
1332 AssertMsg(rc == VINF_SUCCESS
1333 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1334 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1335 || rc == VERR_PAGE_NOT_PRESENT,
1336 ("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1337
1338 pPage->pvDirtyFault = pvFault;
1339
1340 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1341 pgmUnlock(pVM);
1342 return rc;
1343 }
1344 }
1345 }
1346#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1347
1348 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1349flushPage:
1350 /*
1351 * Not worth it, so flush it.
1352 *
1353 * If we considered it to be reused, don't go back to ring-3
1354 * to emulate failed instructions since we usually cannot
1355 * interpret then. This may be a bit risky, in which case
1356 * the reuse detection must be fixed.
1357 */
1358 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1359 if ( rc == VINF_EM_RAW_EMULATE_INSTR
1360 && fReused)
1361 {
1362 /* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1363 if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1364 rc = VINF_SUCCESS; /* safe to restart the instruction. */
1365 }
1366 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1367 pgmUnlock(pVM);
1368 return rc;
1369}
1370
1371# endif /* !IN_RING3 */
1372
1373# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1374
1375# ifdef VBOX_STRICT
1376/**
1377 * Check references to guest physical memory in a PAE / PAE page table.
1378 *
1379 * @param pPool The pool.
1380 * @param pPage The page.
1381 * @param pShwPT The shadow page table (mapping of the page).
1382 * @param pGstPT The guest page table.
1383 */
1384static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
1385{
1386 unsigned cErrors = 0;
1387 int LastRc = -1; /* initialized to shut up gcc */
1388 unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1389 RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1390
1391#ifdef VBOX_STRICT
1392 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1393 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1394#endif
1395 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1396 {
1397 if (pShwPT->a[i].n.u1Present)
1398 {
1399 RTHCPHYS HCPhys = NIL_RTHCPHYS;
1400 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1401 if ( rc != VINF_SUCCESS
1402 || (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys)
1403 {
1404 Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1405 LastPTE = i;
1406 LastRc = rc;
1407 LastHCPhys = HCPhys;
1408 cErrors++;
1409
1410 RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1411 rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pPage->GCPhys, &HCPhysPT);
1412 AssertRC(rc);
1413
1414 for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1415 {
1416 PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1417
1418 if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1419 {
1420 PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pTempPage);
1421
1422 for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1423 {
1424 if ( pShwPT2->a[j].n.u1Present
1425 && pShwPT2->a[j].n.u1Write
1426 && ((pShwPT2->a[j].u & X86_PTE_PAE_PG_MASK) == HCPhysPT))
1427 {
1428 Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, pShwPT->a[j].u, pShwPT2->a[j].u));
1429 }
1430 }
1431 }
1432 }
1433 }
1434 }
1435 }
1436 AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, pShwPT->a[LastPTE].u, LastHCPhys));
1437}
1438# endif /* VBOX_STRICT */
1439
1440/**
1441 * Clear references to guest physical memory in a PAE / PAE page table.
1442 *
1443 * @returns nr of changed PTEs
1444 * @param pPool The pool.
1445 * @param pPage The page.
1446 * @param pShwPT The shadow page table (mapping of the page).
1447 * @param pGstPT The guest page table.
1448 * @param pOldGstPT The old cached guest page table.
1449 * @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1450 * @param pfFlush Flush reused page table (out)
1451 */
1452DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT, PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1453{
1454 unsigned cChanged = 0;
1455
1456#ifdef VBOX_STRICT
1457 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1458 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1459#endif
1460 *pfFlush = false;
1461
1462 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1463 {
1464 /* Check the new value written by the guest. If present and with a bogus physical address, then
1465 * it's fairly safe to assume the guest is reusing the PT.
1466 */
1467 if ( fAllowRemoval
1468 && pGstPT->a[i].n.u1Present)
1469 {
1470 if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1471 {
1472 *pfFlush = true;
1473 return ++cChanged;
1474 }
1475 }
1476 if (pShwPT->a[i].n.u1Present)
1477 {
1478 /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1479 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1480 {
1481#ifdef VBOX_STRICT
1482 RTHCPHYS HCPhys = NIL_RTGCPHYS;
1483 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1484 AssertMsg(rc == VINF_SUCCESS && (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1485#endif
1486 uint64_t uHostAttr = pShwPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1487 bool fHostRW = !!(pShwPT->a[i].u & X86_PTE_RW);
1488 uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1489 bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1490
1491 if ( uHostAttr == uGuestAttr
1492 && fHostRW <= fGuestRW)
1493 continue;
1494 }
1495 cChanged++;
1496 /* Something was changed, so flush it. */
1497 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1498 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1499 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
1500 ASMAtomicWriteSize(&pShwPT->a[i].u, 0);
1501 }
1502 }
1503 return cChanged;
1504}
1505
1506
1507/**
1508 * Flush a dirty page
1509 *
1510 * @param pVM VM Handle.
1511 * @param pPool The pool.
1512 * @param idxSlot Dirty array slot index
1513 * @param fAllowRemoval Allow a reused page table to be removed
1514 */
1515static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1516{
1517 PPGMPOOLPAGE pPage;
1518 unsigned idxPage;
1519
1520 Assert(idxSlot < RT_ELEMENTS(pPool->aIdxDirtyPages));
1521 if (pPool->aIdxDirtyPages[idxSlot] == NIL_PGMPOOL_IDX)
1522 return;
1523
1524 idxPage = pPool->aIdxDirtyPages[idxSlot];
1525 AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1526 pPage = &pPool->aPages[idxPage];
1527 Assert(pPage->idx == idxPage);
1528 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1529
1530 AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1531 Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1532
1533 /* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1534 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys);
1535 Assert(rc == VINF_SUCCESS);
1536 pPage->fDirty = false;
1537
1538#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1539 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(VMMGetCpu(pVM));
1540#endif
1541
1542#ifdef VBOX_STRICT
1543 uint64_t fFlags = 0;
1544 RTHCPHYS HCPhys;
1545 rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys);
1546 AssertMsg( ( rc == VINF_SUCCESS
1547 && (!(fFlags & X86_PTE_RW) || HCPhys != pPage->Core.Key))
1548 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1549 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1550 || rc == VERR_PAGE_NOT_PRESENT,
1551 ("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags));
1552#endif
1553
1554 /* Flush those PTEs that have changed. */
1555 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1556 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1557 void *pvGst;
1558 bool fFlush;
1559 rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1560 unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst, (PCX86PTPAE)&pPool->aDirtyPages[idxSlot][0], fAllowRemoval, &fFlush);
1561 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1562 /** Note: we might want to consider keeping the dirty page active in case there were many changes. */
1563
1564 /* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1565 Assert(pPage->cModifications);
1566 if (cChanges < 4)
1567 pPage->cModifications = 1; /* must use > 0 here */
1568 else
1569 pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1570
1571 STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1572 if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages))
1573 pPool->idxFreeDirtyPage = idxSlot;
1574
1575 pPool->cDirtyPages--;
1576 pPool->aIdxDirtyPages[idxSlot] = NIL_PGMPOOL_IDX;
1577 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1578 if (fFlush)
1579 {
1580 Assert(fAllowRemoval);
1581 Log(("Flush reused page table!\n"));
1582 pgmPoolFlushPage(pPool, pPage);
1583 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1584 }
1585 else
1586 Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1587
1588#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1589 PGMDynMapPopAutoSubset(VMMGetCpu(pVM), iPrevSubset);
1590#endif
1591}
1592
1593# ifndef IN_RING3
1594/**
1595 * Add a new dirty page
1596 *
1597 * @param pVM VM Handle.
1598 * @param pPool The pool.
1599 * @param pPage The page.
1600 */
1601void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1602{
1603 unsigned idxFree;
1604
1605 Assert(PGMIsLocked(pVM));
1606 AssertCompile(RT_ELEMENTS(pPool->aIdxDirtyPages) == 8 || RT_ELEMENTS(pPool->aIdxDirtyPages) == 16);
1607 Assert(!pPage->fDirty);
1608
1609 idxFree = pPool->idxFreeDirtyPage;
1610 Assert(idxFree < RT_ELEMENTS(pPool->aIdxDirtyPages));
1611 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1612
1613 if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aIdxDirtyPages))
1614 {
1615 STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1616 pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1617 }
1618 Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages));
1619 AssertMsg(pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1620
1621 Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1622
1623 /* Make a copy of the guest page table as we require valid GCPhys addresses when removing
1624 * references to physical pages. (the HCPhys linear lookup is *extremely* expensive!)
1625 */
1626 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1627 void *pvGst;
1628 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1629 memcpy(&pPool->aDirtyPages[idxFree][0], pvGst, PAGE_SIZE);
1630#ifdef VBOX_STRICT
1631 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1632#endif
1633
1634 STAM_COUNTER_INC(&pPool->StatDirtyPage);
1635 pPage->fDirty = true;
1636 pPage->idxDirty = idxFree;
1637 pPool->aIdxDirtyPages[idxFree] = pPage->idx;
1638 pPool->cDirtyPages++;
1639
1640 pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1641 if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages)
1642 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1643 {
1644 unsigned i;
1645 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1646 {
1647 idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1648 if (pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX)
1649 {
1650 pPool->idxFreeDirtyPage = idxFree;
1651 break;
1652 }
1653 }
1654 Assert(i != RT_ELEMENTS(pPool->aIdxDirtyPages));
1655 }
1656
1657 Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages) || pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX);
1658 return;
1659}
1660# endif /* !IN_RING3 */
1661
1662/**
1663 * Check if the specified page is dirty (not write monitored)
1664 *
1665 * @return dirty or not
1666 * @param pVM VM Handle.
1667 * @param GCPhys Guest physical address
1668 */
1669bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1670{
1671 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1672 Assert(PGMIsLocked(pVM));
1673 if (!pPool->cDirtyPages)
1674 return false;
1675
1676 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1677
1678 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1679 {
1680 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1681 {
1682 PPGMPOOLPAGE pPage;
1683 unsigned idxPage = pPool->aIdxDirtyPages[i];
1684
1685 pPage = &pPool->aPages[idxPage];
1686 if (pPage->GCPhys == GCPhys)
1687 return true;
1688 }
1689 }
1690 return false;
1691}
1692
1693/**
1694 * Reset all dirty pages by reinstating page monitoring.
1695 *
1696 * @param pVM VM Handle.
1697 */
1698void pgmPoolResetDirtyPages(PVM pVM)
1699{
1700 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1701 Assert(PGMIsLocked(pVM));
1702 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1703
1704 if (!pPool->cDirtyPages)
1705 return;
1706
1707 Log(("pgmPoolResetDirtyPages\n"));
1708 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1709 pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1710
1711 pPool->idxFreeDirtyPage = 0;
1712 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1713 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1714 {
1715 unsigned i;
1716 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1717 {
1718 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1719 {
1720 pPool->idxFreeDirtyPage = i;
1721 break;
1722 }
1723 }
1724 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1725 }
1726
1727 Assert(pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX || pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages));
1728 return;
1729}
1730
1731/**
1732 * Reset all dirty pages by reinstating page monitoring.
1733 *
1734 * @param pVM VM Handle.
1735 * @param GCPhysPT Physical address of the page table
1736 */
1737void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT)
1738{
1739 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1740 Assert(PGMIsLocked(pVM));
1741 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1742 unsigned idxDirtyPage = RT_ELEMENTS(pPool->aIdxDirtyPages);
1743
1744 if (!pPool->cDirtyPages)
1745 return;
1746
1747 GCPhysPT = GCPhysPT & ~(RTGCPHYS)(PAGE_SIZE - 1);
1748
1749 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1750 {
1751 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1752 {
1753 unsigned idxPage = pPool->aIdxDirtyPages[i];
1754
1755 PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1756 if (pPage->GCPhys == GCPhysPT)
1757 {
1758 idxDirtyPage = i;
1759 break;
1760 }
1761 }
1762 }
1763
1764 if (idxDirtyPage != RT_ELEMENTS(pPool->aIdxDirtyPages))
1765 {
1766 pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1767 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1768 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1769 {
1770 unsigned i;
1771 for (i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1772 {
1773 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1774 {
1775 pPool->idxFreeDirtyPage = i;
1776 break;
1777 }
1778 }
1779 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1780 }
1781 }
1782}
1783
1784# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1785
1786/**
1787 * Inserts a page into the GCPhys hash table.
1788 *
1789 * @param pPool The pool.
1790 * @param pPage The page.
1791 */
1792DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1793{
1794 Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1795 Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1796 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1797 pPage->iNext = pPool->aiHash[iHash];
1798 pPool->aiHash[iHash] = pPage->idx;
1799}
1800
1801
1802/**
1803 * Removes a page from the GCPhys hash table.
1804 *
1805 * @param pPool The pool.
1806 * @param pPage The page.
1807 */
1808DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1809{
1810 Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1811 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1812 if (pPool->aiHash[iHash] == pPage->idx)
1813 pPool->aiHash[iHash] = pPage->iNext;
1814 else
1815 {
1816 uint16_t iPrev = pPool->aiHash[iHash];
1817 for (;;)
1818 {
1819 const int16_t i = pPool->aPages[iPrev].iNext;
1820 if (i == pPage->idx)
1821 {
1822 pPool->aPages[iPrev].iNext = pPage->iNext;
1823 break;
1824 }
1825 if (i == NIL_PGMPOOL_IDX)
1826 {
1827 AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1828 break;
1829 }
1830 iPrev = i;
1831 }
1832 }
1833 pPage->iNext = NIL_PGMPOOL_IDX;
1834}
1835
1836
1837/**
1838 * Frees up one cache page.
1839 *
1840 * @returns VBox status code.
1841 * @retval VINF_SUCCESS on success.
1842 * @param pPool The pool.
1843 * @param iUser The user index.
1844 */
1845static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1846{
1847#ifndef IN_RC
1848 const PVM pVM = pPool->CTX_SUFF(pVM);
1849#endif
1850 Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1851 STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1852
1853 /*
1854 * Select one page from the tail of the age list.
1855 */
1856 PPGMPOOLPAGE pPage;
1857 for (unsigned iLoop = 0; ; iLoop++)
1858 {
1859 uint16_t iToFree = pPool->iAgeTail;
1860 if (iToFree == iUser)
1861 iToFree = pPool->aPages[iToFree].iAgePrev;
1862/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1863 if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1864 {
1865 uint16_t i = pPool->aPages[iToFree].iAgePrev;
1866 for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1867 {
1868 if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1869 continue;
1870 iToFree = i;
1871 break;
1872 }
1873 }
1874*/
1875 Assert(iToFree != iUser);
1876 AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1877 pPage = &pPool->aPages[iToFree];
1878
1879 /*
1880 * Reject any attempts at flushing the currently active shadow CR3 mapping.
1881 * Call pgmPoolCacheUsed to move the page to the head of the age list.
1882 */
1883 if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1884 break;
1885 LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1886 pgmPoolCacheUsed(pPool, pPage);
1887 AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1888 }
1889
1890 /*
1891 * Found a usable page, flush it and return.
1892 */
1893 int rc = pgmPoolFlushPage(pPool, pPage);
1894 /* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
1895 /* todo: find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
1896 if (rc == VINF_SUCCESS)
1897 PGM_INVL_ALL_VCPU_TLBS(pVM);
1898 return rc;
1899}
1900
1901
1902/**
1903 * Checks if a kind mismatch is really a page being reused
1904 * or if it's just normal remappings.
1905 *
1906 * @returns true if reused and the cached page (enmKind1) should be flushed
1907 * @returns false if not reused.
1908 * @param enmKind1 The kind of the cached page.
1909 * @param enmKind2 The kind of the requested page.
1910 */
1911static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1912{
1913 switch (enmKind1)
1914 {
1915 /*
1916 * Never reuse them. There is no remapping in non-paging mode.
1917 */
1918 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1919 case PGMPOOLKIND_32BIT_PD_PHYS:
1920 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1921 case PGMPOOLKIND_PAE_PD_PHYS:
1922 case PGMPOOLKIND_PAE_PDPT_PHYS:
1923 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1924 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1925 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1926 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1927 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1928 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1929 return false;
1930
1931 /*
1932 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1933 */
1934 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1935 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1936 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1937 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1938 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1939 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1940 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1941 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1942 case PGMPOOLKIND_32BIT_PD:
1943 case PGMPOOLKIND_PAE_PDPT:
1944 switch (enmKind2)
1945 {
1946 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1947 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1948 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1949 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1950 case PGMPOOLKIND_64BIT_PML4:
1951 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1952 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1953 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1954 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1955 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1956 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1957 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1958 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1959 return true;
1960 default:
1961 return false;
1962 }
1963
1964 /*
1965 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1966 */
1967 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1968 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1969 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1970 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1971 case PGMPOOLKIND_64BIT_PML4:
1972 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1973 switch (enmKind2)
1974 {
1975 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1976 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1977 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1978 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1979 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1980 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1981 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1982 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1983 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1984 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1985 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1986 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1987 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1988 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1989 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1990 return true;
1991 default:
1992 return false;
1993 }
1994
1995 /*
1996 * These cannot be flushed, and it's common to reuse the PDs as PTs.
1997 */
1998 case PGMPOOLKIND_ROOT_NESTED:
1999 return false;
2000
2001 default:
2002 AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
2003 }
2004}
2005
2006
2007/**
2008 * Attempts to satisfy a pgmPoolAlloc request from the cache.
2009 *
2010 * @returns VBox status code.
2011 * @retval VINF_PGM_CACHED_PAGE on success.
2012 * @retval VERR_FILE_NOT_FOUND if not found.
2013 * @param pPool The pool.
2014 * @param GCPhys The GC physical address of the page we're gonna shadow.
2015 * @param enmKind The kind of mapping.
2016 * @param enmAccess Access type for the mapping (only relevant for big pages)
2017 * @param iUser The shadow page pool index of the user table.
2018 * @param iUserTable The index into the user table (shadowed).
2019 * @param ppPage Where to store the pointer to the page.
2020 */
2021static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2022{
2023#ifndef IN_RC
2024 const PVM pVM = pPool->CTX_SUFF(pVM);
2025#endif
2026 /*
2027 * Look up the GCPhys in the hash.
2028 */
2029 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2030 Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2031 if (i != NIL_PGMPOOL_IDX)
2032 {
2033 do
2034 {
2035 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2036 Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2037 if (pPage->GCPhys == GCPhys)
2038 {
2039 if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2040 && (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
2041 {
2042 /* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2043 * doesn't flush it in case there are no more free use records.
2044 */
2045 pgmPoolCacheUsed(pPool, pPage);
2046
2047 int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2048 if (RT_SUCCESS(rc))
2049 {
2050 Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2051 *ppPage = pPage;
2052 if (pPage->cModifications)
2053 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2054 STAM_COUNTER_INC(&pPool->StatCacheHits);
2055 return VINF_PGM_CACHED_PAGE;
2056 }
2057 return rc;
2058 }
2059
2060 if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2061 {
2062 /*
2063 * The kind is different. In some cases we should now flush the page
2064 * as it has been reused, but in most cases this is normal remapping
2065 * of PDs as PT or big pages using the GCPhys field in a slightly
2066 * different way than the other kinds.
2067 */
2068 if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2069 {
2070 STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2071 pgmPoolFlushPage(pPool, pPage);
2072 break;
2073 }
2074 }
2075 }
2076
2077 /* next */
2078 i = pPage->iNext;
2079 } while (i != NIL_PGMPOOL_IDX);
2080 }
2081
2082 Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2083 STAM_COUNTER_INC(&pPool->StatCacheMisses);
2084 return VERR_FILE_NOT_FOUND;
2085}
2086
2087
2088/**
2089 * Inserts a page into the cache.
2090 *
2091 * @param pPool The pool.
2092 * @param pPage The cached page.
2093 * @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2094 */
2095static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2096{
2097 /*
2098 * Insert into the GCPhys hash if the page is fit for that.
2099 */
2100 Assert(!pPage->fCached);
2101 if (fCanBeCached)
2102 {
2103 pPage->fCached = true;
2104 pgmPoolHashInsert(pPool, pPage);
2105 Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2106 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2107 STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2108 }
2109 else
2110 {
2111 Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2112 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2113 STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2114 }
2115
2116 /*
2117 * Insert at the head of the age list.
2118 */
2119 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2120 pPage->iAgeNext = pPool->iAgeHead;
2121 if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2122 pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2123 else
2124 pPool->iAgeTail = pPage->idx;
2125 pPool->iAgeHead = pPage->idx;
2126}
2127
2128
2129/**
2130 * Flushes a cached page.
2131 *
2132 * @param pPool The pool.
2133 * @param pPage The cached page.
2134 */
2135static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2136{
2137 Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2138
2139 /*
2140 * Remove the page from the hash.
2141 */
2142 if (pPage->fCached)
2143 {
2144 pPage->fCached = false;
2145 pgmPoolHashRemove(pPool, pPage);
2146 }
2147 else
2148 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2149
2150 /*
2151 * Remove it from the age list.
2152 */
2153 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2154 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2155 else
2156 pPool->iAgeTail = pPage->iAgePrev;
2157 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2158 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2159 else
2160 pPool->iAgeHead = pPage->iAgeNext;
2161 pPage->iAgeNext = NIL_PGMPOOL_IDX;
2162 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2163}
2164
2165
2166/**
2167 * Looks for pages sharing the monitor.
2168 *
2169 * @returns Pointer to the head page.
2170 * @returns NULL if not found.
2171 * @param pPool The Pool
2172 * @param pNewPage The page which is going to be monitored.
2173 */
2174static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2175{
2176 /*
2177 * Look up the GCPhys in the hash.
2178 */
2179 RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2180 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2181 if (i == NIL_PGMPOOL_IDX)
2182 return NULL;
2183 do
2184 {
2185 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2186 if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2187 && pPage != pNewPage)
2188 {
2189 switch (pPage->enmKind)
2190 {
2191 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2192 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2193 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2194 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2195 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2196 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2197 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2198 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2199 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2200 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2201 case PGMPOOLKIND_64BIT_PML4:
2202 case PGMPOOLKIND_32BIT_PD:
2203 case PGMPOOLKIND_PAE_PDPT:
2204 {
2205 /* find the head */
2206 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2207 {
2208 Assert(pPage->iMonitoredPrev != pPage->idx);
2209 pPage = &pPool->aPages[pPage->iMonitoredPrev];
2210 }
2211 return pPage;
2212 }
2213
2214 /* ignore, no monitoring. */
2215 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2216 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2217 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2218 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2219 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2220 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2221 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2222 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2223 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2224 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2225 case PGMPOOLKIND_ROOT_NESTED:
2226 case PGMPOOLKIND_PAE_PD_PHYS:
2227 case PGMPOOLKIND_PAE_PDPT_PHYS:
2228 case PGMPOOLKIND_32BIT_PD_PHYS:
2229 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2230 break;
2231 default:
2232 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2233 }
2234 }
2235
2236 /* next */
2237 i = pPage->iNext;
2238 } while (i != NIL_PGMPOOL_IDX);
2239 return NULL;
2240}
2241
2242
2243/**
2244 * Enabled write monitoring of a guest page.
2245 *
2246 * @returns VBox status code.
2247 * @retval VINF_SUCCESS on success.
2248 * @param pPool The pool.
2249 * @param pPage The cached page.
2250 */
2251static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2252{
2253 LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
2254
2255 /*
2256 * Filter out the relevant kinds.
2257 */
2258 switch (pPage->enmKind)
2259 {
2260 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2261 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2262 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2263 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2264 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2265 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2266 case PGMPOOLKIND_64BIT_PML4:
2267 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2268 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2269 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2270 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2271 case PGMPOOLKIND_32BIT_PD:
2272 case PGMPOOLKIND_PAE_PDPT:
2273 break;
2274
2275 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2276 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2277 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2278 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2279 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2280 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2281 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2282 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2283 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2284 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2285 case PGMPOOLKIND_ROOT_NESTED:
2286 /* Nothing to monitor here. */
2287 return VINF_SUCCESS;
2288
2289 case PGMPOOLKIND_32BIT_PD_PHYS:
2290 case PGMPOOLKIND_PAE_PDPT_PHYS:
2291 case PGMPOOLKIND_PAE_PD_PHYS:
2292 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2293 /* Nothing to monitor here. */
2294 return VINF_SUCCESS;
2295 default:
2296 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2297 }
2298
2299 /*
2300 * Install handler.
2301 */
2302 int rc;
2303 PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2304 if (pPageHead)
2305 {
2306 Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2307 Assert(pPageHead->iMonitoredPrev != pPage->idx);
2308
2309#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2310 if (pPageHead->fDirty)
2311 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirty, false /* do not remove */);
2312#endif
2313
2314 pPage->iMonitoredPrev = pPageHead->idx;
2315 pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2316 if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2317 pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2318 pPageHead->iMonitoredNext = pPage->idx;
2319 rc = VINF_SUCCESS;
2320 }
2321 else
2322 {
2323 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2324 PVM pVM = pPool->CTX_SUFF(pVM);
2325 const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2326 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2327 GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
2328 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2329 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2330 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2331 pPool->pszAccessHandler);
2332 /** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2333 * the heap size should suffice. */
2334 AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2335 PVMCPU pVCpu = VMMGetCpu(pVM);
2336 AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
2337 }
2338 pPage->fMonitored = true;
2339 return rc;
2340}
2341
2342
2343/**
2344 * Disables write monitoring of a guest page.
2345 *
2346 * @returns VBox status code.
2347 * @retval VINF_SUCCESS on success.
2348 * @param pPool The pool.
2349 * @param pPage The cached page.
2350 */
2351static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2352{
2353 /*
2354 * Filter out the relevant kinds.
2355 */
2356 switch (pPage->enmKind)
2357 {
2358 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2359 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2360 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2361 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2362 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2363 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2364 case PGMPOOLKIND_64BIT_PML4:
2365 case PGMPOOLKIND_32BIT_PD:
2366 case PGMPOOLKIND_PAE_PDPT:
2367 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2368 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2369 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2370 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2371 break;
2372
2373 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2374 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2375 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2376 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2377 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2378 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2379 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2380 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2381 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2382 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2383 case PGMPOOLKIND_ROOT_NESTED:
2384 case PGMPOOLKIND_PAE_PD_PHYS:
2385 case PGMPOOLKIND_PAE_PDPT_PHYS:
2386 case PGMPOOLKIND_32BIT_PD_PHYS:
2387 /* Nothing to monitor here. */
2388 return VINF_SUCCESS;
2389
2390 default:
2391 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2392 }
2393
2394 /*
2395 * Remove the page from the monitored list or uninstall it if last.
2396 */
2397 const PVM pVM = pPool->CTX_SUFF(pVM);
2398 int rc;
2399 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2400 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2401 {
2402 if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2403 {
2404 PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2405 pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2406 rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
2407 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2408 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2409 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2410 pPool->pszAccessHandler);
2411 AssertFatalRCSuccess(rc);
2412 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2413 }
2414 else
2415 {
2416 pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2417 if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2418 {
2419 pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2420 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2421 }
2422 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2423 rc = VINF_SUCCESS;
2424 }
2425 }
2426 else
2427 {
2428 rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
2429 AssertFatalRC(rc);
2430 PVMCPU pVCpu = VMMGetCpu(pVM);
2431 AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2432 ("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2433 }
2434 pPage->fMonitored = false;
2435
2436 /*
2437 * Remove it from the list of modified pages (if in it).
2438 */
2439 pgmPoolMonitorModifiedRemove(pPool, pPage);
2440
2441 return rc;
2442}
2443
2444
2445/**
2446 * Inserts the page into the list of modified pages.
2447 *
2448 * @param pPool The pool.
2449 * @param pPage The page.
2450 */
2451void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2452{
2453 Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2454 AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2455 && pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2456 && pPool->iModifiedHead != pPage->idx,
2457 ("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2458 pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2459 pPool->iModifiedHead, pPool->cModifiedPages));
2460
2461 pPage->iModifiedNext = pPool->iModifiedHead;
2462 if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2463 pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2464 pPool->iModifiedHead = pPage->idx;
2465 pPool->cModifiedPages++;
2466#ifdef VBOX_WITH_STATISTICS
2467 if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2468 pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2469#endif
2470}
2471
2472
2473/**
2474 * Removes the page from the list of modified pages and resets the
2475 * moficiation counter.
2476 *
2477 * @param pPool The pool.
2478 * @param pPage The page which is believed to be in the list of modified pages.
2479 */
2480static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2481{
2482 Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2483 if (pPool->iModifiedHead == pPage->idx)
2484 {
2485 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2486 pPool->iModifiedHead = pPage->iModifiedNext;
2487 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2488 {
2489 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2490 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2491 }
2492 pPool->cModifiedPages--;
2493 }
2494 else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2495 {
2496 pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2497 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2498 {
2499 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2500 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2501 }
2502 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2503 pPool->cModifiedPages--;
2504 }
2505 else
2506 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2507 pPage->cModifications = 0;
2508}
2509
2510
2511/**
2512 * Zaps the list of modified pages, resetting their modification counters in the process.
2513 *
2514 * @param pVM The VM handle.
2515 */
2516static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2517{
2518 pgmLock(pVM);
2519 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2520 LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2521
2522 unsigned cPages = 0; NOREF(cPages);
2523
2524#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2525 pgmPoolResetDirtyPages(pVM);
2526#endif
2527
2528 uint16_t idx = pPool->iModifiedHead;
2529 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2530 while (idx != NIL_PGMPOOL_IDX)
2531 {
2532 PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2533 idx = pPage->iModifiedNext;
2534 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2535 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2536 pPage->cModifications = 0;
2537 Assert(++cPages);
2538 }
2539 AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2540 pPool->cModifiedPages = 0;
2541 pgmUnlock(pVM);
2542}
2543
2544
2545/**
2546 * Handle SyncCR3 pool tasks
2547 *
2548 * @returns VBox status code.
2549 * @retval VINF_SUCCESS if successfully added.
2550 * @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2551 * @param pVCpu The VMCPU handle.
2552 * @remark Should only be used when monitoring is available, thus placed in
2553 * the PGMPOOL_WITH_MONITORING #ifdef.
2554 */
2555int pgmPoolSyncCR3(PVMCPU pVCpu)
2556{
2557 PVM pVM = pVCpu->CTX_SUFF(pVM);
2558 LogFlow(("pgmPoolSyncCR3\n"));
2559
2560 /*
2561 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2562 * Occasionally we will have to clear all the shadow page tables because we wanted
2563 * to monitor a page which was mapped by too many shadowed page tables. This operation
2564 * sometimes refered to as a 'lightweight flush'.
2565 */
2566# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2567 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2568 pgmR3PoolClearAll(pVM);
2569# else /* !IN_RING3 */
2570 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2571 {
2572 Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2573 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2574
2575 /* Make sure all other VCPUs return to ring 3. */
2576 if (pVM->cCpus > 1)
2577 {
2578 VM_FF_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
2579 PGM_INVL_ALL_VCPU_TLBS(pVM);
2580 }
2581 return VINF_PGM_SYNC_CR3;
2582 }
2583# endif /* !IN_RING3 */
2584 else
2585 {
2586 pgmPoolMonitorModifiedClearAll(pVM);
2587
2588 /* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
2589 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2590 {
2591 Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
2592 return pgmPoolSyncCR3(pVCpu);
2593 }
2594 }
2595 return VINF_SUCCESS;
2596}
2597
2598
2599/**
2600 * Frees up at least one user entry.
2601 *
2602 * @returns VBox status code.
2603 * @retval VINF_SUCCESS if successfully added.
2604 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2605 * @param pPool The pool.
2606 * @param iUser The user index.
2607 */
2608static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2609{
2610 STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2611 /*
2612 * Just free cached pages in a braindead fashion.
2613 */
2614 /** @todo walk the age list backwards and free the first with usage. */
2615 int rc = VINF_SUCCESS;
2616 do
2617 {
2618 int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2619 if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2620 rc = rc2;
2621 } while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2622 return rc;
2623}
2624
2625
2626/**
2627 * Inserts a page into the cache.
2628 *
2629 * This will create user node for the page, insert it into the GCPhys
2630 * hash, and insert it into the age list.
2631 *
2632 * @returns VBox status code.
2633 * @retval VINF_SUCCESS if successfully added.
2634 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2635 * @param pPool The pool.
2636 * @param pPage The cached page.
2637 * @param GCPhys The GC physical address of the page we're gonna shadow.
2638 * @param iUser The user index.
2639 * @param iUserTable The user table index.
2640 */
2641DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2642{
2643 int rc = VINF_SUCCESS;
2644 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2645
2646 LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2647
2648#ifdef VBOX_STRICT
2649 /*
2650 * Check that the entry doesn't already exists.
2651 */
2652 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2653 {
2654 uint16_t i = pPage->iUserHead;
2655 do
2656 {
2657 Assert(i < pPool->cMaxUsers);
2658 AssertMsg(paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2659 i = paUsers[i].iNext;
2660 } while (i != NIL_PGMPOOL_USER_INDEX);
2661 }
2662#endif
2663
2664 /*
2665 * Find free a user node.
2666 */
2667 uint16_t i = pPool->iUserFreeHead;
2668 if (i == NIL_PGMPOOL_USER_INDEX)
2669 {
2670 rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2671 if (RT_FAILURE(rc))
2672 return rc;
2673 i = pPool->iUserFreeHead;
2674 }
2675
2676 /*
2677 * Unlink the user node from the free list,
2678 * initialize and insert it into the user list.
2679 */
2680 pPool->iUserFreeHead = paUsers[i].iNext;
2681 paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2682 paUsers[i].iUser = iUser;
2683 paUsers[i].iUserTable = iUserTable;
2684 pPage->iUserHead = i;
2685
2686 /*
2687 * Insert into cache and enable monitoring of the guest page if enabled.
2688 *
2689 * Until we implement caching of all levels, including the CR3 one, we'll
2690 * have to make sure we don't try monitor & cache any recursive reuse of
2691 * a monitored CR3 page. Because all windows versions are doing this we'll
2692 * have to be able to do combined access monitoring, CR3 + PT and
2693 * PD + PT (guest PAE).
2694 *
2695 * Update:
2696 * We're now cooperating with the CR3 monitor if an uncachable page is found.
2697 */
2698 const bool fCanBeMonitored = true;
2699 pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2700 if (fCanBeMonitored)
2701 {
2702 rc = pgmPoolMonitorInsert(pPool, pPage);
2703 AssertRC(rc);
2704 }
2705 return rc;
2706}
2707
2708
2709/**
2710 * Adds a user reference to a page.
2711 *
2712 * This will move the page to the head of the
2713 *
2714 * @returns VBox status code.
2715 * @retval VINF_SUCCESS if successfully added.
2716 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2717 * @param pPool The pool.
2718 * @param pPage The cached page.
2719 * @param iUser The user index.
2720 * @param iUserTable The user table.
2721 */
2722static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2723{
2724 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2725
2726 Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2727
2728# ifdef VBOX_STRICT
2729 /*
2730 * Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2731 */
2732 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2733 {
2734 uint16_t i = pPage->iUserHead;
2735 do
2736 {
2737 Assert(i < pPool->cMaxUsers);
2738 AssertMsg(iUser != PGMPOOL_IDX_PD || iUser != PGMPOOL_IDX_PDPT || iUser != PGMPOOL_IDX_NESTED_ROOT || iUser != PGMPOOL_IDX_AMD64_CR3 ||
2739 paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2740 i = paUsers[i].iNext;
2741 } while (i != NIL_PGMPOOL_USER_INDEX);
2742 }
2743# endif
2744
2745 /*
2746 * Allocate a user node.
2747 */
2748 uint16_t i = pPool->iUserFreeHead;
2749 if (i == NIL_PGMPOOL_USER_INDEX)
2750 {
2751 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2752 if (RT_FAILURE(rc))
2753 return rc;
2754 i = pPool->iUserFreeHead;
2755 }
2756 pPool->iUserFreeHead = paUsers[i].iNext;
2757
2758 /*
2759 * Initialize the user node and insert it.
2760 */
2761 paUsers[i].iNext = pPage->iUserHead;
2762 paUsers[i].iUser = iUser;
2763 paUsers[i].iUserTable = iUserTable;
2764 pPage->iUserHead = i;
2765
2766# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2767 if (pPage->fDirty)
2768 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirty, false /* do not remove */);
2769# endif
2770
2771 /*
2772 * Tell the cache to update its replacement stats for this page.
2773 */
2774 pgmPoolCacheUsed(pPool, pPage);
2775 return VINF_SUCCESS;
2776}
2777
2778
2779/**
2780 * Frees a user record associated with a page.
2781 *
2782 * This does not clear the entry in the user table, it simply replaces the
2783 * user record to the chain of free records.
2784 *
2785 * @param pPool The pool.
2786 * @param HCPhys The HC physical address of the shadow page.
2787 * @param iUser The shadow page pool index of the user table.
2788 * @param iUserTable The index into the user table (shadowed).
2789 */
2790static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2791{
2792 /*
2793 * Unlink and free the specified user entry.
2794 */
2795 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2796
2797 Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2798 /* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2799 uint16_t i = pPage->iUserHead;
2800 if ( i != NIL_PGMPOOL_USER_INDEX
2801 && paUsers[i].iUser == iUser
2802 && paUsers[i].iUserTable == iUserTable)
2803 {
2804 pPage->iUserHead = paUsers[i].iNext;
2805
2806 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2807 paUsers[i].iNext = pPool->iUserFreeHead;
2808 pPool->iUserFreeHead = i;
2809 return;
2810 }
2811
2812 /* General: Linear search. */
2813 uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2814 while (i != NIL_PGMPOOL_USER_INDEX)
2815 {
2816 if ( paUsers[i].iUser == iUser
2817 && paUsers[i].iUserTable == iUserTable)
2818 {
2819 if (iPrev != NIL_PGMPOOL_USER_INDEX)
2820 paUsers[iPrev].iNext = paUsers[i].iNext;
2821 else
2822 pPage->iUserHead = paUsers[i].iNext;
2823
2824 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2825 paUsers[i].iNext = pPool->iUserFreeHead;
2826 pPool->iUserFreeHead = i;
2827 return;
2828 }
2829 iPrev = i;
2830 i = paUsers[i].iNext;
2831 }
2832
2833 /* Fatal: didn't find it */
2834 AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2835 iUser, iUserTable, pPage->GCPhys));
2836}
2837
2838
2839/**
2840 * Gets the entry size of a shadow table.
2841 *
2842 * @param enmKind The kind of page.
2843 *
2844 * @returns The size of the entry in bytes. That is, 4 or 8.
2845 * @returns If the kind is not for a table, an assertion is raised and 0 is
2846 * returned.
2847 */
2848DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2849{
2850 switch (enmKind)
2851 {
2852 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2853 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2854 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2855 case PGMPOOLKIND_32BIT_PD:
2856 case PGMPOOLKIND_32BIT_PD_PHYS:
2857 return 4;
2858
2859 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2860 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2861 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2862 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2863 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2864 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2865 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2866 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2867 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2868 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2869 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2870 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2871 case PGMPOOLKIND_64BIT_PML4:
2872 case PGMPOOLKIND_PAE_PDPT:
2873 case PGMPOOLKIND_ROOT_NESTED:
2874 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2875 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2876 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2877 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2878 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2879 case PGMPOOLKIND_PAE_PD_PHYS:
2880 case PGMPOOLKIND_PAE_PDPT_PHYS:
2881 return 8;
2882
2883 default:
2884 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2885 }
2886}
2887
2888
2889/**
2890 * Gets the entry size of a guest table.
2891 *
2892 * @param enmKind The kind of page.
2893 *
2894 * @returns The size of the entry in bytes. That is, 0, 4 or 8.
2895 * @returns If the kind is not for a table, an assertion is raised and 0 is
2896 * returned.
2897 */
2898DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2899{
2900 switch (enmKind)
2901 {
2902 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2903 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2904 case PGMPOOLKIND_32BIT_PD:
2905 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2906 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2907 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2908 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2909 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2910 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2911 return 4;
2912
2913 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2914 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2915 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2916 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2917 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2918 case PGMPOOLKIND_64BIT_PML4:
2919 case PGMPOOLKIND_PAE_PDPT:
2920 return 8;
2921
2922 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2923 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2924 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2925 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2926 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2927 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2928 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2929 case PGMPOOLKIND_ROOT_NESTED:
2930 case PGMPOOLKIND_PAE_PD_PHYS:
2931 case PGMPOOLKIND_PAE_PDPT_PHYS:
2932 case PGMPOOLKIND_32BIT_PD_PHYS:
2933 /** @todo can we return 0? (nobody is calling this...) */
2934 AssertFailed();
2935 return 0;
2936
2937 default:
2938 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2939 }
2940}
2941
2942
2943/**
2944 * Scans one shadow page table for mappings of a physical page.
2945 *
2946 * @returns true/false indicating removal of all relevant PTEs
2947 * @param pVM The VM handle.
2948 * @param pPhysPage The guest page in question.
2949 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
2950 * @param iShw The shadow page table.
2951 * @param cRefs The number of references made in that PT.
2952 */
2953static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
2954{
2955 LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
2956 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2957 bool bRet = false;
2958
2959 /*
2960 * Assert sanity.
2961 */
2962 Assert(cRefs == 1);
2963 AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2964 PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2965
2966 /*
2967 * Then, clear the actual mappings to the page in the shadow PT.
2968 */
2969 switch (pPage->enmKind)
2970 {
2971 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2972 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2973 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2974 {
2975 const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
2976 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2977 uint32_t u32AndMask, u32OrMask;
2978
2979 u32AndMask = 0;
2980 u32OrMask = 0;
2981
2982 if (!fFlushPTEs)
2983 {
2984 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
2985 {
2986 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
2987 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
2988 u32OrMask = X86_PTE_RW;
2989 u32AndMask = UINT32_MAX;
2990 bRet = true;
2991 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
2992 break;
2993
2994 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
2995 u32OrMask = 0;
2996 u32AndMask = ~X86_PTE_RW;
2997 bRet = true;
2998 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
2999 break;
3000 default:
3001 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3002 break;
3003 }
3004 }
3005 else
3006 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3007
3008 /* Update the counter if we're removing references. */
3009 if (!u32AndMask)
3010 {
3011 Assert(pPage->cPresent >= cRefs);
3012 Assert(pPool->cPresent >= cRefs);
3013 pPage->cPresent -= cRefs;
3014 pPool->cPresent -= cRefs;
3015 }
3016
3017 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3018 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3019 {
3020 X86PTE Pte;
3021
3022 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
3023 Pte.u = (pPT->a[i].u & u32AndMask) | u32OrMask;
3024 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3025 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3026
3027 ASMAtomicWriteSize(&pPT->a[i].u, Pte.u);
3028 cRefs--;
3029 if (!cRefs)
3030 return bRet;
3031 }
3032#ifdef LOG_ENABLED
3033 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3034 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3035 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3036 {
3037 Log(("i=%d cRefs=%d\n", i, cRefs--));
3038 }
3039#endif
3040 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
3041 break;
3042 }
3043
3044 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3045 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3046 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3047 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3048 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3049 {
3050 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3051 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3052 uint64_t u64AndMask, u64OrMask;
3053
3054 u64OrMask = 0;
3055 u64AndMask = 0;
3056 if (!fFlushPTEs)
3057 {
3058 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3059 {
3060 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3061 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3062 u64OrMask = X86_PTE_RW;
3063 u64AndMask = UINT64_MAX;
3064 bRet = true;
3065 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3066 break;
3067
3068 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3069 u64OrMask = 0;
3070 u64AndMask = ~((uint64_t)X86_PTE_RW);
3071 bRet = true;
3072 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3073 break;
3074
3075 default:
3076 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3077 break;
3078 }
3079 }
3080 else
3081 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3082
3083 /* Update the counter if we're removing references. */
3084 if (!u64AndMask)
3085 {
3086 Assert(pPage->cPresent >= cRefs);
3087 Assert(pPool->cPresent >= cRefs);
3088 pPage->cPresent -= cRefs;
3089 pPool->cPresent -= cRefs;
3090 }
3091
3092 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3093 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3094 {
3095 X86PTEPAE Pte;
3096
3097 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3098 Pte.u = (pPT->a[i].u & u64AndMask) | u64OrMask;
3099 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3100 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3101
3102 ASMAtomicWriteSize(&pPT->a[i].u, Pte.u);
3103 cRefs--;
3104 if (!cRefs)
3105 return bRet;
3106 }
3107#ifdef LOG_ENABLED
3108 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3109 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3110 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3111 {
3112 Log(("i=%d cRefs=%d\n", i, cRefs--));
3113 }
3114#endif
3115 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind));
3116 break;
3117 }
3118
3119 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3120 {
3121 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3122 PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3123 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3124 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3125 {
3126 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3127 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3128 pPT->a[i].u = 0;
3129 cRefs--;
3130
3131 /* Update the counter as we're removing references. */
3132 Assert(pPage->cPresent);
3133 Assert(pPool->cPresent);
3134 pPage->cPresent--;
3135 pPool->cPresent--;
3136
3137 if (!cRefs)
3138 return bRet;
3139 }
3140#ifdef LOG_ENABLED
3141 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3142 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3143 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3144 {
3145 Log(("i=%d cRefs=%d\n", i, cRefs--));
3146 }
3147#endif
3148 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3149 break;
3150 }
3151
3152#ifdef PGM_WITH_LARGE_PAGES
3153 /* Large page case only. */
3154 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3155 {
3156 Assert(HWACCMIsNestedPagingActive(pVM));
3157 Assert(cRefs == 1);
3158
3159 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PDE4M_P | X86_PDE4M_PS;
3160 PEPTPD pPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3161 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPD->a); i++)
3162 if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3163 {
3164 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64 cRefs=%#x\n", i, pPD->a[i], cRefs));
3165 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3166 pPD->a[i].u = 0;
3167 cRefs--;
3168
3169 /* Update the counter as we're removing references. */
3170 Assert(pPage->cPresent);
3171 Assert(pPool->cPresent);
3172 pPage->cPresent--;
3173 pPool->cPresent--;
3174
3175 if (!cRefs)
3176 return bRet;
3177 }
3178# ifdef LOG_ENABLED
3179 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3180 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3181 if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3182 {
3183 Log(("i=%d cRefs=%d\n", i, cRefs--));
3184 }
3185# endif
3186 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3187 break;
3188 }
3189
3190 /* AMD-V nested paging - @todo merge with EPT as we only check the parts that are identical. */
3191 case PGMPOOLKIND_PAE_PD_PHYS:
3192 {
3193 Assert(HWACCMIsNestedPagingActive(pVM));
3194 Assert(cRefs == 1);
3195
3196 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PDE4M_P | X86_PDE4M_PS;
3197 PX86PD pPD = (PX86PD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3198 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPD->a); i++)
3199 if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3200 {
3201 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64 cRefs=%#x\n", i, pPD->a[i], cRefs));
3202 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3203 pPD->a[i].u = 0;
3204 cRefs--;
3205
3206 /* Update the counter as we're removing references. */
3207 Assert(pPage->cPresent);
3208 Assert(pPool->cPresent);
3209 pPage->cPresent--;
3210 pPool->cPresent--;
3211
3212 if (!cRefs)
3213 return bRet;
3214 }
3215# ifdef LOG_ENABLED
3216 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3217 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3218 if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3219 {
3220 Log(("i=%d cRefs=%d\n", i, cRefs--));
3221 }
3222# endif
3223 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3224 break;
3225 }
3226#endif /* PGM_WITH_LARGE_PAGES */
3227
3228 default:
3229 AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3230 }
3231 return bRet;
3232}
3233
3234
3235/**
3236 * Scans one shadow page table for mappings of a physical page.
3237 *
3238 * @param pVM The VM handle.
3239 * @param pPhysPage The guest page in question.
3240 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3241 * @param iShw The shadow page table.
3242 * @param cRefs The number of references made in that PT.
3243 */
3244static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
3245{
3246 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3247
3248 /* We should only come here with when there's only one reference to this physical page. */
3249 Assert(PGMPOOL_TD_GET_CREFS(PGM_PAGE_GET_TRACKING(pPhysPage)) == 1);
3250 Assert(cRefs == 1);
3251
3252 Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
3253 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3254 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, cRefs);
3255 if (!fKeptPTEs)
3256 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3257 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3258}
3259
3260
3261/**
3262 * Flushes a list of shadow page tables mapping the same physical page.
3263 *
3264 * @param pVM The VM handle.
3265 * @param pPhysPage The guest page in question.
3266 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3267 * @param iPhysExt The physical cross reference extent list to flush.
3268 */
3269static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3270{
3271 Assert(PGMIsLockOwner(pVM));
3272 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3273 bool fKeepList = false;
3274
3275 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3276 Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3277
3278 const uint16_t iPhysExtStart = iPhysExt;
3279 PPGMPOOLPHYSEXT pPhysExt;
3280 do
3281 {
3282 Assert(iPhysExt < pPool->cMaxPhysExts);
3283 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3284 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3285 {
3286 if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3287 {
3288 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], 1);
3289 if (!fKeptPTEs)
3290 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3291 else
3292 fKeepList = true;
3293 }
3294 }
3295 /* next */
3296 iPhysExt = pPhysExt->iNext;
3297 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3298
3299 if (!fKeepList)
3300 {
3301 /* insert the list into the free list and clear the ram range entry. */
3302 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3303 pPool->iPhysExtFreeHead = iPhysExtStart;
3304 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3305 }
3306
3307 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3308}
3309
3310
3311/**
3312 * Flushes all shadow page table mappings of the given guest page.
3313 *
3314 * This is typically called when the host page backing the guest one has been
3315 * replaced or when the page protection was changed due to an access handler.
3316 *
3317 * @returns VBox status code.
3318 * @retval VINF_SUCCESS if all references has been successfully cleared.
3319 * @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3320 * pool cleaning. FF and sync flags are set.
3321 *
3322 * @param pVM The VM handle.
3323 * @param GCPhysPage GC physical address of the page in question
3324 * @param pPhysPage The guest page in question.
3325 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3326 * @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3327 * flushed, it is NOT touched if this isn't necessary.
3328 * The caller MUST initialized this to @a false.
3329 */
3330int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3331{
3332 PVMCPU pVCpu = VMMGetCpu(pVM);
3333 pgmLock(pVM);
3334 int rc = VINF_SUCCESS;
3335
3336#ifdef PGM_WITH_LARGE_PAGES
3337 /* Is this page part of a large page? */
3338 if (PGM_PAGE_GET_PDE_TYPE(pPhysPage) == PGM_PAGE_PDE_TYPE_PDE)
3339 {
3340 PPGMPAGE pPhysBase;
3341 RTGCPHYS GCPhysBase = GCPhysPage & X86_PDE2M_PAE_PG_MASK;
3342
3343 GCPhysPage &= X86_PDE_PAE_PG_MASK;
3344
3345 /* Fetch the large page base. */
3346 if (GCPhysBase != GCPhysPage)
3347 {
3348 pPhysBase = pgmPhysGetPage(&pVM->pgm.s, GCPhysBase);
3349 AssertFatal(pPhysBase);
3350 }
3351 else
3352 pPhysBase = pPhysPage;
3353
3354 Log(("pgmPoolTrackUpdateGCPhys: update large page PDE for %RGp (%RGp)\n", GCPhysBase, GCPhysPage));
3355
3356 if (PGM_PAGE_GET_PDE_TYPE(pPhysBase) == PGM_PAGE_PDE_TYPE_PDE)
3357 {
3358 /* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
3359 PGM_PAGE_SET_PDE_TYPE(pPhysBase, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3360
3361 /* Update the base as that *only* that one has a reference and there's only one PDE to clear. */
3362 rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysBase, pPhysBase, fFlushPTEs, pfFlushTLBs);
3363
3364 *pfFlushTLBs = true;
3365 pgmUnlock(pVM);
3366 return rc;
3367 }
3368 }
3369#else
3370 NOREF(GCPhysPage);
3371#endif /* PGM_WITH_LARGE_PAGES */
3372
3373 const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3374 if (u16)
3375 {
3376 /*
3377 * The zero page is currently screwing up the tracking and we'll
3378 * have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3379 * is defined, zero pages won't normally be mapped. Some kind of solution
3380 * will be needed for this problem of course, but it will have to wait...
3381 */
3382 if ( PGM_PAGE_IS_ZERO(pPhysPage)
3383 || PGM_PAGE_IS_BALLOONED(pPhysPage))
3384 rc = VINF_PGM_GCPHYS_ALIASED;
3385 else
3386 {
3387# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3388 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3389 pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3390 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3391# endif
3392
3393 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3394 pgmPoolTrackFlushGCPhysPT(pVM,
3395 pPhysPage,
3396 fFlushPTEs,
3397 PGMPOOL_TD_GET_IDX(u16),
3398 PGMPOOL_TD_GET_CREFS(u16));
3399 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3400 pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3401 else
3402 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3403 *pfFlushTLBs = true;
3404
3405# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3406 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3407# endif
3408 }
3409 }
3410
3411 if (rc == VINF_PGM_GCPHYS_ALIASED)
3412 {
3413 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3414 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3415 rc = VINF_PGM_SYNC_CR3;
3416 }
3417 pgmUnlock(pVM);
3418 return rc;
3419}
3420
3421
3422/**
3423 * Scans all shadow page tables for mappings of a physical page.
3424 *
3425 * This may be slow, but it's most likely more efficient than cleaning
3426 * out the entire page pool / cache.
3427 *
3428 * @returns VBox status code.
3429 * @retval VINF_SUCCESS if all references has been successfully cleared.
3430 * @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3431 * a page pool cleaning.
3432 *
3433 * @param pVM The VM handle.
3434 * @param pPhysPage The guest page in question.
3435 */
3436int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3437{
3438 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3439 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3440 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3441 pPool->cUsedPages, pPool->cPresent, pPhysPage));
3442
3443#if 1
3444 /*
3445 * There is a limit to what makes sense.
3446 */
3447 if (pPool->cPresent > 1024)
3448 {
3449 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3450 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3451 return VINF_PGM_GCPHYS_ALIASED;
3452 }
3453#endif
3454
3455 /*
3456 * Iterate all the pages until we've encountered all that in use.
3457 * This is simple but not quite optimal solution.
3458 */
3459 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3460 const uint32_t u32 = u64;
3461 unsigned cLeft = pPool->cUsedPages;
3462 unsigned iPage = pPool->cCurPages;
3463 while (--iPage >= PGMPOOL_IDX_FIRST)
3464 {
3465 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3466 if ( pPage->GCPhys != NIL_RTGCPHYS
3467 && pPage->cPresent)
3468 {
3469 switch (pPage->enmKind)
3470 {
3471 /*
3472 * We only care about shadow page tables.
3473 */
3474 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3475 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3476 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3477 {
3478 unsigned cPresent = pPage->cPresent;
3479 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3480 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3481 if (pPT->a[i].n.u1Present)
3482 {
3483 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3484 {
3485 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3486 pPT->a[i].u = 0;
3487
3488 /* Update the counter as we're removing references. */
3489 Assert(pPage->cPresent);
3490 Assert(pPool->cPresent);
3491 pPage->cPresent--;
3492 pPool->cPresent--;
3493 }
3494 if (!--cPresent)
3495 break;
3496 }
3497 break;
3498 }
3499
3500 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3501 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3502 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3503 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3504 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3505 {
3506 unsigned cPresent = pPage->cPresent;
3507 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3508 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3509 if (pPT->a[i].n.u1Present)
3510 {
3511 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3512 {
3513 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3514 pPT->a[i].u = 0;
3515
3516 /* Update the counter as we're removing references. */
3517 Assert(pPage->cPresent);
3518 Assert(pPool->cPresent);
3519 pPage->cPresent--;
3520 pPool->cPresent--;
3521 }
3522 if (!--cPresent)
3523 break;
3524 }
3525 break;
3526 }
3527#ifndef IN_RC
3528 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3529 {
3530 unsigned cPresent = pPage->cPresent;
3531 PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3532 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3533 if (pPT->a[i].n.u1Present)
3534 {
3535 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3536 {
3537 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3538 pPT->a[i].u = 0;
3539
3540 /* Update the counter as we're removing references. */
3541 Assert(pPage->cPresent);
3542 Assert(pPool->cPresent);
3543 pPage->cPresent--;
3544 pPool->cPresent--;
3545 }
3546 if (!--cPresent)
3547 break;
3548 }
3549 break;
3550 }
3551#endif
3552 }
3553 if (!--cLeft)
3554 break;
3555 }
3556 }
3557
3558 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3559 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3560 return VINF_SUCCESS;
3561}
3562
3563
3564/**
3565 * Clears the user entry in a user table.
3566 *
3567 * This is used to remove all references to a page when flushing it.
3568 */
3569static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3570{
3571 Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3572 Assert(pUser->iUser < pPool->cCurPages);
3573 uint32_t iUserTable = pUser->iUserTable;
3574
3575 /*
3576 * Map the user page.
3577 */
3578 PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3579 union
3580 {
3581 uint64_t *pau64;
3582 uint32_t *pau32;
3583 } u;
3584 u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3585
3586 LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3587
3588 /* Safety precaution in case we change the paging for other modes too in the future. */
3589 Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
3590
3591#ifdef VBOX_STRICT
3592 /*
3593 * Some sanity checks.
3594 */
3595 switch (pUserPage->enmKind)
3596 {
3597 case PGMPOOLKIND_32BIT_PD:
3598 case PGMPOOLKIND_32BIT_PD_PHYS:
3599 Assert(iUserTable < X86_PG_ENTRIES);
3600 break;
3601 case PGMPOOLKIND_PAE_PDPT:
3602 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3603 case PGMPOOLKIND_PAE_PDPT_PHYS:
3604 Assert(iUserTable < 4);
3605 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3606 break;
3607 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3608 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3609 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3610 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3611 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3612 case PGMPOOLKIND_PAE_PD_PHYS:
3613 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3614 break;
3615 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3616 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3617 Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3618 break;
3619 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3620 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3621 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3622 break;
3623 case PGMPOOLKIND_64BIT_PML4:
3624 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3625 /* GCPhys >> PAGE_SHIFT is the index here */
3626 break;
3627 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3628 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3629 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3630 break;
3631
3632 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3633 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3634 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3635 break;
3636
3637 case PGMPOOLKIND_ROOT_NESTED:
3638 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3639 break;
3640
3641 default:
3642 AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3643 break;
3644 }
3645#endif /* VBOX_STRICT */
3646
3647 /*
3648 * Clear the entry in the user page.
3649 */
3650 switch (pUserPage->enmKind)
3651 {
3652 /* 32-bit entries */
3653 case PGMPOOLKIND_32BIT_PD:
3654 case PGMPOOLKIND_32BIT_PD_PHYS:
3655 ASMAtomicWriteSize(&u.pau32[iUserTable], 0);
3656 break;
3657
3658 /* 64-bit entries */
3659 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3660 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3661 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3662 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3663 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3664#if defined(IN_RC)
3665 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
3666 * non-present PDPT will continue to cause page faults.
3667 */
3668 ASMReloadCR3();
3669#endif
3670 /* no break */
3671 case PGMPOOLKIND_PAE_PD_PHYS:
3672 case PGMPOOLKIND_PAE_PDPT_PHYS:
3673 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3674 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3675 case PGMPOOLKIND_64BIT_PML4:
3676 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3677 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3678 case PGMPOOLKIND_PAE_PDPT:
3679 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3680 case PGMPOOLKIND_ROOT_NESTED:
3681 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3682 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3683 ASMAtomicWriteSize(&u.pau64[iUserTable], 0);
3684 break;
3685
3686 default:
3687 AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3688 }
3689}
3690
3691
3692/**
3693 * Clears all users of a page.
3694 */
3695static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3696{
3697 /*
3698 * Free all the user records.
3699 */
3700 LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3701
3702 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3703 uint16_t i = pPage->iUserHead;
3704 while (i != NIL_PGMPOOL_USER_INDEX)
3705 {
3706 /* Clear enter in user table. */
3707 pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3708
3709 /* Free it. */
3710 const uint16_t iNext = paUsers[i].iNext;
3711 paUsers[i].iUser = NIL_PGMPOOL_IDX;
3712 paUsers[i].iNext = pPool->iUserFreeHead;
3713 pPool->iUserFreeHead = i;
3714
3715 /* Next. */
3716 i = iNext;
3717 }
3718 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3719}
3720
3721
3722/**
3723 * Allocates a new physical cross reference extent.
3724 *
3725 * @returns Pointer to the allocated extent on success. NULL if we're out of them.
3726 * @param pVM The VM handle.
3727 * @param piPhysExt Where to store the phys ext index.
3728 */
3729PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3730{
3731 Assert(PGMIsLockOwner(pVM));
3732 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3733 uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3734 if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3735 {
3736 STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3737 return NULL;
3738 }
3739 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3740 pPool->iPhysExtFreeHead = pPhysExt->iNext;
3741 pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3742 *piPhysExt = iPhysExt;
3743 return pPhysExt;
3744}
3745
3746
3747/**
3748 * Frees a physical cross reference extent.
3749 *
3750 * @param pVM The VM handle.
3751 * @param iPhysExt The extent to free.
3752 */
3753void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3754{
3755 Assert(PGMIsLockOwner(pVM));
3756 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3757 Assert(iPhysExt < pPool->cMaxPhysExts);
3758 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3759 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3760 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3761 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3762 pPool->iPhysExtFreeHead = iPhysExt;
3763}
3764
3765
3766/**
3767 * Frees a physical cross reference extent.
3768 *
3769 * @param pVM The VM handle.
3770 * @param iPhysExt The extent to free.
3771 */
3772void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3773{
3774 Assert(PGMIsLockOwner(pVM));
3775 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3776
3777 const uint16_t iPhysExtStart = iPhysExt;
3778 PPGMPOOLPHYSEXT pPhysExt;
3779 do
3780 {
3781 Assert(iPhysExt < pPool->cMaxPhysExts);
3782 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3783 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3784 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3785
3786 /* next */
3787 iPhysExt = pPhysExt->iNext;
3788 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3789
3790 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3791 pPool->iPhysExtFreeHead = iPhysExtStart;
3792}
3793
3794
3795/**
3796 * Insert a reference into a list of physical cross reference extents.
3797 *
3798 * @returns The new tracking data for PGMPAGE.
3799 *
3800 * @param pVM The VM handle.
3801 * @param iPhysExt The physical extent index of the list head.
3802 * @param iShwPT The shadow page table index.
3803 *
3804 */
3805static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3806{
3807 Assert(PGMIsLockOwner(pVM));
3808 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3809 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3810
3811 /* special common case. */
3812 if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3813 {
3814 paPhysExts[iPhysExt].aidx[2] = iShwPT;
3815 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3816 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d}\n", iPhysExt, iShwPT));
3817 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3818 }
3819
3820 /* general treatment. */
3821 const uint16_t iPhysExtStart = iPhysExt;
3822 unsigned cMax = 15;
3823 for (;;)
3824 {
3825 Assert(iPhysExt < pPool->cMaxPhysExts);
3826 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3827 if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3828 {
3829 paPhysExts[iPhysExt].aidx[i] = iShwPT;
3830 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3831 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3832 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3833 }
3834 if (!--cMax)
3835 {
3836 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3837 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3838 LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3839 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3840 }
3841 }
3842
3843 /* add another extent to the list. */
3844 PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3845 if (!pNew)
3846 {
3847 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackNoExtentsLeft);
3848 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3849 LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3850 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3851 }
3852 pNew->iNext = iPhysExtStart;
3853 pNew->aidx[0] = iShwPT;
3854 LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3855 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3856}
3857
3858
3859/**
3860 * Add a reference to guest physical page where extents are in use.
3861 *
3862 * @returns The new tracking data for PGMPAGE.
3863 *
3864 * @param pVM The VM handle.
3865 * @param u16 The ram range flags (top 16-bits).
3866 * @param iShwPT The shadow page table index.
3867 */
3868uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3869{
3870 pgmLock(pVM);
3871 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3872 {
3873 /*
3874 * Convert to extent list.
3875 */
3876 Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3877 uint16_t iPhysExt;
3878 PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3879 if (pPhysExt)
3880 {
3881 LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3882 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3883 pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3884 pPhysExt->aidx[1] = iShwPT;
3885 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3886 }
3887 else
3888 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3889 }
3890 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3891 {
3892 /*
3893 * Insert into the extent list.
3894 */
3895 u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3896 }
3897 else
3898 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3899 pgmUnlock(pVM);
3900 return u16;
3901}
3902
3903
3904/**
3905 * Clear references to guest physical memory.
3906 *
3907 * @param pPool The pool.
3908 * @param pPage The page.
3909 * @param pPhysPage Pointer to the aPages entry in the ram range.
3910 */
3911void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3912{
3913 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3914 AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3915
3916 uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3917 if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3918 {
3919 PVM pVM = pPool->CTX_SUFF(pVM);
3920 pgmLock(pVM);
3921
3922 uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3923 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3924 do
3925 {
3926 Assert(iPhysExt < pPool->cMaxPhysExts);
3927
3928 /*
3929 * Look for the shadow page and check if it's all freed.
3930 */
3931 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3932 {
3933 if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3934 {
3935 paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3936
3937 for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3938 if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3939 {
3940 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3941 pgmUnlock(pVM);
3942 return;
3943 }
3944
3945 /* we can free the node. */
3946 const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3947 if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3948 && iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3949 {
3950 /* lonely node */
3951 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3952 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3953 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3954 }
3955 else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3956 {
3957 /* head */
3958 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3959 PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3960 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3961 }
3962 else
3963 {
3964 /* in list */
3965 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3966 paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3967 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3968 }
3969 iPhysExt = iPhysExtNext;
3970 pgmUnlock(pVM);
3971 return;
3972 }
3973 }
3974
3975 /* next */
3976 iPhysExtPrev = iPhysExt;
3977 iPhysExt = paPhysExts[iPhysExt].iNext;
3978 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3979
3980 pgmUnlock(pVM);
3981 AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3982 }
3983 else /* nothing to do */
3984 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3985}
3986
3987
3988/**
3989 * Clear references to guest physical memory.
3990 *
3991 * This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3992 * is assumed to be correct, so the linear search can be skipped and we can assert
3993 * at an earlier point.
3994 *
3995 * @param pPool The pool.
3996 * @param pPage The page.
3997 * @param HCPhys The host physical address corresponding to the guest page.
3998 * @param GCPhys The guest physical address corresponding to HCPhys.
3999 */
4000static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
4001{
4002 /*
4003 * Walk range list.
4004 */
4005 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4006 while (pRam)
4007 {
4008 RTGCPHYS off = GCPhys - pRam->GCPhys;
4009 if (off < pRam->cb)
4010 {
4011 /* does it match? */
4012 const unsigned iPage = off >> PAGE_SHIFT;
4013 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4014#ifdef LOG_ENABLED
4015 RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
4016 Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
4017#endif
4018 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4019 {
4020 Assert(pPage->cPresent);
4021 Assert(pPool->cPresent);
4022 pPage->cPresent--;
4023 pPool->cPresent--;
4024 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
4025 return;
4026 }
4027 break;
4028 }
4029 pRam = pRam->CTX_SUFF(pNext);
4030 }
4031 AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4032}
4033
4034
4035/**
4036 * Clear references to guest physical memory.
4037 *
4038 * @param pPool The pool.
4039 * @param pPage The page.
4040 * @param HCPhys The host physical address corresponding to the guest page.
4041 * @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4042 */
4043void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
4044{
4045 Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4046
4047 /*
4048 * Walk range list.
4049 */
4050 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4051 while (pRam)
4052 {
4053 RTGCPHYS off = GCPhysHint - pRam->GCPhys;
4054 if (off < pRam->cb)
4055 {
4056 /* does it match? */
4057 const unsigned iPage = off >> PAGE_SHIFT;
4058 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4059 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4060 {
4061 Assert(pPage->cPresent);
4062 Assert(pPool->cPresent);
4063 pPage->cPresent--;
4064 pPool->cPresent--;
4065 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
4066 return;
4067 }
4068 break;
4069 }
4070 pRam = pRam->CTX_SUFF(pNext);
4071 }
4072
4073 /*
4074 * Damn, the hint didn't work. We'll have to do an expensive linear search.
4075 */
4076 STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4077 pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4078 while (pRam)
4079 {
4080 unsigned iPage = pRam->cb >> PAGE_SHIFT;
4081 while (iPage-- > 0)
4082 {
4083 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4084 {
4085 Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4086 HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4087 Assert(pPage->cPresent);
4088 Assert(pPool->cPresent);
4089 pPage->cPresent--;
4090 pPool->cPresent--;
4091 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
4092 return;
4093 }
4094 }
4095 pRam = pRam->CTX_SUFF(pNext);
4096 }
4097
4098 AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
4099}
4100
4101
4102/**
4103 * Clear references to guest physical memory in a 32-bit / 32-bit page table.
4104 *
4105 * @param pPool The pool.
4106 * @param pPage The page.
4107 * @param pShwPT The shadow page table (mapping of the page).
4108 * @param pGstPT The guest page table.
4109 */
4110DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4111{
4112 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4113 if (pShwPT->a[i].n.u1Present)
4114 {
4115 Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4116 i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4117 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
4118 if (!pPage->cPresent)
4119 break;
4120 }
4121}
4122
4123
4124/**
4125 * Clear references to guest physical memory in a PAE / 32-bit page table.
4126 *
4127 * @param pPool The pool.
4128 * @param pPage The page.
4129 * @param pShwPT The shadow page table (mapping of the page).
4130 * @param pGstPT The guest page table (just a half one).
4131 */
4132DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
4133{
4134 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4135 if (pShwPT->a[i].n.u1Present)
4136 {
4137 Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4138 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4139 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
4140 if (!pPage->cPresent)
4141 break;
4142 }
4143}
4144
4145
4146/**
4147 * Clear references to guest physical memory in a PAE / PAE page table.
4148 *
4149 * @param pPool The pool.
4150 * @param pPage The page.
4151 * @param pShwPT The shadow page table (mapping of the page).
4152 * @param pGstPT The guest page table.
4153 */
4154DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
4155{
4156 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4157 if (pShwPT->a[i].n.u1Present)
4158 {
4159 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4160 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4161 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
4162 if (!pPage->cPresent)
4163 break;
4164 }
4165}
4166
4167
4168/**
4169 * Clear references to guest physical memory in a 32-bit / 4MB page table.
4170 *
4171 * @param pPool The pool.
4172 * @param pPage The page.
4173 * @param pShwPT The shadow page table (mapping of the page).
4174 */
4175DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4176{
4177 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4178 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4179 if (pShwPT->a[i].n.u1Present)
4180 {
4181 Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4182 i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4183 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
4184 if (!pPage->cPresent)
4185 break;
4186 }
4187}
4188
4189
4190/**
4191 * Clear references to guest physical memory in a PAE / 2/4MB page table.
4192 *
4193 * @param pPool The pool.
4194 * @param pPage The page.
4195 * @param pShwPT The shadow page table (mapping of the page).
4196 */
4197DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
4198{
4199 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4200 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4201 if (pShwPT->a[i].n.u1Present)
4202 {
4203 Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4204 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
4205 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
4206 if (!pPage->cPresent)
4207 break;
4208 }
4209}
4210
4211
4212/**
4213 * Clear references to shadowed pages in an EPT page table.
4214 *
4215 * @param pPool The pool.
4216 * @param pPage The page.
4217 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4218 */
4219DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4220{
4221 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4222 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4223 if (pShwPT->a[i].n.u1Present)
4224 {
4225 Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4226 i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4227 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
4228 if (!pPage->cPresent)
4229 break;
4230 }
4231}
4232
4233
4234
4235/**
4236 * Clear references to shadowed pages in a 32 bits page directory.
4237 *
4238 * @param pPool The pool.
4239 * @param pPage The page.
4240 * @param pShwPD The shadow page directory (mapping of the page).
4241 */
4242DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4243{
4244 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4245 {
4246 if ( pShwPD->a[i].n.u1Present
4247 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4248 )
4249 {
4250 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4251 if (pSubPage)
4252 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4253 else
4254 AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4255 }
4256 }
4257}
4258
4259/**
4260 * Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4261 *
4262 * @param pPool The pool.
4263 * @param pPage The page.
4264 * @param pShwPD The shadow page directory (mapping of the page).
4265 */
4266DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4267{
4268 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4269 {
4270 if ( pShwPD->a[i].n.u1Present
4271 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4272 )
4273 {
4274#ifdef PGM_WITH_LARGE_PAGES
4275 if (pShwPD->a[i].b.u1Size)
4276 {
4277 Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
4278 i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4279 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys /* == base of 2 MB page */);
4280 }
4281 else
4282#endif
4283 {
4284 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4285 if (pSubPage)
4286 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4287 else
4288 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4289 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4290 }
4291 }
4292 }
4293}
4294
4295/**
4296 * Clear references to shadowed pages in a PAE page directory pointer table.
4297 *
4298 * @param pPool The pool.
4299 * @param pPage The page.
4300 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4301 */
4302DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4303{
4304 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4305 {
4306 if ( pShwPDPT->a[i].n.u1Present
4307 && !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4308 )
4309 {
4310 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4311 if (pSubPage)
4312 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4313 else
4314 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4315 }
4316 }
4317}
4318
4319
4320/**
4321 * Clear references to shadowed pages in a 64-bit page directory pointer table.
4322 *
4323 * @param pPool The pool.
4324 * @param pPage The page.
4325 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4326 */
4327DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4328{
4329 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4330 {
4331 Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
4332 if (pShwPDPT->a[i].n.u1Present)
4333 {
4334 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4335 if (pSubPage)
4336 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4337 else
4338 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4339 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4340 }
4341 }
4342}
4343
4344
4345/**
4346 * Clear references to shadowed pages in a 64-bit level 4 page table.
4347 *
4348 * @param pPool The pool.
4349 * @param pPage The page.
4350 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4351 */
4352DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4353{
4354 for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4355 {
4356 if (pShwPML4->a[i].n.u1Present)
4357 {
4358 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4359 if (pSubPage)
4360 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4361 else
4362 AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4363 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4364 }
4365 }
4366}
4367
4368
4369/**
4370 * Clear references to shadowed pages in an EPT page directory.
4371 *
4372 * @param pPool The pool.
4373 * @param pPage The page.
4374 * @param pShwPD The shadow page directory (mapping of the page).
4375 */
4376DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4377{
4378 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4379 {
4380 if (pShwPD->a[i].n.u1Present)
4381 {
4382#ifdef PGM_WITH_LARGE_PAGES
4383 if (pShwPD->a[i].b.u1Size)
4384 {
4385 Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
4386 i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4387 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys /* == base of 2 MB page */);
4388 }
4389 else
4390#endif
4391 {
4392 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4393 if (pSubPage)
4394 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4395 else
4396 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4397 }
4398 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4399 }
4400 }
4401}
4402
4403
4404/**
4405 * Clear references to shadowed pages in an EPT page directory pointer table.
4406 *
4407 * @param pPool The pool.
4408 * @param pPage The page.
4409 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4410 */
4411DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4412{
4413 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4414 {
4415 if (pShwPDPT->a[i].n.u1Present)
4416 {
4417 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4418 if (pSubPage)
4419 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4420 else
4421 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4422 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4423 }
4424 }
4425}
4426
4427
4428/**
4429 * Clears all references made by this page.
4430 *
4431 * This includes other shadow pages and GC physical addresses.
4432 *
4433 * @param pPool The pool.
4434 * @param pPage The page.
4435 */
4436static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4437{
4438 /*
4439 * Map the shadow page and take action according to the page kind.
4440 */
4441 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
4442 switch (pPage->enmKind)
4443 {
4444 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4445 {
4446 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4447 void *pvGst;
4448 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4449 pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4450 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4451 break;
4452 }
4453
4454 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4455 {
4456 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4457 void *pvGst;
4458 int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4459 pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
4460 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4461 break;
4462 }
4463
4464 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4465 {
4466 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4467 void *pvGst;
4468 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4469 pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
4470 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4471 break;
4472 }
4473
4474 case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4475 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4476 {
4477 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4478 pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4479 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4480 break;
4481 }
4482
4483 case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4484 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4485 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4486 {
4487 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4488 pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
4489 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4490 break;
4491 }
4492
4493 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4494 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4495 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4496 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4497 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4498 case PGMPOOLKIND_PAE_PD_PHYS:
4499 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4500 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4501 pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4502 break;
4503
4504 case PGMPOOLKIND_32BIT_PD_PHYS:
4505 case PGMPOOLKIND_32BIT_PD:
4506 pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4507 break;
4508
4509 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4510 case PGMPOOLKIND_PAE_PDPT:
4511 case PGMPOOLKIND_PAE_PDPT_PHYS:
4512 pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4513 break;
4514
4515 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4516 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4517 pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4518 break;
4519
4520 case PGMPOOLKIND_64BIT_PML4:
4521 pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4522 break;
4523
4524 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4525 pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4526 break;
4527
4528 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4529 pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4530 break;
4531
4532 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4533 pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4534 break;
4535
4536 default:
4537 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4538 }
4539
4540 /* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4541 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4542 ASMMemZeroPage(pvShw);
4543 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4544 pPage->fZeroed = true;
4545 PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
4546 Assert(!pPage->cPresent);
4547}
4548
4549/**
4550 * Flushes a pool page.
4551 *
4552 * This moves the page to the free list after removing all user references to it.
4553 *
4554 * @returns VBox status code.
4555 * @retval VINF_SUCCESS on success.
4556 * @param pPool The pool.
4557 * @param HCPhys The HC physical address of the shadow page.
4558 * @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
4559 */
4560int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush)
4561{
4562 PVM pVM = pPool->CTX_SUFF(pVM);
4563 bool fFlushRequired = false;
4564
4565 int rc = VINF_SUCCESS;
4566 STAM_PROFILE_START(&pPool->StatFlushPage, f);
4567 LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4568 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4569
4570 /*
4571 * Quietly reject any attempts at flushing any of the special root pages.
4572 */
4573 if (pPage->idx < PGMPOOL_IDX_FIRST)
4574 {
4575 AssertFailed(); /* can no longer happen */
4576 Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4577 return VINF_SUCCESS;
4578 }
4579
4580 pgmLock(pVM);
4581
4582 /*
4583 * Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4584 */
4585 if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4586 {
4587 AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4588 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4589 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4590 || pPage->enmKind == PGMPOOLKIND_32BIT_PD
4591 || pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4592 || pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4593 || pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4594 || pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4595 || pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4596 ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4597 Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4598 pgmUnlock(pVM);
4599 return VINF_SUCCESS;
4600 }
4601
4602#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4603 /* Start a subset so we won't run out of mapping space. */
4604 PVMCPU pVCpu = VMMGetCpu(pVM);
4605 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4606#endif
4607
4608 /*
4609 * Mark the page as being in need of an ASMMemZeroPage().
4610 */
4611 pPage->fZeroed = false;
4612
4613#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4614 if (pPage->fDirty)
4615 pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirty, false /* do not remove */);
4616#endif
4617
4618 /* If there are any users of this table, then we *must* issue a tlb flush on all VCPUs. */
4619 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
4620 fFlushRequired = true;
4621
4622 /*
4623 * Clear the page.
4624 */
4625 pgmPoolTrackClearPageUsers(pPool, pPage);
4626 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4627 pgmPoolTrackDeref(pPool, pPage);
4628 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4629
4630 /*
4631 * Flush it from the cache.
4632 */
4633 pgmPoolCacheFlushPage(pPool, pPage);
4634
4635#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4636 /* Heavy stuff done. */
4637 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4638#endif
4639
4640 /*
4641 * Deregistering the monitoring.
4642 */
4643 if (pPage->fMonitored)
4644 rc = pgmPoolMonitorFlush(pPool, pPage);
4645
4646 /*
4647 * Free the page.
4648 */
4649 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4650 pPage->iNext = pPool->iFreeHead;
4651 pPool->iFreeHead = pPage->idx;
4652 pPage->enmKind = PGMPOOLKIND_FREE;
4653 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4654 pPage->GCPhys = NIL_RTGCPHYS;
4655 pPage->fReusedFlushPending = false;
4656
4657 pPool->cUsedPages--;
4658
4659 /* Flush the TLBs of all VCPUs if required. */
4660 if ( fFlushRequired
4661 && fFlush)
4662 {
4663 PGM_INVL_ALL_VCPU_TLBS(pVM);
4664 }
4665
4666 pgmUnlock(pVM);
4667 STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4668 return rc;
4669}
4670
4671
4672/**
4673 * Frees a usage of a pool page.
4674 *
4675 * The caller is responsible to updating the user table so that it no longer
4676 * references the shadow page.
4677 *
4678 * @param pPool The pool.
4679 * @param HCPhys The HC physical address of the shadow page.
4680 * @param iUser The shadow page pool index of the user table.
4681 * @param iUserTable The index into the user table (shadowed).
4682 */
4683void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4684{
4685 PVM pVM = pPool->CTX_SUFF(pVM);
4686
4687 STAM_PROFILE_START(&pPool->StatFree, a);
4688 LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4689 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4690 Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4691 pgmLock(pVM);
4692 pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4693 if (!pPage->fCached)
4694 pgmPoolFlushPage(pPool, pPage);
4695 pgmUnlock(pVM);
4696 STAM_PROFILE_STOP(&pPool->StatFree, a);
4697}
4698
4699
4700/**
4701 * Makes one or more free page free.
4702 *
4703 * @returns VBox status code.
4704 * @retval VINF_SUCCESS on success.
4705 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4706 *
4707 * @param pPool The pool.
4708 * @param enmKind Page table kind
4709 * @param iUser The user of the page.
4710 */
4711static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4712{
4713 PVM pVM = pPool->CTX_SUFF(pVM);
4714
4715 LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4716
4717 /*
4718 * If the pool isn't full grown yet, expand it.
4719 */
4720 if ( pPool->cCurPages < pPool->cMaxPages
4721#if defined(IN_RC)
4722 /* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4723 && enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4724 && (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD || enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4725#endif
4726 )
4727 {
4728 STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4729#ifdef IN_RING3
4730 int rc = PGMR3PoolGrow(pVM);
4731#else
4732 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4733#endif
4734 if (RT_FAILURE(rc))
4735 return rc;
4736 STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4737 if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4738 return VINF_SUCCESS;
4739 }
4740
4741 /*
4742 * Free one cached page.
4743 */
4744 return pgmPoolCacheFreeOne(pPool, iUser);
4745}
4746
4747/**
4748 * Allocates a page from the pool.
4749 *
4750 * This page may actually be a cached page and not in need of any processing
4751 * on the callers part.
4752 *
4753 * @returns VBox status code.
4754 * @retval VINF_SUCCESS if a NEW page was allocated.
4755 * @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4756 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4757 * @param pVM The VM handle.
4758 * @param GCPhys The GC physical address of the page we're gonna shadow.
4759 * For 4MB and 2MB PD entries, it's the first address the
4760 * shadow PT is covering.
4761 * @param enmKind The kind of mapping.
4762 * @param enmAccess Access type for the mapping (only relevant for big pages)
4763 * @param iUser The shadow page pool index of the user table.
4764 * @param iUserTable The index into the user table (shadowed).
4765 * @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4766 * @param fLockPage Lock the page
4767 */
4768int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage)
4769{
4770 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4771 STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4772 LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4773 *ppPage = NULL;
4774 /** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4775 * (TRPMR3SyncIDT) because of FF priority. Try fix that?
4776 * Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4777
4778 pgmLock(pVM);
4779
4780 if (pPool->fCacheEnabled)
4781 {
4782 int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4783 if (RT_SUCCESS(rc2))
4784 {
4785 if (fLockPage)
4786 pgmPoolLockPage(pPool, *ppPage);
4787 pgmUnlock(pVM);
4788 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4789 LogFlow(("pgmPoolAlloc: cached returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, *ppPage, (*ppPage)->Core.Key, (*ppPage)->idx));
4790 return rc2;
4791 }
4792 }
4793
4794 /*
4795 * Allocate a new one.
4796 */
4797 int rc = VINF_SUCCESS;
4798 uint16_t iNew = pPool->iFreeHead;
4799 if (iNew == NIL_PGMPOOL_IDX)
4800 {
4801 rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4802 if (RT_FAILURE(rc))
4803 {
4804 pgmUnlock(pVM);
4805 Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4806 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4807 return rc;
4808 }
4809 iNew = pPool->iFreeHead;
4810 AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4811 }
4812
4813 /* unlink the free head */
4814 PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4815 pPool->iFreeHead = pPage->iNext;
4816 pPage->iNext = NIL_PGMPOOL_IDX;
4817
4818 /*
4819 * Initialize it.
4820 */
4821 pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4822 pPage->enmKind = enmKind;
4823 pPage->enmAccess = enmAccess;
4824 pPage->GCPhys = GCPhys;
4825 pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4826 pPage->fMonitored = false;
4827 pPage->fCached = false;
4828#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4829 pPage->fDirty = false;
4830#endif
4831 pPage->fReusedFlushPending = false;
4832 pPage->cModifications = 0;
4833 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4834 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4835 pPage->cPresent = 0;
4836 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
4837 pPage->pvLastAccessHandlerFault = 0;
4838 pPage->cLastAccessHandlerCount = 0;
4839 pPage->pvLastAccessHandlerRip = 0;
4840
4841 /*
4842 * Insert into the tracking and cache. If this fails, free the page.
4843 */
4844 int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4845 if (RT_FAILURE(rc3))
4846 {
4847 pPool->cUsedPages--;
4848 pPage->enmKind = PGMPOOLKIND_FREE;
4849 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4850 pPage->GCPhys = NIL_RTGCPHYS;
4851 pPage->iNext = pPool->iFreeHead;
4852 pPool->iFreeHead = pPage->idx;
4853 pgmUnlock(pVM);
4854 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4855 Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4856 return rc3;
4857 }
4858
4859 /*
4860 * Commit the allocation, clear the page and return.
4861 */
4862#ifdef VBOX_WITH_STATISTICS
4863 if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4864 pPool->cUsedPagesHigh = pPool->cUsedPages;
4865#endif
4866
4867 if (!pPage->fZeroed)
4868 {
4869 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4870 void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4871 ASMMemZeroPage(pv);
4872 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4873 }
4874
4875 *ppPage = pPage;
4876 if (fLockPage)
4877 pgmPoolLockPage(pPool, pPage);
4878 pgmUnlock(pVM);
4879 LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4880 rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4881 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4882 return rc;
4883}
4884
4885
4886/**
4887 * Frees a usage of a pool page.
4888 *
4889 * @param pVM The VM handle.
4890 * @param HCPhys The HC physical address of the shadow page.
4891 * @param iUser The shadow page pool index of the user table.
4892 * @param iUserTable The index into the user table (shadowed).
4893 */
4894void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4895{
4896 LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4897 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4898 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4899}
4900
4901/**
4902 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4903 *
4904 * @returns Pointer to the shadow page structure.
4905 * @param pPool The pool.
4906 * @param HCPhys The HC physical address of the shadow page.
4907 */
4908PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4909{
4910 PVM pVM = pPool->CTX_SUFF(pVM);
4911
4912 Assert(PGMIsLockOwner(pVM));
4913
4914 /*
4915 * Look up the page.
4916 */
4917 pgmLock(pVM);
4918 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4919 pgmUnlock(pVM);
4920
4921 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4922 return pPage;
4923}
4924
4925#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
4926/**
4927 * Flush the specified page if present
4928 *
4929 * @param pVM The VM handle.
4930 * @param GCPhys Guest physical address of the page to flush
4931 */
4932void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
4933{
4934 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4935
4936 VM_ASSERT_EMT(pVM);
4937
4938 /*
4939 * Look up the GCPhys in the hash.
4940 */
4941 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
4942 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
4943 if (i == NIL_PGMPOOL_IDX)
4944 return;
4945
4946 do
4947 {
4948 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4949 if (pPage->GCPhys - GCPhys < PAGE_SIZE)
4950 {
4951 switch (pPage->enmKind)
4952 {
4953 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4954 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4955 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4956 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4957 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4958 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4959 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4960 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4961 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4962 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4963 case PGMPOOLKIND_64BIT_PML4:
4964 case PGMPOOLKIND_32BIT_PD:
4965 case PGMPOOLKIND_PAE_PDPT:
4966 {
4967 Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
4968#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4969 if (pPage->fDirty)
4970 STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
4971 else
4972#endif
4973 STAM_COUNTER_INC(&pPool->StatForceFlushPage);
4974 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
4975 pgmPoolMonitorChainFlush(pPool, pPage);
4976 return;
4977 }
4978
4979 /* ignore, no monitoring. */
4980 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4981 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4982 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4983 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4984 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4985 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4986 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4987 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4988 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4989 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4990 case PGMPOOLKIND_ROOT_NESTED:
4991 case PGMPOOLKIND_PAE_PD_PHYS:
4992 case PGMPOOLKIND_PAE_PDPT_PHYS:
4993 case PGMPOOLKIND_32BIT_PD_PHYS:
4994 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4995 break;
4996
4997 default:
4998 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
4999 }
5000 }
5001
5002 /* next */
5003 i = pPage->iNext;
5004 } while (i != NIL_PGMPOOL_IDX);
5005 return;
5006}
5007#endif /* IN_RING3 */
5008
5009#ifdef IN_RING3
5010
5011
5012/**
5013 * Reset CPU on hot plugging.
5014 *
5015 * @param pVM The VM handle.
5016 * @param pVCpu The virtual CPU.
5017 */
5018void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
5019{
5020 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
5021
5022 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5023 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5024 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5025}
5026
5027
5028/**
5029 * Flushes the entire cache.
5030 *
5031 * It will assert a global CR3 flush (FF) and assumes the caller is aware of
5032 * this and execute this CR3 flush.
5033 *
5034 * @param pPool The pool.
5035 */
5036void pgmR3PoolReset(PVM pVM)
5037{
5038 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5039
5040 Assert(PGMIsLockOwner(pVM));
5041 STAM_PROFILE_START(&pPool->StatR3Reset, a);
5042 LogFlow(("pgmR3PoolReset:\n"));
5043
5044 /*
5045 * If there are no pages in the pool, there is nothing to do.
5046 */
5047 if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5048 {
5049 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5050 return;
5051 }
5052
5053 /*
5054 * Exit the shadow mode since we're going to clear everything,
5055 * including the root page.
5056 */
5057 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5058 {
5059 PVMCPU pVCpu = &pVM->aCpus[i];
5060 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
5061 }
5062
5063 /*
5064 * Nuke the free list and reinsert all pages into it.
5065 */
5066 for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5067 {
5068 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5069
5070 Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
5071 if (pPage->fMonitored)
5072 pgmPoolMonitorFlush(pPool, pPage);
5073 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5074 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5075 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5076 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5077 pPage->cModifications = 0;
5078 pPage->GCPhys = NIL_RTGCPHYS;
5079 pPage->enmKind = PGMPOOLKIND_FREE;
5080 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5081 Assert(pPage->idx == i);
5082 pPage->iNext = i + 1;
5083 pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5084 pPage->fSeenNonGlobal = false;
5085 pPage->fMonitored = false;
5086#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5087 pPage->fDirty = false;
5088#endif
5089 pPage->fCached = false;
5090 pPage->fReusedFlushPending = false;
5091 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5092 pPage->iAgeNext = NIL_PGMPOOL_IDX;
5093 pPage->iAgePrev = NIL_PGMPOOL_IDX;
5094 pPage->cLocked = 0;
5095 }
5096 pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5097 pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5098 pPool->cUsedPages = 0;
5099
5100 /*
5101 * Zap and reinitialize the user records.
5102 */
5103 pPool->cPresent = 0;
5104 pPool->iUserFreeHead = 0;
5105 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5106 const unsigned cMaxUsers = pPool->cMaxUsers;
5107 for (unsigned i = 0; i < cMaxUsers; i++)
5108 {
5109 paUsers[i].iNext = i + 1;
5110 paUsers[i].iUser = NIL_PGMPOOL_IDX;
5111 paUsers[i].iUserTable = 0xfffffffe;
5112 }
5113 paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5114
5115 /*
5116 * Clear all the GCPhys links and rebuild the phys ext free list.
5117 */
5118 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
5119 pRam;
5120 pRam = pRam->CTX_SUFF(pNext))
5121 {
5122 unsigned iPage = pRam->cb >> PAGE_SHIFT;
5123 while (iPage-- > 0)
5124 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
5125 }
5126
5127 pPool->iPhysExtFreeHead = 0;
5128 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5129 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5130 for (unsigned i = 0; i < cMaxPhysExts; i++)
5131 {
5132 paPhysExts[i].iNext = i + 1;
5133 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5134 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5135 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5136 }
5137 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5138
5139 /*
5140 * Just zap the modified list.
5141 */
5142 pPool->cModifiedPages = 0;
5143 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5144
5145 /*
5146 * Clear the GCPhys hash and the age list.
5147 */
5148 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5149 pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5150 pPool->iAgeHead = NIL_PGMPOOL_IDX;
5151 pPool->iAgeTail = NIL_PGMPOOL_IDX;
5152
5153#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5154 /* Clear all dirty pages. */
5155 pPool->idxFreeDirtyPage = 0;
5156 pPool->cDirtyPages = 0;
5157 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
5158 pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
5159#endif
5160
5161 /*
5162 * Reinsert active pages into the hash and ensure monitoring chains are correct.
5163 */
5164 for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
5165 {
5166 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5167 pPage->iNext = NIL_PGMPOOL_IDX;
5168 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5169 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5170 pPage->cModifications = 0;
5171 /* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
5172 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5173 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5174 if (pPage->fMonitored)
5175 {
5176 int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
5177 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
5178 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
5179 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
5180 pPool->pszAccessHandler);
5181 AssertFatalRCSuccess(rc);
5182 pgmPoolHashInsert(pPool, pPage);
5183 }
5184 Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
5185 Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
5186 Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
5187 }
5188
5189 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5190 {
5191 /*
5192 * Re-enter the shadowing mode and assert Sync CR3 FF.
5193 */
5194 PVMCPU pVCpu = &pVM->aCpus[i];
5195 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5196 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5197 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5198 }
5199
5200 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5201}
5202#endif /* IN_RING3 */
5203
5204#ifdef LOG_ENABLED
5205static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5206{
5207 switch(enmKind)
5208 {
5209 case PGMPOOLKIND_INVALID:
5210 return "PGMPOOLKIND_INVALID";
5211 case PGMPOOLKIND_FREE:
5212 return "PGMPOOLKIND_FREE";
5213 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5214 return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5215 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5216 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5217 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5218 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5219 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5220 return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5221 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5222 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5223 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5224 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5225 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5226 return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5227 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5228 return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5229 case PGMPOOLKIND_32BIT_PD:
5230 return "PGMPOOLKIND_32BIT_PD";
5231 case PGMPOOLKIND_32BIT_PD_PHYS:
5232 return "PGMPOOLKIND_32BIT_PD_PHYS";
5233 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5234 return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5235 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5236 return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5237 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5238 return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5239 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5240 return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5241 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5242 return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5243 case PGMPOOLKIND_PAE_PD_PHYS:
5244 return "PGMPOOLKIND_PAE_PD_PHYS";
5245 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5246 return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5247 case PGMPOOLKIND_PAE_PDPT:
5248 return "PGMPOOLKIND_PAE_PDPT";
5249 case PGMPOOLKIND_PAE_PDPT_PHYS:
5250 return "PGMPOOLKIND_PAE_PDPT_PHYS";
5251 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5252 return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5253 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5254 return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5255 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5256 return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5257 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5258 return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5259 case PGMPOOLKIND_64BIT_PML4:
5260 return "PGMPOOLKIND_64BIT_PML4";
5261 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5262 return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5263 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5264 return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5265 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5266 return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5267 case PGMPOOLKIND_ROOT_NESTED:
5268 return "PGMPOOLKIND_ROOT_NESTED";
5269 }
5270 return "Unknown kind!";
5271}
5272#endif /* LOG_ENABLED*/
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