VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 23521

Last change on this file since 23521 was 23374, checked in by vboxsync, 16 years ago

PGMPool: Moved pgmR3PoolClearAll to from VMMAll to PGMPool.cpp.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 189.9 KB
Line 
1/* $Id: PGMAllPool.cpp 23374 2009-09-28 12:53:55Z vboxsync $ */
2/** @file
3 * PGM Shadow Page Pool.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_POOL
27#include <VBox/pgm.h>
28#include <VBox/mm.h>
29#include <VBox/em.h>
30#include <VBox/cpum.h>
31#ifdef IN_RC
32# include <VBox/patm.h>
33#endif
34#include "PGMInternal.h"
35#include <VBox/vm.h>
36#include <VBox/disopcode.h>
37#include <VBox/hwacc_vmx.h>
38
39#include <VBox/log.h>
40#include <VBox/err.h>
41#include <iprt/asm.h>
42#include <iprt/string.h>
43
44
45/*******************************************************************************
46* Internal Functions *
47*******************************************************************************/
48RT_C_DECLS_BEGIN
49static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50#ifdef PGMPOOL_WITH_USER_TRACKING
51DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54#endif
55#ifdef PGMPOOL_WITH_CACHE
56static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
57#endif
58#ifdef PGMPOOL_WITH_MONITORING
59static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
60#endif
61#ifndef IN_RING3
62DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
63#endif
64#ifdef LOG_ENABLED
65static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
66#endif
67#if defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)
68static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT);
69#endif
70
71int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
72PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
73void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
74void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
75
76RT_C_DECLS_END
77
78
79/**
80 * Checks if the specified page pool kind is for a 4MB or 2MB guest page.
81 *
82 * @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
83 * @param enmKind The page kind.
84 */
85DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
86{
87 switch (enmKind)
88 {
89 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
90 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
91 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
92 return true;
93 default:
94 return false;
95 }
96}
97
98/** @def PGMPOOL_PAGE_2_LOCKED_PTR
99 * Maps a pool page pool into the current context and lock it (RC only).
100 *
101 * @returns VBox status code.
102 * @param pVM The VM handle.
103 * @param pPage The pool page.
104 *
105 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
106 * small page window employeed by that function. Be careful.
107 * @remark There is no need to assert on the result.
108 */
109#if defined(IN_RC)
110DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
111{
112 void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
113
114 /* Make sure the dynamic mapping will not be reused. */
115 if (pv)
116 PGMDynLockHCPage(pVM, (uint8_t *)pv);
117
118 return pv;
119}
120#else
121# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
122#endif
123
124/** @def PGMPOOL_UNLOCK_PTR
125 * Unlock a previously locked dynamic caching (RC only).
126 *
127 * @returns VBox status code.
128 * @param pVM The VM handle.
129 * @param pPage The pool page.
130 *
131 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
132 * small page window employeed by that function. Be careful.
133 * @remark There is no need to assert on the result.
134 */
135#if defined(IN_RC)
136DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
137{
138 if (pvPage)
139 PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
140}
141#else
142# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
143#endif
144
145
146#ifdef PGMPOOL_WITH_MONITORING
147/**
148 * Determin the size of a write instruction.
149 * @returns number of bytes written.
150 * @param pDis The disassembler state.
151 */
152static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
153{
154 /*
155 * This is very crude and possibly wrong for some opcodes,
156 * but since it's not really supposed to be called we can
157 * probably live with that.
158 */
159 return DISGetParamSize(pDis, &pDis->param1);
160}
161
162
163/**
164 * Flushes a chain of pages sharing the same access monitor.
165 *
166 * @returns VBox status code suitable for scheduling.
167 * @param pPool The pool.
168 * @param pPage A page in the chain.
169 */
170int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
171{
172 LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
173
174 /*
175 * Find the list head.
176 */
177 uint16_t idx = pPage->idx;
178 if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
179 {
180 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181 {
182 idx = pPage->iMonitoredPrev;
183 Assert(idx != pPage->idx);
184 pPage = &pPool->aPages[idx];
185 }
186 }
187
188 /*
189 * Iterate the list flushing each shadow page.
190 */
191 int rc = VINF_SUCCESS;
192 for (;;)
193 {
194 idx = pPage->iMonitoredNext;
195 Assert(idx != pPage->idx);
196 if (pPage->idx >= PGMPOOL_IDX_FIRST)
197 {
198 int rc2 = pgmPoolFlushPage(pPool, pPage);
199 AssertRC(rc2);
200 }
201 /* next */
202 if (idx == NIL_PGMPOOL_IDX)
203 break;
204 pPage = &pPool->aPages[idx];
205 }
206 return rc;
207}
208
209
210/**
211 * Wrapper for getting the current context pointer to the entry being modified.
212 *
213 * @returns VBox status code suitable for scheduling.
214 * @param pVM VM Handle.
215 * @param pvDst Destination address
216 * @param pvSrc Source guest virtual address.
217 * @param GCPhysSrc The source guest physical address.
218 * @param cb Size of data to read
219 */
220DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
221{
222#if defined(IN_RING3)
223 memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
224 return VINF_SUCCESS;
225#else
226 /* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
227 return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
228#endif
229}
230
231/**
232 * Process shadow entries before they are changed by the guest.
233 *
234 * For PT entries we will clear them. For PD entries, we'll simply check
235 * for mapping conflicts and set the SyncCR3 FF if found.
236 *
237 * @param pVCpu VMCPU handle
238 * @param pPool The pool.
239 * @param pPage The head page.
240 * @param GCPhysFault The guest physical fault address.
241 * @param uAddress In R0 and GC this is the guest context fault address (flat).
242 * In R3 this is the host context 'fault' address.
243 * @param pDis The disassembler state for figuring out the write size.
244 * This need not be specified if the caller knows we won't do cross entry accesses.
245 */
246void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pDis)
247{
248 AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%#x (idx=%#x)\n", pPage->iMonitoredPrev, pPage->idx));
249 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
250 const unsigned cbWrite = pDis ? pgmPoolDisasWriteSize(pDis) : 0;
251 PVM pVM = pPool->CTX_SUFF(pVM);
252
253 LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, cbWrite));
254
255 for (;;)
256 {
257 union
258 {
259 void *pv;
260 PX86PT pPT;
261 PX86PTPAE pPTPae;
262 PX86PD pPD;
263 PX86PDPAE pPDPae;
264 PX86PDPT pPDPT;
265 PX86PML4 pPML4;
266 } uShw;
267
268 LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
269
270 uShw.pv = NULL;
271 switch (pPage->enmKind)
272 {
273 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
274 {
275 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
276 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
277 const unsigned iShw = off / sizeof(X86PTE);
278 LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
279 if (uShw.pPT->a[iShw].n.u1Present)
280 {
281# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
282 X86PTE GstPte;
283
284 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
285 AssertRC(rc);
286 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
287 pgmPoolTracDerefGCPhysHint(pPool, pPage,
288 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
289 GstPte.u & X86_PTE_PG_MASK);
290# endif
291 ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
292 }
293 break;
294 }
295
296 /* page/2 sized */
297 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
298 {
299 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
300 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
301 if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
302 {
303 const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
304 LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
305 if (uShw.pPTPae->a[iShw].n.u1Present)
306 {
307# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
308 X86PTE GstPte;
309 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
310 AssertRC(rc);
311
312 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
313 pgmPoolTracDerefGCPhysHint(pPool, pPage,
314 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
315 GstPte.u & X86_PTE_PG_MASK);
316# endif
317 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
318 }
319 }
320 break;
321 }
322
323 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
324 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
325 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
326 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
327 {
328 unsigned iGst = off / sizeof(X86PDE);
329 unsigned iShwPdpt = iGst / 256;
330 unsigned iShw = (iGst % 256) * 2;
331 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
332
333 LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
334 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
335 if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
336 {
337 for (unsigned i = 0; i < 2; i++)
338 {
339# ifndef IN_RING0
340 if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
341 {
342 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
343 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
344 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
345 break;
346 }
347 else
348# endif /* !IN_RING0 */
349 if (uShw.pPDPae->a[iShw+i].n.u1Present)
350 {
351 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
352 pgmPoolFree(pVM,
353 uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
354 pPage->idx,
355 iShw + i);
356 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
357 }
358
359 /* paranoia / a bit assumptive. */
360 if ( pDis
361 && (off & 3)
362 && (off & 3) + cbWrite > 4)
363 {
364 const unsigned iShw2 = iShw + 2 + i;
365 if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
366 {
367# ifndef IN_RING0
368 if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
369 {
370 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
371 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
372 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
373 break;
374 }
375 else
376# endif /* !IN_RING0 */
377 if (uShw.pPDPae->a[iShw2].n.u1Present)
378 {
379 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
380 pgmPoolFree(pVM,
381 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
382 pPage->idx,
383 iShw2);
384 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
385 }
386 }
387 }
388 }
389 }
390 break;
391 }
392
393 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
394 {
395 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
396 const unsigned iShw = off / sizeof(X86PTEPAE);
397 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
398 if (uShw.pPTPae->a[iShw].n.u1Present)
399 {
400# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
401 X86PTEPAE GstPte;
402 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
403 AssertRC(rc);
404
405 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
406 pgmPoolTracDerefGCPhysHint(pPool, pPage,
407 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
408 GstPte.u & X86_PTE_PAE_PG_MASK);
409# endif
410 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
411 }
412
413 /* paranoia / a bit assumptive. */
414 if ( pDis
415 && (off & 7)
416 && (off & 7) + cbWrite > sizeof(X86PTEPAE))
417 {
418 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
419 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
420
421 if (uShw.pPTPae->a[iShw2].n.u1Present)
422 {
423# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
424 X86PTEPAE GstPte;
425# ifdef IN_RING3
426 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
427# else
428 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
429# endif
430 AssertRC(rc);
431 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
432 pgmPoolTracDerefGCPhysHint(pPool, pPage,
433 uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
434 GstPte.u & X86_PTE_PAE_PG_MASK);
435# endif
436 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
437 }
438 }
439 break;
440 }
441
442 case PGMPOOLKIND_32BIT_PD:
443 {
444 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
445 const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
446
447 LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
448 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
449# ifndef IN_RING0
450 if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
451 {
452 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
453 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
454 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
455 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
456 break;
457 }
458# endif /* !IN_RING0 */
459# ifndef IN_RING0
460 else
461# endif /* !IN_RING0 */
462 {
463 if (uShw.pPD->a[iShw].n.u1Present)
464 {
465 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
466 pgmPoolFree(pVM,
467 uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
468 pPage->idx,
469 iShw);
470 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
471 }
472 }
473 /* paranoia / a bit assumptive. */
474 if ( pDis
475 && (off & 3)
476 && (off & 3) + cbWrite > sizeof(X86PTE))
477 {
478 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
479 if ( iShw2 != iShw
480 && iShw2 < RT_ELEMENTS(uShw.pPD->a))
481 {
482# ifndef IN_RING0
483 if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
484 {
485 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
486 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
487 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
488 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
489 break;
490 }
491# endif /* !IN_RING0 */
492# ifndef IN_RING0
493 else
494# endif /* !IN_RING0 */
495 {
496 if (uShw.pPD->a[iShw2].n.u1Present)
497 {
498 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
499 pgmPoolFree(pVM,
500 uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
501 pPage->idx,
502 iShw2);
503 ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
504 }
505 }
506 }
507 }
508#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
509 if ( uShw.pPD->a[iShw].n.u1Present
510 && !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
511 {
512 LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
513# ifdef IN_RC /* TLB load - we're pushing things a bit... */
514 ASMProbeReadByte(pvAddress);
515# endif
516 pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
517 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
518 }
519#endif
520 break;
521 }
522
523 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
524 {
525 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
526 const unsigned iShw = off / sizeof(X86PDEPAE);
527 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
528#ifndef IN_RING0
529 if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
530 {
531 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
532 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
533 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
534 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
535 break;
536 }
537#endif /* !IN_RING0 */
538 /*
539 * Causes trouble when the guest uses a PDE to refer to the whole page table level
540 * structure. (Invalidate here; faults later on when it tries to change the page
541 * table entries -> recheck; probably only applies to the RC case.)
542 */
543# ifndef IN_RING0
544 else
545# endif /* !IN_RING0 */
546 {
547 if (uShw.pPDPae->a[iShw].n.u1Present)
548 {
549 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
550 pgmPoolFree(pVM,
551 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
552 pPage->idx,
553 iShw);
554 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
555 }
556 }
557 /* paranoia / a bit assumptive. */
558 if ( pDis
559 && (off & 7)
560 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
561 {
562 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
563 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
564
565#ifndef IN_RING0
566 if ( iShw2 != iShw
567 && uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
568 {
569 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
570 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
571 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
572 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
573 break;
574 }
575#endif /* !IN_RING0 */
576# ifndef IN_RING0
577 else
578# endif /* !IN_RING0 */
579 if (uShw.pPDPae->a[iShw2].n.u1Present)
580 {
581 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
582 pgmPoolFree(pVM,
583 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
584 pPage->idx,
585 iShw2);
586 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
587 }
588 }
589 break;
590 }
591
592 case PGMPOOLKIND_PAE_PDPT:
593 {
594 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
595 /*
596 * Hopefully this doesn't happen very often:
597 * - touching unused parts of the page
598 * - messing with the bits of pd pointers without changing the physical address
599 */
600 /* PDPT roots are not page aligned; 32 byte only! */
601 const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
602
603 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
604 const unsigned iShw = offPdpt / sizeof(X86PDPE);
605 if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
606 {
607# ifndef IN_RING0
608 if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
609 {
610 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
611 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
612 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
613 LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
614 break;
615 }
616# endif /* !IN_RING0 */
617# ifndef IN_RING0
618 else
619# endif /* !IN_RING0 */
620 if (uShw.pPDPT->a[iShw].n.u1Present)
621 {
622 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
623 pgmPoolFree(pVM,
624 uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
625 pPage->idx,
626 iShw);
627 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
628 }
629
630 /* paranoia / a bit assumptive. */
631 if ( pDis
632 && (offPdpt & 7)
633 && (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
634 {
635 const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
636 if ( iShw2 != iShw
637 && iShw2 < X86_PG_PAE_PDPE_ENTRIES)
638 {
639# ifndef IN_RING0
640 if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
641 {
642 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
643 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
644 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
645 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
646 break;
647 }
648# endif /* !IN_RING0 */
649# ifndef IN_RING0
650 else
651# endif /* !IN_RING0 */
652 if (uShw.pPDPT->a[iShw2].n.u1Present)
653 {
654 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
655 pgmPoolFree(pVM,
656 uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
657 pPage->idx,
658 iShw2);
659 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
660 }
661 }
662 }
663 }
664 break;
665 }
666
667#ifndef IN_RC
668 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
669 {
670 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
671 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
672 const unsigned iShw = off / sizeof(X86PDEPAE);
673 Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
674 if (uShw.pPDPae->a[iShw].n.u1Present)
675 {
676 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
677 pgmPoolFree(pVM,
678 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
679 pPage->idx,
680 iShw);
681 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
682 }
683 /* paranoia / a bit assumptive. */
684 if ( pDis
685 && (off & 7)
686 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
687 {
688 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
689 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
690
691 Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
692 if (uShw.pPDPae->a[iShw2].n.u1Present)
693 {
694 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
695 pgmPoolFree(pVM,
696 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
697 pPage->idx,
698 iShw2);
699 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
700 }
701 }
702 break;
703 }
704
705 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
706 {
707 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
708 /*
709 * Hopefully this doesn't happen very often:
710 * - messing with the bits of pd pointers without changing the physical address
711 */
712 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
713 {
714 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
715 const unsigned iShw = off / sizeof(X86PDPE);
716 if (uShw.pPDPT->a[iShw].n.u1Present)
717 {
718 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
719 pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
720 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
721 }
722 /* paranoia / a bit assumptive. */
723 if ( pDis
724 && (off & 7)
725 && (off & 7) + cbWrite > sizeof(X86PDPE))
726 {
727 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
728 if (uShw.pPDPT->a[iShw2].n.u1Present)
729 {
730 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
731 pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
732 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
733 }
734 }
735 }
736 break;
737 }
738
739 case PGMPOOLKIND_64BIT_PML4:
740 {
741 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
742 /*
743 * Hopefully this doesn't happen very often:
744 * - messing with the bits of pd pointers without changing the physical address
745 */
746 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
747 {
748 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
749 const unsigned iShw = off / sizeof(X86PDPE);
750 if (uShw.pPML4->a[iShw].n.u1Present)
751 {
752 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
753 pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
754 ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
755 }
756 /* paranoia / a bit assumptive. */
757 if ( pDis
758 && (off & 7)
759 && (off & 7) + cbWrite > sizeof(X86PDPE))
760 {
761 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
762 if (uShw.pPML4->a[iShw2].n.u1Present)
763 {
764 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
765 pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
766 ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
767 }
768 }
769 }
770 break;
771 }
772#endif /* IN_RING0 */
773
774 default:
775 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
776 }
777 PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
778
779 /* next */
780 if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
781 return;
782 pPage = &pPool->aPages[pPage->iMonitoredNext];
783 }
784}
785
786# ifndef IN_RING3
787/**
788 * Checks if a access could be a fork operation in progress.
789 *
790 * Meaning, that the guest is setting up the parent process for Copy-On-Write.
791 *
792 * @returns true if it's likly that we're forking, otherwise false.
793 * @param pPool The pool.
794 * @param pDis The disassembled instruction.
795 * @param offFault The access offset.
796 */
797DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
798{
799 /*
800 * i386 linux is using btr to clear X86_PTE_RW.
801 * The functions involved are (2.6.16 source inspection):
802 * clear_bit
803 * ptep_set_wrprotect
804 * copy_one_pte
805 * copy_pte_range
806 * copy_pmd_range
807 * copy_pud_range
808 * copy_page_range
809 * dup_mmap
810 * dup_mm
811 * copy_mm
812 * copy_process
813 * do_fork
814 */
815 if ( pDis->pCurInstr->opcode == OP_BTR
816 && !(offFault & 4)
817 /** @todo Validate that the bit index is X86_PTE_RW. */
818 )
819 {
820 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
821 return true;
822 }
823 return false;
824}
825
826
827/**
828 * Determine whether the page is likely to have been reused.
829 *
830 * @returns true if we consider the page as being reused for a different purpose.
831 * @returns false if we consider it to still be a paging page.
832 * @param pVM VM Handle.
833 * @param pVCpu VMCPU Handle.
834 * @param pRegFrame Trap register frame.
835 * @param pDis The disassembly info for the faulting instruction.
836 * @param pvFault The fault address.
837 *
838 * @remark The REP prefix check is left to the caller because of STOSD/W.
839 */
840DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
841{
842#ifndef IN_RC
843 /** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
844 if ( HWACCMHasPendingIrq(pVM)
845 && (pRegFrame->rsp - pvFault) < 32)
846 {
847 /* Fault caused by stack writes while trying to inject an interrupt event. */
848 Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
849 return true;
850 }
851#else
852 NOREF(pVM); NOREF(pvFault);
853#endif
854
855 LogFlow(("Reused instr %RGv %d at %RGv param1.flags=%x param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.flags, pDis->param1.base.reg_gen));
856
857 /* Non-supervisor mode write means it's used for something else. */
858 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
859 return true;
860
861 switch (pDis->pCurInstr->opcode)
862 {
863 /* call implies the actual push of the return address faulted */
864 case OP_CALL:
865 Log4(("pgmPoolMonitorIsReused: CALL\n"));
866 return true;
867 case OP_PUSH:
868 Log4(("pgmPoolMonitorIsReused: PUSH\n"));
869 return true;
870 case OP_PUSHF:
871 Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
872 return true;
873 case OP_PUSHA:
874 Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
875 return true;
876 case OP_FXSAVE:
877 Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
878 return true;
879 case OP_MOVNTI: /* solaris - block_zero_no_xmm */
880 Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
881 return true;
882 case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
883 Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
884 return true;
885 case OP_MOVSWD:
886 case OP_STOSWD:
887 if ( pDis->prefix == (PREFIX_REP|PREFIX_REX)
888 && pRegFrame->rcx >= 0x40
889 )
890 {
891 Assert(pDis->mode == CPUMODE_64BIT);
892
893 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
894 return true;
895 }
896 return false;
897 }
898 if ( ( (pDis->param1.flags & USE_REG_GEN32)
899 || (pDis->param1.flags & USE_REG_GEN64))
900 && (pDis->param1.base.reg_gen == USE_REG_ESP))
901 {
902 Log4(("pgmPoolMonitorIsReused: ESP\n"));
903 return true;
904 }
905
906 return false;
907}
908
909/**
910 * Flushes the page being accessed.
911 *
912 * @returns VBox status code suitable for scheduling.
913 * @param pVM The VM handle.
914 * @param pVCpu The VMCPU handle.
915 * @param pPool The pool.
916 * @param pPage The pool page (head).
917 * @param pDis The disassembly of the write instruction.
918 * @param pRegFrame The trap register frame.
919 * @param GCPhysFault The fault address as guest physical address.
920 * @param pvFault The fault address.
921 */
922static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
923 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
924{
925 /*
926 * First, do the flushing.
927 */
928 int rc = pgmPoolMonitorChainFlush(pPool, pPage);
929
930 /*
931 * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). Must do this in raw mode (!); XP boot will fail otherwise
932 */
933 uint32_t cbWritten;
934 int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten);
935 if (RT_SUCCESS(rc2))
936 pRegFrame->rip += pDis->opsize;
937 else if (rc2 == VERR_EM_INTERPRETER)
938 {
939#ifdef IN_RC
940 if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
941 {
942 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
943 pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
944 rc = VINF_SUCCESS;
945 STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
946 }
947 else
948#endif
949 {
950 rc = VINF_EM_RAW_EMULATE_INSTR;
951 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
952 }
953 }
954 else
955 rc = rc2;
956
957 /* See use in pgmPoolAccessHandlerSimple(). */
958 PGM_INVL_VCPU_TLBS(pVCpu);
959 LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
960 return rc;
961}
962
963/**
964 * Handles the STOSD write accesses.
965 *
966 * @returns VBox status code suitable for scheduling.
967 * @param pVM The VM handle.
968 * @param pPool The pool.
969 * @param pPage The pool page (head).
970 * @param pDis The disassembly of the write instruction.
971 * @param pRegFrame The trap register frame.
972 * @param GCPhysFault The fault address as guest physical address.
973 * @param pvFault The fault address.
974 */
975DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
976 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
977{
978 unsigned uIncrement = pDis->param1.size;
979
980 Assert(pDis->mode == CPUMODE_32BIT || pDis->mode == CPUMODE_64BIT);
981 Assert(pRegFrame->rcx <= 0x20);
982
983#ifdef VBOX_STRICT
984 if (pDis->opmode == CPUMODE_32BIT)
985 Assert(uIncrement == 4);
986 else
987 Assert(uIncrement == 8);
988#endif
989
990 Log3(("pgmPoolAccessHandlerSTOSD\n"));
991
992 /*
993 * Increment the modification counter and insert it into the list
994 * of modified pages the first time.
995 */
996 if (!pPage->cModifications++)
997 pgmPoolMonitorModifiedInsert(pPool, pPage);
998
999 /*
1000 * Execute REP STOSD.
1001 *
1002 * This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
1003 * write situation, meaning that it's safe to write here.
1004 */
1005 PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
1006 RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
1007 while (pRegFrame->rcx)
1008 {
1009#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1010 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1011 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
1012 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1013#else
1014 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
1015#endif
1016#ifdef IN_RC
1017 *(uint32_t *)pu32 = pRegFrame->eax;
1018#else
1019 PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
1020#endif
1021 pu32 += uIncrement;
1022 GCPhysFault += uIncrement;
1023 pRegFrame->rdi += uIncrement;
1024 pRegFrame->rcx--;
1025 }
1026 pRegFrame->rip += pDis->opsize;
1027
1028#ifdef IN_RC
1029 /* See use in pgmPoolAccessHandlerSimple(). */
1030 PGM_INVL_VCPU_TLBS(pVCpu);
1031#endif
1032
1033 LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1034 return VINF_SUCCESS;
1035}
1036
1037
1038/**
1039 * Handles the simple write accesses.
1040 *
1041 * @returns VBox status code suitable for scheduling.
1042 * @param pVM The VM handle.
1043 * @param pVCpu The VMCPU handle.
1044 * @param pPool The pool.
1045 * @param pPage The pool page (head).
1046 * @param pDis The disassembly of the write instruction.
1047 * @param pRegFrame The trap register frame.
1048 * @param GCPhysFault The fault address as guest physical address.
1049 * @param pvFault The fault address.
1050 * @param pfReused Reused state (out)
1051 */
1052DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
1053 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
1054{
1055 Log3(("pgmPoolAccessHandlerSimple\n"));
1056 /*
1057 * Increment the modification counter and insert it into the list
1058 * of modified pages the first time.
1059 */
1060 if (!pPage->cModifications++)
1061 pgmPoolMonitorModifiedInsert(pPool, pPage);
1062
1063 /*
1064 * Clear all the pages. ASSUMES that pvFault is readable.
1065 */
1066#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1067 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1068 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1069 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1070#else
1071 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1072#endif
1073
1074 /*
1075 * Interpret the instruction.
1076 */
1077 uint32_t cb;
1078 int rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb);
1079 if (RT_SUCCESS(rc))
1080 pRegFrame->rip += pDis->opsize;
1081 else if (rc == VERR_EM_INTERPRETER)
1082 {
1083 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1084 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
1085 rc = VINF_EM_RAW_EMULATE_INSTR;
1086 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1087 }
1088
1089#if 0 /* experimental code */
1090 if (rc == VINF_SUCCESS)
1091 {
1092 switch (pPage->enmKind)
1093 {
1094 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1095 {
1096 X86PTEPAE GstPte;
1097 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1098 AssertRC(rc);
1099
1100 /* Check the new value written by the guest. If present and with a bogus physical address, then
1101 * it's fairly safe to assume the guest is reusing the PT.
1102 */
1103 if (GstPte.n.u1Present)
1104 {
1105 RTHCPHYS HCPhys = -1;
1106 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1107 if (rc != VINF_SUCCESS)
1108 {
1109 *pfReused = true;
1110 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1111 }
1112 }
1113 break;
1114 }
1115 }
1116 }
1117#endif
1118
1119#ifdef IN_RC
1120 /*
1121 * Quick hack, with logging enabled we're getting stale
1122 * code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1123 * Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1124 * have to be fixed to support this. But that'll have to wait till next week.
1125 *
1126 * An alternative is to keep track of the changed PTEs together with the
1127 * GCPhys from the guest PT. This may proove expensive though.
1128 *
1129 * At the moment, it's VITAL that it's done AFTER the instruction interpreting
1130 * because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1131 */
1132 PGM_INVL_VCPU_TLBS(pVCpu);
1133#endif
1134
1135 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1136 return rc;
1137}
1138
1139/**
1140 * \#PF Handler callback for PT write accesses.
1141 *
1142 * @returns VBox status code (appropriate for GC return).
1143 * @param pVM VM Handle.
1144 * @param uErrorCode CPU Error code.
1145 * @param pRegFrame Trap register frame.
1146 * NULL on DMA and other non CPU access.
1147 * @param pvFault The fault address (cr2).
1148 * @param GCPhysFault The GC physical address corresponding to pvFault.
1149 * @param pvUser User argument.
1150 */
1151DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1152{
1153 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1154 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1155 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1156 PVMCPU pVCpu = VMMGetCpu(pVM);
1157 unsigned cMaxModifications;
1158 bool fForcedFlush = false;
1159
1160 LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1161
1162 pgmLock(pVM);
1163 if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1164 {
1165 /* Pool page changed while we were waiting for the lock; ignore. */
1166 Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1167 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1168 pgmUnlock(pVM);
1169 return VINF_SUCCESS;
1170 }
1171#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1172 if (pPage->fDirty)
1173 {
1174 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH));
1175 return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1176 }
1177#endif
1178
1179#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1180 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1181 {
1182 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1183 void *pvGst;
1184 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1185 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1186 }
1187#endif
1188
1189 /*
1190 * Disassemble the faulting instruction.
1191 */
1192 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1193 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1194 AssertReturnStmt(rc == VINF_SUCCESS, pgmUnlock(pVM), rc);
1195
1196 Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1197
1198 /*
1199 * We should ALWAYS have the list head as user parameter. This
1200 * is because we use that page to record the changes.
1201 */
1202 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1203
1204#ifdef IN_RING0
1205 /* Maximum nr of modifications depends on the page type. */
1206 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1207 cMaxModifications = 4;
1208 else
1209 cMaxModifications = 24;
1210#else
1211 cMaxModifications = 48;
1212#endif
1213
1214 /*
1215 * Incremental page table updates should weight more than random ones.
1216 * (Only applies when started from offset 0)
1217 */
1218 pVCpu->pgm.s.cPoolAccessHandler++;
1219 if ( pPage->pvLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1220 && pPage->pvLastAccessHandlerRip < pRegFrame->rip + 0x40
1221 && pvFault == (pPage->pvLastAccessHandlerFault + pDis->param1.size)
1222 && pVCpu->pgm.s.cPoolAccessHandler == (pPage->cLastAccessHandlerCount + 1))
1223 {
1224 Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1225 pPage->cModifications = pPage->cModifications * 2;
1226 pPage->pvLastAccessHandlerFault = pvFault;
1227 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1228 if (pPage->cModifications >= cMaxModifications)
1229 {
1230 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1231 fForcedFlush = true;
1232 }
1233 }
1234
1235 if (pPage->cModifications >= cMaxModifications)
1236 Log(("Mod overflow %VGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1237
1238 /*
1239 * Check if it's worth dealing with.
1240 */
1241 bool fReused = false;
1242 bool fNotReusedNotForking = false;
1243 if ( ( pPage->cModifications < cMaxModifications /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
1244 || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1245 )
1246 && !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1247 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1248 {
1249 /*
1250 * Simple instructions, no REP prefix.
1251 */
1252 if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE)))
1253 {
1254 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1255 if (fReused)
1256 goto flushPage;
1257
1258 /* A mov instruction to change the first page table entry will be remembered so we can detect
1259 * full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1260 */
1261 if ( rc == VINF_SUCCESS
1262 && pDis->pCurInstr->opcode == OP_MOV
1263 && (pvFault & PAGE_OFFSET_MASK) == 0)
1264 {
1265 pPage->pvLastAccessHandlerFault = pvFault;
1266 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1267 pPage->pvLastAccessHandlerRip = pRegFrame->rip;
1268 /* Make sure we don't kick out a page too quickly. */
1269 if (pPage->cModifications > 8)
1270 pPage->cModifications = 2;
1271 }
1272 else
1273 if (pPage->pvLastAccessHandlerFault == pvFault)
1274 {
1275 /* ignore the 2nd write to this page table entry. */
1276 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1277 }
1278 else
1279 {
1280 pPage->pvLastAccessHandlerFault = 0;
1281 pPage->pvLastAccessHandlerRip = 0;
1282 }
1283
1284 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1285 pgmUnlock(pVM);
1286 return rc;
1287 }
1288
1289 /*
1290 * Windows is frequently doing small memset() operations (netio test 4k+).
1291 * We have to deal with these or we'll kill the cache and performance.
1292 */
1293 if ( pDis->pCurInstr->opcode == OP_STOSWD
1294 && !pRegFrame->eflags.Bits.u1DF
1295 && pDis->opmode == pDis->mode
1296 && pDis->addrmode == pDis->mode)
1297 {
1298 bool fValidStosd = false;
1299
1300 if ( pDis->mode == CPUMODE_32BIT
1301 && pDis->prefix == PREFIX_REP
1302 && pRegFrame->ecx <= 0x20
1303 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1304 && !((uintptr_t)pvFault & 3)
1305 && (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */
1306 )
1307 {
1308 fValidStosd = true;
1309 pRegFrame->rcx &= 0xffffffff; /* paranoia */
1310 }
1311 else
1312 if ( pDis->mode == CPUMODE_64BIT
1313 && pDis->prefix == (PREFIX_REP | PREFIX_REX)
1314 && pRegFrame->rcx <= 0x20
1315 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1316 && !((uintptr_t)pvFault & 7)
1317 && (pRegFrame->rax == 0 || pRegFrame->rax == 0x80) /* the two values observed. */
1318 )
1319 {
1320 fValidStosd = true;
1321 }
1322
1323 if (fValidStosd)
1324 {
1325 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1326 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1327 pgmUnlock(pVM);
1328 return rc;
1329 }
1330 }
1331
1332 /* REP prefix, don't bother. */
1333 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1334 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1335 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1336 fNotReusedNotForking = true;
1337 }
1338
1339#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1340 /* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1341 * leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1342 */
1343 if ( pPage->cModifications >= cMaxModifications
1344 && !fForcedFlush
1345 && pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1346 && ( fNotReusedNotForking
1347 || ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1348 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1349 )
1350 )
1351 {
1352 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
1353 Assert(pPage->fDirty == false);
1354
1355 /* Flush any monitored duplicates as we will disable write protection. */
1356 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1357 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1358 {
1359 PPGMPOOLPAGE pPageHead = pPage;
1360
1361 /* Find the monitor head. */
1362 while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1363 pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1364
1365 while (pPageHead)
1366 {
1367 unsigned idxNext = pPageHead->iMonitoredNext;
1368
1369 if (pPageHead != pPage)
1370 {
1371 STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1372 Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1373 int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1374 AssertRC(rc2);
1375 }
1376
1377 if (idxNext == NIL_PGMPOOL_IDX)
1378 break;
1379
1380 pPageHead = &pPool->aPages[idxNext];
1381 }
1382 }
1383
1384 /* The flushing above might fail for locked pages, so double check. */
1385 if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1386 && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1387 {
1388 pgmPoolAddDirtyPage(pVM, pPool, pPage);
1389
1390 /* Temporarily allow write access to the page table again. */
1391 rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys, pPage->GCPhys);
1392 if (rc == VINF_SUCCESS)
1393 {
1394 rc = PGMShwModifyPage(pVCpu, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
1395 AssertMsg(rc == VINF_SUCCESS
1396 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1397 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1398 || rc == VERR_PAGE_NOT_PRESENT,
1399 ("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1400
1401 pPage->pvDirtyFault = pvFault;
1402
1403 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1404 pgmUnlock(pVM);
1405 return rc;
1406 }
1407 }
1408 }
1409#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1410
1411 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1412flushPage:
1413 /*
1414 * Not worth it, so flush it.
1415 *
1416 * If we considered it to be reused, don't go back to ring-3
1417 * to emulate failed instructions since we usually cannot
1418 * interpret then. This may be a bit risky, in which case
1419 * the reuse detection must be fixed.
1420 */
1421 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1422 if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1423 rc = VINF_SUCCESS;
1424 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1425 pgmUnlock(pVM);
1426 return rc;
1427}
1428
1429# endif /* !IN_RING3 */
1430
1431# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1432
1433# ifdef VBOX_STRICT
1434/**
1435 * Check references to guest physical memory in a PAE / PAE page table.
1436 *
1437 * @param pPool The pool.
1438 * @param pPage The page.
1439 * @param pShwPT The shadow page table (mapping of the page).
1440 * @param pGstPT The guest page table.
1441 */
1442static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
1443{
1444 unsigned cErrors = 0;
1445 int LastRc;
1446 unsigned LastPTE;
1447 RTHCPHYS LastHCPhys;
1448
1449#ifdef VBOX_STRICT
1450 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1451 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1452#endif
1453 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1454 {
1455 if (pShwPT->a[i].n.u1Present)
1456 {
1457 RTHCPHYS HCPhys = -1;
1458 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1459 if ( rc != VINF_SUCCESS
1460 || (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys)
1461 {
1462 RTHCPHYS HCPhysPT = -1;
1463 Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1464 LastPTE = i;
1465 LastRc = rc;
1466 LastHCPhys = HCPhys;
1467 cErrors++;
1468
1469 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pPage->GCPhys, &HCPhysPT);
1470 AssertRC(rc);
1471
1472 for (unsigned i = 0; i < pPool->cCurPages; i++)
1473 {
1474 PPGMPOOLPAGE pTempPage = &pPool->aPages[i];
1475
1476 if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1477 {
1478 PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pTempPage);
1479
1480 for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1481 {
1482 if ( pShwPT2->a[j].n.u1Present
1483 && pShwPT2->a[j].n.u1Write
1484 && ((pShwPT2->a[j].u & X86_PTE_PAE_PG_MASK) == HCPhysPT))
1485 {
1486 Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, pShwPT->a[j].u, pShwPT2->a[j].u));
1487 }
1488 }
1489 }
1490 }
1491 }
1492 }
1493 }
1494 AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, pShwPT->a[LastPTE].u, LastHCPhys));
1495}
1496# endif /* VBOX_STRICT */
1497
1498/**
1499 * Clear references to guest physical memory in a PAE / PAE page table.
1500 *
1501 * @returns nr of changed PTEs
1502 * @param pPool The pool.
1503 * @param pPage The page.
1504 * @param pShwPT The shadow page table (mapping of the page).
1505 * @param pGstPT The guest page table.
1506 * @param pOldGstPT The old cached guest page table.
1507 * @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1508 * @param pfFlush Flush reused page table (out)
1509 */
1510DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT, PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1511{
1512 unsigned cChanged = 0;
1513
1514#ifdef VBOX_STRICT
1515 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1516 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1517#endif
1518 *pfFlush = false;
1519
1520 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1521 {
1522 /* Check the new value written by the guest. If present and with a bogus physical address, then
1523 * it's fairly safe to assume the guest is reusing the PT.
1524 */
1525 if ( fAllowRemoval
1526 && pGstPT->a[i].n.u1Present)
1527 {
1528 if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1529 {
1530 *pfFlush = true;
1531 return ++cChanged;
1532 }
1533 }
1534 if (pShwPT->a[i].n.u1Present)
1535 {
1536 /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1537 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1538 {
1539#ifdef VBOX_STRICT
1540 RTHCPHYS HCPhys = -1;
1541 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1542 AssertMsg(rc == VINF_SUCCESS && (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1543#endif
1544 uint64_t uHostAttr = pShwPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1545 bool fHostRW = !!(pShwPT->a[i].u & X86_PTE_RW);
1546 uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1547 bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1548
1549 if ( uHostAttr == uGuestAttr
1550 && fHostRW <= fGuestRW)
1551 continue;
1552 }
1553 cChanged++;
1554 /* Something was changed, so flush it. */
1555 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1556 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1557 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
1558 ASMAtomicWriteSize(&pShwPT->a[i].u, 0);
1559 }
1560 }
1561 return cChanged;
1562}
1563
1564
1565/**
1566 * Flush a dirty page
1567 *
1568 * @param pVM VM Handle.
1569 * @param pPool The pool.
1570 * @param idxSlot Dirty array slot index
1571 * @param fAllowRemoval Allow a reused page table to be removed
1572 */
1573static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1574{
1575 PPGMPOOLPAGE pPage;
1576 unsigned idxPage;
1577
1578 Assert(idxSlot < RT_ELEMENTS(pPool->aIdxDirtyPages));
1579 if (pPool->aIdxDirtyPages[idxSlot] == NIL_PGMPOOL_IDX)
1580 return;
1581
1582 idxPage = pPool->aIdxDirtyPages[idxSlot];
1583 AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1584 pPage = &pPool->aPages[idxPage];
1585 Assert(pPage->idx == idxPage);
1586 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1587
1588 AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1589 Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1590
1591 /* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1592 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys);
1593 Assert(rc == VINF_SUCCESS);
1594 pPage->fDirty = false;
1595
1596#ifdef VBOX_STRICT
1597 uint64_t fFlags = 0;
1598 RTHCPHYS HCPhys;
1599 rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys);
1600 AssertMsg( ( rc == VINF_SUCCESS
1601 && (!(fFlags & X86_PTE_RW) || HCPhys != pPage->Core.Key))
1602 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1603 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1604 || rc == VERR_PAGE_NOT_PRESENT,
1605 ("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags));
1606#endif
1607
1608 /* Flush those PTEs that have changed. */
1609 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1610 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1611 void *pvGst;
1612 bool fFlush;
1613 rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1614 unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst, (PCX86PTPAE)&pPool->aDirtyPages[idxSlot][0], fAllowRemoval, &fFlush);
1615 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1616 /** Note: we might want to consider keeping the dirty page active in case there were many changes. */
1617
1618 /* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1619 Assert(pPage->cModifications);
1620 if (cChanges < 4)
1621 pPage->cModifications = 1; /* must use > 0 here */
1622 else
1623 pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1624
1625 STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1626 if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages))
1627 pPool->idxFreeDirtyPage = idxSlot;
1628
1629 pPool->cDirtyPages--;
1630 pPool->aIdxDirtyPages[idxSlot] = NIL_PGMPOOL_IDX;
1631 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1632 if (fFlush)
1633 {
1634 Assert(fAllowRemoval);
1635 Log(("Flush reused page table!\n"));
1636 pgmPoolFlushPage(pPool, pPage);
1637 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1638 }
1639 else
1640 Log(("Removed dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1641}
1642
1643# ifndef IN_RING3
1644/**
1645 * Add a new dirty page
1646 *
1647 * @param pVM VM Handle.
1648 * @param pPool The pool.
1649 * @param pPage The page.
1650 */
1651void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1652{
1653 unsigned idxFree;
1654
1655 Assert(PGMIsLocked(pVM));
1656 AssertCompile(RT_ELEMENTS(pPool->aIdxDirtyPages) == 8 || RT_ELEMENTS(pPool->aIdxDirtyPages) == 16);
1657 Assert(!pPage->fDirty);
1658
1659 idxFree = pPool->idxFreeDirtyPage;
1660 Assert(idxFree < RT_ELEMENTS(pPool->aIdxDirtyPages));
1661 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1662
1663 if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aIdxDirtyPages))
1664 {
1665 STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1666 pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1667 }
1668 Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages));
1669 AssertMsg(pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1670
1671 Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1672
1673 /* Make a copy of the guest page table as we require valid GCPhys addresses when removing
1674 * references to physical pages. (the HCPhys linear lookup is *extremely* expensive!)
1675 */
1676 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1677 void *pvGst;
1678 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1679 memcpy(&pPool->aDirtyPages[idxFree][0], pvGst, PAGE_SIZE);
1680#ifdef VBOX_STRICT
1681 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1682#endif
1683
1684 STAM_COUNTER_INC(&pPool->StatDirtyPage);
1685 pPage->fDirty = true;
1686 pPage->idxDirty = idxFree;
1687 pPool->aIdxDirtyPages[idxFree] = pPage->idx;
1688 pPool->cDirtyPages++;
1689
1690 pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1691 if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages)
1692 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1693 {
1694 unsigned i;
1695 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1696 {
1697 idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1698 if (pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX)
1699 {
1700 pPool->idxFreeDirtyPage = idxFree;
1701 break;
1702 }
1703 }
1704 Assert(i != RT_ELEMENTS(pPool->aIdxDirtyPages));
1705 }
1706
1707 Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages) || pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX);
1708 return;
1709}
1710# endif /* !IN_RING3 */
1711
1712/**
1713 * Check if the specified page is dirty (not write monitored)
1714 *
1715 * @return dirty or not
1716 * @param pVM VM Handle.
1717 * @param GCPhys Guest physical address
1718 */
1719bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1720{
1721 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1722 Assert(PGMIsLocked(pVM));
1723 if (!pPool->cDirtyPages)
1724 return false;
1725
1726 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1727
1728 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1729 {
1730 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1731 {
1732 PPGMPOOLPAGE pPage;
1733 unsigned idxPage = pPool->aIdxDirtyPages[i];
1734
1735 pPage = &pPool->aPages[idxPage];
1736 if (pPage->GCPhys == GCPhys)
1737 return true;
1738 }
1739 }
1740 return false;
1741}
1742
1743/**
1744 * Reset all dirty pages by reinstating page monitoring.
1745 *
1746 * @param pVM VM Handle.
1747 */
1748void pgmPoolResetDirtyPages(PVM pVM)
1749{
1750 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1751 Assert(PGMIsLocked(pVM));
1752 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1753
1754 if (!pPool->cDirtyPages)
1755 return;
1756
1757 Log(("pgmPoolResetDirtyPages\n"));
1758 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1759 pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1760
1761 pPool->idxFreeDirtyPage = 0;
1762 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1763 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1764 {
1765 unsigned i;
1766 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1767 {
1768 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1769 {
1770 pPool->idxFreeDirtyPage = i;
1771 break;
1772 }
1773 }
1774 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1775 }
1776
1777 Assert(pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX || pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages));
1778 return;
1779}
1780# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1781#endif /* PGMPOOL_WITH_MONITORING */
1782
1783#ifdef PGMPOOL_WITH_CACHE
1784
1785/**
1786 * Inserts a page into the GCPhys hash table.
1787 *
1788 * @param pPool The pool.
1789 * @param pPage The page.
1790 */
1791DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1792{
1793 Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1794 Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1795 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1796 pPage->iNext = pPool->aiHash[iHash];
1797 pPool->aiHash[iHash] = pPage->idx;
1798}
1799
1800
1801/**
1802 * Removes a page from the GCPhys hash table.
1803 *
1804 * @param pPool The pool.
1805 * @param pPage The page.
1806 */
1807DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1808{
1809 Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1810 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1811 if (pPool->aiHash[iHash] == pPage->idx)
1812 pPool->aiHash[iHash] = pPage->iNext;
1813 else
1814 {
1815 uint16_t iPrev = pPool->aiHash[iHash];
1816 for (;;)
1817 {
1818 const int16_t i = pPool->aPages[iPrev].iNext;
1819 if (i == pPage->idx)
1820 {
1821 pPool->aPages[iPrev].iNext = pPage->iNext;
1822 break;
1823 }
1824 if (i == NIL_PGMPOOL_IDX)
1825 {
1826 AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1827 break;
1828 }
1829 iPrev = i;
1830 }
1831 }
1832 pPage->iNext = NIL_PGMPOOL_IDX;
1833}
1834
1835
1836/**
1837 * Frees up one cache page.
1838 *
1839 * @returns VBox status code.
1840 * @retval VINF_SUCCESS on success.
1841 * @param pPool The pool.
1842 * @param iUser The user index.
1843 */
1844static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1845{
1846#ifndef IN_RC
1847 const PVM pVM = pPool->CTX_SUFF(pVM);
1848#endif
1849 Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1850 STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1851
1852 /*
1853 * Select one page from the tail of the age list.
1854 */
1855 PPGMPOOLPAGE pPage;
1856 for (unsigned iLoop = 0; ; iLoop++)
1857 {
1858 uint16_t iToFree = pPool->iAgeTail;
1859 if (iToFree == iUser)
1860 iToFree = pPool->aPages[iToFree].iAgePrev;
1861/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1862 if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1863 {
1864 uint16_t i = pPool->aPages[iToFree].iAgePrev;
1865 for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1866 {
1867 if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1868 continue;
1869 iToFree = i;
1870 break;
1871 }
1872 }
1873*/
1874 Assert(iToFree != iUser);
1875 AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1876 pPage = &pPool->aPages[iToFree];
1877
1878 /*
1879 * Reject any attempts at flushing the currently active shadow CR3 mapping.
1880 * Call pgmPoolCacheUsed to move the page to the head of the age list.
1881 */
1882 if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1883 break;
1884 LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1885 pgmPoolCacheUsed(pPool, pPage);
1886 AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1887 }
1888
1889 /*
1890 * Found a usable page, flush it and return.
1891 */
1892 return pgmPoolFlushPage(pPool, pPage);
1893}
1894
1895
1896/**
1897 * Checks if a kind mismatch is really a page being reused
1898 * or if it's just normal remappings.
1899 *
1900 * @returns true if reused and the cached page (enmKind1) should be flushed
1901 * @returns false if not reused.
1902 * @param enmKind1 The kind of the cached page.
1903 * @param enmKind2 The kind of the requested page.
1904 */
1905static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1906{
1907 switch (enmKind1)
1908 {
1909 /*
1910 * Never reuse them. There is no remapping in non-paging mode.
1911 */
1912 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1913 case PGMPOOLKIND_32BIT_PD_PHYS:
1914 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1915 case PGMPOOLKIND_PAE_PD_PHYS:
1916 case PGMPOOLKIND_PAE_PDPT_PHYS:
1917 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1918 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1919 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1920 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1921 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1922 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1923 return false;
1924
1925 /*
1926 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1927 */
1928 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1929 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1930 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1931 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1932 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1933 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1934 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1935 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1936 case PGMPOOLKIND_32BIT_PD:
1937 case PGMPOOLKIND_PAE_PDPT:
1938 switch (enmKind2)
1939 {
1940 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1941 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1942 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1943 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1944 case PGMPOOLKIND_64BIT_PML4:
1945 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1946 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1947 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1948 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1949 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1950 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1951 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1952 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1953 return true;
1954 default:
1955 return false;
1956 }
1957
1958 /*
1959 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1960 */
1961 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1962 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1963 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1964 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1965 case PGMPOOLKIND_64BIT_PML4:
1966 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1967 switch (enmKind2)
1968 {
1969 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1970 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1971 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1972 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1973 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1974 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1975 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1976 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1977 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1978 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1979 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1980 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1981 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1982 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1983 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1984 return true;
1985 default:
1986 return false;
1987 }
1988
1989 /*
1990 * These cannot be flushed, and it's common to reuse the PDs as PTs.
1991 */
1992 case PGMPOOLKIND_ROOT_NESTED:
1993 return false;
1994
1995 default:
1996 AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1997 }
1998}
1999
2000
2001/**
2002 * Attempts to satisfy a pgmPoolAlloc request from the cache.
2003 *
2004 * @returns VBox status code.
2005 * @retval VINF_PGM_CACHED_PAGE on success.
2006 * @retval VERR_FILE_NOT_FOUND if not found.
2007 * @param pPool The pool.
2008 * @param GCPhys The GC physical address of the page we're gonna shadow.
2009 * @param enmKind The kind of mapping.
2010 * @param enmAccess Access type for the mapping (only relevant for big pages)
2011 * @param iUser The shadow page pool index of the user table.
2012 * @param iUserTable The index into the user table (shadowed).
2013 * @param ppPage Where to store the pointer to the page.
2014 */
2015static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2016{
2017#ifndef IN_RC
2018 const PVM pVM = pPool->CTX_SUFF(pVM);
2019#endif
2020 /*
2021 * Look up the GCPhys in the hash.
2022 */
2023 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2024 Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2025 if (i != NIL_PGMPOOL_IDX)
2026 {
2027 do
2028 {
2029 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2030 Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2031 if (pPage->GCPhys == GCPhys)
2032 {
2033 if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2034 && (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
2035 {
2036 /* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2037 * doesn't flush it in case there are no more free use records.
2038 */
2039 pgmPoolCacheUsed(pPool, pPage);
2040
2041 int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2042 if (RT_SUCCESS(rc))
2043 {
2044 Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2045 *ppPage = pPage;
2046 if (pPage->cModifications)
2047 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2048 STAM_COUNTER_INC(&pPool->StatCacheHits);
2049 return VINF_PGM_CACHED_PAGE;
2050 }
2051 return rc;
2052 }
2053
2054 if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2055 {
2056 /*
2057 * The kind is different. In some cases we should now flush the page
2058 * as it has been reused, but in most cases this is normal remapping
2059 * of PDs as PT or big pages using the GCPhys field in a slightly
2060 * different way than the other kinds.
2061 */
2062 if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2063 {
2064 STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2065 pgmPoolFlushPage(pPool, pPage);
2066 break;
2067 }
2068 }
2069 }
2070
2071 /* next */
2072 i = pPage->iNext;
2073 } while (i != NIL_PGMPOOL_IDX);
2074 }
2075
2076 Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2077 STAM_COUNTER_INC(&pPool->StatCacheMisses);
2078 return VERR_FILE_NOT_FOUND;
2079}
2080
2081
2082/**
2083 * Inserts a page into the cache.
2084 *
2085 * @param pPool The pool.
2086 * @param pPage The cached page.
2087 * @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2088 */
2089static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2090{
2091 /*
2092 * Insert into the GCPhys hash if the page is fit for that.
2093 */
2094 Assert(!pPage->fCached);
2095 if (fCanBeCached)
2096 {
2097 pPage->fCached = true;
2098 pgmPoolHashInsert(pPool, pPage);
2099 Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2100 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2101 STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2102 }
2103 else
2104 {
2105 Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2106 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2107 STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2108 }
2109
2110 /*
2111 * Insert at the head of the age list.
2112 */
2113 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2114 pPage->iAgeNext = pPool->iAgeHead;
2115 if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2116 pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2117 else
2118 pPool->iAgeTail = pPage->idx;
2119 pPool->iAgeHead = pPage->idx;
2120}
2121
2122
2123/**
2124 * Flushes a cached page.
2125 *
2126 * @param pPool The pool.
2127 * @param pPage The cached page.
2128 */
2129static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2130{
2131 Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2132
2133 /*
2134 * Remove the page from the hash.
2135 */
2136 if (pPage->fCached)
2137 {
2138 pPage->fCached = false;
2139 pgmPoolHashRemove(pPool, pPage);
2140 }
2141 else
2142 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2143
2144 /*
2145 * Remove it from the age list.
2146 */
2147 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2148 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2149 else
2150 pPool->iAgeTail = pPage->iAgePrev;
2151 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2152 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2153 else
2154 pPool->iAgeHead = pPage->iAgeNext;
2155 pPage->iAgeNext = NIL_PGMPOOL_IDX;
2156 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2157}
2158
2159#endif /* PGMPOOL_WITH_CACHE */
2160#ifdef PGMPOOL_WITH_MONITORING
2161
2162/**
2163 * Looks for pages sharing the monitor.
2164 *
2165 * @returns Pointer to the head page.
2166 * @returns NULL if not found.
2167 * @param pPool The Pool
2168 * @param pNewPage The page which is going to be monitored.
2169 */
2170static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2171{
2172#ifdef PGMPOOL_WITH_CACHE
2173 /*
2174 * Look up the GCPhys in the hash.
2175 */
2176 RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2177 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2178 if (i == NIL_PGMPOOL_IDX)
2179 return NULL;
2180 do
2181 {
2182 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2183 if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2184 && pPage != pNewPage)
2185 {
2186 switch (pPage->enmKind)
2187 {
2188 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2189 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2190 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2191 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2192 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2193 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2194 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2195 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2196 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2197 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2198 case PGMPOOLKIND_64BIT_PML4:
2199 case PGMPOOLKIND_32BIT_PD:
2200 case PGMPOOLKIND_PAE_PDPT:
2201 {
2202 /* find the head */
2203 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2204 {
2205 Assert(pPage->iMonitoredPrev != pPage->idx);
2206 pPage = &pPool->aPages[pPage->iMonitoredPrev];
2207 }
2208 return pPage;
2209 }
2210
2211 /* ignore, no monitoring. */
2212 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2213 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2214 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2215 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2216 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2217 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2218 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2219 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2220 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2221 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2222 case PGMPOOLKIND_ROOT_NESTED:
2223 case PGMPOOLKIND_PAE_PD_PHYS:
2224 case PGMPOOLKIND_PAE_PDPT_PHYS:
2225 case PGMPOOLKIND_32BIT_PD_PHYS:
2226 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2227 break;
2228 default:
2229 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2230 }
2231 }
2232
2233 /* next */
2234 i = pPage->iNext;
2235 } while (i != NIL_PGMPOOL_IDX);
2236#endif
2237 return NULL;
2238}
2239
2240
2241/**
2242 * Enabled write monitoring of a guest page.
2243 *
2244 * @returns VBox status code.
2245 * @retval VINF_SUCCESS on success.
2246 * @param pPool The pool.
2247 * @param pPage The cached page.
2248 */
2249static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2250{
2251 LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
2252
2253 /*
2254 * Filter out the relevant kinds.
2255 */
2256 switch (pPage->enmKind)
2257 {
2258 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2259 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2260 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2261 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2262 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2263 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2264 case PGMPOOLKIND_64BIT_PML4:
2265 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2266 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2267 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2268 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2269 case PGMPOOLKIND_32BIT_PD:
2270 case PGMPOOLKIND_PAE_PDPT:
2271 break;
2272
2273 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2274 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2275 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2276 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2277 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2278 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2279 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2280 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2281 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2282 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2283 case PGMPOOLKIND_ROOT_NESTED:
2284 /* Nothing to monitor here. */
2285 return VINF_SUCCESS;
2286
2287 case PGMPOOLKIND_32BIT_PD_PHYS:
2288 case PGMPOOLKIND_PAE_PDPT_PHYS:
2289 case PGMPOOLKIND_PAE_PD_PHYS:
2290 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2291 /* Nothing to monitor here. */
2292 return VINF_SUCCESS;
2293#ifdef PGMPOOL_WITH_MIXED_PT_CR3
2294 break;
2295#else
2296 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2297#endif
2298 default:
2299 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2300 }
2301
2302 /*
2303 * Install handler.
2304 */
2305 int rc;
2306 PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2307 if (pPageHead)
2308 {
2309 Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2310 Assert(pPageHead->iMonitoredPrev != pPage->idx);
2311
2312#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2313 if (pPageHead->fDirty)
2314 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirty, false /* do not remove */);
2315#endif
2316
2317 pPage->iMonitoredPrev = pPageHead->idx;
2318 pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2319 if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2320 pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2321 pPageHead->iMonitoredNext = pPage->idx;
2322 rc = VINF_SUCCESS;
2323 }
2324 else
2325 {
2326 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2327 PVM pVM = pPool->CTX_SUFF(pVM);
2328 const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2329 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2330 GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
2331 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2332 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2333 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2334 pPool->pszAccessHandler);
2335 /** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2336 * the heap size should suffice. */
2337 AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2338 Assert(!(VMMGetCpu(pVM)->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
2339 }
2340 pPage->fMonitored = true;
2341 return rc;
2342}
2343
2344
2345/**
2346 * Disables write monitoring of a guest page.
2347 *
2348 * @returns VBox status code.
2349 * @retval VINF_SUCCESS on success.
2350 * @param pPool The pool.
2351 * @param pPage The cached page.
2352 */
2353static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2354{
2355 /*
2356 * Filter out the relevant kinds.
2357 */
2358 switch (pPage->enmKind)
2359 {
2360 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2361 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2362 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2363 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2364 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2365 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2366 case PGMPOOLKIND_64BIT_PML4:
2367 case PGMPOOLKIND_32BIT_PD:
2368 case PGMPOOLKIND_PAE_PDPT:
2369 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2370 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2371 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2372 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2373 break;
2374
2375 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2376 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2377 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2378 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2379 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2380 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2381 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2382 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2383 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2384 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2385 case PGMPOOLKIND_ROOT_NESTED:
2386 case PGMPOOLKIND_PAE_PD_PHYS:
2387 case PGMPOOLKIND_PAE_PDPT_PHYS:
2388 case PGMPOOLKIND_32BIT_PD_PHYS:
2389 /* Nothing to monitor here. */
2390 return VINF_SUCCESS;
2391
2392#ifdef PGMPOOL_WITH_MIXED_PT_CR3
2393 break;
2394#endif
2395 default:
2396 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2397 }
2398
2399 /*
2400 * Remove the page from the monitored list or uninstall it if last.
2401 */
2402 const PVM pVM = pPool->CTX_SUFF(pVM);
2403 int rc;
2404 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2405 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2406 {
2407 if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2408 {
2409 PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2410 pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2411 rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
2412 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2413 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2414 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2415 pPool->pszAccessHandler);
2416 AssertFatalRCSuccess(rc);
2417 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2418 }
2419 else
2420 {
2421 pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2422 if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2423 {
2424 pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2425 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2426 }
2427 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2428 rc = VINF_SUCCESS;
2429 }
2430 }
2431 else
2432 {
2433 rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
2434 AssertFatalRC(rc);
2435#ifdef VBOX_STRICT
2436 PVMCPU pVCpu = VMMGetCpu(pVM);
2437#endif
2438 AssertMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2439 ("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2440 }
2441 pPage->fMonitored = false;
2442
2443 /*
2444 * Remove it from the list of modified pages (if in it).
2445 */
2446 pgmPoolMonitorModifiedRemove(pPool, pPage);
2447
2448 return rc;
2449}
2450
2451
2452/**
2453 * Inserts the page into the list of modified pages.
2454 *
2455 * @param pPool The pool.
2456 * @param pPage The page.
2457 */
2458void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2459{
2460 Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2461 AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2462 && pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2463 && pPool->iModifiedHead != pPage->idx,
2464 ("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2465 pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2466 pPool->iModifiedHead, pPool->cModifiedPages));
2467
2468 pPage->iModifiedNext = pPool->iModifiedHead;
2469 if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2470 pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2471 pPool->iModifiedHead = pPage->idx;
2472 pPool->cModifiedPages++;
2473#ifdef VBOX_WITH_STATISTICS
2474 if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2475 pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2476#endif
2477}
2478
2479
2480/**
2481 * Removes the page from the list of modified pages and resets the
2482 * moficiation counter.
2483 *
2484 * @param pPool The pool.
2485 * @param pPage The page which is believed to be in the list of modified pages.
2486 */
2487static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2488{
2489 Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2490 if (pPool->iModifiedHead == pPage->idx)
2491 {
2492 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2493 pPool->iModifiedHead = pPage->iModifiedNext;
2494 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2495 {
2496 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2497 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2498 }
2499 pPool->cModifiedPages--;
2500 }
2501 else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2502 {
2503 pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2504 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2505 {
2506 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2507 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2508 }
2509 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2510 pPool->cModifiedPages--;
2511 }
2512 else
2513 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2514 pPage->cModifications = 0;
2515}
2516
2517
2518/**
2519 * Zaps the list of modified pages, resetting their modification counters in the process.
2520 *
2521 * @param pVM The VM handle.
2522 */
2523static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2524{
2525 pgmLock(pVM);
2526 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2527 LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2528
2529 unsigned cPages = 0; NOREF(cPages);
2530
2531#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2532 pgmPoolResetDirtyPages(pVM);
2533#endif
2534
2535 uint16_t idx = pPool->iModifiedHead;
2536 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2537 while (idx != NIL_PGMPOOL_IDX)
2538 {
2539 PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2540 idx = pPage->iModifiedNext;
2541 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2542 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2543 pPage->cModifications = 0;
2544 Assert(++cPages);
2545 }
2546 AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2547 pPool->cModifiedPages = 0;
2548 pgmUnlock(pVM);
2549}
2550
2551
2552/**
2553 * Handle SyncCR3 pool tasks
2554 *
2555 * @returns VBox status code.
2556 * @retval VINF_SUCCESS if successfully added.
2557 * @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2558 * @param pVCpu The VMCPU handle.
2559 * @remark Should only be used when monitoring is available, thus placed in
2560 * the PGMPOOL_WITH_MONITORING #ifdef.
2561 */
2562int pgmPoolSyncCR3(PVMCPU pVCpu)
2563{
2564 PVM pVM = pVCpu->CTX_SUFF(pVM);
2565 LogFlow(("pgmPoolSyncCR3\n"));
2566
2567 /*
2568 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2569 * Occasionally we will have to clear all the shadow page tables because we wanted
2570 * to monitor a page which was mapped by too many shadowed page tables. This operation
2571 * sometimes refered to as a 'lightweight flush'.
2572 */
2573# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2574 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2575 pgmR3PoolClearAll(pVM);
2576# else /* !IN_RING3 */
2577 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2578 {
2579 LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2580 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2581 return VINF_PGM_SYNC_CR3;
2582 }
2583# endif /* !IN_RING3 */
2584 else
2585 pgmPoolMonitorModifiedClearAll(pVM);
2586
2587 return VINF_SUCCESS;
2588}
2589
2590#endif /* PGMPOOL_WITH_MONITORING */
2591#ifdef PGMPOOL_WITH_USER_TRACKING
2592
2593/**
2594 * Frees up at least one user entry.
2595 *
2596 * @returns VBox status code.
2597 * @retval VINF_SUCCESS if successfully added.
2598 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2599 * @param pPool The pool.
2600 * @param iUser The user index.
2601 */
2602static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2603{
2604 STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2605#ifdef PGMPOOL_WITH_CACHE
2606 /*
2607 * Just free cached pages in a braindead fashion.
2608 */
2609 /** @todo walk the age list backwards and free the first with usage. */
2610 int rc = VINF_SUCCESS;
2611 do
2612 {
2613 int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2614 if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2615 rc = rc2;
2616 } while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2617 return rc;
2618#else
2619 /*
2620 * Lazy approach.
2621 */
2622 /* @todo This path no longer works (CR3 root pages will be flushed)!! */
2623 AssertCompileFailed();
2624 Assert(!CPUMIsGuestInLongMode(pVM));
2625 pgmPoolFlushAllInt(pPool);
2626 return VERR_PGM_POOL_FLUSHED;
2627#endif
2628}
2629
2630
2631/**
2632 * Inserts a page into the cache.
2633 *
2634 * This will create user node for the page, insert it into the GCPhys
2635 * hash, and insert it into the age list.
2636 *
2637 * @returns VBox status code.
2638 * @retval VINF_SUCCESS if successfully added.
2639 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2640 * @param pPool The pool.
2641 * @param pPage The cached page.
2642 * @param GCPhys The GC physical address of the page we're gonna shadow.
2643 * @param iUser The user index.
2644 * @param iUserTable The user table index.
2645 */
2646DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2647{
2648 int rc = VINF_SUCCESS;
2649 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2650
2651 LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2652
2653#ifdef VBOX_STRICT
2654 /*
2655 * Check that the entry doesn't already exists.
2656 */
2657 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2658 {
2659 uint16_t i = pPage->iUserHead;
2660 do
2661 {
2662 Assert(i < pPool->cMaxUsers);
2663 AssertMsg(paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2664 i = paUsers[i].iNext;
2665 } while (i != NIL_PGMPOOL_USER_INDEX);
2666 }
2667#endif
2668
2669 /*
2670 * Find free a user node.
2671 */
2672 uint16_t i = pPool->iUserFreeHead;
2673 if (i == NIL_PGMPOOL_USER_INDEX)
2674 {
2675 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2676 if (RT_FAILURE(rc))
2677 return rc;
2678 i = pPool->iUserFreeHead;
2679 }
2680
2681 /*
2682 * Unlink the user node from the free list,
2683 * initialize and insert it into the user list.
2684 */
2685 pPool->iUserFreeHead = paUsers[i].iNext;
2686 paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2687 paUsers[i].iUser = iUser;
2688 paUsers[i].iUserTable = iUserTable;
2689 pPage->iUserHead = i;
2690
2691 /*
2692 * Insert into cache and enable monitoring of the guest page if enabled.
2693 *
2694 * Until we implement caching of all levels, including the CR3 one, we'll
2695 * have to make sure we don't try monitor & cache any recursive reuse of
2696 * a monitored CR3 page. Because all windows versions are doing this we'll
2697 * have to be able to do combined access monitoring, CR3 + PT and
2698 * PD + PT (guest PAE).
2699 *
2700 * Update:
2701 * We're now cooperating with the CR3 monitor if an uncachable page is found.
2702 */
2703#if defined(PGMPOOL_WITH_MONITORING) || defined(PGMPOOL_WITH_CACHE)
2704# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2705 const bool fCanBeMonitored = true;
2706# else
2707 bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2708 || (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2709 || pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2710# endif
2711# ifdef PGMPOOL_WITH_CACHE
2712 pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2713# endif
2714 if (fCanBeMonitored)
2715 {
2716# ifdef PGMPOOL_WITH_MONITORING
2717 rc = pgmPoolMonitorInsert(pPool, pPage);
2718 AssertRC(rc);
2719 }
2720# endif
2721#endif /* PGMPOOL_WITH_MONITORING */
2722 return rc;
2723}
2724
2725
2726# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2727/**
2728 * Adds a user reference to a page.
2729 *
2730 * This will move the page to the head of the
2731 *
2732 * @returns VBox status code.
2733 * @retval VINF_SUCCESS if successfully added.
2734 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2735 * @param pPool The pool.
2736 * @param pPage The cached page.
2737 * @param iUser The user index.
2738 * @param iUserTable The user table.
2739 */
2740static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2741{
2742 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2743
2744 Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2745
2746# ifdef VBOX_STRICT
2747 /*
2748 * Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2749 */
2750 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2751 {
2752 uint16_t i = pPage->iUserHead;
2753 do
2754 {
2755 Assert(i < pPool->cMaxUsers);
2756 AssertMsg(iUser != PGMPOOL_IDX_PD || iUser != PGMPOOL_IDX_PDPT || iUser != PGMPOOL_IDX_NESTED_ROOT || iUser != PGMPOOL_IDX_AMD64_CR3 ||
2757 paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2758 i = paUsers[i].iNext;
2759 } while (i != NIL_PGMPOOL_USER_INDEX);
2760 }
2761# endif
2762
2763 /*
2764 * Allocate a user node.
2765 */
2766 uint16_t i = pPool->iUserFreeHead;
2767 if (i == NIL_PGMPOOL_USER_INDEX)
2768 {
2769 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2770 if (RT_FAILURE(rc))
2771 return rc;
2772 i = pPool->iUserFreeHead;
2773 }
2774 pPool->iUserFreeHead = paUsers[i].iNext;
2775
2776 /*
2777 * Initialize the user node and insert it.
2778 */
2779 paUsers[i].iNext = pPage->iUserHead;
2780 paUsers[i].iUser = iUser;
2781 paUsers[i].iUserTable = iUserTable;
2782 pPage->iUserHead = i;
2783
2784# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2785 if (pPage->fDirty)
2786 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirty, false /* do not remove */);
2787# endif
2788
2789# ifdef PGMPOOL_WITH_CACHE
2790 /*
2791 * Tell the cache to update its replacement stats for this page.
2792 */
2793 pgmPoolCacheUsed(pPool, pPage);
2794# endif
2795 return VINF_SUCCESS;
2796}
2797# endif /* PGMPOOL_WITH_CACHE */
2798
2799
2800/**
2801 * Frees a user record associated with a page.
2802 *
2803 * This does not clear the entry in the user table, it simply replaces the
2804 * user record to the chain of free records.
2805 *
2806 * @param pPool The pool.
2807 * @param HCPhys The HC physical address of the shadow page.
2808 * @param iUser The shadow page pool index of the user table.
2809 * @param iUserTable The index into the user table (shadowed).
2810 */
2811static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2812{
2813 /*
2814 * Unlink and free the specified user entry.
2815 */
2816 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2817
2818 Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2819 /* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2820 uint16_t i = pPage->iUserHead;
2821 if ( i != NIL_PGMPOOL_USER_INDEX
2822 && paUsers[i].iUser == iUser
2823 && paUsers[i].iUserTable == iUserTable)
2824 {
2825 pPage->iUserHead = paUsers[i].iNext;
2826
2827 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2828 paUsers[i].iNext = pPool->iUserFreeHead;
2829 pPool->iUserFreeHead = i;
2830 return;
2831 }
2832
2833 /* General: Linear search. */
2834 uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2835 while (i != NIL_PGMPOOL_USER_INDEX)
2836 {
2837 if ( paUsers[i].iUser == iUser
2838 && paUsers[i].iUserTable == iUserTable)
2839 {
2840 if (iPrev != NIL_PGMPOOL_USER_INDEX)
2841 paUsers[iPrev].iNext = paUsers[i].iNext;
2842 else
2843 pPage->iUserHead = paUsers[i].iNext;
2844
2845 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2846 paUsers[i].iNext = pPool->iUserFreeHead;
2847 pPool->iUserFreeHead = i;
2848 return;
2849 }
2850 iPrev = i;
2851 i = paUsers[i].iNext;
2852 }
2853
2854 /* Fatal: didn't find it */
2855 AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2856 iUser, iUserTable, pPage->GCPhys));
2857}
2858
2859
2860/**
2861 * Gets the entry size of a shadow table.
2862 *
2863 * @param enmKind The kind of page.
2864 *
2865 * @returns The size of the entry in bytes. That is, 4 or 8.
2866 * @returns If the kind is not for a table, an assertion is raised and 0 is
2867 * returned.
2868 */
2869DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2870{
2871 switch (enmKind)
2872 {
2873 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2874 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2875 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2876 case PGMPOOLKIND_32BIT_PD:
2877 case PGMPOOLKIND_32BIT_PD_PHYS:
2878 return 4;
2879
2880 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2881 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2882 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2883 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2884 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2885 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2886 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2887 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2888 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2889 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2890 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2891 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2892 case PGMPOOLKIND_64BIT_PML4:
2893 case PGMPOOLKIND_PAE_PDPT:
2894 case PGMPOOLKIND_ROOT_NESTED:
2895 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2896 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2897 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2898 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2899 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2900 case PGMPOOLKIND_PAE_PD_PHYS:
2901 case PGMPOOLKIND_PAE_PDPT_PHYS:
2902 return 8;
2903
2904 default:
2905 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2906 }
2907}
2908
2909
2910/**
2911 * Gets the entry size of a guest table.
2912 *
2913 * @param enmKind The kind of page.
2914 *
2915 * @returns The size of the entry in bytes. That is, 0, 4 or 8.
2916 * @returns If the kind is not for a table, an assertion is raised and 0 is
2917 * returned.
2918 */
2919DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2920{
2921 switch (enmKind)
2922 {
2923 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2924 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2925 case PGMPOOLKIND_32BIT_PD:
2926 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2927 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2928 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2929 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2930 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2931 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2932 return 4;
2933
2934 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2935 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2936 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2937 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2938 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2939 case PGMPOOLKIND_64BIT_PML4:
2940 case PGMPOOLKIND_PAE_PDPT:
2941 return 8;
2942
2943 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2944 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2945 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2946 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2947 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2948 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2949 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2950 case PGMPOOLKIND_ROOT_NESTED:
2951 case PGMPOOLKIND_PAE_PD_PHYS:
2952 case PGMPOOLKIND_PAE_PDPT_PHYS:
2953 case PGMPOOLKIND_32BIT_PD_PHYS:
2954 /** @todo can we return 0? (nobody is calling this...) */
2955 AssertFailed();
2956 return 0;
2957
2958 default:
2959 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2960 }
2961}
2962
2963#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2964
2965/**
2966 * Scans one shadow page table for mappings of a physical page.
2967 *
2968 * @returns true/false indicating removal of all relevant PTEs
2969 * @param pVM The VM handle.
2970 * @param pPhysPage The guest page in question.
2971 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
2972 * @param iShw The shadow page table.
2973 * @param cRefs The number of references made in that PT.
2974 * @param pfKeptPTEs Flag indicating removal of all relevant PTEs (out)
2975 */
2976static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
2977{
2978 LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
2979 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2980 bool bRet = false;
2981
2982 /*
2983 * Assert sanity.
2984 */
2985 Assert(cRefs == 1);
2986 AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2987 PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2988
2989 /*
2990 * Then, clear the actual mappings to the page in the shadow PT.
2991 */
2992 switch (pPage->enmKind)
2993 {
2994 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2995 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2996 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2997 {
2998 const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
2999 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3000 uint32_t u32AndMask, u32OrMask;
3001
3002 u32AndMask = 0;
3003 u32OrMask = 0;
3004
3005 if (!fFlushPTEs)
3006 {
3007 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3008 {
3009 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3010 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3011 u32OrMask = X86_PTE_RW;
3012 u32AndMask = UINT32_MAX;
3013 bRet = true;
3014 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3015 break;
3016
3017 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3018 u32OrMask = 0;
3019 u32AndMask = ~X86_PTE_RW;
3020 bRet = true;
3021 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3022 break;
3023 default:
3024 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3025 break;
3026 }
3027 }
3028 else
3029 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3030
3031 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3032 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3033 {
3034 X86PTE Pte;
3035
3036 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
3037 Pte.u = (pPT->a[i].u & u32AndMask) | u32OrMask;
3038 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3039 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3040
3041 ASMAtomicWriteSize(&pPT->a[i].u, Pte.u);
3042 cRefs--;
3043 if (!cRefs)
3044 return bRet;
3045 }
3046#ifdef LOG_ENABLED
3047 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3048 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3049 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3050 {
3051 Log(("i=%d cRefs=%d\n", i, cRefs--));
3052 }
3053#endif
3054 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3055 break;
3056 }
3057
3058 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3059 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3060 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3061 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3062 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3063 {
3064 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3065 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3066 uint64_t u64AndMask, u64OrMask;
3067
3068 u64OrMask = 0;
3069 u64AndMask = 0;
3070 if (!fFlushPTEs)
3071 {
3072 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3073 {
3074 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3075 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3076 u64OrMask = X86_PTE_RW;
3077 u64AndMask = UINT64_MAX;
3078 bRet = true;
3079 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3080 break;
3081
3082 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3083 u64OrMask = 0;
3084 u64AndMask = ~((uint64_t)X86_PTE_RW);
3085 bRet = true;
3086 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3087 break;
3088
3089 default:
3090 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3091 break;
3092 }
3093 }
3094 else
3095 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3096
3097 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3098 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3099 {
3100 X86PTEPAE Pte;
3101
3102 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3103 Pte.u = (pPT->a[i].u & u64AndMask) | u64OrMask;
3104 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3105 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3106
3107 ASMAtomicWriteSize(&pPT->a[i].u, Pte.u);
3108 cRefs--;
3109 if (!cRefs)
3110 return bRet;
3111 }
3112#ifdef LOG_ENABLED
3113 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3114 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3115 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3116 {
3117 Log(("i=%d cRefs=%d\n", i, cRefs--));
3118 }
3119#endif
3120 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
3121 break;
3122 }
3123
3124 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3125 {
3126 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3127 PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3128 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3129 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3130 {
3131 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3132 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3133 pPT->a[i].u = 0;
3134 cRefs--;
3135 if (!cRefs)
3136 return bRet;
3137 }
3138#ifdef LOG_ENABLED
3139 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3140 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3141 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3142 {
3143 Log(("i=%d cRefs=%d\n", i, cRefs--));
3144 }
3145#endif
3146 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3147 break;
3148 }
3149
3150 default:
3151 AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3152 }
3153 return bRet;
3154}
3155
3156
3157/**
3158 * Scans one shadow page table for mappings of a physical page.
3159 *
3160 * @param pVM The VM handle.
3161 * @param pPhysPage The guest page in question.
3162 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3163 * @param iShw The shadow page table.
3164 * @param cRefs The number of references made in that PT.
3165 */
3166static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
3167{
3168 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3169
3170 Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
3171 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3172 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, cRefs);
3173 if (!fKeptPTEs)
3174 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3175 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3176}
3177
3178
3179/**
3180 * Flushes a list of shadow page tables mapping the same physical page.
3181 *
3182 * @param pVM The VM handle.
3183 * @param pPhysPage The guest page in question.
3184 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3185 * @param iPhysExt The physical cross reference extent list to flush.
3186 */
3187static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3188{
3189 Assert(PGMIsLockOwner(pVM));
3190 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3191 bool fKeepList = false;
3192
3193 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3194 Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3195
3196 const uint16_t iPhysExtStart = iPhysExt;
3197 PPGMPOOLPHYSEXT pPhysExt;
3198 do
3199 {
3200 Assert(iPhysExt < pPool->cMaxPhysExts);
3201 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3202 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3203 {
3204 if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3205 {
3206 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], 1);
3207 if (!fKeptPTEs)
3208 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3209 else
3210 fKeepList = true;
3211 }
3212 }
3213 /* next */
3214 iPhysExt = pPhysExt->iNext;
3215 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3216
3217 if (!fKeepList)
3218 {
3219 /* insert the list into the free list and clear the ram range entry. */
3220 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3221 pPool->iPhysExtFreeHead = iPhysExtStart;
3222 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3223 }
3224
3225 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3226}
3227
3228#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3229
3230/**
3231 * Flushes all shadow page table mappings of the given guest page.
3232 *
3233 * This is typically called when the host page backing the guest one has been
3234 * replaced or when the page protection was changed due to an access handler.
3235 *
3236 * @returns VBox status code.
3237 * @retval VINF_SUCCESS if all references has been successfully cleared.
3238 * @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3239 * pool cleaning. FF and sync flags are set.
3240 *
3241 * @param pVM The VM handle.
3242 * @param pPhysPage The guest page in question.
3243 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3244 * @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3245 * flushed, it is NOT touched if this isn't necessary.
3246 * The caller MUST initialized this to @a false.
3247 */
3248int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3249{
3250 PVMCPU pVCpu = VMMGetCpu(pVM);
3251 pgmLock(pVM);
3252 int rc = VINF_SUCCESS;
3253#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3254 const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3255 if (u16)
3256 {
3257 /*
3258 * The zero page is currently screwing up the tracking and we'll
3259 * have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3260 * is defined, zero pages won't normally be mapped. Some kind of solution
3261 * will be needed for this problem of course, but it will have to wait...
3262 */
3263 if (PGM_PAGE_IS_ZERO(pPhysPage))
3264 rc = VINF_PGM_GCPHYS_ALIASED;
3265 else
3266 {
3267# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3268 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3269 pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3270 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3271# endif
3272
3273 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3274 pgmPoolTrackFlushGCPhysPT(pVM,
3275 pPhysPage,
3276 fFlushPTEs,
3277 PGMPOOL_TD_GET_IDX(u16),
3278 PGMPOOL_TD_GET_CREFS(u16));
3279 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3280 pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3281 else
3282 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3283 *pfFlushTLBs = true;
3284
3285# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3286 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3287# endif
3288 }
3289 }
3290
3291#elif defined(PGMPOOL_WITH_CACHE)
3292 if (PGM_PAGE_IS_ZERO(pPhysPage))
3293 rc = VINF_PGM_GCPHYS_ALIASED;
3294 else
3295 {
3296# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3297 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kills the pool otherwise. */
3298 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3299# endif
3300 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3301 if (rc == VINF_SUCCESS)
3302 *pfFlushTLBs = true;
3303 }
3304
3305# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3306 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3307# endif
3308
3309#else
3310 rc = VINF_PGM_GCPHYS_ALIASED;
3311#endif
3312
3313 if (rc == VINF_PGM_GCPHYS_ALIASED)
3314 {
3315 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3316 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3317 rc = VINF_PGM_SYNC_CR3;
3318 }
3319 pgmUnlock(pVM);
3320 return rc;
3321}
3322
3323
3324/**
3325 * Scans all shadow page tables for mappings of a physical page.
3326 *
3327 * This may be slow, but it's most likely more efficient than cleaning
3328 * out the entire page pool / cache.
3329 *
3330 * @returns VBox status code.
3331 * @retval VINF_SUCCESS if all references has been successfully cleared.
3332 * @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3333 * a page pool cleaning.
3334 *
3335 * @param pVM The VM handle.
3336 * @param pPhysPage The guest page in question.
3337 */
3338int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3339{
3340 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3341 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3342 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3343 pPool->cUsedPages, pPool->cPresent, pPhysPage));
3344
3345#if 1
3346 /*
3347 * There is a limit to what makes sense.
3348 */
3349 if (pPool->cPresent > 1024)
3350 {
3351 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3352 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3353 return VINF_PGM_GCPHYS_ALIASED;
3354 }
3355#endif
3356
3357 /*
3358 * Iterate all the pages until we've encountered all that in use.
3359 * This is simple but not quite optimal solution.
3360 */
3361 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3362 const uint32_t u32 = u64;
3363 unsigned cLeft = pPool->cUsedPages;
3364 unsigned iPage = pPool->cCurPages;
3365 while (--iPage >= PGMPOOL_IDX_FIRST)
3366 {
3367 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3368 if (pPage->GCPhys != NIL_RTGCPHYS)
3369 {
3370 switch (pPage->enmKind)
3371 {
3372 /*
3373 * We only care about shadow page tables.
3374 */
3375 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3376 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3377 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3378 {
3379 unsigned cPresent = pPage->cPresent;
3380 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3381 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3382 if (pPT->a[i].n.u1Present)
3383 {
3384 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3385 {
3386 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3387 pPT->a[i].u = 0;
3388 }
3389 if (!--cPresent)
3390 break;
3391 }
3392 break;
3393 }
3394
3395 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3396 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3397 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3398 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3399 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3400 {
3401 unsigned cPresent = pPage->cPresent;
3402 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3403 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3404 if (pPT->a[i].n.u1Present)
3405 {
3406 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3407 {
3408 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3409 pPT->a[i].u = 0;
3410 }
3411 if (!--cPresent)
3412 break;
3413 }
3414 break;
3415 }
3416 }
3417 if (!--cLeft)
3418 break;
3419 }
3420 }
3421
3422 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3423 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3424 return VINF_SUCCESS;
3425}
3426
3427
3428/**
3429 * Clears the user entry in a user table.
3430 *
3431 * This is used to remove all references to a page when flushing it.
3432 */
3433static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3434{
3435 Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3436 Assert(pUser->iUser < pPool->cCurPages);
3437 uint32_t iUserTable = pUser->iUserTable;
3438
3439 /*
3440 * Map the user page.
3441 */
3442 PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3443 union
3444 {
3445 uint64_t *pau64;
3446 uint32_t *pau32;
3447 } u;
3448 u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3449
3450 LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3451
3452 /* Safety precaution in case we change the paging for other modes too in the future. */
3453 Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
3454
3455#ifdef VBOX_STRICT
3456 /*
3457 * Some sanity checks.
3458 */
3459 switch (pUserPage->enmKind)
3460 {
3461 case PGMPOOLKIND_32BIT_PD:
3462 case PGMPOOLKIND_32BIT_PD_PHYS:
3463 Assert(iUserTable < X86_PG_ENTRIES);
3464 break;
3465 case PGMPOOLKIND_PAE_PDPT:
3466 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3467 case PGMPOOLKIND_PAE_PDPT_PHYS:
3468 Assert(iUserTable < 4);
3469 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3470 break;
3471 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3472 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3473 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3474 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3475 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3476 case PGMPOOLKIND_PAE_PD_PHYS:
3477 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3478 break;
3479 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3480 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3481 Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3482 break;
3483 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3484 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3485 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3486 break;
3487 case PGMPOOLKIND_64BIT_PML4:
3488 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3489 /* GCPhys >> PAGE_SHIFT is the index here */
3490 break;
3491 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3492 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3493 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3494 break;
3495
3496 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3497 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3498 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3499 break;
3500
3501 case PGMPOOLKIND_ROOT_NESTED:
3502 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3503 break;
3504
3505 default:
3506 AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3507 break;
3508 }
3509#endif /* VBOX_STRICT */
3510
3511 /*
3512 * Clear the entry in the user page.
3513 */
3514 switch (pUserPage->enmKind)
3515 {
3516 /* 32-bit entries */
3517 case PGMPOOLKIND_32BIT_PD:
3518 case PGMPOOLKIND_32BIT_PD_PHYS:
3519 u.pau32[iUserTable] = 0;
3520 break;
3521
3522 /* 64-bit entries */
3523 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3524 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3525 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3526 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3527 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3528#if defined(IN_RC)
3529 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
3530 * non-present PDPT will continue to cause page faults.
3531 */
3532 ASMReloadCR3();
3533#endif
3534 /* no break */
3535 case PGMPOOLKIND_PAE_PD_PHYS:
3536 case PGMPOOLKIND_PAE_PDPT_PHYS:
3537 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3538 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3539 case PGMPOOLKIND_64BIT_PML4:
3540 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3541 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3542 case PGMPOOLKIND_PAE_PDPT:
3543 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3544 case PGMPOOLKIND_ROOT_NESTED:
3545 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3546 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3547 u.pau64[iUserTable] = 0;
3548 break;
3549
3550 default:
3551 AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3552 }
3553}
3554
3555
3556/**
3557 * Clears all users of a page.
3558 */
3559static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3560{
3561 /*
3562 * Free all the user records.
3563 */
3564 LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3565
3566 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3567 uint16_t i = pPage->iUserHead;
3568 while (i != NIL_PGMPOOL_USER_INDEX)
3569 {
3570 /* Clear enter in user table. */
3571 pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3572
3573 /* Free it. */
3574 const uint16_t iNext = paUsers[i].iNext;
3575 paUsers[i].iUser = NIL_PGMPOOL_IDX;
3576 paUsers[i].iNext = pPool->iUserFreeHead;
3577 pPool->iUserFreeHead = i;
3578
3579 /* Next. */
3580 i = iNext;
3581 }
3582 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3583}
3584
3585#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3586
3587/**
3588 * Allocates a new physical cross reference extent.
3589 *
3590 * @returns Pointer to the allocated extent on success. NULL if we're out of them.
3591 * @param pVM The VM handle.
3592 * @param piPhysExt Where to store the phys ext index.
3593 */
3594PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3595{
3596 Assert(PGMIsLockOwner(pVM));
3597 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3598 uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3599 if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3600 {
3601 STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3602 return NULL;
3603 }
3604 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3605 pPool->iPhysExtFreeHead = pPhysExt->iNext;
3606 pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3607 *piPhysExt = iPhysExt;
3608 return pPhysExt;
3609}
3610
3611
3612/**
3613 * Frees a physical cross reference extent.
3614 *
3615 * @param pVM The VM handle.
3616 * @param iPhysExt The extent to free.
3617 */
3618void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3619{
3620 Assert(PGMIsLockOwner(pVM));
3621 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3622 Assert(iPhysExt < pPool->cMaxPhysExts);
3623 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3624 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3625 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3626 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3627 pPool->iPhysExtFreeHead = iPhysExt;
3628}
3629
3630
3631/**
3632 * Frees a physical cross reference extent.
3633 *
3634 * @param pVM The VM handle.
3635 * @param iPhysExt The extent to free.
3636 */
3637void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3638{
3639 Assert(PGMIsLockOwner(pVM));
3640 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3641
3642 const uint16_t iPhysExtStart = iPhysExt;
3643 PPGMPOOLPHYSEXT pPhysExt;
3644 do
3645 {
3646 Assert(iPhysExt < pPool->cMaxPhysExts);
3647 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3648 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3649 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3650
3651 /* next */
3652 iPhysExt = pPhysExt->iNext;
3653 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3654
3655 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3656 pPool->iPhysExtFreeHead = iPhysExtStart;
3657}
3658
3659
3660/**
3661 * Insert a reference into a list of physical cross reference extents.
3662 *
3663 * @returns The new tracking data for PGMPAGE.
3664 *
3665 * @param pVM The VM handle.
3666 * @param iPhysExt The physical extent index of the list head.
3667 * @param iShwPT The shadow page table index.
3668 *
3669 */
3670static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3671{
3672 Assert(PGMIsLockOwner(pVM));
3673 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3674 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3675
3676 /* special common case. */
3677 if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3678 {
3679 paPhysExts[iPhysExt].aidx[2] = iShwPT;
3680 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3681 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d}\n", iPhysExt, iShwPT));
3682 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3683 }
3684
3685 /* general treatment. */
3686 const uint16_t iPhysExtStart = iPhysExt;
3687 unsigned cMax = 15;
3688 for (;;)
3689 {
3690 Assert(iPhysExt < pPool->cMaxPhysExts);
3691 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3692 if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3693 {
3694 paPhysExts[iPhysExt].aidx[i] = iShwPT;
3695 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3696 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3697 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3698 }
3699 if (!--cMax)
3700 {
3701 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3702 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3703 LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3704 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3705 }
3706 }
3707
3708 /* add another extent to the list. */
3709 PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3710 if (!pNew)
3711 {
3712 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3713 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3714 LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3715 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3716 }
3717 pNew->iNext = iPhysExtStart;
3718 pNew->aidx[0] = iShwPT;
3719 LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3720 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3721}
3722
3723
3724/**
3725 * Add a reference to guest physical page where extents are in use.
3726 *
3727 * @returns The new tracking data for PGMPAGE.
3728 *
3729 * @param pVM The VM handle.
3730 * @param u16 The ram range flags (top 16-bits).
3731 * @param iShwPT The shadow page table index.
3732 */
3733uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3734{
3735 pgmLock(pVM);
3736 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3737 {
3738 /*
3739 * Convert to extent list.
3740 */
3741 Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3742 uint16_t iPhysExt;
3743 PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3744 if (pPhysExt)
3745 {
3746 LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3747 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3748 pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3749 pPhysExt->aidx[1] = iShwPT;
3750 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3751 }
3752 else
3753 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3754 }
3755 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3756 {
3757 /*
3758 * Insert into the extent list.
3759 */
3760 u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3761 }
3762 else
3763 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3764 pgmUnlock(pVM);
3765 return u16;
3766}
3767
3768
3769/**
3770 * Clear references to guest physical memory.
3771 *
3772 * @param pPool The pool.
3773 * @param pPage The page.
3774 * @param pPhysPage Pointer to the aPages entry in the ram range.
3775 */
3776void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3777{
3778 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3779 AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3780
3781 uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3782 if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3783 {
3784 PVM pVM = pPool->CTX_SUFF(pVM);
3785 pgmLock(pVM);
3786
3787 uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3788 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3789 do
3790 {
3791 Assert(iPhysExt < pPool->cMaxPhysExts);
3792
3793 /*
3794 * Look for the shadow page and check if it's all freed.
3795 */
3796 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3797 {
3798 if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3799 {
3800 paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3801
3802 for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3803 if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3804 {
3805 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3806 pgmUnlock(pVM);
3807 return;
3808 }
3809
3810 /* we can free the node. */
3811 const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3812 if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3813 && iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3814 {
3815 /* lonely node */
3816 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3817 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3818 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3819 }
3820 else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3821 {
3822 /* head */
3823 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3824 PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3825 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3826 }
3827 else
3828 {
3829 /* in list */
3830 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3831 paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3832 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3833 }
3834 iPhysExt = iPhysExtNext;
3835 pgmUnlock(pVM);
3836 return;
3837 }
3838 }
3839
3840 /* next */
3841 iPhysExtPrev = iPhysExt;
3842 iPhysExt = paPhysExts[iPhysExt].iNext;
3843 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3844
3845 pgmUnlock(pVM);
3846 AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3847 }
3848 else /* nothing to do */
3849 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3850}
3851
3852
3853/**
3854 * Clear references to guest physical memory.
3855 *
3856 * This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3857 * is assumed to be correct, so the linear search can be skipped and we can assert
3858 * at an earlier point.
3859 *
3860 * @param pPool The pool.
3861 * @param pPage The page.
3862 * @param HCPhys The host physical address corresponding to the guest page.
3863 * @param GCPhys The guest physical address corresponding to HCPhys.
3864 */
3865static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3866{
3867 /*
3868 * Walk range list.
3869 */
3870 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3871 while (pRam)
3872 {
3873 RTGCPHYS off = GCPhys - pRam->GCPhys;
3874 if (off < pRam->cb)
3875 {
3876 /* does it match? */
3877 const unsigned iPage = off >> PAGE_SHIFT;
3878 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3879#ifdef LOG_ENABLED
3880RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3881Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3882#endif
3883 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3884 {
3885 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3886 return;
3887 }
3888 break;
3889 }
3890 pRam = pRam->CTX_SUFF(pNext);
3891 }
3892 AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3893}
3894
3895
3896/**
3897 * Clear references to guest physical memory.
3898 *
3899 * @param pPool The pool.
3900 * @param pPage The page.
3901 * @param HCPhys The host physical address corresponding to the guest page.
3902 * @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3903 */
3904void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3905{
3906 Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3907
3908 /*
3909 * Walk range list.
3910 */
3911 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3912 while (pRam)
3913 {
3914 RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3915 if (off < pRam->cb)
3916 {
3917 /* does it match? */
3918 const unsigned iPage = off >> PAGE_SHIFT;
3919 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3920 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3921 {
3922 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3923 return;
3924 }
3925 break;
3926 }
3927 pRam = pRam->CTX_SUFF(pNext);
3928 }
3929
3930 /*
3931 * Damn, the hint didn't work. We'll have to do an expensive linear search.
3932 */
3933 STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3934 pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3935 while (pRam)
3936 {
3937 unsigned iPage = pRam->cb >> PAGE_SHIFT;
3938 while (iPage-- > 0)
3939 {
3940 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3941 {
3942 Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3943 HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3944 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3945 return;
3946 }
3947 }
3948 pRam = pRam->CTX_SUFF(pNext);
3949 }
3950
3951 AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3952}
3953
3954
3955/**
3956 * Clear references to guest physical memory in a 32-bit / 32-bit page table.
3957 *
3958 * @param pPool The pool.
3959 * @param pPage The page.
3960 * @param pShwPT The shadow page table (mapping of the page).
3961 * @param pGstPT The guest page table.
3962 */
3963DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3964{
3965 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3966 if (pShwPT->a[i].n.u1Present)
3967 {
3968 Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3969 i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3970 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3971 if (!--pPage->cPresent)
3972 break;
3973 }
3974}
3975
3976
3977/**
3978 * Clear references to guest physical memory in a PAE / 32-bit page table.
3979 *
3980 * @param pPool The pool.
3981 * @param pPage The page.
3982 * @param pShwPT The shadow page table (mapping of the page).
3983 * @param pGstPT The guest page table (just a half one).
3984 */
3985DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3986{
3987 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3988 if (pShwPT->a[i].n.u1Present)
3989 {
3990 Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3991 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3992 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3993 if (!--pPage->cPresent)
3994 break;
3995 }
3996}
3997
3998
3999/**
4000 * Clear references to guest physical memory in a PAE / PAE page table.
4001 *
4002 * @param pPool The pool.
4003 * @param pPage The page.
4004 * @param pShwPT The shadow page table (mapping of the page).
4005 * @param pGstPT The guest page table.
4006 */
4007DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
4008{
4009 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4010 if (pShwPT->a[i].n.u1Present)
4011 {
4012 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4013 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4014 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
4015 if (!--pPage->cPresent)
4016 break;
4017 }
4018}
4019
4020
4021/**
4022 * Clear references to guest physical memory in a 32-bit / 4MB page table.
4023 *
4024 * @param pPool The pool.
4025 * @param pPage The page.
4026 * @param pShwPT The shadow page table (mapping of the page).
4027 */
4028DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4029{
4030 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4031 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4032 if (pShwPT->a[i].n.u1Present)
4033 {
4034 Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4035 i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4036 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
4037 if (!--pPage->cPresent)
4038 break;
4039 }
4040}
4041
4042
4043/**
4044 * Clear references to guest physical memory in a PAE / 2/4MB page table.
4045 *
4046 * @param pPool The pool.
4047 * @param pPage The page.
4048 * @param pShwPT The shadow page table (mapping of the page).
4049 */
4050DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
4051{
4052 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4053 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4054 if (pShwPT->a[i].n.u1Present)
4055 {
4056 Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4057 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
4058 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
4059 if (!--pPage->cPresent)
4060 break;
4061 }
4062}
4063
4064
4065/**
4066 * Clear references to shadowed pages in an EPT page table.
4067 *
4068 * @param pPool The pool.
4069 * @param pPage The page.
4070 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4071 */
4072DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4073{
4074 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4075 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4076 if (pShwPT->a[i].n.u1Present)
4077 {
4078 Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4079 i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4080 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
4081 if (!--pPage->cPresent)
4082 break;
4083 }
4084}
4085
4086#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4087
4088
4089/**
4090 * Clear references to shadowed pages in a 32 bits page directory.
4091 *
4092 * @param pPool The pool.
4093 * @param pPage The page.
4094 * @param pShwPD The shadow page directory (mapping of the page).
4095 */
4096DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4097{
4098 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4099 {
4100 if ( pShwPD->a[i].n.u1Present
4101 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4102 )
4103 {
4104 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4105 if (pSubPage)
4106 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4107 else
4108 AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4109 }
4110 }
4111}
4112
4113/**
4114 * Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4115 *
4116 * @param pPool The pool.
4117 * @param pPage The page.
4118 * @param pShwPD The shadow page directory (mapping of the page).
4119 */
4120DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4121{
4122 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4123 {
4124 if ( pShwPD->a[i].n.u1Present
4125 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4126 )
4127 {
4128 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4129 if (pSubPage)
4130 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4131 else
4132 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4133 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4134 }
4135 }
4136}
4137
4138/**
4139 * Clear references to shadowed pages in a PAE page directory pointer table.
4140 *
4141 * @param pPool The pool.
4142 * @param pPage The page.
4143 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4144 */
4145DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4146{
4147 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4148 {
4149 if ( pShwPDPT->a[i].n.u1Present
4150 && !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4151 )
4152 {
4153 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4154 if (pSubPage)
4155 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4156 else
4157 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4158 }
4159 }
4160}
4161
4162
4163/**
4164 * Clear references to shadowed pages in a 64-bit page directory pointer table.
4165 *
4166 * @param pPool The pool.
4167 * @param pPage The page.
4168 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4169 */
4170DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4171{
4172 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4173 {
4174 Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
4175 if (pShwPDPT->a[i].n.u1Present)
4176 {
4177 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4178 if (pSubPage)
4179 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4180 else
4181 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4182 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4183 }
4184 }
4185}
4186
4187
4188/**
4189 * Clear references to shadowed pages in a 64-bit level 4 page table.
4190 *
4191 * @param pPool The pool.
4192 * @param pPage The page.
4193 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4194 */
4195DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4196{
4197 for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4198 {
4199 if (pShwPML4->a[i].n.u1Present)
4200 {
4201 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4202 if (pSubPage)
4203 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4204 else
4205 AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4206 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4207 }
4208 }
4209}
4210
4211
4212/**
4213 * Clear references to shadowed pages in an EPT page directory.
4214 *
4215 * @param pPool The pool.
4216 * @param pPage The page.
4217 * @param pShwPD The shadow page directory (mapping of the page).
4218 */
4219DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4220{
4221 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4222 {
4223 if (pShwPD->a[i].n.u1Present)
4224 {
4225 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4226 if (pSubPage)
4227 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4228 else
4229 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4230 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4231 }
4232 }
4233}
4234
4235
4236/**
4237 * Clear references to shadowed pages in an EPT page directory pointer table.
4238 *
4239 * @param pPool The pool.
4240 * @param pPage The page.
4241 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4242 */
4243DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4244{
4245 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4246 {
4247 if (pShwPDPT->a[i].n.u1Present)
4248 {
4249 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4250 if (pSubPage)
4251 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4252 else
4253 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4254 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4255 }
4256 }
4257}
4258
4259
4260/**
4261 * Clears all references made by this page.
4262 *
4263 * This includes other shadow pages and GC physical addresses.
4264 *
4265 * @param pPool The pool.
4266 * @param pPage The page.
4267 */
4268static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4269{
4270 /*
4271 * Map the shadow page and take action according to the page kind.
4272 */
4273 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
4274 switch (pPage->enmKind)
4275 {
4276#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4277 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4278 {
4279 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4280 void *pvGst;
4281 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4282 pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4283 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4284 break;
4285 }
4286
4287 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4288 {
4289 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4290 void *pvGst;
4291 int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4292 pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
4293 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4294 break;
4295 }
4296
4297 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4298 {
4299 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4300 void *pvGst;
4301 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4302 pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
4303 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4304 break;
4305 }
4306
4307 case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4308 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4309 {
4310 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4311 pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4312 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4313 break;
4314 }
4315
4316 case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4317 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4318 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4319 {
4320 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4321 pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
4322 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4323 break;
4324 }
4325
4326#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
4327 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4328 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4329 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4330 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4331 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4332 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4333 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4334 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4335 break;
4336#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
4337
4338 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4339 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4340 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4341 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4342 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4343 case PGMPOOLKIND_PAE_PD_PHYS:
4344 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4345 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4346 pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4347 break;
4348
4349 case PGMPOOLKIND_32BIT_PD_PHYS:
4350 case PGMPOOLKIND_32BIT_PD:
4351 pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4352 break;
4353
4354 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4355 case PGMPOOLKIND_PAE_PDPT:
4356 case PGMPOOLKIND_PAE_PDPT_PHYS:
4357 pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4358 break;
4359
4360 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4361 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4362 pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4363 break;
4364
4365 case PGMPOOLKIND_64BIT_PML4:
4366 pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4367 break;
4368
4369 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4370 pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4371 break;
4372
4373 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4374 pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4375 break;
4376
4377 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4378 pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4379 break;
4380
4381 default:
4382 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4383 }
4384
4385 /* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4386 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4387 ASMMemZeroPage(pvShw);
4388 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4389 pPage->fZeroed = true;
4390 PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
4391}
4392#endif /* PGMPOOL_WITH_USER_TRACKING */
4393
4394/**
4395 * Flushes a pool page.
4396 *
4397 * This moves the page to the free list after removing all user references to it.
4398 *
4399 * @returns VBox status code.
4400 * @retval VINF_SUCCESS on success.
4401 * @param pPool The pool.
4402 * @param HCPhys The HC physical address of the shadow page.
4403 */
4404int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4405{
4406 PVM pVM = pPool->CTX_SUFF(pVM);
4407
4408 int rc = VINF_SUCCESS;
4409 STAM_PROFILE_START(&pPool->StatFlushPage, f);
4410 LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4411 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4412
4413 /*
4414 * Quietly reject any attempts at flushing any of the special root pages.
4415 */
4416 if (pPage->idx < PGMPOOL_IDX_FIRST)
4417 {
4418 AssertFailed(); /* can no longer happen */
4419 Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4420 return VINF_SUCCESS;
4421 }
4422
4423 pgmLock(pVM);
4424
4425 /*
4426 * Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4427 */
4428 if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4429 {
4430 AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4431 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4432 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4433 || pPage->enmKind == PGMPOOLKIND_32BIT_PD
4434 || pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4435 || pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4436 || pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4437 || pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4438 || pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4439 ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4440 Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4441 pgmUnlock(pVM);
4442 return VINF_SUCCESS;
4443 }
4444
4445#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4446 /* Start a subset so we won't run out of mapping space. */
4447 PVMCPU pVCpu = VMMGetCpu(pVM);
4448 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4449#endif
4450
4451 /*
4452 * Mark the page as being in need of an ASMMemZeroPage().
4453 */
4454 pPage->fZeroed = false;
4455
4456#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4457 if (pPage->fDirty)
4458 pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirty, false /* do not remove */);
4459#endif
4460
4461#ifdef PGMPOOL_WITH_USER_TRACKING
4462 /*
4463 * Clear the page.
4464 */
4465 pgmPoolTrackClearPageUsers(pPool, pPage);
4466 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4467 pgmPoolTrackDeref(pPool, pPage);
4468 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4469#endif
4470
4471#ifdef PGMPOOL_WITH_CACHE
4472 /*
4473 * Flush it from the cache.
4474 */
4475 pgmPoolCacheFlushPage(pPool, pPage);
4476#endif /* PGMPOOL_WITH_CACHE */
4477
4478#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4479 /* Heavy stuff done. */
4480 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4481#endif
4482
4483#ifdef PGMPOOL_WITH_MONITORING
4484 /*
4485 * Deregistering the monitoring.
4486 */
4487 if (pPage->fMonitored)
4488 rc = pgmPoolMonitorFlush(pPool, pPage);
4489#endif
4490
4491 /*
4492 * Free the page.
4493 */
4494 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4495 pPage->iNext = pPool->iFreeHead;
4496 pPool->iFreeHead = pPage->idx;
4497 pPage->enmKind = PGMPOOLKIND_FREE;
4498 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4499 pPage->GCPhys = NIL_RTGCPHYS;
4500 pPage->fReusedFlushPending = false;
4501
4502 pPool->cUsedPages--;
4503 pgmUnlock(pVM);
4504 STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4505 return rc;
4506}
4507
4508
4509/**
4510 * Frees a usage of a pool page.
4511 *
4512 * The caller is responsible to updating the user table so that it no longer
4513 * references the shadow page.
4514 *
4515 * @param pPool The pool.
4516 * @param HCPhys The HC physical address of the shadow page.
4517 * @param iUser The shadow page pool index of the user table.
4518 * @param iUserTable The index into the user table (shadowed).
4519 */
4520void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4521{
4522 PVM pVM = pPool->CTX_SUFF(pVM);
4523
4524 STAM_PROFILE_START(&pPool->StatFree, a);
4525 LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4526 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4527 Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4528 pgmLock(pVM);
4529#ifdef PGMPOOL_WITH_USER_TRACKING
4530 pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4531#endif
4532#ifdef PGMPOOL_WITH_CACHE
4533 if (!pPage->fCached)
4534#endif
4535 pgmPoolFlushPage(pPool, pPage);
4536 pgmUnlock(pVM);
4537 STAM_PROFILE_STOP(&pPool->StatFree, a);
4538}
4539
4540
4541/**
4542 * Makes one or more free page free.
4543 *
4544 * @returns VBox status code.
4545 * @retval VINF_SUCCESS on success.
4546 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4547 *
4548 * @param pPool The pool.
4549 * @param enmKind Page table kind
4550 * @param iUser The user of the page.
4551 */
4552static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4553{
4554 PVM pVM = pPool->CTX_SUFF(pVM);
4555
4556 LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4557
4558 /*
4559 * If the pool isn't full grown yet, expand it.
4560 */
4561 if ( pPool->cCurPages < pPool->cMaxPages
4562#if defined(IN_RC)
4563 /* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4564 && enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4565 && (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD || enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4566#endif
4567 )
4568 {
4569 STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4570#ifdef IN_RING3
4571 int rc = PGMR3PoolGrow(pVM);
4572#else
4573 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4574#endif
4575 if (RT_FAILURE(rc))
4576 return rc;
4577 STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4578 if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4579 return VINF_SUCCESS;
4580 }
4581
4582#ifdef PGMPOOL_WITH_CACHE
4583 /*
4584 * Free one cached page.
4585 */
4586 return pgmPoolCacheFreeOne(pPool, iUser);
4587#else
4588 /*
4589 * Flush the pool.
4590 *
4591 * If we have tracking enabled, it should be possible to come up with
4592 * a cheap replacement strategy...
4593 */
4594 /* @todo This path no longer works (CR3 root pages will be flushed)!! */
4595 AssertCompileFailed();
4596 Assert(!CPUMIsGuestInLongMode(pVM));
4597 pgmPoolFlushAllInt(pPool);
4598 return VERR_PGM_POOL_FLUSHED;
4599#endif
4600}
4601
4602/**
4603 * Allocates a page from the pool.
4604 *
4605 * This page may actually be a cached page and not in need of any processing
4606 * on the callers part.
4607 *
4608 * @returns VBox status code.
4609 * @retval VINF_SUCCESS if a NEW page was allocated.
4610 * @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4611 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4612 * @param pVM The VM handle.
4613 * @param GCPhys The GC physical address of the page we're gonna shadow.
4614 * For 4MB and 2MB PD entries, it's the first address the
4615 * shadow PT is covering.
4616 * @param enmKind The kind of mapping.
4617 * @param enmAccess Access type for the mapping (only relevant for big pages)
4618 * @param iUser The shadow page pool index of the user table.
4619 * @param iUserTable The index into the user table (shadowed).
4620 * @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4621 * @param fLockPage Lock the page
4622 */
4623int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage)
4624{
4625 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4626 STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4627 LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4628 *ppPage = NULL;
4629 /** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4630 * (TRPMR3SyncIDT) because of FF priority. Try fix that?
4631 * Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4632
4633 pgmLock(pVM);
4634
4635#ifdef PGMPOOL_WITH_CACHE
4636 if (pPool->fCacheEnabled)
4637 {
4638 int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4639 if (RT_SUCCESS(rc2))
4640 {
4641 if (fLockPage)
4642 pgmPoolLockPage(pPool, *ppPage);
4643 pgmUnlock(pVM);
4644 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4645 LogFlow(("pgmPoolAlloc: cached returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, *ppPage, (*ppPage)->Core.Key, (*ppPage)->idx));
4646 return rc2;
4647 }
4648 }
4649#endif
4650
4651 /*
4652 * Allocate a new one.
4653 */
4654 int rc = VINF_SUCCESS;
4655 uint16_t iNew = pPool->iFreeHead;
4656 if (iNew == NIL_PGMPOOL_IDX)
4657 {
4658 rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4659 if (RT_FAILURE(rc))
4660 {
4661 pgmUnlock(pVM);
4662 Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4663 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4664 return rc;
4665 }
4666 iNew = pPool->iFreeHead;
4667 AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4668 }
4669
4670 /* unlink the free head */
4671 PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4672 pPool->iFreeHead = pPage->iNext;
4673 pPage->iNext = NIL_PGMPOOL_IDX;
4674
4675 /*
4676 * Initialize it.
4677 */
4678 pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4679 pPage->enmKind = enmKind;
4680 pPage->enmAccess = enmAccess;
4681 pPage->GCPhys = GCPhys;
4682 pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4683 pPage->fMonitored = false;
4684 pPage->fCached = false;
4685#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4686 pPage->fDirty = false;
4687#endif
4688 pPage->fReusedFlushPending = false;
4689#ifdef PGMPOOL_WITH_MONITORING
4690 pPage->cModifications = 0;
4691 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4692 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4693#else
4694 pPage->fCR3Mix = false;
4695#endif
4696#ifdef PGMPOOL_WITH_USER_TRACKING
4697 pPage->cPresent = 0;
4698 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
4699 pPage->pvLastAccessHandlerFault = 0;
4700 pPage->cLastAccessHandlerCount = 0;
4701 pPage->pvLastAccessHandlerRip = 0;
4702
4703 /*
4704 * Insert into the tracking and cache. If this fails, free the page.
4705 */
4706 int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4707 if (RT_FAILURE(rc3))
4708 {
4709 pPool->cUsedPages--;
4710 pPage->enmKind = PGMPOOLKIND_FREE;
4711 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4712 pPage->GCPhys = NIL_RTGCPHYS;
4713 pPage->iNext = pPool->iFreeHead;
4714 pPool->iFreeHead = pPage->idx;
4715 pgmUnlock(pVM);
4716 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4717 Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4718 return rc3;
4719 }
4720#endif /* PGMPOOL_WITH_USER_TRACKING */
4721
4722 /*
4723 * Commit the allocation, clear the page and return.
4724 */
4725#ifdef VBOX_WITH_STATISTICS
4726 if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4727 pPool->cUsedPagesHigh = pPool->cUsedPages;
4728#endif
4729
4730 if (!pPage->fZeroed)
4731 {
4732 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4733 void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4734 ASMMemZeroPage(pv);
4735 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4736 }
4737
4738 *ppPage = pPage;
4739 if (fLockPage)
4740 pgmPoolLockPage(pPool, pPage);
4741 pgmUnlock(pVM);
4742 LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4743 rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4744 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4745 return rc;
4746}
4747
4748
4749/**
4750 * Frees a usage of a pool page.
4751 *
4752 * @param pVM The VM handle.
4753 * @param HCPhys The HC physical address of the shadow page.
4754 * @param iUser The shadow page pool index of the user table.
4755 * @param iUserTable The index into the user table (shadowed).
4756 */
4757void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4758{
4759 LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4760 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4761 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4762}
4763
4764/**
4765 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4766 *
4767 * @returns Pointer to the shadow page structure.
4768 * @param pPool The pool.
4769 * @param HCPhys The HC physical address of the shadow page.
4770 */
4771PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4772{
4773 PVM pVM = pPool->CTX_SUFF(pVM);
4774
4775 Assert(PGMIsLockOwner(pVM));
4776
4777 /*
4778 * Look up the page.
4779 */
4780 pgmLock(pVM);
4781 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4782 pgmUnlock(pVM);
4783
4784 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4785 return pPage;
4786}
4787
4788#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
4789/**
4790 * Flush the specified page if present
4791 *
4792 * @param pVM The VM handle.
4793 * @param GCPhys Guest physical address of the page to flush
4794 */
4795void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
4796{
4797#ifdef PGMPOOL_WITH_CACHE
4798 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4799
4800 VM_ASSERT_EMT(pVM);
4801
4802 /*
4803 * Look up the GCPhys in the hash.
4804 */
4805 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
4806 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
4807 if (i == NIL_PGMPOOL_IDX)
4808 return;
4809
4810 do
4811 {
4812 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4813 if (pPage->GCPhys - GCPhys < PAGE_SIZE)
4814 {
4815 switch (pPage->enmKind)
4816 {
4817 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4818 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4819 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4820 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4821 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4822 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4823 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4824 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4825 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4826 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4827 case PGMPOOLKIND_64BIT_PML4:
4828 case PGMPOOLKIND_32BIT_PD:
4829 case PGMPOOLKIND_PAE_PDPT:
4830 {
4831 Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
4832#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4833 if (pPage->fDirty)
4834 STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
4835 else
4836#endif
4837 STAM_COUNTER_INC(&pPool->StatForceFlushPage);
4838 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
4839 pgmPoolMonitorChainFlush(pPool, pPage);
4840 return;
4841 }
4842
4843 /* ignore, no monitoring. */
4844 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4845 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4846 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4847 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4848 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4849 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4850 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4851 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4852 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4853 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4854 case PGMPOOLKIND_ROOT_NESTED:
4855 case PGMPOOLKIND_PAE_PD_PHYS:
4856 case PGMPOOLKIND_PAE_PDPT_PHYS:
4857 case PGMPOOLKIND_32BIT_PD_PHYS:
4858 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4859 break;
4860
4861 default:
4862 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
4863 }
4864 }
4865
4866 /* next */
4867 i = pPage->iNext;
4868 } while (i != NIL_PGMPOOL_IDX);
4869#endif
4870 return;
4871}
4872#endif /* IN_RING3 */
4873
4874#ifdef IN_RING3
4875/**
4876 * Flushes the entire cache.
4877 *
4878 * It will assert a global CR3 flush (FF) and assumes the caller is aware of
4879 * this and execute this CR3 flush.
4880 *
4881 * @param pPool The pool.
4882 */
4883void pgmR3PoolReset(PVM pVM)
4884{
4885 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4886
4887 Assert(PGMIsLockOwner(pVM));
4888 STAM_PROFILE_START(&pPool->StatR3Reset, a);
4889 LogFlow(("pgmR3PoolReset:\n"));
4890
4891 /*
4892 * If there are no pages in the pool, there is nothing to do.
4893 */
4894 if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
4895 {
4896 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
4897 return;
4898 }
4899
4900 /*
4901 * Exit the shadow mode since we're going to clear everything,
4902 * including the root page.
4903 */
4904 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4905 {
4906 PVMCPU pVCpu = &pVM->aCpus[i];
4907 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4908 }
4909
4910 /*
4911 * Nuke the free list and reinsert all pages into it.
4912 */
4913 for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
4914 {
4915 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4916
4917 Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
4918#ifdef PGMPOOL_WITH_MONITORING
4919 if (pPage->fMonitored)
4920 pgmPoolMonitorFlush(pPool, pPage);
4921 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4922 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4923 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4924 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4925 pPage->cModifications = 0;
4926#endif
4927 pPage->GCPhys = NIL_RTGCPHYS;
4928 pPage->enmKind = PGMPOOLKIND_FREE;
4929 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4930 Assert(pPage->idx == i);
4931 pPage->iNext = i + 1;
4932 pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
4933 pPage->fSeenNonGlobal = false;
4934 pPage->fMonitored = false;
4935#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4936 pPage->fDirty = false;
4937#endif
4938 pPage->fCached = false;
4939 pPage->fReusedFlushPending = false;
4940#ifdef PGMPOOL_WITH_USER_TRACKING
4941 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
4942#else
4943 pPage->fCR3Mix = false;
4944#endif
4945#ifdef PGMPOOL_WITH_CACHE
4946 pPage->iAgeNext = NIL_PGMPOOL_IDX;
4947 pPage->iAgePrev = NIL_PGMPOOL_IDX;
4948#endif
4949 pPage->cLocked = 0;
4950 }
4951 pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
4952 pPool->iFreeHead = PGMPOOL_IDX_FIRST;
4953 pPool->cUsedPages = 0;
4954
4955#ifdef PGMPOOL_WITH_USER_TRACKING
4956 /*
4957 * Zap and reinitialize the user records.
4958 */
4959 pPool->cPresent = 0;
4960 pPool->iUserFreeHead = 0;
4961 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
4962 const unsigned cMaxUsers = pPool->cMaxUsers;
4963 for (unsigned i = 0; i < cMaxUsers; i++)
4964 {
4965 paUsers[i].iNext = i + 1;
4966 paUsers[i].iUser = NIL_PGMPOOL_IDX;
4967 paUsers[i].iUserTable = 0xfffffffe;
4968 }
4969 paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
4970#endif
4971
4972#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4973 /*
4974 * Clear all the GCPhys links and rebuild the phys ext free list.
4975 */
4976 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
4977 pRam;
4978 pRam = pRam->CTX_SUFF(pNext))
4979 {
4980 unsigned iPage = pRam->cb >> PAGE_SHIFT;
4981 while (iPage-- > 0)
4982 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
4983 }
4984
4985 pPool->iPhysExtFreeHead = 0;
4986 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4987 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
4988 for (unsigned i = 0; i < cMaxPhysExts; i++)
4989 {
4990 paPhysExts[i].iNext = i + 1;
4991 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
4992 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
4993 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
4994 }
4995 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
4996#endif
4997
4998#ifdef PGMPOOL_WITH_MONITORING
4999 /*
5000 * Just zap the modified list.
5001 */
5002 pPool->cModifiedPages = 0;
5003 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5004#endif
5005
5006#ifdef PGMPOOL_WITH_CACHE
5007 /*
5008 * Clear the GCPhys hash and the age list.
5009 */
5010 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5011 pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5012 pPool->iAgeHead = NIL_PGMPOOL_IDX;
5013 pPool->iAgeTail = NIL_PGMPOOL_IDX;
5014#endif
5015
5016#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5017 /* Clear all dirty pages. */
5018 pPool->idxFreeDirtyPage = 0;
5019 pPool->cDirtyPages = 0;
5020 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
5021 pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
5022#endif
5023
5024 /*
5025 * Reinsert active pages into the hash and ensure monitoring chains are correct.
5026 */
5027 for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
5028 {
5029 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5030 pPage->iNext = NIL_PGMPOOL_IDX;
5031#ifdef PGMPOOL_WITH_MONITORING
5032 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5033 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5034 pPage->cModifications = 0;
5035 /* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
5036 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5037 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5038 if (pPage->fMonitored)
5039 {
5040 int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
5041 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
5042 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
5043 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
5044 pPool->pszAccessHandler);
5045 AssertFatalRCSuccess(rc);
5046# ifdef PGMPOOL_WITH_CACHE
5047 pgmPoolHashInsert(pPool, pPage);
5048# endif
5049 }
5050#endif
5051#ifdef PGMPOOL_WITH_USER_TRACKING
5052 Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
5053#endif
5054#ifdef PGMPOOL_WITH_CACHE
5055 Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
5056 Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
5057#endif
5058 }
5059
5060 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5061 {
5062 /*
5063 * Re-enter the shadowing mode and assert Sync CR3 FF.
5064 */
5065 PVMCPU pVCpu = &pVM->aCpus[i];
5066 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5067 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5068 }
5069
5070 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5071}
5072#endif /* IN_RING3 */
5073
5074#ifdef LOG_ENABLED
5075static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5076{
5077 switch(enmKind)
5078 {
5079 case PGMPOOLKIND_INVALID:
5080 return "PGMPOOLKIND_INVALID";
5081 case PGMPOOLKIND_FREE:
5082 return "PGMPOOLKIND_FREE";
5083 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5084 return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5085 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5086 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5087 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5088 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5089 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5090 return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5091 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5092 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5093 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5094 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5095 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5096 return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5097 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5098 return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5099 case PGMPOOLKIND_32BIT_PD:
5100 return "PGMPOOLKIND_32BIT_PD";
5101 case PGMPOOLKIND_32BIT_PD_PHYS:
5102 return "PGMPOOLKIND_32BIT_PD_PHYS";
5103 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5104 return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5105 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5106 return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5107 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5108 return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5109 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5110 return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5111 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5112 return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5113 case PGMPOOLKIND_PAE_PD_PHYS:
5114 return "PGMPOOLKIND_PAE_PD_PHYS";
5115 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5116 return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5117 case PGMPOOLKIND_PAE_PDPT:
5118 return "PGMPOOLKIND_PAE_PDPT";
5119 case PGMPOOLKIND_PAE_PDPT_PHYS:
5120 return "PGMPOOLKIND_PAE_PDPT_PHYS";
5121 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5122 return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5123 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5124 return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5125 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5126 return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5127 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5128 return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5129 case PGMPOOLKIND_64BIT_PML4:
5130 return "PGMPOOLKIND_64BIT_PML4";
5131 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5132 return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5133 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5134 return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5135 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5136 return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5137 case PGMPOOLKIND_ROOT_NESTED:
5138 return "PGMPOOLKIND_ROOT_NESTED";
5139 }
5140 return "Unknown kind!";
5141}
5142#endif /* LOG_ENABLED*/
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette