PGMAllPool.cpp@ 15348

Last change on this file since 15348 was 15348, checked in by vboxsync, 16 years ago
#3202: Optimized PGMPOOL_PAGE_2_PTR for darwin/R0 and */RC.
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1	/* $Id: PGMAllPool.cpp 15348 2008-12-12 02:00:10Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42
43
44	/*******************************************************************************
45	* Internal Functions *
46	*******************************************************************************/
47	__BEGIN_DECLS
48	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
49	#ifdef PGMPOOL_WITH_USER_TRACKING
50	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
51	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
52	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
53	#endif
54	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
55	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
56	#endif
57	#ifdef PGMPOOL_WITH_CACHE
58	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
59	#endif
60	#ifdef PGMPOOL_WITH_MONITORING
61	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
62	#endif
63	#ifndef IN_RING3
64	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
65	#endif
66	__END_DECLS
67
68
69	/**
70	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
71	*
72	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
73	* @param enmKind The page kind.
74	*/
75	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
76	{
77	switch (enmKind)
78	{
79	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
80	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
81	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
82	return true;
83	default:
84	return false;
85	}
86	}
87
88
89	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
90	/**
91	* Maps a pool page into the current context.
92	*
93	* @returns Pointer to the mapping.
94	* @param pPGM Pointer to the PGM instance data.
95	* @param pPage The page to map.
96	*/
97	void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage)
98	{
99	/* general pages are take care of by the inlined part, it
100	only ends up here in case of failure. */
101	AssertReleaseReturn(pPage->idx < PGMPOOL_IDX_FIRST, NULL);
102
103	/** @todo make sure HCPhys is valid for all indexes. */
104	/* special pages. */
105	# ifdef IN_RC
106	switch (pPage->idx)
107	{
108	case PGMPOOL_IDX_PD:
109	return pPGM->pShw32BitPdRC;
110	case PGMPOOL_IDX_PAE_PD:
111	case PGMPOOL_IDX_PAE_PD_0:
112	return pPGM->apShwPaePDsRC[0];
113	case PGMPOOL_IDX_PAE_PD_1:
114	return pPGM->apShwPaePDsRC[1];
115	case PGMPOOL_IDX_PAE_PD_2:
116	return pPGM->apShwPaePDsRC[2];
117	case PGMPOOL_IDX_PAE_PD_3:
118	return pPGM->apShwPaePDsRC[3];
119	case PGMPOOL_IDX_PDPT:
120	return pPGM->pShwPaePdptRC;
121	default:
122	AssertReleaseMsgFailed(("Invalid index %d\n", pPage->idx));
123	return NULL;
124	}
125
126	# else /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
127	RTHCPHYS HCPhys;
128	switch (pPage->idx)
129	{
130	case PGMPOOL_IDX_PD:
131	HCPhys = pPGM->HCPhysShw32BitPD;
132	break;
133	case PGMPOOL_IDX_PAE_PD_0:
134	HCPhys = pPGM->aHCPhysPaePDs[0];
135	break;
136	case PGMPOOL_IDX_PAE_PD_1:
137	HCPhys = pPGM->aHCPhysPaePDs[1];
138	break;
139	case PGMPOOL_IDX_PAE_PD_2:
140	HCPhys = pPGM->aHCPhysPaePDs[2];
141	break;
142	case PGMPOOL_IDX_PAE_PD_3:
143	HCPhys = pPGM->aHCPhysPaePDs[3];
144	break;
145	case PGMPOOL_IDX_PDPT:
146	HCPhys = pPGM->HCPhysShwPaePdpt;
147	break;
148	case PGMPOOL_IDX_PAE_PD:
149	AssertReleaseMsgFailed(("PGMPOOL_IDX_PAE_PD is not usable in VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 context\n"));
150	return NULL;
151	default:
152	AssertReleaseMsgFailed(("Invalid index %d\n", pPage->idx));
153	return NULL;
154	}
155	void *pv;
156	int rc = pgmR0DynMapHCPageInlined(pPGM, HCPhys, &pv);
157	AssertReleaseRCReturn(rc, NULL);
158	return pv;
159	# endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
160	}
161	#endif /* IN_RC \|\| VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
162
163
164	#ifdef PGMPOOL_WITH_MONITORING
165	/**
166	* Determin the size of a write instruction.
167	* @returns number of bytes written.
168	* @param pDis The disassembler state.
169	*/
170	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
171	{
172	/*
173	* This is very crude and possibly wrong for some opcodes,
174	* but since it's not really supposed to be called we can
175	* probably live with that.
176	*/
177	return DISGetParamSize(pDis, &pDis->param1);
178	}
179
180
181	/**
182	* Flushes a chain of pages sharing the same access monitor.
183	*
184	* @returns VBox status code suitable for scheduling.
185	* @param pPool The pool.
186	* @param pPage A page in the chain.
187	*/
188	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
189	{
190	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
191
192	/*
193	* Find the list head.
194	*/
195	uint16_t idx = pPage->idx;
196	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
197	{
198	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
199	{
200	idx = pPage->iMonitoredPrev;
201	Assert(idx != pPage->idx);
202	pPage = &pPool->aPages[idx];
203	}
204	}
205
206	/*
207	* Iterate the list flushing each shadow page.
208	*/
209	int rc = VINF_SUCCESS;
210	for (;;)
211	{
212	idx = pPage->iMonitoredNext;
213	Assert(idx != pPage->idx);
214	if (pPage->idx >= PGMPOOL_IDX_FIRST)
215	{
216	int rc2 = pgmPoolFlushPage(pPool, pPage);
217	if (rc2 == VERR_PGM_POOL_CLEARED && rc == VINF_SUCCESS)
218	rc = VINF_PGM_SYNC_CR3;
219	}
220	/* next */
221	if (idx == NIL_PGMPOOL_IDX)
222	break;
223	pPage = &pPool->aPages[idx];
224	}
225	return rc;
226	}
227
228
229	/**
230	* Wrapper for getting the current context pointer to the entry being modified.
231	*
232	* @returns Pointer to the current context mapping of the entry.
233	* @param pPool The pool.
234	* @param pvFault The fault virtual address.
235	* @param GCPhysFault The fault physical address.
236	* @param cbEntry The entry size.
237	*/
238	#ifdef IN_RING3
239	DECLINLINE(const void *) pgmPoolMonitorGCPtr2CCPtr(PPGMPOOL pPool, RTHCPTR pvFault, RTGCPHYS GCPhysFault, const unsigned cbEntry)
240	#else
241	DECLINLINE(const void *) pgmPoolMonitorGCPtr2CCPtr(PPGMPOOL pPool, RTGCPTR pvFault, RTGCPHYS GCPhysFault, const unsigned cbEntry)
242	#endif
243	{
244	#ifdef IN_RC
245	return (const void *)((RTGCUINTPTR)pvFault & ~(RTGCUINTPTR)(cbEntry - 1));
246
247	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
248	void *pvRet;
249	int rc = PGMDynMapGCPageOff(pPool->pVMR0, GCPhysFault & ~(RTGCPHYS)(cbEntry - 1), &pvRet);
250	AssertFatalRCSuccess(rc);
251	return pvRet;
252
253	#elif defined(IN_RING0)
254	void *pvRet;
255	int rc = pgmRamGCPhys2HCPtr(&pPool->pVMR0->pgm.s, GCPhysFault & ~(RTGCPHYS)(cbEntry - 1), &pvRet);
256	AssertFatalRCSuccess(rc);
257	return pvRet;
258
259	#elif defined(IN_RING3)
260	return (RTHCPTR)((uintptr_t)pvFault & ~(RTHCUINTPTR)(cbEntry - 1));
261	#else
262	# error "huh?"
263	#endif
264	}
265
266
267	/**
268	* Process shadow entries before they are changed by the guest.
269	*
270	* For PT entries we will clear them. For PD entries, we'll simply check
271	* for mapping conflicts and set the SyncCR3 FF if found.
272	*
273	* @param pPool The pool.
274	* @param pPage The head page.
275	* @param GCPhysFault The guest physical fault address.
276	* @param uAddress In R0 and GC this is the guest context fault address (flat).
277	* In R3 this is the host context 'fault' address.
278	* @param pCpu The disassembler state for figuring out the write size.
279	* This need not be specified if the caller knows we won't do cross entry accesses.
280	*/
281	#ifdef IN_RING3
282	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu)
283	#else
284	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu)
285	#endif
286	{
287	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
288	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
289	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
290
291	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%d cbWrite=%d\n", pvAddress, GCPhysFault, pPage->enmKind, cbWrite));
292
293	for (;;)
294	{
295	union
296	{
297	void *pv;
298	PX86PT pPT;
299	PX86PTPAE pPTPae;
300	PX86PD pPD;
301	PX86PDPAE pPDPae;
302	PX86PDPT pPDPT;
303	PX86PML4 pPML4;
304	} uShw;
305
306	switch (pPage->enmKind)
307	{
308	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
309	{
310	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
311	const unsigned iShw = off / sizeof(X86PTE);
312	if (uShw.pPT->a[iShw].n.u1Present)
313	{
314	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
315	PCX86PTE pGstPte = (PCX86PTE)pgmPoolMonitorGCPtr2CCPtr(pPool, pvAddress, GCPhysFault, sizeof(*pGstPte));
316	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, pGstPte->u & X86_PTE_PG_MASK));
317	pgmPoolTracDerefGCPhysHint(pPool, pPage,
318	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
319	pGstPte->u & X86_PTE_PG_MASK);
320	# endif
321	uShw.pPT->a[iShw].u = 0;
322	}
323	break;
324	}
325
326	/* page/2 sized */
327	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
328	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
329	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
330	{
331	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
332	if (uShw.pPTPae->a[iShw].n.u1Present)
333	{
334	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
335	PCX86PTE pGstPte = (PCX86PTE)pgmPoolMonitorGCPtr2CCPtr(pPool, pvAddress, GCPhysFault, sizeof(*pGstPte));
336	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, pGstPte->u & X86_PTE_PG_MASK));
337	pgmPoolTracDerefGCPhysHint(pPool, pPage,
338	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
339	pGstPte->u & X86_PTE_PG_MASK);
340	# endif
341	uShw.pPTPae->a[iShw].u = 0;
342	}
343	}
344	break;
345
346	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
347	{
348	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
349	const unsigned iShw = off / sizeof(X86PTEPAE);
350	if (uShw.pPTPae->a[iShw].n.u1Present)
351	{
352	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
353	PCX86PTEPAE pGstPte = (PCX86PTEPAE)pgmPoolMonitorGCPtr2CCPtr(pPool, pvAddress, GCPhysFault, sizeof(*pGstPte));
354	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, pGstPte->u & X86_PTE_PAE_PG_MASK));
355	pgmPoolTracDerefGCPhysHint(pPool, pPage,
356	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
357	pGstPte->u & X86_PTE_PAE_PG_MASK);
358	# endif
359	uShw.pPTPae->a[iShw].u = 0;
360	}
361
362	/* paranoia / a bit assumptive. */
363	if ( pCpu
364	&& (off & 7)
365	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
366	{
367	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
368	AssertReturnVoid(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
369
370	if (uShw.pPTPae->a[iShw2].n.u1Present)
371	{
372	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
373	PCX86PTEPAE pGstPte = (PCX86PTEPAE)pgmPoolMonitorGCPtr2CCPtr(pPool, pvAddress, GCPhysFault, sizeof(*pGstPte));
374	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, pGstPte->u & X86_PTE_PAE_PG_MASK));
375	pgmPoolTracDerefGCPhysHint(pPool, pPage,
376	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
377	pGstPte->u & X86_PTE_PAE_PG_MASK);
378	# endif
379	uShw.pPTPae->a[iShw2].u = 0;
380	}
381	}
382
383	break;
384	}
385
386	case PGMPOOLKIND_ROOT_32BIT_PD:
387	{
388	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
389	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
390	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
391	{
392	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
393	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
394	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
395	}
396	/* paranoia / a bit assumptive. */
397	else if ( pCpu
398	&& (off & 3)
399	&& (off & 3) + cbWrite > sizeof(X86PTE))
400	{
401	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
402	if ( iShw2 != iShw
403	&& iShw2 < RT_ELEMENTS(uShw.pPD->a)
404	&& uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
405	{
406	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
407	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
408	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
409	}
410	}
411	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
412	if ( uShw.pPD->a[iShw].n.u1Present
413	&& !VM_FF_ISSET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3))
414	{
415	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
416	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
417	ASMProbeReadByte(pvAddress);
418	# endif
419	pgmPoolFree(pPool->CTX_SUFF(pVM), uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
420	uShw.pPD->a[iShw].u = 0;
421	}
422	#endif
423	break;
424	}
425
426	case PGMPOOLKIND_ROOT_PAE_PD:
427	{
428	unsigned iGst = off / sizeof(X86PDE); // ASSUMING 32-bit guest paging!
429	unsigned iShwPdpt = iGst / 256;
430	unsigned iShw = (iGst % 256) * 2;
431	Assert(pPage->idx == PGMPOOL_IDX_PAE_PD);
432	PPGMPOOLPAGE pPage2 = pPage + 1 + iShwPdpt;
433	Assert(pPage2->idx == PGMPOOL_IDX_PAE_PD_0 + iShwPdpt);
434	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage2);
435	for (unsigned i = 0; i < 2; i++, iShw++)
436	{
437	if ((uShw.pPDPae->a[iShw].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
438	{
439	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
440	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
441	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw));
442	}
443	/* paranoia / a bit assumptive. */
444	else if ( pCpu
445	&& (off & 3)
446	&& (off & 3) + cbWrite > 4)
447	{
448	const unsigned iShw2 = iShw + 2;
449	if ( iShw2 < RT_ELEMENTS(uShw.pPDPae->a) /** @todo was completely wrong, it's better now after #1865 but still wrong from cross PD. */
450	&& (uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
451	{
452	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
453	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
454	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
455	}
456	}
457	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
458	if ( uShw.pPDPae->a[iShw].n.u1Present
459	&& !VM_FF_ISSET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3))
460	{
461	LogFlow(("pgmPoolMonitorChainChanging: iShwPdpt=%#x iShw=%#x: %RX64 -> freeing it!\n", iShwPdpt, iShw, uShw.pPDPae->a[iShw].u));
462	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
463	ASMProbeReadByte(pvAddress);
464	# endif
465	pgmPoolFree(pPool->CTX_SUFF(pVM), uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK, pPage->idx, iShw + iShwPdpt * X86_PG_PAE_ENTRIES);
466	uShw.pPDPae->a[iShw].u = 0;
467	}
468	#endif
469	}
470	break;
471	}
472
473	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
474	{
475	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
476	const unsigned iShw = off / sizeof(X86PDEPAE);
477	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
480	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
481	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
482	}
483	#ifdef PGMPOOL_INVALIDATE_UPPER_SHADOW_TABLE_ENTRIES
484	/*
485	* Causes trouble when the guest uses a PDE to refer to the whole page table level
486	* structure. (Invalidate here; faults later on when it tries to change the page
487	* table entries -> recheck; probably only applies to the RC case.)
488	*/
489	else
490	{
491	if (uShw.pPDPae->a[iShw].n.u1Present)
492	{
493	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
494	pgmPoolFree(pPool->CTX_SUFF(pVM),
495	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
496	/* Note: hardcoded PAE implementation dependency */
497	(pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD) ? PGMPOOL_IDX_PAE_PD : pPage->idx,
498	(pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD) ? iShw + (pPage->idx - PGMPOOL_IDX_PAE_PD_0) * X86_PG_PAE_ENTRIES : iShw);
499	uShw.pPDPae->a[iShw].u = 0;
500	}
501	}
502	#endif
503	/* paranoia / a bit assumptive. */
504	if ( pCpu
505	&& (off & 7)
506	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
507	{
508	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
509	AssertReturnVoid(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
510
511	if ( iShw2 != iShw
512	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
513	{
514	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
515	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
516	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
517	}
518	#ifdef PGMPOOL_INVALIDATE_UPPER_SHADOW_TABLE_ENTRIES
519	else if (uShw.pPDPae->a[iShw2].n.u1Present)
520	{
521	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
522	pgmPoolFree(pPool->CTX_SUFF(pVM),
523	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
524	/* Note: hardcoded PAE implementation dependency */
525	(pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD) ? PGMPOOL_IDX_PAE_PD : pPage->idx,
526	(pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD) ? iShw2 + (pPage->idx - PGMPOOL_IDX_PAE_PD_0) * X86_PG_PAE_ENTRIES : iShw2);
527	uShw.pPDPae->a[iShw2].u = 0;
528	}
529	#endif
530	}
531	break;
532	}
533
534	case PGMPOOLKIND_ROOT_PDPT:
535	{
536	/*
537	* Hopefully this doesn't happen very often:
538	* - touching unused parts of the page
539	* - messing with the bits of pd pointers without changing the physical address
540	*/
541	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
542	const unsigned iShw = off / sizeof(X86PDPE);
543	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
544	{
545	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
546	{
547	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
548	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
549	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
550	}
551	/* paranoia / a bit assumptive. */
552	else if ( pCpu
553	&& (off & 7)
554	&& (off & 7) + cbWrite > sizeof(X86PDPE))
555	{
556	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
557	if ( iShw2 != iShw
558	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES
559	&& uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
560	{
561	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
562	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
563	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
564	}
565	}
566	}
567	break;
568	}
569
570	#ifndef IN_RC
571	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
572	{
573	Assert(pPage->enmKind == PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD);
574
575	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
576	const unsigned iShw = off / sizeof(X86PDEPAE);
577	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
578	{
579	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
580	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
581	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
582	}
583	else
584	{
585	if (uShw.pPDPae->a[iShw].n.u1Present)
586	{
587	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
588	pgmPoolFree(pPool->CTX_SUFF(pVM),
589	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
590	pPage->idx,
591	iShw);
592	uShw.pPDPae->a[iShw].u = 0;
593	}
594	}
595	/* paranoia / a bit assumptive. */
596	if ( pCpu
597	&& (off & 7)
598	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
599	{
600	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
601	AssertReturnVoid(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
602
603	if ( iShw2 != iShw
604	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
605	{
606	Assert(pgmMapAreMappingsEnabled(&pPool->CTX_SUFF(pVM)->pgm.s));
607	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
608	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
609	}
610	else
611	if (uShw.pPDPae->a[iShw2].n.u1Present)
612	{
613	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
614	pgmPoolFree(pPool->CTX_SUFF(pVM),
615	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
616	pPage->idx,
617	iShw2);
618	uShw.pPDPae->a[iShw2].u = 0;
619	}
620	}
621	break;
622	}
623
624	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
625	{
626	/*
627	* Hopefully this doesn't happen very often:
628	* - messing with the bits of pd pointers without changing the physical address
629	*/
630	if (!VM_FF_ISSET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3))
631	{
632	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
633	const unsigned iShw = off / sizeof(X86PDPE);
634	if (uShw.pPDPT->a[iShw].n.u1Present)
635	{
636	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
637	pgmPoolFree(pPool->CTX_SUFF(pVM), uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
638	uShw.pPDPT->a[iShw].u = 0;
639	}
640	/* paranoia / a bit assumptive. */
641	if ( pCpu
642	&& (off & 7)
643	&& (off & 7) + cbWrite > sizeof(X86PDPE))
644	{
645	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
646	if (uShw.pPDPT->a[iShw2].n.u1Present)
647	{
648	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
649	pgmPoolFree(pPool->CTX_SUFF(pVM), uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
650	uShw.pPDPT->a[iShw2].u = 0;
651	}
652	}
653	}
654	break;
655	}
656
657	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
658	{
659	/*
660	* Hopefully this doesn't happen very often:
661	* - messing with the bits of pd pointers without changing the physical address
662	*/
663	if (!VM_FF_ISSET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3))
664	{
665	uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
666	const unsigned iShw = off / sizeof(X86PDPE);
667	if (uShw.pPML4->a[iShw].n.u1Present)
668	{
669	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
670	pgmPoolFree(pPool->CTX_SUFF(pVM), uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
671	uShw.pPML4->a[iShw].u = 0;
672	}
673	/* paranoia / a bit assumptive. */
674	if ( pCpu
675	&& (off & 7)
676	&& (off & 7) + cbWrite > sizeof(X86PDPE))
677	{
678	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
679	if (uShw.pPML4->a[iShw2].n.u1Present)
680	{
681	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
682	pgmPoolFree(pPool->CTX_SUFF(pVM), uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
683	uShw.pPML4->a[iShw2].u = 0;
684	}
685	}
686	}
687	break;
688	}
689	#endif /* IN_RING0 */
690
691	default:
692	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
693	}
694
695	/* next */
696	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
697	return;
698	pPage = &pPool->aPages[pPage->iMonitoredNext];
699	}
700	}
701
702
703	# ifndef IN_RING3
704	/**
705	* Checks if a access could be a fork operation in progress.
706	*
707	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
708	*
709	* @returns true if it's likly that we're forking, otherwise false.
710	* @param pPool The pool.
711	* @param pCpu The disassembled instruction.
712	* @param offFault The access offset.
713	*/
714	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
715	{
716	/*
717	* i386 linux is using btr to clear X86_PTE_RW.
718	* The functions involved are (2.6.16 source inspection):
719	* clear_bit
720	* ptep_set_wrprotect
721	* copy_one_pte
722	* copy_pte_range
723	* copy_pmd_range
724	* copy_pud_range
725	* copy_page_range
726	* dup_mmap
727	* dup_mm
728	* copy_mm
729	* copy_process
730	* do_fork
731	*/
732	if ( pCpu->pCurInstr->opcode == OP_BTR
733	&& !(offFault & 4)
734	/** @todo Validate that the bit index is X86_PTE_RW. */
735	)
736	{
737	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
738	return true;
739	}
740	return false;
741	}
742
743
744	/**
745	* Determine whether the page is likely to have been reused.
746	*
747	* @returns true if we consider the page as being reused for a different purpose.
748	* @returns false if we consider it to still be a paging page.
749	* @param pVM VM Handle.
750	* @param pPage The page in question.
751	* @param pRegFrame Trap register frame.
752	* @param pCpu The disassembly info for the faulting instruction.
753	* @param pvFault The fault address.
754	*
755	* @remark The REP prefix check is left to the caller because of STOSD/W.
756	*/
757	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PPGMPOOLPAGE pPage, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
758	{
759	#ifndef IN_RC
760	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
761	if ( HWACCMHasPendingIrq(pVM)
762	&& (pRegFrame->rsp - pvFault) < 32)
763	{
764	/* Fault caused by stack writes while trying to inject an interrupt event. */
765	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
766	return true;
767	}
768	#else
769	NOREF(pVM); NOREF(pvFault);
770	#endif
771
772	switch (pCpu->pCurInstr->opcode)
773	{
774	/* call implies the actual push of the return address faulted */
775	case OP_CALL:
776	Log4(("pgmPoolMonitorIsReused: CALL\n"));
777	return true;
778	case OP_PUSH:
779	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
780	return true;
781	case OP_PUSHF:
782	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
783	return true;
784	case OP_PUSHA:
785	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
786	return true;
787	case OP_FXSAVE:
788	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
789	return true;
790	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
791	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
792	return true;
793	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
794	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
795	return true;
796	case OP_MOVSWD:
797	case OP_STOSWD:
798	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
799	&& pRegFrame->rcx >= 0x40
800	)
801	{
802	Assert(pCpu->mode == CPUMODE_64BIT);
803
804	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
805	return true;
806	}
807	return false;
808	}
809	if ( (pCpu->param1.flags & USE_REG_GEN32)
810	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
811	{
812	Log4(("pgmPoolMonitorIsReused: ESP\n"));
813	return true;
814	}
815
816	//if (pPage->fCR3Mix)
817	// return false;
818	return false;
819	}
820
821
822	/**
823	* Flushes the page being accessed.
824	*
825	* @returns VBox status code suitable for scheduling.
826	* @param pVM The VM handle.
827	* @param pPool The pool.
828	* @param pPage The pool page (head).
829	* @param pCpu The disassembly of the write instruction.
830	* @param pRegFrame The trap register frame.
831	* @param GCPhysFault The fault address as guest physical address.
832	* @param pvFault The fault address.
833	*/
834	static int pgmPoolAccessHandlerFlush(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
835	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
836	{
837	/*
838	* First, do the flushing.
839	*/
840	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
841
842	/*
843	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
844	*/
845	uint32_t cbWritten;
846	int rc2 = EMInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, &cbWritten);
847	if (RT_SUCCESS(rc2))
848	pRegFrame->rip += pCpu->opsize;
849	else if (rc2 == VERR_EM_INTERPRETER)
850	{
851	#ifdef IN_RC
852	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
853	{
854	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
855	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
856	rc = VINF_SUCCESS;
857	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
858	}
859	else
860	#endif
861	{
862	rc = VINF_EM_RAW_EMULATE_INSTR;
863	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
864	}
865	}
866	else
867	rc = rc2;
868
869	/* See use in pgmPoolAccessHandlerSimple(). */
870	PGM_INVL_GUEST_TLBS();
871
872	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
873	return rc;
874
875	}
876
877
878	/**
879	* Handles the STOSD write accesses.
880	*
881	* @returns VBox status code suitable for scheduling.
882	* @param pVM The VM handle.
883	* @param pPool The pool.
884	* @param pPage The pool page (head).
885	* @param pCpu The disassembly of the write instruction.
886	* @param pRegFrame The trap register frame.
887	* @param GCPhysFault The fault address as guest physical address.
888	* @param pvFault The fault address.
889	*/
890	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
891	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
892	{
893	Assert(pCpu->mode == CPUMODE_32BIT);
894
895	/*
896	* Increment the modification counter and insert it into the list
897	* of modified pages the first time.
898	*/
899	if (!pPage->cModifications++)
900	pgmPoolMonitorModifiedInsert(pPool, pPage);
901
902	/*
903	* Execute REP STOSD.
904	*
905	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
906	* write situation, meaning that it's safe to write here.
907	*/
908	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
909	while (pRegFrame->ecx)
910	{
911	pgmPoolMonitorChainChanging(pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
912	#ifdef IN_RC
913	(uint32_t )pu32 = pRegFrame->eax;
914	#else
915	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
916	#endif
917	pu32 += 4;
918	GCPhysFault += 4;
919	pRegFrame->edi += 4;
920	pRegFrame->ecx--;
921	}
922	pRegFrame->rip += pCpu->opsize;
923
924	/* See use in pgmPoolAccessHandlerSimple(). */
925	PGM_INVL_GUEST_TLBS();
926
927	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
928	return VINF_SUCCESS;
929	}
930
931
932	/**
933	* Handles the simple write accesses.
934	*
935	* @returns VBox status code suitable for scheduling.
936	* @param pVM The VM handle.
937	* @param pPool The pool.
938	* @param pPage The pool page (head).
939	* @param pCpu The disassembly of the write instruction.
940	* @param pRegFrame The trap register frame.
941	* @param GCPhysFault The fault address as guest physical address.
942	* @param pvFault The fault address.
943	*/
944	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
945	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
946	{
947	/*
948	* Increment the modification counter and insert it into the list
949	* of modified pages the first time.
950	*/
951	if (!pPage->cModifications++)
952	pgmPoolMonitorModifiedInsert(pPool, pPage);
953
954	/*
955	* Clear all the pages. ASSUMES that pvFault is readable.
956	*/
957	pgmPoolMonitorChainChanging(pPool, pPage, GCPhysFault, pvFault, pCpu);
958
959	/*
960	* Interpret the instruction.
961	*/
962	uint32_t cb;
963	int rc = EMInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, &cb);
964	if (RT_SUCCESS(rc))
965	pRegFrame->rip += pCpu->opsize;
966	else if (rc == VERR_EM_INTERPRETER)
967	{
968	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
969	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
970	rc = VINF_EM_RAW_EMULATE_INSTR;
971	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
972	}
973
974	/*
975	* Quick hack, with logging enabled we're getting stale
976	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
977	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
978	* have to be fixed to support this. But that'll have to wait till next week.
979	*
980	* An alternative is to keep track of the changed PTEs together with the
981	* GCPhys from the guest PT. This may proove expensive though.
982	*
983	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
984	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
985	*/
986	PGM_INVL_GUEST_TLBS();
987
988	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
989	return rc;
990	}
991
992
993	/**
994	* \#PF Handler callback for PT write accesses.
995	*
996	* @returns VBox status code (appropriate for GC return).
997	* @param pVM VM Handle.
998	* @param uErrorCode CPU Error code.
999	* @param pRegFrame Trap register frame.
1000	* NULL on DMA and other non CPU access.
1001	* @param pvFault The fault address (cr2).
1002	* @param GCPhysFault The GC physical address corresponding to pvFault.
1003	* @param pvUser User argument.
1004	*/
1005	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1006	{
1007	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1008	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1009	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1010	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1011
1012	/*
1013	* We should ALWAYS have the list head as user parameter. This
1014	* is because we use that page to record the changes.
1015	*/
1016	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1017
1018	/*
1019	* Disassemble the faulting instruction.
1020	*/
1021	DISCPUSTATE Cpu;
1022	int rc = EMInterpretDisasOne(pVM, pRegFrame, &Cpu, NULL);
1023	AssertRCReturn(rc, rc);
1024
1025	/*
1026	* Check if it's worth dealing with.
1027	*/
1028	bool fReused = false;
1029	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1030	\|\| pPage->fCR3Mix)
1031	&& !(fReused = pgmPoolMonitorIsReused(pVM, pPage, pRegFrame, &Cpu, pvFault))
1032	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1033	{
1034	/*
1035	* Simple instructions, no REP prefix.
1036	*/
1037	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1038	{
1039	rc = pgmPoolAccessHandlerSimple(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1040	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1041	return rc;
1042	}
1043
1044	/*
1045	* Windows is frequently doing small memset() operations (netio test 4k+).
1046	* We have to deal with these or we'll kill the cache and performance.
1047	*/
1048	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1049	&& CPUMGetGuestCPL(pVM, pRegFrame) == 0
1050	&& pRegFrame->ecx <= 0x20
1051	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1052	&& !((uintptr_t)pvFault & 3)
1053	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1054	&& Cpu.mode == CPUMODE_32BIT
1055	&& Cpu.opmode == CPUMODE_32BIT
1056	&& Cpu.addrmode == CPUMODE_32BIT
1057	&& Cpu.prefix == PREFIX_REP
1058	&& !pRegFrame->eflags.Bits.u1DF
1059	)
1060	{
1061	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1062	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1063	return rc;
1064	}
1065
1066	/* REP prefix, don't bother. */
1067	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1068	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1069	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1070	}
1071
1072	/*
1073	* Not worth it, so flush it.
1074	*
1075	* If we considered it to be reused, don't to back to ring-3
1076	* to emulate failed instructions since we usually cannot
1077	* interpret then. This may be a bit risky, in which case
1078	* the reuse detection must be fixed.
1079	*/
1080	rc = pgmPoolAccessHandlerFlush(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1081	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1082	rc = VINF_SUCCESS;
1083	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1084	return rc;
1085	}
1086
1087	# endif /* !IN_RING3 */
1088	#endif /* PGMPOOL_WITH_MONITORING */
1089
1090	#ifdef PGMPOOL_WITH_CACHE
1091
1092	/**
1093	* Inserts a page into the GCPhys hash table.
1094	*
1095	* @param pPool The pool.
1096	* @param pPage The page.
1097	*/
1098	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1099	{
1100	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1101	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1102	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1103	pPage->iNext = pPool->aiHash[iHash];
1104	pPool->aiHash[iHash] = pPage->idx;
1105	}
1106
1107
1108	/**
1109	* Removes a page from the GCPhys hash table.
1110	*
1111	* @param pPool The pool.
1112	* @param pPage The page.
1113	*/
1114	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1115	{
1116	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1117	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1118	if (pPool->aiHash[iHash] == pPage->idx)
1119	pPool->aiHash[iHash] = pPage->iNext;
1120	else
1121	{
1122	uint16_t iPrev = pPool->aiHash[iHash];
1123	for (;;)
1124	{
1125	const int16_t i = pPool->aPages[iPrev].iNext;
1126	if (i == pPage->idx)
1127	{
1128	pPool->aPages[iPrev].iNext = pPage->iNext;
1129	break;
1130	}
1131	if (i == NIL_PGMPOOL_IDX)
1132	{
1133	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1134	break;
1135	}
1136	iPrev = i;
1137	}
1138	}
1139	pPage->iNext = NIL_PGMPOOL_IDX;
1140	}
1141
1142
1143	/**
1144	* Frees up one cache page.
1145	*
1146	* @returns VBox status code.
1147	* @retval VINF_SUCCESS on success.
1148	* @retval VERR_PGM_POOL_CLEARED if the deregistration of a physical handler will cause a light weight pool flush.
1149	* @param pPool The pool.
1150	* @param iUser The user index.
1151	*/
1152	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1153	{
1154	#ifndef IN_RC
1155	const PVM pVM = pPool->CTX_SUFF(pVM);
1156	#endif
1157	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1158	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1159
1160	/*
1161	* Select one page from the tail of the age list.
1162	*/
1163	uint16_t iToFree = pPool->iAgeTail;
1164	if (iToFree == iUser)
1165	iToFree = pPool->aPages[iToFree].iAgePrev;
1166	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1167	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1168	{
1169	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1170	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1171	{
1172	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1173	continue;
1174	iToFree = i;
1175	break;
1176	}
1177	}
1178	*/
1179
1180	Assert(iToFree != iUser);
1181	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1182
1183	PPGMPOOLPAGE pPage = &pPool->aPages[iToFree];
1184
1185	/*
1186	* Reject any attempts at flushing the currently active shadow CR3 mapping
1187	*/
1188	if (PGMGetHyperCR3(pPool->CTX_SUFF(pVM)) == pPage->Core.Key)
1189	{
1190	/* Refresh the cr3 mapping by putting it at the head of the age list. */
1191	pgmPoolCacheUsed(pPool, pPage);
1192	return pgmPoolCacheFreeOne(pPool, iUser);
1193	}
1194
1195	int rc = pgmPoolFlushPage(pPool, pPage);
1196	if (rc == VINF_SUCCESS)
1197	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1198	return rc;
1199	}
1200
1201
1202	/**
1203	* Checks if a kind mismatch is really a page being reused
1204	* or if it's just normal remappings.
1205	*
1206	* @returns true if reused and the cached page (enmKind1) should be flushed
1207	* @returns false if not reused.
1208	* @param enmKind1 The kind of the cached page.
1209	* @param enmKind2 The kind of the requested page.
1210	*/
1211	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1212	{
1213	switch (enmKind1)
1214	{
1215	/*
1216	* Never reuse them. There is no remapping in non-paging mode.
1217	*/
1218	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1219	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1220	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1221	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1222	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1223	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1224	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1225	return true;
1226
1227	/*
1228	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1229	*/
1230	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1231	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1232	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1233	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1234	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
1235	switch (enmKind2)
1236	{
1237	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1238	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1239	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1240	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1241	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
1242	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1243	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1244	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1245	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1246	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1247	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1248	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1249	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1250	return true;
1251	default:
1252	return false;
1253	}
1254
1255	/*
1256	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1257	*/
1258	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1259	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1260	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1261	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1262	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
1263	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1264	switch (enmKind2)
1265	{
1266	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1267	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1268	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1269	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1270	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
1271	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1272	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1273	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1274	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1275	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1276	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1277	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1278	return true;
1279	default:
1280	return false;
1281	}
1282
1283	/*
1284	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1285	*/
1286	case PGMPOOLKIND_ROOT_32BIT_PD:
1287	case PGMPOOLKIND_ROOT_PAE_PD:
1288	case PGMPOOLKIND_ROOT_PDPT:
1289	case PGMPOOLKIND_ROOT_NESTED:
1290	return false;
1291
1292	default:
1293	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1294	}
1295	}
1296
1297
1298	/**
1299	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1300	*
1301	* @returns VBox status code.
1302	* @retval VINF_PGM_CACHED_PAGE on success.
1303	* @retval VERR_FILE_NOT_FOUND if not found.
1304	* @param pPool The pool.
1305	* @param GCPhys The GC physical address of the page we're gonna shadow.
1306	* @param enmKind The kind of mapping.
1307	* @param iUser The shadow page pool index of the user table.
1308	* @param iUserTable The index into the user table (shadowed).
1309	* @param ppPage Where to store the pointer to the page.
1310	*/
1311	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1312	{
1313	#ifndef IN_RC
1314	const PVM pVM = pPool->CTX_SUFF(pVM);
1315	#endif
1316	/*
1317	* Look up the GCPhys in the hash.
1318	*/
1319	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1320	Log3(("pgmPoolCacheAlloc: %RGp kind %d iUser=%d iUserTable=%x SLOT=%d\n", GCPhys, enmKind, iUser, iUserTable, i));
1321	if (i != NIL_PGMPOOL_IDX)
1322	{
1323	do
1324	{
1325	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1326	Log3(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1327	if (pPage->GCPhys == GCPhys)
1328	{
1329	if ((PGMPOOLKIND)pPage->enmKind == enmKind)
1330	{
1331	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1332	if (RT_SUCCESS(rc))
1333	{
1334	*ppPage = pPage;
1335	STAM_COUNTER_INC(&pPool->StatCacheHits);
1336	return VINF_PGM_CACHED_PAGE;
1337	}
1338	return rc;
1339	}
1340
1341	/*
1342	* The kind is different. In some cases we should now flush the page
1343	* as it has been reused, but in most cases this is normal remapping
1344	* of PDs as PT or big pages using the GCPhys field in a slightly
1345	* different way than the other kinds.
1346	*/
1347	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1348	{
1349	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1350	pgmPoolFlushPage(pPool, pPage); /* ASSUMES that VERR_PGM_POOL_CLEARED will be returned by pgmPoolTracInsert. */
1351	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1352	break;
1353	}
1354	}
1355
1356	/* next */
1357	i = pPage->iNext;
1358	} while (i != NIL_PGMPOOL_IDX);
1359	}
1360
1361	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%d\n", GCPhys, enmKind));
1362	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1363	return VERR_FILE_NOT_FOUND;
1364	}
1365
1366
1367	/**
1368	* Inserts a page into the cache.
1369	*
1370	* @param pPool The pool.
1371	* @param pPage The cached page.
1372	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1373	*/
1374	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1375	{
1376	/*
1377	* Insert into the GCPhys hash if the page is fit for that.
1378	*/
1379	Assert(!pPage->fCached);
1380	if (fCanBeCached)
1381	{
1382	pPage->fCached = true;
1383	pgmPoolHashInsert(pPool, pPage);
1384	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%d, GCPhys=%RGp}\n",
1385	pPage, pPage->Core.Key, pPage->idx, pPage->enmKind, pPage->GCPhys));
1386	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1387	}
1388	else
1389	{
1390	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%d, GCPhys=%RGp}\n",
1391	pPage, pPage->Core.Key, pPage->idx, pPage->enmKind, pPage->GCPhys));
1392	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1393	}
1394
1395	/*
1396	* Insert at the head of the age list.
1397	*/
1398	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1399	pPage->iAgeNext = pPool->iAgeHead;
1400	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1401	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1402	else
1403	pPool->iAgeTail = pPage->idx;
1404	pPool->iAgeHead = pPage->idx;
1405	}
1406
1407
1408	/**
1409	* Flushes a cached page.
1410	*
1411	* @param pPool The pool.
1412	* @param pPage The cached page.
1413	*/
1414	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1415	{
1416	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1417
1418	/*
1419	* Remove the page from the hash.
1420	*/
1421	if (pPage->fCached)
1422	{
1423	pPage->fCached = false;
1424	pgmPoolHashRemove(pPool, pPage);
1425	}
1426	else
1427	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1428
1429	/*
1430	* Remove it from the age list.
1431	*/
1432	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1433	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1434	else
1435	pPool->iAgeTail = pPage->iAgePrev;
1436	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1437	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1438	else
1439	pPool->iAgeHead = pPage->iAgeNext;
1440	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1441	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1442	}
1443
1444	#endif /* PGMPOOL_WITH_CACHE */
1445	#ifdef PGMPOOL_WITH_MONITORING
1446
1447	/**
1448	* Looks for pages sharing the monitor.
1449	*
1450	* @returns Pointer to the head page.
1451	* @returns NULL if not found.
1452	* @param pPool The Pool
1453	* @param pNewPage The page which is going to be monitored.
1454	*/
1455	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1456	{
1457	#ifdef PGMPOOL_WITH_CACHE
1458	/*
1459	* Look up the GCPhys in the hash.
1460	*/
1461	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1462	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1463	if (i == NIL_PGMPOOL_IDX)
1464	return NULL;
1465	do
1466	{
1467	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1468	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1469	&& pPage != pNewPage)
1470	{
1471	switch (pPage->enmKind)
1472	{
1473	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1474	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1475	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1476	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
1477	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1478	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1479	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1480	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
1481	case PGMPOOLKIND_ROOT_32BIT_PD:
1482	case PGMPOOLKIND_ROOT_PAE_PD:
1483	case PGMPOOLKIND_ROOT_PDPT:
1484	{
1485	/* find the head */
1486	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1487	{
1488	Assert(pPage->iMonitoredPrev != pPage->idx);
1489	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1490	}
1491	return pPage;
1492	}
1493
1494	/* ignore, no monitoring. */
1495	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1496	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1497	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1498	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1499	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1500	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1501	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1502	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1503	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1504	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1505	case PGMPOOLKIND_ROOT_NESTED:
1506	break;
1507	default:
1508	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1509	}
1510	}
1511
1512	/* next */
1513	i = pPage->iNext;
1514	} while (i != NIL_PGMPOOL_IDX);
1515	#endif
1516	return NULL;
1517	}
1518
1519
1520	/**
1521	* Enabled write monitoring of a guest page.
1522	*
1523	* @returns VBox status code.
1524	* @retval VINF_SUCCESS on success.
1525	* @retval VERR_PGM_POOL_CLEARED if the registration of the physical handler will cause a light weight pool flush.
1526	* @param pPool The pool.
1527	* @param pPage The cached page.
1528	*/
1529	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1530	{
1531	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1532
1533	/*
1534	* Filter out the relevant kinds.
1535	*/
1536	switch (pPage->enmKind)
1537	{
1538	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1539	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1540	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1541	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1542	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1543	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1544	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
1545	case PGMPOOLKIND_ROOT_PDPT:
1546	break;
1547
1548	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1549	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1550	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1551	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1552	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1553	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1554	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1555	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1556	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1557	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1558	case PGMPOOLKIND_ROOT_NESTED:
1559	/* Nothing to monitor here. */
1560	return VINF_SUCCESS;
1561
1562	case PGMPOOLKIND_ROOT_32BIT_PD:
1563	case PGMPOOLKIND_ROOT_PAE_PD:
1564	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1565	break;
1566	#endif
1567	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
1568	default:
1569	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1570	}
1571
1572	/*
1573	* Install handler.
1574	*/
1575	int rc;
1576	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1577	if (pPageHead)
1578	{
1579	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1580	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1581	pPage->iMonitoredPrev = pPageHead->idx;
1582	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1583	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1584	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1585	pPageHead->iMonitoredNext = pPage->idx;
1586	rc = VINF_SUCCESS;
1587	}
1588	else
1589	{
1590	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1591	PVM pVM = pPool->CTX_SUFF(pVM);
1592	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1593	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1594	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1595	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1596	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1597	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1598	pPool->pszAccessHandler);
1599	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1600	* the heap size should suffice. */
1601	AssertFatalRC(rc);
1602	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
1603	rc = VERR_PGM_POOL_CLEARED;
1604	}
1605	pPage->fMonitored = true;
1606	return rc;
1607	}
1608
1609
1610	/**
1611	* Disables write monitoring of a guest page.
1612	*
1613	* @returns VBox status code.
1614	* @retval VINF_SUCCESS on success.
1615	* @retval VERR_PGM_POOL_CLEARED if the deregistration of the physical handler will cause a light weight pool flush.
1616	* @param pPool The pool.
1617	* @param pPage The cached page.
1618	*/
1619	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1620	{
1621	/*
1622	* Filter out the relevant kinds.
1623	*/
1624	switch (pPage->enmKind)
1625	{
1626	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1627	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1628	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1629	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1630	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1631	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1632	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
1633	case PGMPOOLKIND_ROOT_PDPT:
1634	break;
1635
1636	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1637	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1638	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1639	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1640	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1641	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1642	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1643	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1644	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1645	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1646	case PGMPOOLKIND_ROOT_NESTED:
1647	/* Nothing to monitor here. */
1648	return VINF_SUCCESS;
1649
1650	case PGMPOOLKIND_ROOT_32BIT_PD:
1651	case PGMPOOLKIND_ROOT_PAE_PD:
1652	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1653	break;
1654	#endif
1655	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
1656	default:
1657	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1658	}
1659
1660	/*
1661	* Remove the page from the monitored list or uninstall it if last.
1662	*/
1663	const PVM pVM = pPool->CTX_SUFF(pVM);
1664	int rc;
1665	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1666	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1667	{
1668	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1669	{
1670	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1671	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1672	pNewHead->fCR3Mix = pPage->fCR3Mix;
1673	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1674	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1675	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1676	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1677	pPool->pszAccessHandler);
1678	AssertFatalRCSuccess(rc);
1679	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1680	}
1681	else
1682	{
1683	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1684	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1685	{
1686	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1687	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1688	}
1689	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1690	rc = VINF_SUCCESS;
1691	}
1692	}
1693	else
1694	{
1695	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1696	AssertFatalRC(rc);
1697	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
1698	rc = VERR_PGM_POOL_CLEARED;
1699	}
1700	pPage->fMonitored = false;
1701
1702	/*
1703	* Remove it from the list of modified pages (if in it).
1704	*/
1705	pgmPoolMonitorModifiedRemove(pPool, pPage);
1706
1707	return rc;
1708	}
1709
1710	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
1711
1712	/**
1713	* Set or clear the fCR3Mix attribute in a chain of monitored pages.
1714	*
1715	* @param pPool The Pool.
1716	* @param pPage A page in the chain.
1717	* @param fCR3Mix The new fCR3Mix value.
1718	*/
1719	static void pgmPoolMonitorChainChangeCR3Mix(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCR3Mix)
1720	{
1721	/* current */
1722	pPage->fCR3Mix = fCR3Mix;
1723
1724	/* before */
1725	int16_t idx = pPage->iMonitoredPrev;
1726	while (idx != NIL_PGMPOOL_IDX)
1727	{
1728	pPool->aPages[idx].fCR3Mix = fCR3Mix;
1729	idx = pPool->aPages[idx].iMonitoredPrev;
1730	}
1731
1732	/* after */
1733	idx = pPage->iMonitoredNext;
1734	while (idx != NIL_PGMPOOL_IDX)
1735	{
1736	pPool->aPages[idx].fCR3Mix = fCR3Mix;
1737	idx = pPool->aPages[idx].iMonitoredNext;
1738	}
1739	}
1740
1741
1742	/**
1743	* Installs or modifies monitoring of a CR3 page (special).
1744	*
1745	* We're pretending the CR3 page is shadowed by the pool so we can use the
1746	* generic mechanisms in detecting chained monitoring. (This also gives us a
1747	* tast of what code changes are required to really pool CR3 shadow pages.)
1748	*
1749	* @returns VBox status code.
1750	* @param pPool The pool.
1751	* @param idxRoot The CR3 (root) page index.
1752	* @param GCPhysCR3 The (new) CR3 value.
1753	*/
1754	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3)
1755	{
1756	Assert(idxRoot != NIL_PGMPOOL_IDX && idxRoot < PGMPOOL_IDX_FIRST);
1757	PPGMPOOLPAGE pPage = &pPool->aPages[idxRoot];
1758	LogFlow(("pgmPoolMonitorMonitorCR3: idxRoot=%d pPage=%p:{.GCPhys=%RGp, .fMonitored=%d} GCPhysCR3=%RGp\n",
1759	idxRoot, pPage, pPage->GCPhys, pPage->fMonitored, GCPhysCR3));
1760
1761	/*
1762	* The unlikely case where it already matches.
1763	*/
1764	if (pPage->GCPhys == GCPhysCR3)
1765	{
1766	Assert(pPage->fMonitored);
1767	return VINF_SUCCESS;
1768	}
1769
1770	/*
1771	* Flush the current monitoring and remove it from the hash.
1772	*/
1773	int rc = VINF_SUCCESS;
1774	if (pPage->fMonitored)
1775	{
1776	pgmPoolMonitorChainChangeCR3Mix(pPool, pPage, false);
1777	rc = pgmPoolMonitorFlush(pPool, pPage);
1778	if (rc == VERR_PGM_POOL_CLEARED)
1779	rc = VINF_SUCCESS;
1780	else
1781	AssertFatalRC(rc);
1782	pgmPoolHashRemove(pPool, pPage);
1783	}
1784
1785	/*
1786	* Monitor the page at the new location and insert it into the hash.
1787	*/
1788	pPage->GCPhys = GCPhysCR3;
1789	int rc2 = pgmPoolMonitorInsert(pPool, pPage);
1790	if (rc2 != VERR_PGM_POOL_CLEARED)
1791	{
1792	AssertFatalRC(rc2);
1793	if (rc2 != VINF_SUCCESS && rc == VINF_SUCCESS)
1794	rc = rc2;
1795	}
1796	pgmPoolHashInsert(pPool, pPage);
1797	pgmPoolMonitorChainChangeCR3Mix(pPool, pPage, true);
1798	return rc;
1799	}
1800
1801
1802	/**
1803	* Removes the monitoring of a CR3 page (special).
1804	*
1805	* @returns VBox status code.
1806	* @param pPool The pool.
1807	* @param idxRoot The CR3 (root) page index.
1808	*/
1809	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot)
1810	{
1811	Assert(idxRoot != NIL_PGMPOOL_IDX && idxRoot < PGMPOOL_IDX_FIRST);
1812	PPGMPOOLPAGE pPage = &pPool->aPages[idxRoot];
1813	LogFlow(("pgmPoolMonitorUnmonitorCR3: idxRoot=%d pPage=%p:{.GCPhys=%RGp, .fMonitored=%d}\n",
1814	idxRoot, pPage, pPage->GCPhys, pPage->fMonitored));
1815
1816	if (!pPage->fMonitored)
1817	return VINF_SUCCESS;
1818
1819	pgmPoolMonitorChainChangeCR3Mix(pPool, pPage, false);
1820	int rc = pgmPoolMonitorFlush(pPool, pPage);
1821	if (rc != VERR_PGM_POOL_CLEARED)
1822	AssertFatalRC(rc);
1823	else
1824	rc = VINF_SUCCESS;
1825	pgmPoolHashRemove(pPool, pPage);
1826	Assert(!pPage->fMonitored);
1827	pPage->GCPhys = NIL_RTGCPHYS;
1828	return rc;
1829	}
1830
1831	# endif /* PGMPOOL_WITH_MIXED_PT_CR3 */
1832
1833	/**
1834	* Inserts the page into the list of modified pages.
1835	*
1836	* @param pPool The pool.
1837	* @param pPage The page.
1838	*/
1839	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1840	{
1841	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1842	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1843	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1844	&& pPool->iModifiedHead != pPage->idx,
1845	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1846	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1847	pPool->iModifiedHead, pPool->cModifiedPages));
1848
1849	pPage->iModifiedNext = pPool->iModifiedHead;
1850	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1851	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1852	pPool->iModifiedHead = pPage->idx;
1853	pPool->cModifiedPages++;
1854	#ifdef VBOX_WITH_STATISTICS
1855	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1856	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1857	#endif
1858	}
1859
1860
1861	/**
1862	* Removes the page from the list of modified pages and resets the
1863	* moficiation counter.
1864	*
1865	* @param pPool The pool.
1866	* @param pPage The page which is believed to be in the list of modified pages.
1867	*/
1868	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1869	{
1870	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1871	if (pPool->iModifiedHead == pPage->idx)
1872	{
1873	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1874	pPool->iModifiedHead = pPage->iModifiedNext;
1875	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1876	{
1877	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1878	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1879	}
1880	pPool->cModifiedPages--;
1881	}
1882	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1883	{
1884	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1885	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1886	{
1887	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1888	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1889	}
1890	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1891	pPool->cModifiedPages--;
1892	}
1893	else
1894	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1895	pPage->cModifications = 0;
1896	}
1897
1898
1899	/**
1900	* Zaps the list of modified pages, resetting their modification counters in the process.
1901	*
1902	* @param pVM The VM handle.
1903	*/
1904	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1905	{
1906	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1907	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1908
1909	unsigned cPages = 0; NOREF(cPages);
1910	uint16_t idx = pPool->iModifiedHead;
1911	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1912	while (idx != NIL_PGMPOOL_IDX)
1913	{
1914	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1915	idx = pPage->iModifiedNext;
1916	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1917	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1918	pPage->cModifications = 0;
1919	Assert(++cPages);
1920	}
1921	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1922	pPool->cModifiedPages = 0;
1923	}
1924
1925
1926	/**
1927	* Clear all shadow pages and clear all modification counters.
1928	*
1929	* @param pVM The VM handle.
1930	* @remark Should only be used when monitoring is available, thus placed in
1931	* the PGMPOOL_WITH_MONITORING #ifdef.
1932	*/
1933	void pgmPoolClearAll(PVM pVM)
1934	{
1935	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1936	STAM_PROFILE_START(&pPool->StatClearAll, c);
1937	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1938
1939	/*
1940	* Iterate all the pages until we've encountered all that in use.
1941	* This is simple but not quite optimal solution.
1942	*/
1943	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1944	unsigned cLeft = pPool->cUsedPages;
1945	unsigned iPage = pPool->cCurPages;
1946	while (--iPage >= PGMPOOL_IDX_FIRST)
1947	{
1948	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1949	if (pPage->GCPhys != NIL_RTGCPHYS)
1950	{
1951	switch (pPage->enmKind)
1952	{
1953	/*
1954	* We only care about shadow page tables.
1955	*/
1956	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1957	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1958	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1959	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1960	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1961	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1962	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1963	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1964	{
1965	#ifdef PGMPOOL_WITH_USER_TRACKING
1966	if (pPage->cPresent)
1967	#endif
1968	{
1969	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1970	STAM_PROFILE_START(&pPool->StatZeroPage, z);
1971	ASMMemZeroPage(pvShw);
1972	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
1973	#ifdef PGMPOOL_WITH_USER_TRACKING
1974	pPage->cPresent = 0;
1975	pPage->iFirstPresent = ~0;
1976	#endif
1977	}
1978	}
1979	/* fall thru */
1980
1981	default:
1982	Assert(!pPage->cModifications \|\| ++cModifiedPages);
1983	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
1984	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
1985	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1986	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1987	pPage->cModifications = 0;
1988	break;
1989
1990	}
1991	if (!--cLeft)
1992	break;
1993	}
1994	}
1995
1996	/* swipe the special pages too. */
1997	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
1998	{
1999	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2000	if (pPage->GCPhys != NIL_RTGCPHYS)
2001	{
2002	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2003	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2004	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2005	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2006	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2007	pPage->cModifications = 0;
2008	}
2009	}
2010
2011	#ifndef DEBUG_michael
2012	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2013	#endif
2014	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2015	pPool->cModifiedPages = 0;
2016
2017	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2018	/*
2019	* Clear all the GCPhys links and rebuild the phys ext free list.
2020	*/
2021	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2022	pRam;
2023	pRam = pRam->CTX_SUFF(pNext))
2024	{
2025	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2026	while (iPage-- > 0)
2027	pRam->aPages[iPage].HCPhys &= MM_RAM_FLAGS_NO_REFS_MASK; /** @todo PAGE FLAGS */
2028	}
2029
2030	pPool->iPhysExtFreeHead = 0;
2031	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2032	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2033	for (unsigned i = 0; i < cMaxPhysExts; i++)
2034	{
2035	paPhysExts[i].iNext = i + 1;
2036	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2037	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2038	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2039	}
2040	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2041	#endif
2042
2043
2044	pPool->cPresent = 0;
2045	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2046	}
2047
2048
2049	/**
2050	* Handle SyncCR3 pool tasks
2051	*
2052	* @returns VBox status code.
2053	* @retval VINF_SUCCESS if successfully added.
2054	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2055	* @param pVM The VM handle.
2056	* @remark Should only be used when monitoring is available, thus placed in
2057	* the PGMPOOL_WITH_MONITORING #ifdef.
2058	*/
2059	int pgmPoolSyncCR3(PVM pVM)
2060	{
2061	/*
2062	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2063	* Occasionally we will have to clear all the shadow page tables because we wanted
2064	* to monitor a page which was mapped by too many shadowed page tables. This operation
2065	* sometimes refered to as a 'lightweight flush'.
2066	*/
2067	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2068	pgmPoolMonitorModifiedClearAll(pVM);
2069	else
2070	{
2071	# ifndef IN_RC
2072	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2073	pgmPoolClearAll(pVM);
2074	# else
2075	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2076	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2077	return VINF_PGM_SYNC_CR3;
2078	# endif
2079	}
2080	return VINF_SUCCESS;
2081	}
2082
2083	#endif /* PGMPOOL_WITH_MONITORING */
2084	#ifdef PGMPOOL_WITH_USER_TRACKING
2085
2086	/**
2087	* Frees up at least one user entry.
2088	*
2089	* @returns VBox status code.
2090	* @retval VINF_SUCCESS if successfully added.
2091	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2092	* @param pPool The pool.
2093	* @param iUser The user index.
2094	*/
2095	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2096	{
2097	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2098	#ifdef PGMPOOL_WITH_CACHE
2099	/*
2100	* Just free cached pages in a braindead fashion.
2101	*/
2102	/** @todo walk the age list backwards and free the first with usage. */
2103	int rc = VINF_SUCCESS;
2104	do
2105	{
2106	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2107	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2108	rc = rc2;
2109	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2110	return rc;
2111	#else
2112	/*
2113	* Lazy approach.
2114	*/
2115	/* @todo incompatible with long mode paging (cr3 root will be flushed) */
2116	Assert(!CPUMIsGuestInLongMode(pVM));
2117	pgmPoolFlushAllInt(pPool);
2118	return VERR_PGM_POOL_FLUSHED;
2119	#endif
2120	}
2121
2122
2123	/**
2124	* Inserts a page into the cache.
2125	*
2126	* This will create user node for the page, insert it into the GCPhys
2127	* hash, and insert it into the age list.
2128	*
2129	* @returns VBox status code.
2130	* @retval VINF_SUCCESS if successfully added.
2131	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2132	* @retval VERR_PGM_POOL_CLEARED if the deregistration of the physical handler will cause a light weight pool flush.
2133	* @param pPool The pool.
2134	* @param pPage The cached page.
2135	* @param GCPhys The GC physical address of the page we're gonna shadow.
2136	* @param iUser The user index.
2137	* @param iUserTable The user table index.
2138	*/
2139	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2140	{
2141	int rc = VINF_SUCCESS;
2142	PPGMPOOLUSER pUser = pPool->CTX_SUFF(paUsers);
2143
2144	LogFlow(("pgmPoolTrackInsert iUser %d iUserTable %d\n", iUser, iUserTable));
2145
2146	/*
2147	* Find free a user node.
2148	*/
2149	uint16_t i = pPool->iUserFreeHead;
2150	if (i == NIL_PGMPOOL_USER_INDEX)
2151	{
2152	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2153	if (RT_FAILURE(rc))
2154	return rc;
2155	i = pPool->iUserFreeHead;
2156	}
2157
2158	/*
2159	* Unlink the user node from the free list,
2160	* initialize and insert it into the user list.
2161	*/
2162	pPool->iUserFreeHead = pUser[i].iNext;
2163	pUser[i].iNext = NIL_PGMPOOL_USER_INDEX;
2164	pUser[i].iUser = iUser;
2165	pUser[i].iUserTable = iUserTable;
2166	pPage->iUserHead = i;
2167
2168	/*
2169	* Insert into cache and enable monitoring of the guest page if enabled.
2170	*
2171	* Until we implement caching of all levels, including the CR3 one, we'll
2172	* have to make sure we don't try monitor & cache any recursive reuse of
2173	* a monitored CR3 page. Because all windows versions are doing this we'll
2174	* have to be able to do combined access monitoring, CR3 + PT and
2175	* PD + PT (guest PAE).
2176	*
2177	* Update:
2178	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2179	*/
2180	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2181	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2182	const bool fCanBeMonitored = true;
2183	# else
2184	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2185	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2186	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2187	# endif
2188	# ifdef PGMPOOL_WITH_CACHE
2189	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2190	# endif
2191	if (fCanBeMonitored)
2192	{
2193	# ifdef PGMPOOL_WITH_MONITORING
2194	rc = pgmPoolMonitorInsert(pPool, pPage);
2195	if (rc == VERR_PGM_POOL_CLEARED)
2196	{
2197	/* 'Failed' - free the usage, and keep it in the cache (if enabled). */
2198	# ifndef PGMPOOL_WITH_CACHE
2199	pgmPoolMonitorFlush(pPool, pPage);
2200	rc = VERR_PGM_POOL_FLUSHED;
2201	# endif
2202	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
2203	pUser[i].iNext = pPool->iUserFreeHead;
2204	pUser[i].iUser = NIL_PGMPOOL_IDX;
2205	pPool->iUserFreeHead = i;
2206	}
2207	}
2208	# endif
2209	#endif /* PGMPOOL_WITH_MONITORING */
2210	return rc;
2211	}
2212
2213
2214	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2215	/**
2216	* Adds a user reference to a page.
2217	*
2218	* This will
2219	* This will move the page to the head of the
2220	*
2221	* @returns VBox status code.
2222	* @retval VINF_SUCCESS if successfully added.
2223	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2224	* @param pPool The pool.
2225	* @param pPage The cached page.
2226	* @param iUser The user index.
2227	* @param iUserTable The user table.
2228	*/
2229	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2230	{
2231	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2232
2233	LogFlow(("pgmPoolTrackAddUser iUser %d iUserTable %d\n", iUser, iUserTable));
2234	# ifdef VBOX_STRICT
2235	/*
2236	* Check that the entry doesn't already exists.
2237	*/
2238	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2239	{
2240	uint16_t i = pPage->iUserHead;
2241	do
2242	{
2243	Assert(i < pPool->cMaxUsers);
2244	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2245	i = paUsers[i].iNext;
2246	} while (i != NIL_PGMPOOL_USER_INDEX);
2247	}
2248	# endif
2249
2250	/*
2251	* Allocate a user node.
2252	*/
2253	uint16_t i = pPool->iUserFreeHead;
2254	if (i == NIL_PGMPOOL_USER_INDEX)
2255	{
2256	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2257	if (RT_FAILURE(rc))
2258	return rc;
2259	i = pPool->iUserFreeHead;
2260	}
2261	pPool->iUserFreeHead = paUsers[i].iNext;
2262
2263	/*
2264	* Initialize the user node and insert it.
2265	*/
2266	paUsers[i].iNext = pPage->iUserHead;
2267	paUsers[i].iUser = iUser;
2268	paUsers[i].iUserTable = iUserTable;
2269	pPage->iUserHead = i;
2270
2271	# ifdef PGMPOOL_WITH_CACHE
2272	/*
2273	* Tell the cache to update its replacement stats for this page.
2274	*/
2275	pgmPoolCacheUsed(pPool, pPage);
2276	# endif
2277	return VINF_SUCCESS;
2278	}
2279	# endif /* PGMPOOL_WITH_CACHE */
2280
2281
2282	/**
2283	* Frees a user record associated with a page.
2284	*
2285	* This does not clear the entry in the user table, it simply replaces the
2286	* user record to the chain of free records.
2287	*
2288	* @param pPool The pool.
2289	* @param HCPhys The HC physical address of the shadow page.
2290	* @param iUser The shadow page pool index of the user table.
2291	* @param iUserTable The index into the user table (shadowed).
2292	*/
2293	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2294	{
2295	/*
2296	* Unlink and free the specified user entry.
2297	*/
2298	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2299
2300	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2301	uint16_t i = pPage->iUserHead;
2302	if ( i != NIL_PGMPOOL_USER_INDEX
2303	&& paUsers[i].iUser == iUser
2304	&& paUsers[i].iUserTable == iUserTable)
2305	{
2306	pPage->iUserHead = paUsers[i].iNext;
2307
2308	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2309	paUsers[i].iNext = pPool->iUserFreeHead;
2310	pPool->iUserFreeHead = i;
2311	return;
2312	}
2313
2314	/* General: Linear search. */
2315	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2316	while (i != NIL_PGMPOOL_USER_INDEX)
2317	{
2318	if ( paUsers[i].iUser == iUser
2319	&& paUsers[i].iUserTable == iUserTable)
2320	{
2321	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2322	paUsers[iPrev].iNext = paUsers[i].iNext;
2323	else
2324	pPage->iUserHead = paUsers[i].iNext;
2325
2326	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2327	paUsers[i].iNext = pPool->iUserFreeHead;
2328	pPool->iUserFreeHead = i;
2329	return;
2330	}
2331	iPrev = i;
2332	i = paUsers[i].iNext;
2333	}
2334
2335	/* Fatal: didn't find it */
2336	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2337	iUser, iUserTable, pPage->GCPhys));
2338	}
2339
2340
2341	/**
2342	* Gets the entry size of a shadow table.
2343	*
2344	* @param enmKind The kind of page.
2345	*
2346	* @returns The size of the entry in bytes. That is, 4 or 8.
2347	* @returns If the kind is not for a table, an assertion is raised and 0 is
2348	* returned.
2349	*/
2350	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2351	{
2352	switch (enmKind)
2353	{
2354	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2355	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2356	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2357	case PGMPOOLKIND_ROOT_32BIT_PD:
2358	return 4;
2359
2360	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2361	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2362	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2363	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2364	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2365	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
2366	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2367	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2368	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2369	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
2370	case PGMPOOLKIND_ROOT_PAE_PD:
2371	case PGMPOOLKIND_ROOT_PDPT:
2372	case PGMPOOLKIND_ROOT_NESTED:
2373	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2374	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2375	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2376	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2377	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2378	return 8;
2379
2380	default:
2381	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2382	}
2383	}
2384
2385
2386	/**
2387	* Gets the entry size of a guest table.
2388	*
2389	* @param enmKind The kind of page.
2390	*
2391	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2392	* @returns If the kind is not for a table, an assertion is raised and 0 is
2393	* returned.
2394	*/
2395	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2396	{
2397	switch (enmKind)
2398	{
2399	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2400	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2401	case PGMPOOLKIND_ROOT_32BIT_PD:
2402	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2403	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2404	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
2405	return 4;
2406
2407	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2408	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2409	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2410	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2411	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2412	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
2413	case PGMPOOLKIND_ROOT_PAE_PD:
2414	case PGMPOOLKIND_ROOT_PDPT:
2415	return 8;
2416
2417	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2418	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2419	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2420	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2421	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2422	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2423	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2424	case PGMPOOLKIND_ROOT_NESTED:
2425	/** @todo can we return 0? (nobody is calling this...) */
2426	AssertFailed();
2427	return 0;
2428
2429	default:
2430	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2431	}
2432	}
2433
2434	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2435
2436	/**
2437	* Scans one shadow page table for mappings of a physical page.
2438	*
2439	* @param pVM The VM handle.
2440	* @param pPhysPage The guest page in question.
2441	* @param iShw The shadow page table.
2442	* @param cRefs The number of references made in that PT.
2443	*/
2444	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2445	{
2446	LogFlow(("pgmPoolTrackFlushGCPhysPT: HCPhys=%RHp iShw=%d cRefs=%d\n", pPhysPage->HCPhys, iShw, cRefs));
2447	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2448
2449	/*
2450	* Assert sanity.
2451	*/
2452	Assert(cRefs == 1);
2453	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2454	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2455
2456	/*
2457	* Then, clear the actual mappings to the page in the shadow PT.
2458	*/
2459	switch (pPage->enmKind)
2460	{
2461	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2462	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2463	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2464	{
2465	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2466	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2467	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2468	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2469	{
2470	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2471	pPT->a[i].u = 0;
2472	cRefs--;
2473	if (!cRefs)
2474	return;
2475	}
2476	#ifdef LOG_ENABLED
2477	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2478	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2479	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2480	{
2481	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2482	pPT->a[i].u = 0;
2483	}
2484	#endif
2485	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2486	break;
2487	}
2488
2489	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2490	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2491	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2492	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2493	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2494	{
2495	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2496	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2497	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2498	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2499	{
2500	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2501	pPT->a[i].u = 0;
2502	cRefs--;
2503	if (!cRefs)
2504	return;
2505	}
2506	#ifdef LOG_ENABLED
2507	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2508	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2509	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2510	{
2511	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2512	pPT->a[i].u = 0;
2513	}
2514	#endif
2515	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2516	break;
2517	}
2518
2519	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2520	{
2521	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2522	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2523	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2524	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2525	{
2526	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2527	pPT->a[i].u = 0;
2528	cRefs--;
2529	if (!cRefs)
2530	return;
2531	}
2532	#ifdef LOG_ENABLED
2533	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2534	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2535	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2536	{
2537	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2538	pPT->a[i].u = 0;
2539	}
2540	#endif
2541	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2542	break;
2543	}
2544
2545	default:
2546	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2547	}
2548	}
2549
2550
2551	/**
2552	* Scans one shadow page table for mappings of a physical page.
2553	*
2554	* @param pVM The VM handle.
2555	* @param pPhysPage The guest page in question.
2556	* @param iShw The shadow page table.
2557	* @param cRefs The number of references made in that PT.
2558	*/
2559	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2560	{
2561	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2562	LogFlow(("pgmPoolTrackFlushGCPhysPT: HCPhys=%RHp iShw=%d cRefs=%d\n", pPhysPage->HCPhys, iShw, cRefs));
2563	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2564	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2565	pPhysPage->HCPhys &= MM_RAM_FLAGS_NO_REFS_MASK; /** @todo PAGE FLAGS */
2566	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2567	}
2568
2569
2570	/**
2571	* Flushes a list of shadow page tables mapping the same physical page.
2572	*
2573	* @param pVM The VM handle.
2574	* @param pPhysPage The guest page in question.
2575	* @param iPhysExt The physical cross reference extent list to flush.
2576	*/
2577	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2578	{
2579	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2580	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2581	LogFlow(("pgmPoolTrackFlushGCPhysPTs: HCPhys=%RHp iPhysExt\n", pPhysPage->HCPhys, iPhysExt));
2582
2583	const uint16_t iPhysExtStart = iPhysExt;
2584	PPGMPOOLPHYSEXT pPhysExt;
2585	do
2586	{
2587	Assert(iPhysExt < pPool->cMaxPhysExts);
2588	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2589	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2590	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2591	{
2592	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2593	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2594	}
2595
2596	/* next */
2597	iPhysExt = pPhysExt->iNext;
2598	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2599
2600	/* insert the list into the free list and clear the ram range entry. */
2601	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2602	pPool->iPhysExtFreeHead = iPhysExtStart;
2603	pPhysPage->HCPhys &= MM_RAM_FLAGS_NO_REFS_MASK; /** @todo PAGE FLAGS */
2604
2605	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2606	}
2607
2608	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2609
2610	/**
2611	* Scans all shadow page tables for mappings of a physical page.
2612	*
2613	* This may be slow, but it's most likely more efficient than cleaning
2614	* out the entire page pool / cache.
2615	*
2616	* @returns VBox status code.
2617	* @retval VINF_SUCCESS if all references has been successfully cleared.
2618	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2619	* a page pool cleaning.
2620	*
2621	* @param pVM The VM handle.
2622	* @param pPhysPage The guest page in question.
2623	*/
2624	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2625	{
2626	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2627	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2628	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d HCPhys=%RHp\n",
2629	pPool->cUsedPages, pPool->cPresent, pPhysPage->HCPhys));
2630
2631	#if 1
2632	/*
2633	* There is a limit to what makes sense.
2634	*/
2635	if (pPool->cPresent > 1024)
2636	{
2637	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2638	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2639	return VINF_PGM_GCPHYS_ALIASED;
2640	}
2641	#endif
2642
2643	/*
2644	* Iterate all the pages until we've encountered all that in use.
2645	* This is simple but not quite optimal solution.
2646	*/
2647	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2648	const uint32_t u32 = u64;
2649	unsigned cLeft = pPool->cUsedPages;
2650	unsigned iPage = pPool->cCurPages;
2651	while (--iPage >= PGMPOOL_IDX_FIRST)
2652	{
2653	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2654	if (pPage->GCPhys != NIL_RTGCPHYS)
2655	{
2656	switch (pPage->enmKind)
2657	{
2658	/*
2659	* We only care about shadow page tables.
2660	*/
2661	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2662	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2663	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2664	{
2665	unsigned cPresent = pPage->cPresent;
2666	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2667	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2668	if (pPT->a[i].n.u1Present)
2669	{
2670	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2671	{
2672	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2673	pPT->a[i].u = 0;
2674	}
2675	if (!--cPresent)
2676	break;
2677	}
2678	break;
2679	}
2680
2681	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2682	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2683	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2684	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2685	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2686	{
2687	unsigned cPresent = pPage->cPresent;
2688	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2689	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2690	if (pPT->a[i].n.u1Present)
2691	{
2692	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2693	{
2694	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2695	pPT->a[i].u = 0;
2696	}
2697	if (!--cPresent)
2698	break;
2699	}
2700	break;
2701	}
2702	}
2703	if (!--cLeft)
2704	break;
2705	}
2706	}
2707
2708	pPhysPage->HCPhys &= MM_RAM_FLAGS_NO_REFS_MASK; /** @todo PAGE FLAGS */
2709	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2710	return VINF_SUCCESS;
2711	}
2712
2713
2714	/**
2715	* Clears the user entry in a user table.
2716	*
2717	* This is used to remove all references to a page when flushing it.
2718	*/
2719	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2720	{
2721	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2722	Assert(pUser->iUser < pPool->cCurPages);
2723	uint32_t iUserTable = pUser->iUserTable;
2724
2725	/*
2726	* Map the user page.
2727	*/
2728	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2729	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2730	if (pUserPage->enmKind == PGMPOOLKIND_ROOT_PAE_PD)
2731	{
2732	/* Must translate the fake 2048 entry PD to a 512 PD one since the R0 mapping is not linear. */
2733	Assert(pUser->iUser == PGMPOOL_IDX_PAE_PD);
2734	uint32_t iPdpt = iUserTable / X86_PG_PAE_ENTRIES;
2735	iUserTable %= X86_PG_PAE_ENTRIES;
2736	pUserPage = &pPool->aPages[PGMPOOL_IDX_PAE_PD_0 + iPdpt];
2737	Assert(pUserPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD);
2738	}
2739	#endif
2740	union
2741	{
2742	uint64_t *pau64;
2743	uint32_t *pau32;
2744	} u;
2745	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2746
2747	/* Safety precaution in case we change the paging for other modes too in the future. */
2748	Assert(PGMGetHyperCR3(pPool->CTX_SUFF(pVM)) != pPage->Core.Key);
2749
2750	#ifdef VBOX_STRICT
2751	/*
2752	* Some sanity checks.
2753	*/
2754	switch (pUserPage->enmKind)
2755	{
2756	case PGMPOOLKIND_ROOT_32BIT_PD:
2757	Assert(iUserTable < X86_PG_ENTRIES);
2758	Assert(!(u.pau32[iUserTable] & PGM_PDFLAGS_MAPPING));
2759	break;
2760	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2761	case PGMPOOLKIND_ROOT_PAE_PD:
2762	Assert(iUserTable < 2048 && pUser->iUser == PGMPOOL_IDX_PAE_PD);
2763	AssertMsg(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING), ("%llx %d\n", u.pau64[iUserTable], iUserTable));
2764	break;
2765	# endif
2766	case PGMPOOLKIND_ROOT_PDPT:
2767	Assert(iUserTable < 4);
2768	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2769	break;
2770	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
2771	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2772	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2773	break;
2774	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2775	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2776	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2777	break;
2778	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2779	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2780	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2781	break;
2782	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
2783	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2784	/* GCPhys >> PAGE_SHIFT is the index here */
2785	break;
2786	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2787	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2788	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2789	break;
2790
2791	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2792	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2793	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2794	break;
2795
2796	case PGMPOOLKIND_ROOT_NESTED:
2797	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2798	break;
2799
2800	default:
2801	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2802	break;
2803	}
2804	#endif /* VBOX_STRICT */
2805
2806	/*
2807	* Clear the entry in the user page.
2808	*/
2809	switch (pUserPage->enmKind)
2810	{
2811	/* 32-bit entries */
2812	case PGMPOOLKIND_ROOT_32BIT_PD:
2813	u.pau32[iUserTable] = 0;
2814	break;
2815
2816	/* 64-bit entries */
2817	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
2818	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2819	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2820	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2821	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
2822	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2823	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2824	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2825	case PGMPOOLKIND_ROOT_PAE_PD:
2826	#endif
2827	case PGMPOOLKIND_ROOT_PDPT:
2828	case PGMPOOLKIND_ROOT_NESTED:
2829	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2830	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2831	u.pau64[iUserTable] = 0;
2832	break;
2833
2834	default:
2835	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2836	}
2837	}
2838
2839
2840	/**
2841	* Clears all users of a page.
2842	*/
2843	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2844	{
2845	/*
2846	* Free all the user records.
2847	*/
2848	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2849	uint16_t i = pPage->iUserHead;
2850	while (i != NIL_PGMPOOL_USER_INDEX)
2851	{
2852	/* Clear enter in user table. */
2853	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
2854
2855	/* Free it. */
2856	const uint16_t iNext = paUsers[i].iNext;
2857	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2858	paUsers[i].iNext = pPool->iUserFreeHead;
2859	pPool->iUserFreeHead = i;
2860
2861	/* Next. */
2862	i = iNext;
2863	}
2864	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
2865	}
2866
2867	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2868
2869	/**
2870	* Allocates a new physical cross reference extent.
2871	*
2872	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
2873	* @param pVM The VM handle.
2874	* @param piPhysExt Where to store the phys ext index.
2875	*/
2876	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
2877	{
2878	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2879	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
2880	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
2881	{
2882	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
2883	return NULL;
2884	}
2885	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2886	pPool->iPhysExtFreeHead = pPhysExt->iNext;
2887	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2888	*piPhysExt = iPhysExt;
2889	return pPhysExt;
2890	}
2891
2892
2893	/**
2894	* Frees a physical cross reference extent.
2895	*
2896	* @param pVM The VM handle.
2897	* @param iPhysExt The extent to free.
2898	*/
2899	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
2900	{
2901	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2902	Assert(iPhysExt < pPool->cMaxPhysExts);
2903	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2904	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2905	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2906	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2907	pPool->iPhysExtFreeHead = iPhysExt;
2908	}
2909
2910
2911	/**
2912	* Frees a physical cross reference extent.
2913	*
2914	* @param pVM The VM handle.
2915	* @param iPhysExt The extent to free.
2916	*/
2917	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
2918	{
2919	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2920
2921	const uint16_t iPhysExtStart = iPhysExt;
2922	PPGMPOOLPHYSEXT pPhysExt;
2923	do
2924	{
2925	Assert(iPhysExt < pPool->cMaxPhysExts);
2926	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2927	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2928	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2929
2930	/* next */
2931	iPhysExt = pPhysExt->iNext;
2932	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2933
2934	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2935	pPool->iPhysExtFreeHead = iPhysExtStart;
2936	}
2937
2938
2939	/**
2940	* Insert a reference into a list of physical cross reference extents.
2941	*
2942	* @returns The new ram range flags (top 16-bits).
2943	*
2944	* @param pVM The VM handle.
2945	* @param iPhysExt The physical extent index of the list head.
2946	* @param iShwPT The shadow page table index.
2947	*
2948	*/
2949	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
2950	{
2951	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2952	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2953
2954	/* special common case. */
2955	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
2956	{
2957	paPhysExts[iPhysExt].aidx[2] = iShwPT;
2958	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
2959	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
2960	return iPhysExt \| (MM_RAM_FLAGS_CREFS_PHYSEXT << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT));
2961	}
2962
2963	/* general treatment. */
2964	const uint16_t iPhysExtStart = iPhysExt;
2965	unsigned cMax = 15;
2966	for (;;)
2967	{
2968	Assert(iPhysExt < pPool->cMaxPhysExts);
2969	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
2970	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
2971	{
2972	paPhysExts[iPhysExt].aidx[i] = iShwPT;
2973	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
2974	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
2975	return iPhysExtStart \| (MM_RAM_FLAGS_CREFS_PHYSEXT << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT));
2976	}
2977	if (!--cMax)
2978	{
2979	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
2980	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
2981	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
2982	return MM_RAM_FLAGS_IDX_OVERFLOWED \| (MM_RAM_FLAGS_CREFS_PHYSEXT << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT));
2983	}
2984	}
2985
2986	/* add another extent to the list. */
2987	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
2988	if (!pNew)
2989	{
2990	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
2991	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
2992	return MM_RAM_FLAGS_IDX_OVERFLOWED \| (MM_RAM_FLAGS_CREFS_PHYSEXT << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT));
2993	}
2994	pNew->iNext = iPhysExtStart;
2995	pNew->aidx[0] = iShwPT;
2996	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
2997	return iPhysExt \| (MM_RAM_FLAGS_CREFS_PHYSEXT << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT));
2998	}
2999
3000
3001	/**
3002	* Add a reference to guest physical page where extents are in use.
3003	*
3004	* @returns The new ram range flags (top 16-bits).
3005	*
3006	* @param pVM The VM handle.
3007	* @param u16 The ram range flags (top 16-bits).
3008	* @param iShwPT The shadow page table index.
3009	*/
3010	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3011	{
3012	if ((u16 >> (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) != MM_RAM_FLAGS_CREFS_PHYSEXT)
3013	{
3014	/*
3015	* Convert to extent list.
3016	*/
3017	Assert((u16 >> (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) == 1);
3018	uint16_t iPhysExt;
3019	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3020	if (pPhysExt)
3021	{
3022	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, u16 & MM_RAM_FLAGS_IDX_MASK, iShwPT));
3023	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3024	pPhysExt->aidx[0] = u16 & MM_RAM_FLAGS_IDX_MASK;
3025	pPhysExt->aidx[1] = iShwPT;
3026	u16 = iPhysExt \| (MM_RAM_FLAGS_CREFS_PHYSEXT << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT));
3027	}
3028	else
3029	u16 = MM_RAM_FLAGS_IDX_OVERFLOWED \| (MM_RAM_FLAGS_CREFS_PHYSEXT << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT));
3030	}
3031	else if (u16 != (MM_RAM_FLAGS_IDX_OVERFLOWED \| (MM_RAM_FLAGS_CREFS_PHYSEXT << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT))))
3032	{
3033	/*
3034	* Insert into the extent list.
3035	*/
3036	u16 = pgmPoolTrackPhysExtInsert(pVM, u16 & MM_RAM_FLAGS_IDX_MASK, iShwPT);
3037	}
3038	else
3039	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3040	return u16;
3041	}
3042
3043
3044	/**
3045	* Clear references to guest physical memory.
3046	*
3047	* @param pPool The pool.
3048	* @param pPage The page.
3049	* @param pPhysPage Pointer to the aPages entry in the ram range.
3050	*/
3051	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3052	{
3053	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
3054	AssertFatalMsg(cRefs == MM_RAM_FLAGS_CREFS_PHYSEXT, ("cRefs=%d HCPhys=%RHp pPage=%p:{.idx=%d}\n", cRefs, pPhysPage->HCPhys, pPage, pPage->idx));
3055
3056	uint16_t iPhysExt = (pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK;
3057	if (iPhysExt != MM_RAM_FLAGS_IDX_OVERFLOWED)
3058	{
3059	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3060	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3061	do
3062	{
3063	Assert(iPhysExt < pPool->cMaxPhysExts);
3064
3065	/*
3066	* Look for the shadow page and check if it's all freed.
3067	*/
3068	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3069	{
3070	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3071	{
3072	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3073
3074	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3075	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3076	{
3077	LogFlow(("pgmPoolTrackPhysExtDerefGCPhys: HCPhys=%RX64 idx=%d\n", pPhysPage->HCPhys, pPage->idx));
3078	return;
3079	}
3080
3081	/* we can free the node. */
3082	PVM pVM = pPool->CTX_SUFF(pVM);
3083	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3084	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3085	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3086	{
3087	/* lonely node */
3088	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3089	LogFlow(("pgmPoolTrackPhysExtDerefGCPhys: HCPhys=%RX64 idx=%d lonely\n", pPhysPage->HCPhys, pPage->idx));
3090	pPhysPage->HCPhys &= MM_RAM_FLAGS_NO_REFS_MASK; /** @todo PAGE FLAGS */
3091	}
3092	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3093	{
3094	/* head */
3095	LogFlow(("pgmPoolTrackPhysExtDerefGCPhys: HCPhys=%RX64 idx=%d head\n", pPhysPage->HCPhys, pPage->idx));
3096	pPhysPage->HCPhys = (pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) /** @todo PAGE FLAGS */
3097	\| ((uint64_t)MM_RAM_FLAGS_CREFS_PHYSEXT << MM_RAM_FLAGS_CREFS_SHIFT)
3098	\| ((uint64_t)iPhysExtNext << MM_RAM_FLAGS_IDX_SHIFT);
3099	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3100	}
3101	else
3102	{
3103	/* in list */
3104	LogFlow(("pgmPoolTrackPhysExtDerefGCPhys: HCPhys=%RX64 idx=%d\n", pPhysPage->HCPhys, pPage->idx));
3105	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3106	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3107	}
3108	iPhysExt = iPhysExtNext;
3109	return;
3110	}
3111	}
3112
3113	/* next */
3114	iPhysExtPrev = iPhysExt;
3115	iPhysExt = paPhysExts[iPhysExt].iNext;
3116	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3117
3118	AssertFatalMsgFailed(("not-found! cRefs=%d HCPhys=%RHp pPage=%p:{.idx=%d}\n", cRefs, pPhysPage->HCPhys, pPage, pPage->idx));
3119	}
3120	else /* nothing to do */
3121	LogFlow(("pgmPoolTrackPhysExtDerefGCPhys: HCPhys=%RX64\n", pPhysPage->HCPhys));
3122	}
3123
3124
3125	/**
3126	* Clear references to guest physical memory.
3127	*
3128	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3129	* is assumed to be correct, so the linear search can be skipped and we can assert
3130	* at an earlier point.
3131	*
3132	* @param pPool The pool.
3133	* @param pPage The page.
3134	* @param HCPhys The host physical address corresponding to the guest page.
3135	* @param GCPhys The guest physical address corresponding to HCPhys.
3136	*/
3137	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3138	{
3139	/*
3140	* Walk range list.
3141	*/
3142	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3143	while (pRam)
3144	{
3145	RTGCPHYS off = GCPhys - pRam->GCPhys;
3146	if (off < pRam->cb)
3147	{
3148	/* does it match? */
3149	const unsigned iPage = off >> PAGE_SHIFT;
3150	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3151	#ifdef LOG_ENABLED
3152	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3153	Log(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3154	#endif
3155	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3156	{
3157	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3158	return;
3159	}
3160	break;
3161	}
3162	pRam = pRam->CTX_SUFF(pNext);
3163	}
3164	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3165	}
3166
3167
3168	/**
3169	* Clear references to guest physical memory.
3170	*
3171	* @param pPool The pool.
3172	* @param pPage The page.
3173	* @param HCPhys The host physical address corresponding to the guest page.
3174	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3175	*/
3176	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3177	{
3178	/*
3179	* Walk range list.
3180	*/
3181	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3182	while (pRam)
3183	{
3184	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3185	if (off < pRam->cb)
3186	{
3187	/* does it match? */
3188	const unsigned iPage = off >> PAGE_SHIFT;
3189	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3190	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3191	{
3192	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3193	return;
3194	}
3195	break;
3196	}
3197	pRam = pRam->CTX_SUFF(pNext);
3198	}
3199
3200	/*
3201	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3202	*/
3203	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3204	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3205	while (pRam)
3206	{
3207	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3208	while (iPage-- > 0)
3209	{
3210	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3211	{
3212	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3213	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3214	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3215	return;
3216	}
3217	}
3218	pRam = pRam->CTX_SUFF(pNext);
3219	}
3220
3221	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3222	}
3223
3224
3225	/**
3226	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3227	*
3228	* @param pPool The pool.
3229	* @param pPage The page.
3230	* @param pShwPT The shadow page table (mapping of the page).
3231	* @param pGstPT The guest page table.
3232	*/
3233	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3234	{
3235	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3236	if (pShwPT->a[i].n.u1Present)
3237	{
3238	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3239	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3240	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3241	if (!--pPage->cPresent)
3242	break;
3243	}
3244	}
3245
3246
3247	/**
3248	* Clear references to guest physical memory in a PAE / 32-bit page table.
3249	*
3250	* @param pPool The pool.
3251	* @param pPage The page.
3252	* @param pShwPT The shadow page table (mapping of the page).
3253	* @param pGstPT The guest page table (just a half one).
3254	*/
3255	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3256	{
3257	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3258	if (pShwPT->a[i].n.u1Present)
3259	{
3260	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX32 hint=%RX32\n",
3261	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3262	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3263	}
3264	}
3265
3266
3267	/**
3268	* Clear references to guest physical memory in a PAE / PAE page table.
3269	*
3270	* @param pPool The pool.
3271	* @param pPage The page.
3272	* @param pShwPT The shadow page table (mapping of the page).
3273	* @param pGstPT The guest page table.
3274	*/
3275	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3276	{
3277	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3278	if (pShwPT->a[i].n.u1Present)
3279	{
3280	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3281	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3282	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3283	}
3284	}
3285
3286
3287	/**
3288	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3289	*
3290	* @param pPool The pool.
3291	* @param pPage The page.
3292	* @param pShwPT The shadow page table (mapping of the page).
3293	*/
3294	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3295	{
3296	RTGCPHYS GCPhys = pPage->GCPhys;
3297	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3298	if (pShwPT->a[i].n.u1Present)
3299	{
3300	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3301	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3302	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3303	}
3304	}
3305
3306
3307	/**
3308	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3309	*
3310	* @param pPool The pool.
3311	* @param pPage The page.
3312	* @param pShwPT The shadow page table (mapping of the page).
3313	*/
3314	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3315	{
3316	RTGCPHYS GCPhys = pPage->GCPhys;
3317	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3318	if (pShwPT->a[i].n.u1Present)
3319	{
3320	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3321	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3322	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3323	}
3324	}
3325
3326	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3327
3328	/**
3329	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3330	*
3331	* @param pPool The pool.
3332	* @param pPage The page.
3333	* @param pShwPD The shadow page directory (mapping of the page).
3334	*/
3335	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3336	{
3337	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3338	{
3339	if (pShwPD->a[i].n.u1Present)
3340	{
3341	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3342	if (pSubPage)
3343	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3344	else
3345	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3346	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3347	}
3348	}
3349	}
3350
3351
3352	/**
3353	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3354	*
3355	* @param pPool The pool.
3356	* @param pPage The page.
3357	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3358	*/
3359	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3360	{
3361	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3362	{
3363	if (pShwPDPT->a[i].n.u1Present)
3364	{
3365	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3366	if (pSubPage)
3367	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3368	else
3369	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3370	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3371	}
3372	}
3373	}
3374
3375
3376	/**
3377	* Clear references to shadowed pages in a 64-bit level 4 page table.
3378	*
3379	* @param pPool The pool.
3380	* @param pPage The page.
3381	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3382	*/
3383	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3384	{
3385	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3386	{
3387	if (pShwPML4->a[i].n.u1Present)
3388	{
3389	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3390	if (pSubPage)
3391	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3392	else
3393	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3394	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3395	}
3396	}
3397	}
3398
3399
3400	/**
3401	* Clear references to shadowed pages in an EPT page table.
3402	*
3403	* @param pPool The pool.
3404	* @param pPage The page.
3405	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3406	*/
3407	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3408	{
3409	RTGCPHYS GCPhys = pPage->GCPhys;
3410	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3411	if (pShwPT->a[i].n.u1Present)
3412	{
3413	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3414	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3415	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3416	}
3417	}
3418
3419
3420	/**
3421	* Clear references to shadowed pages in an EPT page directory.
3422	*
3423	* @param pPool The pool.
3424	* @param pPage The page.
3425	* @param pShwPD The shadow page directory (mapping of the page).
3426	*/
3427	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3428	{
3429	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3430	{
3431	if (pShwPD->a[i].n.u1Present)
3432	{
3433	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3434	if (pSubPage)
3435	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3436	else
3437	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3438	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3439	}
3440	}
3441	}
3442
3443
3444	/**
3445	* Clear references to shadowed pages in an EPT page directory pointer table.
3446	*
3447	* @param pPool The pool.
3448	* @param pPage The page.
3449	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3450	*/
3451	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3452	{
3453	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3454	{
3455	if (pShwPDPT->a[i].n.u1Present)
3456	{
3457	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3458	if (pSubPage)
3459	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3460	else
3461	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3462	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3463	}
3464	}
3465	}
3466
3467
3468	/**
3469	* Clears all references made by this page.
3470	*
3471	* This includes other shadow pages and GC physical addresses.
3472	*
3473	* @param pPool The pool.
3474	* @param pPage The page.
3475	*/
3476	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3477	{
3478	/*
3479	* Map the shadow page and take action according to the page kind.
3480	*/
3481	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
3482	switch (pPage->enmKind)
3483	{
3484	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3485	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3486	{
3487	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3488	void *pvGst;
3489	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3490	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3491	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3492	break;
3493	}
3494
3495	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3496	{
3497	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3498	void *pvGst;
3499	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3500	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3501	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3502	break;
3503	}
3504
3505	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3506	{
3507	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3508	void *pvGst;
3509	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3510	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3511	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3512	break;
3513	}
3514
3515	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3516	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3517	{
3518	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3519	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3520	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3521	break;
3522	}
3523
3524	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3525	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3526	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3527	{
3528	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3529	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3530	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3531	break;
3532	}
3533
3534	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3535	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3536	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3537	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3538	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3539	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3540	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3541	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3542	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3543	break;
3544	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3545
3546	case PGMPOOLKIND_PAE_PD_FOR_32BIT_PD:
3547	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3548	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3549	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3550	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3551	break;
3552
3553	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3554	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3555	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3556	break;
3557
3558	case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
3559	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3560	break;
3561
3562	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3563	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3564	break;
3565
3566	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3567	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3568	break;
3569
3570	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3571	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3572	break;
3573
3574	default:
3575	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3576	}
3577
3578	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3579	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3580	ASMMemZeroPage(pvShw);
3581	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3582	pPage->fZeroed = true;
3583	}
3584
3585	#endif /* PGMPOOL_WITH_USER_TRACKING */
3586
3587	/**
3588	* Flushes all the special root pages as part of a pgmPoolFlushAllInt operation.
3589	*
3590	* @param pPool The pool.
3591	*/
3592	static void pgmPoolFlushAllSpecialRoots(PPGMPOOL pPool)
3593	{
3594	/*
3595	* These special pages are all mapped into the indexes 1..PGMPOOL_IDX_FIRST.
3596	*/
3597	Assert(NIL_PGMPOOL_IDX == 0);
3598	for (unsigned i = 1; i < PGMPOOL_IDX_FIRST; i++)
3599	{
3600	/*
3601	* Get the page address.
3602	*/
3603	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3604	union
3605	{
3606	uint64_t *pau64;
3607	uint32_t *pau32;
3608	} u;
3609
3610	/*
3611	* Mark stuff not present.
3612	*/
3613	switch (pPage->enmKind)
3614	{
3615	case PGMPOOLKIND_ROOT_32BIT_PD:
3616	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
3617	for (unsigned iPage = 0; iPage < X86_PG_ENTRIES; iPage++)
3618	if ((u.pau32[iPage] & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == X86_PDE_P)
3619	u.pau32[iPage] = 0;
3620	break;
3621
3622	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3623	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
3624	for (unsigned iPage = 0; iPage < X86_PG_PAE_ENTRIES; iPage++)
3625	if ((u.pau64[iPage] & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == X86_PDE_P)
3626	u.pau64[iPage] = 0;
3627	break;
3628
3629	case PGMPOOLKIND_ROOT_PDPT:
3630	/* Not root of shadowed pages currently, ignore it. */
3631	break;
3632
3633	case PGMPOOLKIND_ROOT_NESTED:
3634	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
3635	ASMMemZero32(u.pau64, PAGE_SIZE);
3636	break;
3637	}
3638	}
3639
3640	/*
3641	* Paranoia (to be removed), flag a global CR3 sync.
3642	*/
3643	VM_FF_SET(pPool->CTX_SUFF(pVM), VM_FF_PGM_SYNC_CR3);
3644	}
3645
3646
3647	/**
3648	* Flushes the entire cache.
3649	*
3650	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
3651	* and execute this CR3 flush.
3652	*
3653	* @param pPool The pool.
3654	*/
3655	static void pgmPoolFlushAllInt(PPGMPOOL pPool)
3656	{
3657	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
3658	LogFlow(("pgmPoolFlushAllInt:\n"));
3659
3660	/*
3661	* If there are no pages in the pool, there is nothing to do.
3662	*/
3663	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
3664	{
3665	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3666	return;
3667	}
3668
3669	/*
3670	* Nuke the free list and reinsert all pages into it.
3671	*/
3672	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
3673	{
3674	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3675
3676	#ifdef IN_RING3
3677	Assert(pPage->Core.Key == MMPage2Phys(pPool->pVMR3, pPage->pvPageR3));
3678	#endif
3679	#ifdef PGMPOOL_WITH_MONITORING
3680	if (pPage->fMonitored)
3681	pgmPoolMonitorFlush(pPool, pPage);
3682	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3683	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3684	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3685	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3686	pPage->cModifications = 0;
3687	#endif
3688	pPage->GCPhys = NIL_RTGCPHYS;
3689	pPage->enmKind = PGMPOOLKIND_FREE;
3690	Assert(pPage->idx == i);
3691	pPage->iNext = i + 1;
3692	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
3693	pPage->fSeenNonGlobal = false;
3694	pPage->fMonitored= false;
3695	pPage->fCached = false;
3696	pPage->fReusedFlushPending = false;
3697	pPage->fCR3Mix = false;
3698	#ifdef PGMPOOL_WITH_USER_TRACKING
3699	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3700	#endif
3701	#ifdef PGMPOOL_WITH_CACHE
3702	pPage->iAgeNext = NIL_PGMPOOL_IDX;
3703	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3704	#endif
3705	}
3706	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
3707	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
3708	pPool->cUsedPages = 0;
3709
3710	#ifdef PGMPOOL_WITH_USER_TRACKING
3711	/*
3712	* Zap and reinitialize the user records.
3713	*/
3714	pPool->cPresent = 0;
3715	pPool->iUserFreeHead = 0;
3716	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3717	const unsigned cMaxUsers = pPool->cMaxUsers;
3718	for (unsigned i = 0; i < cMaxUsers; i++)
3719	{
3720	paUsers[i].iNext = i + 1;
3721	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3722	paUsers[i].iUserTable = 0xfffffffe;
3723	}
3724	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
3725	#endif
3726
3727	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3728	/*
3729	* Clear all the GCPhys links and rebuild the phys ext free list.
3730	*/
3731	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3732	pRam;
3733	pRam = pRam->CTX_SUFF(pNext))
3734	{
3735	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3736	while (iPage-- > 0)
3737	pRam->aPages[iPage].HCPhys &= MM_RAM_FLAGS_NO_REFS_MASK; /** @todo PAGE FLAGS */
3738	}
3739
3740	pPool->iPhysExtFreeHead = 0;
3741	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3742	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
3743	for (unsigned i = 0; i < cMaxPhysExts; i++)
3744	{
3745	paPhysExts[i].iNext = i + 1;
3746	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
3747	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
3748	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
3749	}
3750	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3751	#endif
3752
3753	#ifdef PGMPOOL_WITH_MONITORING
3754	/*
3755	* Just zap the modified list.
3756	*/
3757	pPool->cModifiedPages = 0;
3758	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
3759	#endif
3760
3761	#ifdef PGMPOOL_WITH_CACHE
3762	/*
3763	* Clear the GCPhys hash and the age list.
3764	*/
3765	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
3766	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
3767	pPool->iAgeHead = NIL_PGMPOOL_IDX;
3768	pPool->iAgeTail = NIL_PGMPOOL_IDX;
3769	#endif
3770
3771	/*
3772	* Flush all the special root pages.
3773	* Reinsert active pages into the hash and ensure monitoring chains are correct.
3774	*/
3775	pgmPoolFlushAllSpecialRoots(pPool);
3776	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
3777	{
3778	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3779	pPage->iNext = NIL_PGMPOOL_IDX;
3780	#ifdef PGMPOOL_WITH_MONITORING
3781	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3782	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3783	pPage->cModifications = 0;
3784	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
3785	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3786	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3787	if (pPage->fMonitored)
3788	{
3789	PVM pVM = pPool->CTX_SUFF(pVM);
3790	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
3791	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
3792	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
3793	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
3794	pPool->pszAccessHandler);
3795	AssertFatalRCSuccess(rc);
3796	# ifdef PGMPOOL_WITH_CACHE
3797	pgmPoolHashInsert(pPool, pPage);
3798	# endif
3799	}
3800	#endif
3801	#ifdef PGMPOOL_WITH_USER_TRACKING
3802	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
3803	#endif
3804	#ifdef PGMPOOL_WITH_CACHE
3805	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
3806	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
3807	#endif
3808	}
3809
3810	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3811	}
3812
3813
3814	/**
3815	* Flushes a pool page.
3816	*
3817	* This moves the page to the free list after removing all user references to it.
3818	* In GC this will cause a CR3 reload if the page is traced back to an active root page.
3819	*
3820	* @returns VBox status code.
3821	* @retval VINF_SUCCESS on success.
3822	* @retval VERR_PGM_POOL_CLEARED if the deregistration of the physical handler will cause a light weight pool flush.
3823	* @param pPool The pool.
3824	* @param HCPhys The HC physical address of the shadow page.
3825	*/
3826	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3827	{
3828	int rc = VINF_SUCCESS;
3829	STAM_PROFILE_START(&pPool->StatFlushPage, f);
3830	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%d, .GCPhys=%RGp}\n",
3831	pPage, pPage->Core.Key, pPage->idx, pPage->enmKind, pPage->GCPhys));
3832
3833	/*
3834	* Quietly reject any attempts at flushing any of the special root pages.
3835	*/
3836	if (pPage->idx < PGMPOOL_IDX_FIRST)
3837	{
3838	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
3839	return VINF_SUCCESS;
3840	}
3841
3842	/*
3843	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
3844	*/
3845	if (PGMGetHyperCR3(pPool->CTX_SUFF(pVM)) == pPage->Core.Key)
3846	{
3847	AssertMsg(pPage->enmKind == PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
3848	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(pPool->CTX_SUFF(pVM)), pPage->Core.Key, pPage->enmKind));
3849	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
3850	return VINF_SUCCESS;
3851	}
3852
3853	/*
3854	* Mark the page as being in need of a ASMMemZeroPage().
3855	*/
3856	pPage->fZeroed = false;
3857
3858	#ifdef PGMPOOL_WITH_USER_TRACKING
3859	/*
3860	* Clear the page.
3861	*/
3862	pgmPoolTrackClearPageUsers(pPool, pPage);
3863	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
3864	pgmPoolTrackDeref(pPool, pPage);
3865	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
3866	#endif
3867
3868	#ifdef PGMPOOL_WITH_CACHE
3869	/*
3870	* Flush it from the cache.
3871	*/
3872	pgmPoolCacheFlushPage(pPool, pPage);
3873	#endif /* PGMPOOL_WITH_CACHE */
3874
3875	#ifdef PGMPOOL_WITH_MONITORING
3876	/*
3877	* Deregistering the monitoring.
3878	*/
3879	if (pPage->fMonitored)
3880	rc = pgmPoolMonitorFlush(pPool, pPage);
3881	#endif
3882
3883	/*
3884	* Free the page.
3885	*/
3886	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
3887	pPage->iNext = pPool->iFreeHead;
3888	pPool->iFreeHead = pPage->idx;
3889	pPage->enmKind = PGMPOOLKIND_FREE;
3890	pPage->GCPhys = NIL_RTGCPHYS;
3891	pPage->fReusedFlushPending = false;
3892
3893	pPool->cUsedPages--;
3894	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
3895	return rc;
3896	}
3897
3898
3899	/**
3900	* Frees a usage of a pool page.
3901	*
3902	* The caller is responsible to updating the user table so that it no longer
3903	* references the shadow page.
3904	*
3905	* @param pPool The pool.
3906	* @param HCPhys The HC physical address of the shadow page.
3907	* @param iUser The shadow page pool index of the user table.
3908	* @param iUserTable The index into the user table (shadowed).
3909	*/
3910	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
3911	{
3912	STAM_PROFILE_START(&pPool->StatFree, a);
3913	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%d} iUser=%#x iUserTable=%#x\n",
3914	pPage, pPage->Core.Key, pPage->idx, pPage->enmKind, iUser, iUserTable));
3915	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
3916	#ifdef PGMPOOL_WITH_USER_TRACKING
3917	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
3918	#endif
3919	#ifdef PGMPOOL_WITH_CACHE
3920	if (!pPage->fCached)
3921	#endif
3922	pgmPoolFlushPage(pPool, pPage); /* ASSUMES that VERR_PGM_POOL_CLEARED can be ignored here. */
3923	STAM_PROFILE_STOP(&pPool->StatFree, a);
3924	}
3925
3926
3927	/**
3928	* Makes one or more free page free.
3929	*
3930	* @returns VBox status code.
3931	* @retval VINF_SUCCESS on success.
3932	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
3933	*
3934	* @param pPool The pool.
3935	* @param iUser The user of the page.
3936	*/
3937	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, uint16_t iUser)
3938	{
3939	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
3940
3941	/*
3942	* If the pool isn't full grown yet, expand it.
3943	*/
3944	if (pPool->cCurPages < pPool->cMaxPages)
3945	{
3946	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
3947	#ifdef IN_RING3
3948	int rc = PGMR3PoolGrow(pPool->pVMR3);
3949	#else
3950	int rc = CTXALLMID(VMM, CallHost)(pPool->CTX_SUFF(pVM), VMMCALLHOST_PGM_POOL_GROW, 0);
3951	#endif
3952	if (RT_FAILURE(rc))
3953	return rc;
3954	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
3955	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
3956	return VINF_SUCCESS;
3957	}
3958
3959	#ifdef PGMPOOL_WITH_CACHE
3960	/*
3961	* Free one cached page.
3962	*/
3963	return pgmPoolCacheFreeOne(pPool, iUser);
3964	#else
3965	/*
3966	* Flush the pool.
3967	* If we have tracking enabled, it should be possible to come up with
3968	* a cheap replacement strategy...
3969	*/
3970	/* @todo incompatible with long mode paging (cr3 root will be flushed) */
3971	Assert(!CPUMIsGuestInLongMode(pVM));
3972	pgmPoolFlushAllInt(pPool);
3973	return VERR_PGM_POOL_FLUSHED;
3974	#endif
3975	}
3976
3977
3978	/**
3979	* Allocates a page from the pool.
3980	*
3981	* This page may actually be a cached page and not in need of any processing
3982	* on the callers part.
3983	*
3984	* @returns VBox status code.
3985	* @retval VINF_SUCCESS if a NEW page was allocated.
3986	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
3987	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
3988	* @param pVM The VM handle.
3989	* @param GCPhys The GC physical address of the page we're gonna shadow.
3990	* For 4MB and 2MB PD entries, it's the first address the
3991	* shadow PT is covering.
3992	* @param enmKind The kind of mapping.
3993	* @param iUser The shadow page pool index of the user table.
3994	* @param iUserTable The index into the user table (shadowed).
3995	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
3996	*/
3997	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
3998	{
3999	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4000	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4001	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%d iUser=%#x iUserTable=%#x\n", GCPhys, enmKind, iUser, iUserTable));
4002	*ppPage = NULL;
4003
4004	#ifdef PGMPOOL_WITH_CACHE
4005	if (pPool->fCacheEnabled)
4006	{
4007	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, iUser, iUserTable, ppPage);
4008	if (RT_SUCCESS(rc2))
4009	{
4010	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4011	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4012	return rc2;
4013	}
4014	}
4015	#endif
4016
4017	/*
4018	* Allocate a new one.
4019	*/
4020	int rc = VINF_SUCCESS;
4021	uint16_t iNew = pPool->iFreeHead;
4022	if (iNew == NIL_PGMPOOL_IDX)
4023	{
4024	rc = pgmPoolMakeMoreFreePages(pPool, iUser);
4025	if (RT_FAILURE(rc))
4026	{
4027	if (rc != VERR_PGM_POOL_CLEARED)
4028	{
4029	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4030	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4031	return rc;
4032	}
4033	Log(("pgmPoolMakeMoreFreePages failed with %Rrc -> return VERR_PGM_POOL_FLUSHED\n", rc));
4034	rc = VERR_PGM_POOL_FLUSHED;
4035	}
4036	iNew = pPool->iFreeHead;
4037	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4038	}
4039
4040	/* unlink the free head */
4041	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4042	pPool->iFreeHead = pPage->iNext;
4043	pPage->iNext = NIL_PGMPOOL_IDX;
4044
4045	/*
4046	* Initialize it.
4047	*/
4048	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4049	pPage->enmKind = enmKind;
4050	pPage->GCPhys = GCPhys;
4051	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4052	pPage->fMonitored = false;
4053	pPage->fCached = false;
4054	pPage->fReusedFlushPending = false;
4055	pPage->fCR3Mix = false;
4056	#ifdef PGMPOOL_WITH_MONITORING
4057	pPage->cModifications = 0;
4058	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4059	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4060	#endif
4061	#ifdef PGMPOOL_WITH_USER_TRACKING
4062	pPage->cPresent = 0;
4063	pPage->iFirstPresent = ~0;
4064
4065	/*
4066	* Insert into the tracking and cache. If this fails, free the page.
4067	*/
4068	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4069	if (RT_FAILURE(rc3))
4070	{
4071	if (rc3 != VERR_PGM_POOL_CLEARED)
4072	{
4073	pPool->cUsedPages--;
4074	pPage->enmKind = PGMPOOLKIND_FREE;
4075	pPage->GCPhys = NIL_RTGCPHYS;
4076	pPage->iNext = pPool->iFreeHead;
4077	pPool->iFreeHead = pPage->idx;
4078	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4079	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4080	return rc3;
4081	}
4082	Log(("pgmPoolTrackInsert failed with %Rrc -> return VERR_PGM_POOL_FLUSHED\n", rc3));
4083	rc = VERR_PGM_POOL_FLUSHED;
4084	}
4085	#endif /* PGMPOOL_WITH_USER_TRACKING */
4086
4087	/*
4088	* Commit the allocation, clear the page and return.
4089	*/
4090	#ifdef VBOX_WITH_STATISTICS
4091	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4092	pPool->cUsedPagesHigh = pPool->cUsedPages;
4093	#endif
4094
4095	if (!pPage->fZeroed)
4096	{
4097	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4098	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4099	ASMMemZeroPage(pv);
4100	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4101	}
4102
4103	*ppPage = pPage;
4104	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4105	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4106	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4107	return rc;
4108	}
4109
4110
4111	/**
4112	* Frees a usage of a pool page.
4113	*
4114	* @param pVM The VM handle.
4115	* @param HCPhys The HC physical address of the shadow page.
4116	* @param iUser The shadow page pool index of the user table.
4117	* @param iUserTable The index into the user table (shadowed).
4118	*/
4119	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4120	{
4121	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4122	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4123	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4124	}
4125
4126
4127	/**
4128	* Gets a in-use page in the pool by it's physical address.
4129	*
4130	* @returns Pointer to the page.
4131	* @param pVM The VM handle.
4132	* @param HCPhys The HC physical address of the shadow page.
4133	* @remark This function will NEVER return NULL. It will assert if HCPhys is invalid.
4134	*/
4135	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys)
4136	{
4137	/** @todo profile this! */
4138	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4139	PPGMPOOLPAGE pPage = pgmPoolGetPage(pPool, HCPhys);
4140	Log3(("pgmPoolGetPageByHCPhys: HCPhys=%RHp -> %p:{.idx=%d .GCPhys=%RGp .enmKind=%d}\n",
4141	HCPhys, pPage, pPage->idx, pPage->GCPhys, pPage->enmKind));
4142	return pPage;
4143	}
4144
4145
4146	/**
4147	* Flushes the entire cache.
4148	*
4149	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4150	* and execute this CR3 flush.
4151	*
4152	* @param pPool The pool.
4153	*/
4154	void pgmPoolFlushAll(PVM pVM)
4155	{
4156	LogFlow(("pgmPoolFlushAll:\n"));
4157	pgmPoolFlushAllInt(pVM->pgm.s.CTX_SUFF(pPool));
4158	}
4159

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 15348

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