PGMAllPool.cpp@ 19690

Last change on this file since 19690 was 19690, checked in by vboxsync, 16 years ago
More pgm pool locking.
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1	/* $Id: PGMAllPool.cpp 19690 2009-05-14 11:49:00Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	__BEGIN_DECLS
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	__END_DECLS
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pCpu The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
249	{
250	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	uShw.pPT->a[iShw].u = 0;
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	uShw.pPTPae->a[iShw].u = 0;
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	uShw.pPDPae->a[iShw+i].u = 0;
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pCpu
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	uShw.pPDPae->a[iShw2].u = 0;
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	uShw.pPTPae->a[iShw].u = 0;
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pCpu
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	uShw.pPTPae->a[iShw2].u = 0;
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	uShw.pPD->a[iShw].u = 0;
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pCpu
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	uShw.pPD->a[iShw2].u = 0;
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	uShw.pPD->a[iShw].u = 0;
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	uShw.pPDPae->a[iShw].u = 0;
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pCpu
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	uShw.pPDPae->a[iShw2].u = 0;
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	uShw.pPDPT->a[iShw].u = 0;
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pCpu
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	uShw.pPDPT->a[iShw2].u = 0;
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	uShw.pPDPae->a[iShw].u = 0;
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pCpu
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	uShw.pPDPae->a[iShw2].u = 0;
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	uShw.pPDPT->a[iShw].u = 0;
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pCpu
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	uShw.pPDPT->a[iShw2].u = 0;
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	uShw.pPML4->a[iShw].u = 0;
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pCpu
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	uShw.pPML4->a[iShw2].u = 0;
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pCpu The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pCpu->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pPage The page in question.
823	* @param pRegFrame Trap register frame.
824	* @param pCpu The disassembly info for the faulting instruction.
825	* @param pvFault The fault address.
826	*
827	* @remark The REP prefix check is left to the caller because of STOSD/W.
828	*/
829	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PPGMPOOLPAGE pPage, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
830	{
831	#ifndef IN_RC
832	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
833	if ( HWACCMHasPendingIrq(pVM)
834	&& (pRegFrame->rsp - pvFault) < 32)
835	{
836	/* Fault caused by stack writes while trying to inject an interrupt event. */
837	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
838	return true;
839	}
840	#else
841	NOREF(pVM); NOREF(pvFault);
842	#endif
843
844	switch (pCpu->pCurInstr->opcode)
845	{
846	/* call implies the actual push of the return address faulted */
847	case OP_CALL:
848	Log4(("pgmPoolMonitorIsReused: CALL\n"));
849	return true;
850	case OP_PUSH:
851	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
852	return true;
853	case OP_PUSHF:
854	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
855	return true;
856	case OP_PUSHA:
857	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
858	return true;
859	case OP_FXSAVE:
860	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
861	return true;
862	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
863	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
864	return true;
865	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
866	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
867	return true;
868	case OP_MOVSWD:
869	case OP_STOSWD:
870	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
871	&& pRegFrame->rcx >= 0x40
872	)
873	{
874	Assert(pCpu->mode == CPUMODE_64BIT);
875
876	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
877	return true;
878	}
879	return false;
880	}
881	if ( (pCpu->param1.flags & USE_REG_GEN32)
882	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
883	{
884	Log4(("pgmPoolMonitorIsReused: ESP\n"));
885	return true;
886	}
887
888	//if (pPage->fCR3Mix)
889	// return false;
890	return false;
891	}
892
893
894	/**
895	* Flushes the page being accessed.
896	*
897	* @returns VBox status code suitable for scheduling.
898	* @param pVM The VM handle.
899	* @param pVCpu The VMCPU handle.
900	* @param pPool The pool.
901	* @param pPage The pool page (head).
902	* @param pCpu The disassembly of the write instruction.
903	* @param pRegFrame The trap register frame.
904	* @param GCPhysFault The fault address as guest physical address.
905	* @param pvFault The fault address.
906	*/
907	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
908	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
909	{
910	/*
911	* First, do the flushing.
912	*/
913	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
914
915	/*
916	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
917	*/
918	uint32_t cbWritten;
919	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
920	if (RT_SUCCESS(rc2))
921	pRegFrame->rip += pCpu->opsize;
922	else if (rc2 == VERR_EM_INTERPRETER)
923	{
924	#ifdef IN_RC
925	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
926	{
927	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
928	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
929	rc = VINF_SUCCESS;
930	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
931	}
932	else
933	#endif
934	{
935	rc = VINF_EM_RAW_EMULATE_INSTR;
936	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
937	}
938	}
939	else
940	rc = rc2;
941
942	/* See use in pgmPoolAccessHandlerSimple(). */
943	PGM_INVL_GUEST_TLBS();
944
945	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
946	return rc;
947
948	}
949
950
951	/**
952	* Handles the STOSD write accesses.
953	*
954	* @returns VBox status code suitable for scheduling.
955	* @param pVM The VM handle.
956	* @param pPool The pool.
957	* @param pPage The pool page (head).
958	* @param pCpu The disassembly of the write instruction.
959	* @param pRegFrame The trap register frame.
960	* @param GCPhysFault The fault address as guest physical address.
961	* @param pvFault The fault address.
962	*/
963	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
964	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
965	{
966	Assert(pCpu->mode == CPUMODE_32BIT);
967
968	Log3(("pgmPoolAccessHandlerSTOSD\n"));
969
970	/*
971	* Increment the modification counter and insert it into the list
972	* of modified pages the first time.
973	*/
974	if (!pPage->cModifications++)
975	pgmPoolMonitorModifiedInsert(pPool, pPage);
976
977	/*
978	* Execute REP STOSD.
979	*
980	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
981	* write situation, meaning that it's safe to write here.
982	*/
983	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
984	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
985	while (pRegFrame->ecx)
986	{
987	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
988	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
989	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
990	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
991	#else
992	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
993	#endif
994	#ifdef IN_RC
995	(uint32_t )pu32 = pRegFrame->eax;
996	#else
997	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
998	#endif
999	pu32 += 4;
1000	GCPhysFault += 4;
1001	pRegFrame->edi += 4;
1002	pRegFrame->ecx--;
1003	}
1004	pRegFrame->rip += pCpu->opsize;
1005
1006	#ifdef IN_RC
1007	/* See use in pgmPoolAccessHandlerSimple(). */
1008	PGM_INVL_GUEST_TLBS();
1009	#endif
1010
1011	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1012	return VINF_SUCCESS;
1013	}
1014
1015
1016	/**
1017	* Handles the simple write accesses.
1018	*
1019	* @returns VBox status code suitable for scheduling.
1020	* @param pVM The VM handle.
1021	* @param pVCpu The VMCPU handle.
1022	* @param pPool The pool.
1023	* @param pPage The pool page (head).
1024	* @param pCpu The disassembly of the write instruction.
1025	* @param pRegFrame The trap register frame.
1026	* @param GCPhysFault The fault address as guest physical address.
1027	* @param pvFault The fault address.
1028	*/
1029	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
1030	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1031	{
1032	Log3(("pgmPoolAccessHandlerSimple\n"));
1033	/*
1034	* Increment the modification counter and insert it into the list
1035	* of modified pages the first time.
1036	*/
1037	if (!pPage->cModifications++)
1038	pgmPoolMonitorModifiedInsert(pPool, pPage);
1039
1040	/*
1041	* Clear all the pages. ASSUMES that pvFault is readable.
1042	*/
1043	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1044	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1045	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1046	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1047	#else
1048	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1049	#endif
1050
1051	/*
1052	* Interpret the instruction.
1053	*/
1054	uint32_t cb;
1055	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
1056	if (RT_SUCCESS(rc))
1057	pRegFrame->rip += pCpu->opsize;
1058	else if (rc == VERR_EM_INTERPRETER)
1059	{
1060	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1061	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
1062	rc = VINF_EM_RAW_EMULATE_INSTR;
1063	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1064	}
1065
1066	#ifdef IN_RC
1067	/*
1068	* Quick hack, with logging enabled we're getting stale
1069	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1070	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1071	* have to be fixed to support this. But that'll have to wait till next week.
1072	*
1073	* An alternative is to keep track of the changed PTEs together with the
1074	* GCPhys from the guest PT. This may proove expensive though.
1075	*
1076	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1077	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1078	*/
1079	PGM_INVL_GUEST_TLBS();
1080	#endif
1081
1082	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1083	return rc;
1084	}
1085
1086	/**
1087	* \#PF Handler callback for PT write accesses.
1088	*
1089	* @returns VBox status code (appropriate for GC return).
1090	* @param pVM VM Handle.
1091	* @param uErrorCode CPU Error code.
1092	* @param pRegFrame Trap register frame.
1093	* NULL on DMA and other non CPU access.
1094	* @param pvFault The fault address (cr2).
1095	* @param GCPhysFault The GC physical address corresponding to pvFault.
1096	* @param pvUser User argument.
1097	*/
1098	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1099	{
1100	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1101	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1102	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1103	PVMCPU pVCpu = VMMGetCpu(pVM);
1104
1105	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1106
1107	/*
1108	* We should ALWAYS have the list head as user parameter. This
1109	* is because we use that page to record the changes.
1110	*/
1111	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1112
1113	/*
1114	* Disassemble the faulting instruction.
1115	*/
1116	DISCPUSTATE Cpu;
1117	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
1118	AssertRCReturn(rc, rc);
1119
1120	pgmLock(pVM);
1121
1122	/*
1123	* Check if it's worth dealing with.
1124	*/
1125	bool fReused = false;
1126	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1127	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1128	)
1129	&& !(fReused = pgmPoolMonitorIsReused(pVM, pPage, pRegFrame, &Cpu, pvFault))
1130	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1131	{
1132	/*
1133	* Simple instructions, no REP prefix.
1134	*/
1135	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1136	{
1137	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1138	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1139	pgmUnlock(pVM);
1140	return rc;
1141	}
1142
1143	/*
1144	* Windows is frequently doing small memset() operations (netio test 4k+).
1145	* We have to deal with these or we'll kill the cache and performance.
1146	*/
1147	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1148	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1149	&& pRegFrame->ecx <= 0x20
1150	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1151	&& !((uintptr_t)pvFault & 3)
1152	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1153	&& Cpu.mode == CPUMODE_32BIT
1154	&& Cpu.opmode == CPUMODE_32BIT
1155	&& Cpu.addrmode == CPUMODE_32BIT
1156	&& Cpu.prefix == PREFIX_REP
1157	&& !pRegFrame->eflags.Bits.u1DF
1158	)
1159	{
1160	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1161	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1162	pgmUnlock(pVM);
1163	return rc;
1164	}
1165
1166	/* REP prefix, don't bother. */
1167	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1168	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1169	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1170	}
1171
1172	/*
1173	* Not worth it, so flush it.
1174	*
1175	* If we considered it to be reused, don't go back to ring-3
1176	* to emulate failed instructions since we usually cannot
1177	* interpret then. This may be a bit risky, in which case
1178	* the reuse detection must be fixed.
1179	*/
1180	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1181	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1182	rc = VINF_SUCCESS;
1183	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1184	pgmUnlock(pVM);
1185	return rc;
1186	}
1187
1188	# endif /* !IN_RING3 */
1189	#endif /* PGMPOOL_WITH_MONITORING */
1190
1191	#ifdef PGMPOOL_WITH_CACHE
1192
1193	/**
1194	* Inserts a page into the GCPhys hash table.
1195	*
1196	* @param pPool The pool.
1197	* @param pPage The page.
1198	*/
1199	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1200	{
1201	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1202	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1203	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1204	pPage->iNext = pPool->aiHash[iHash];
1205	pPool->aiHash[iHash] = pPage->idx;
1206	}
1207
1208
1209	/**
1210	* Removes a page from the GCPhys hash table.
1211	*
1212	* @param pPool The pool.
1213	* @param pPage The page.
1214	*/
1215	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1216	{
1217	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1218	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1219	if (pPool->aiHash[iHash] == pPage->idx)
1220	pPool->aiHash[iHash] = pPage->iNext;
1221	else
1222	{
1223	uint16_t iPrev = pPool->aiHash[iHash];
1224	for (;;)
1225	{
1226	const int16_t i = pPool->aPages[iPrev].iNext;
1227	if (i == pPage->idx)
1228	{
1229	pPool->aPages[iPrev].iNext = pPage->iNext;
1230	break;
1231	}
1232	if (i == NIL_PGMPOOL_IDX)
1233	{
1234	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1235	break;
1236	}
1237	iPrev = i;
1238	}
1239	}
1240	pPage->iNext = NIL_PGMPOOL_IDX;
1241	}
1242
1243
1244	/**
1245	* Frees up one cache page.
1246	*
1247	* @returns VBox status code.
1248	* @retval VINF_SUCCESS on success.
1249	* @param pPool The pool.
1250	* @param iUser The user index.
1251	*/
1252	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1253	{
1254	#ifndef IN_RC
1255	const PVM pVM = pPool->CTX_SUFF(pVM);
1256	#endif
1257	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1258	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1259
1260	/*
1261	* Select one page from the tail of the age list.
1262	*/
1263	PPGMPOOLPAGE pPage;
1264	for (unsigned iLoop = 0; ; iLoop++)
1265	{
1266	uint16_t iToFree = pPool->iAgeTail;
1267	if (iToFree == iUser)
1268	iToFree = pPool->aPages[iToFree].iAgePrev;
1269	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1270	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1271	{
1272	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1273	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1274	{
1275	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1276	continue;
1277	iToFree = i;
1278	break;
1279	}
1280	}
1281	*/
1282	Assert(iToFree != iUser);
1283	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1284	pPage = &pPool->aPages[iToFree];
1285
1286	/*
1287	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1288	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1289	*/
1290	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1291	break;
1292	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1293	pgmPoolCacheUsed(pPool, pPage);
1294	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1295	}
1296
1297	/*
1298	* Found a usable page, flush it and return.
1299	*/
1300	int rc = pgmPoolFlushPage(pPool, pPage);
1301	if (rc == VINF_SUCCESS)
1302	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1303	return rc;
1304	}
1305
1306
1307	/**
1308	* Checks if a kind mismatch is really a page being reused
1309	* or if it's just normal remappings.
1310	*
1311	* @returns true if reused and the cached page (enmKind1) should be flushed
1312	* @returns false if not reused.
1313	* @param enmKind1 The kind of the cached page.
1314	* @param enmKind2 The kind of the requested page.
1315	*/
1316	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1317	{
1318	switch (enmKind1)
1319	{
1320	/*
1321	* Never reuse them. There is no remapping in non-paging mode.
1322	*/
1323	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1324	case PGMPOOLKIND_32BIT_PD_PHYS:
1325	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1326	case PGMPOOLKIND_PAE_PD_PHYS:
1327	case PGMPOOLKIND_PAE_PDPT_PHYS:
1328	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1329	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1330	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1331	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1332	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1333	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1334	return false;
1335
1336	/*
1337	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1338	*/
1339	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1340	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1341	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1342	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1343	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1344	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1345	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1346	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1347	case PGMPOOLKIND_32BIT_PD:
1348	case PGMPOOLKIND_PAE_PDPT:
1349	switch (enmKind2)
1350	{
1351	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1352	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1353	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1354	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1355	case PGMPOOLKIND_64BIT_PML4:
1356	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1357	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1358	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1359	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1360	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1361	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1362	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1363	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1364	return true;
1365	default:
1366	return false;
1367	}
1368
1369	/*
1370	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1371	*/
1372	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1373	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1374	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1375	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1376	case PGMPOOLKIND_64BIT_PML4:
1377	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1378	switch (enmKind2)
1379	{
1380	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1381	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1382	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1383	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1384	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1385	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1386	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1387	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1388	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1389	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1390	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1391	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1392	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1393	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1394	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1395	return true;
1396	default:
1397	return false;
1398	}
1399
1400	/*
1401	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1402	*/
1403	case PGMPOOLKIND_ROOT_NESTED:
1404	return false;
1405
1406	default:
1407	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1408	}
1409	}
1410
1411
1412	/**
1413	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1414	*
1415	* @returns VBox status code.
1416	* @retval VINF_PGM_CACHED_PAGE on success.
1417	* @retval VERR_FILE_NOT_FOUND if not found.
1418	* @param pPool The pool.
1419	* @param GCPhys The GC physical address of the page we're gonna shadow.
1420	* @param enmKind The kind of mapping.
1421	* @param iUser The shadow page pool index of the user table.
1422	* @param iUserTable The index into the user table (shadowed).
1423	* @param ppPage Where to store the pointer to the page.
1424	*/
1425	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1426	{
1427	#ifndef IN_RC
1428	const PVM pVM = pPool->CTX_SUFF(pVM);
1429	#endif
1430	/*
1431	* Look up the GCPhys in the hash.
1432	*/
1433	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1434	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1435	if (i != NIL_PGMPOOL_IDX)
1436	{
1437	do
1438	{
1439	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1440	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1441	if (pPage->GCPhys == GCPhys)
1442	{
1443	if ((PGMPOOLKIND)pPage->enmKind == enmKind)
1444	{
1445	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1446	* doesn't flush it in case there are no more free use records.
1447	*/
1448	pgmPoolCacheUsed(pPool, pPage);
1449
1450	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1451	if (RT_SUCCESS(rc))
1452	{
1453	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1454	*ppPage = pPage;
1455	STAM_COUNTER_INC(&pPool->StatCacheHits);
1456	return VINF_PGM_CACHED_PAGE;
1457	}
1458	return rc;
1459	}
1460
1461	/*
1462	* The kind is different. In some cases we should now flush the page
1463	* as it has been reused, but in most cases this is normal remapping
1464	* of PDs as PT or big pages using the GCPhys field in a slightly
1465	* different way than the other kinds.
1466	*/
1467	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1468	{
1469	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1470	pgmPoolFlushPage(pPool, pPage);
1471	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1472	break;
1473	}
1474	}
1475
1476	/* next */
1477	i = pPage->iNext;
1478	} while (i != NIL_PGMPOOL_IDX);
1479	}
1480
1481	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1482	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1483	return VERR_FILE_NOT_FOUND;
1484	}
1485
1486
1487	/**
1488	* Inserts a page into the cache.
1489	*
1490	* @param pPool The pool.
1491	* @param pPage The cached page.
1492	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1493	*/
1494	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1495	{
1496	/*
1497	* Insert into the GCPhys hash if the page is fit for that.
1498	*/
1499	Assert(!pPage->fCached);
1500	if (fCanBeCached)
1501	{
1502	pPage->fCached = true;
1503	pgmPoolHashInsert(pPool, pPage);
1504	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1505	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1506	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1507	}
1508	else
1509	{
1510	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1511	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1512	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1513	}
1514
1515	/*
1516	* Insert at the head of the age list.
1517	*/
1518	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1519	pPage->iAgeNext = pPool->iAgeHead;
1520	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1521	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1522	else
1523	pPool->iAgeTail = pPage->idx;
1524	pPool->iAgeHead = pPage->idx;
1525	}
1526
1527
1528	/**
1529	* Flushes a cached page.
1530	*
1531	* @param pPool The pool.
1532	* @param pPage The cached page.
1533	*/
1534	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1535	{
1536	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1537
1538	/*
1539	* Remove the page from the hash.
1540	*/
1541	if (pPage->fCached)
1542	{
1543	pPage->fCached = false;
1544	pgmPoolHashRemove(pPool, pPage);
1545	}
1546	else
1547	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1548
1549	/*
1550	* Remove it from the age list.
1551	*/
1552	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1553	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1554	else
1555	pPool->iAgeTail = pPage->iAgePrev;
1556	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1557	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1558	else
1559	pPool->iAgeHead = pPage->iAgeNext;
1560	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1561	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1562	}
1563
1564	#endif /* PGMPOOL_WITH_CACHE */
1565	#ifdef PGMPOOL_WITH_MONITORING
1566
1567	/**
1568	* Looks for pages sharing the monitor.
1569	*
1570	* @returns Pointer to the head page.
1571	* @returns NULL if not found.
1572	* @param pPool The Pool
1573	* @param pNewPage The page which is going to be monitored.
1574	*/
1575	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1576	{
1577	#ifdef PGMPOOL_WITH_CACHE
1578	/*
1579	* Look up the GCPhys in the hash.
1580	*/
1581	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1582	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1583	if (i == NIL_PGMPOOL_IDX)
1584	return NULL;
1585	do
1586	{
1587	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1588	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1589	&& pPage != pNewPage)
1590	{
1591	switch (pPage->enmKind)
1592	{
1593	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1594	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1595	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1596	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1597	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1598	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1599	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1600	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1601	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1602	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1603	case PGMPOOLKIND_64BIT_PML4:
1604	case PGMPOOLKIND_32BIT_PD:
1605	case PGMPOOLKIND_PAE_PDPT:
1606	{
1607	/* find the head */
1608	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1609	{
1610	Assert(pPage->iMonitoredPrev != pPage->idx);
1611	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1612	}
1613	return pPage;
1614	}
1615
1616	/* ignore, no monitoring. */
1617	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1618	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1619	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1620	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1621	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1622	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1623	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1624	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1625	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1626	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1627	case PGMPOOLKIND_ROOT_NESTED:
1628	case PGMPOOLKIND_PAE_PD_PHYS:
1629	case PGMPOOLKIND_PAE_PDPT_PHYS:
1630	case PGMPOOLKIND_32BIT_PD_PHYS:
1631	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1632	break;
1633	default:
1634	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1635	}
1636	}
1637
1638	/* next */
1639	i = pPage->iNext;
1640	} while (i != NIL_PGMPOOL_IDX);
1641	#endif
1642	return NULL;
1643	}
1644
1645
1646	/**
1647	* Enabled write monitoring of a guest page.
1648	*
1649	* @returns VBox status code.
1650	* @retval VINF_SUCCESS on success.
1651	* @param pPool The pool.
1652	* @param pPage The cached page.
1653	*/
1654	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1655	{
1656	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1657
1658	/*
1659	* Filter out the relevant kinds.
1660	*/
1661	switch (pPage->enmKind)
1662	{
1663	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1664	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1665	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1666	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1667	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1668	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1669	case PGMPOOLKIND_64BIT_PML4:
1670	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1671	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1672	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1673	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1674	case PGMPOOLKIND_32BIT_PD:
1675	case PGMPOOLKIND_PAE_PDPT:
1676	break;
1677
1678	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1679	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1680	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1681	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1682	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1683	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1684	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1685	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1686	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1687	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1688	case PGMPOOLKIND_ROOT_NESTED:
1689	/* Nothing to monitor here. */
1690	return VINF_SUCCESS;
1691
1692	case PGMPOOLKIND_32BIT_PD_PHYS:
1693	case PGMPOOLKIND_PAE_PDPT_PHYS:
1694	case PGMPOOLKIND_PAE_PD_PHYS:
1695	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1696	/* Nothing to monitor here. */
1697	return VINF_SUCCESS;
1698	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1699	break;
1700	#else
1701	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1702	#endif
1703	default:
1704	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1705	}
1706
1707	/*
1708	* Install handler.
1709	*/
1710	int rc;
1711	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1712	if (pPageHead)
1713	{
1714	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1715	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1716	pPage->iMonitoredPrev = pPageHead->idx;
1717	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1718	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1719	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1720	pPageHead->iMonitoredNext = pPage->idx;
1721	rc = VINF_SUCCESS;
1722	}
1723	else
1724	{
1725	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1726	PVM pVM = pPool->CTX_SUFF(pVM);
1727	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1728	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1729	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1730	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1731	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1732	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1733	pPool->pszAccessHandler);
1734	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1735	* the heap size should suffice. */
1736	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1737	Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1738	}
1739	pPage->fMonitored = true;
1740	return rc;
1741	}
1742
1743
1744	/**
1745	* Disables write monitoring of a guest page.
1746	*
1747	* @returns VBox status code.
1748	* @retval VINF_SUCCESS on success.
1749	* @param pPool The pool.
1750	* @param pPage The cached page.
1751	*/
1752	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1753	{
1754	/*
1755	* Filter out the relevant kinds.
1756	*/
1757	switch (pPage->enmKind)
1758	{
1759	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1760	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1761	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1762	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1763	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1764	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1765	case PGMPOOLKIND_64BIT_PML4:
1766	case PGMPOOLKIND_32BIT_PD:
1767	case PGMPOOLKIND_PAE_PDPT:
1768	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1769	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1770	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1771	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1772	break;
1773
1774	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1775	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1776	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1777	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1778	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1779	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1780	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1781	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1782	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1783	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1784	case PGMPOOLKIND_ROOT_NESTED:
1785	case PGMPOOLKIND_PAE_PD_PHYS:
1786	case PGMPOOLKIND_PAE_PDPT_PHYS:
1787	case PGMPOOLKIND_32BIT_PD_PHYS:
1788	/* Nothing to monitor here. */
1789	return VINF_SUCCESS;
1790
1791	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1792	break;
1793	#endif
1794	default:
1795	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1796	}
1797
1798	/*
1799	* Remove the page from the monitored list or uninstall it if last.
1800	*/
1801	const PVM pVM = pPool->CTX_SUFF(pVM);
1802	int rc;
1803	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1804	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1805	{
1806	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1807	{
1808	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1809	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1810	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1811	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1812	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1813	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1814	pPool->pszAccessHandler);
1815	AssertFatalRCSuccess(rc);
1816	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1817	}
1818	else
1819	{
1820	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1821	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1822	{
1823	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1824	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1825	}
1826	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1827	rc = VINF_SUCCESS;
1828	}
1829	}
1830	else
1831	{
1832	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1833	AssertFatalRC(rc);
1834	AssertMsg(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3),
1835	("%#x %#x\n", pVM->pgm.s.fGlobalSyncFlags, pVM->fGlobalForcedActions));
1836	}
1837	pPage->fMonitored = false;
1838
1839	/*
1840	* Remove it from the list of modified pages (if in it).
1841	*/
1842	pgmPoolMonitorModifiedRemove(pPool, pPage);
1843
1844	return rc;
1845	}
1846
1847
1848	/**
1849	* Inserts the page into the list of modified pages.
1850	*
1851	* @param pPool The pool.
1852	* @param pPage The page.
1853	*/
1854	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1855	{
1856	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1857	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1858	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1859	&& pPool->iModifiedHead != pPage->idx,
1860	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1861	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1862	pPool->iModifiedHead, pPool->cModifiedPages));
1863
1864	pPage->iModifiedNext = pPool->iModifiedHead;
1865	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1866	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1867	pPool->iModifiedHead = pPage->idx;
1868	pPool->cModifiedPages++;
1869	#ifdef VBOX_WITH_STATISTICS
1870	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1871	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1872	#endif
1873	}
1874
1875
1876	/**
1877	* Removes the page from the list of modified pages and resets the
1878	* moficiation counter.
1879	*
1880	* @param pPool The pool.
1881	* @param pPage The page which is believed to be in the list of modified pages.
1882	*/
1883	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1884	{
1885	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1886	if (pPool->iModifiedHead == pPage->idx)
1887	{
1888	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1889	pPool->iModifiedHead = pPage->iModifiedNext;
1890	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1891	{
1892	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1893	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1894	}
1895	pPool->cModifiedPages--;
1896	}
1897	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1898	{
1899	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1900	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1901	{
1902	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1903	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1904	}
1905	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1906	pPool->cModifiedPages--;
1907	}
1908	else
1909	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1910	pPage->cModifications = 0;
1911	}
1912
1913
1914	/**
1915	* Zaps the list of modified pages, resetting their modification counters in the process.
1916	*
1917	* @param pVM The VM handle.
1918	*/
1919	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1920	{
1921	pgmLock(pVM);
1922	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1923	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1924
1925	unsigned cPages = 0; NOREF(cPages);
1926	uint16_t idx = pPool->iModifiedHead;
1927	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1928	while (idx != NIL_PGMPOOL_IDX)
1929	{
1930	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1931	idx = pPage->iModifiedNext;
1932	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1933	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1934	pPage->cModifications = 0;
1935	Assert(++cPages);
1936	}
1937	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1938	pPool->cModifiedPages = 0;
1939	pgmUnlock(pVM);
1940	}
1941
1942
1943	#ifdef IN_RING3
1944	/**
1945	* Callback to clear all shadow pages and clear all modification counters.
1946	*
1947	* @returns VBox status code.
1948	* @param pVM The VM handle.
1949	* @param pvUser Unused parameter
1950	* @remark Should only be used when monitoring is available, thus placed in
1951	* the PGMPOOL_WITH_MONITORING #ifdef.
1952	*/
1953	DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, void *pvUser)
1954	{
1955	NOREF(pvUser);
1956	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1957	STAM_PROFILE_START(&pPool->StatClearAll, c);
1958	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1959
1960	/*
1961	* Iterate all the pages until we've encountered all that in use.
1962	* This is simple but not quite optimal solution.
1963	*/
1964	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1965	unsigned cLeft = pPool->cUsedPages;
1966	unsigned iPage = pPool->cCurPages;
1967	while (--iPage >= PGMPOOL_IDX_FIRST)
1968	{
1969	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1970	if (pPage->GCPhys != NIL_RTGCPHYS)
1971	{
1972	switch (pPage->enmKind)
1973	{
1974	/*
1975	* We only care about shadow page tables.
1976	*/
1977	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1978	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1979	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1980	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1981	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1982	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1983	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1984	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1985	{
1986	#ifdef PGMPOOL_WITH_USER_TRACKING
1987	if (pPage->cPresent)
1988	#endif
1989	{
1990	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1991	STAM_PROFILE_START(&pPool->StatZeroPage, z);
1992	ASMMemZeroPage(pvShw);
1993	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
1994	#ifdef PGMPOOL_WITH_USER_TRACKING
1995	pPage->cPresent = 0;
1996	pPage->iFirstPresent = ~0;
1997	#endif
1998	}
1999	}
2000	/* fall thru */
2001
2002	default:
2003	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2004	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2005	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2006	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2007	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2008	pPage->cModifications = 0;
2009	break;
2010
2011	}
2012	if (!--cLeft)
2013	break;
2014	}
2015	}
2016
2017	/* swipe the special pages too. */
2018	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2019	{
2020	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2021	if (pPage->GCPhys != NIL_RTGCPHYS)
2022	{
2023	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2024	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2025	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2026	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2027	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2028	pPage->cModifications = 0;
2029	}
2030	}
2031
2032	#ifndef DEBUG_michael
2033	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2034	#endif
2035	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2036	pPool->cModifiedPages = 0;
2037
2038	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2039	/*
2040	* Clear all the GCPhys links and rebuild the phys ext free list.
2041	*/
2042	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2043	pRam;
2044	pRam = pRam->CTX_SUFF(pNext))
2045	{
2046	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2047	while (iPage-- > 0)
2048	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2049	}
2050
2051	pPool->iPhysExtFreeHead = 0;
2052	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2053	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2054	for (unsigned i = 0; i < cMaxPhysExts; i++)
2055	{
2056	paPhysExts[i].iNext = i + 1;
2057	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2058	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2059	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2060	}
2061	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2062	#endif
2063
2064	pPool->cPresent = 0;
2065	PGM_INVL_GUEST_TLBS();
2066	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2067	return VINF_SUCCESS;
2068	}
2069	#endif /* IN_RING3 */
2070
2071
2072	/**
2073	* Handle SyncCR3 pool tasks
2074	*
2075	* @returns VBox status code.
2076	* @retval VINF_SUCCESS if successfully added.
2077	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2078	* @param pVM The VM handle.
2079	* @remark Should only be used when monitoring is available, thus placed in
2080	* the PGMPOOL_WITH_MONITORING #ifdef.
2081	*/
2082	int pgmPoolSyncCR3(PVM pVM)
2083	{
2084	LogFlow(("pgmPoolSyncCR3\n"));
2085	/*
2086	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2087	* Occasionally we will have to clear all the shadow page tables because we wanted
2088	* to monitor a page which was mapped by too many shadowed page tables. This operation
2089	* sometimes refered to as a 'lightweight flush'.
2090	*/
2091	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2092	if (ASMBitTestAndClear(&pVM->pgm.s.fGlobalSyncFlags, PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT))
2093	{
2094	VMMR3AtomicExecuteHandler(pVM, pgmPoolClearAll, NULL);
2095	# else /* !IN_RING3 */
2096	if (pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)
2097	{
2098	LogFlow(("SyncCR3: PGM_GLOBAL_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2099	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2100	return VINF_PGM_SYNC_CR3;
2101	# endif /* !IN_RING3 */
2102	}
2103	else
2104	pgmPoolMonitorModifiedClearAll(pVM);
2105
2106	return VINF_SUCCESS;
2107	}
2108
2109	#endif /* PGMPOOL_WITH_MONITORING */
2110	#ifdef PGMPOOL_WITH_USER_TRACKING
2111
2112	/**
2113	* Frees up at least one user entry.
2114	*
2115	* @returns VBox status code.
2116	* @retval VINF_SUCCESS if successfully added.
2117	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2118	* @param pPool The pool.
2119	* @param iUser The user index.
2120	*/
2121	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2122	{
2123	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2124	#ifdef PGMPOOL_WITH_CACHE
2125	/*
2126	* Just free cached pages in a braindead fashion.
2127	*/
2128	/** @todo walk the age list backwards and free the first with usage. */
2129	int rc = VINF_SUCCESS;
2130	do
2131	{
2132	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2133	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2134	rc = rc2;
2135	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2136	return rc;
2137	#else
2138	/*
2139	* Lazy approach.
2140	*/
2141	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2142	AssertCompileFailed();
2143	Assert(!CPUMIsGuestInLongMode(pVM));
2144	pgmPoolFlushAllInt(pPool);
2145	return VERR_PGM_POOL_FLUSHED;
2146	#endif
2147	}
2148
2149
2150	/**
2151	* Inserts a page into the cache.
2152	*
2153	* This will create user node for the page, insert it into the GCPhys
2154	* hash, and insert it into the age list.
2155	*
2156	* @returns VBox status code.
2157	* @retval VINF_SUCCESS if successfully added.
2158	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2159	* @param pPool The pool.
2160	* @param pPage The cached page.
2161	* @param GCPhys The GC physical address of the page we're gonna shadow.
2162	* @param iUser The user index.
2163	* @param iUserTable The user table index.
2164	*/
2165	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2166	{
2167	int rc = VINF_SUCCESS;
2168	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2169
2170	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2171
2172	#ifdef VBOX_STRICT
2173	/*
2174	* Check that the entry doesn't already exists.
2175	*/
2176	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2177	{
2178	uint16_t i = pPage->iUserHead;
2179	do
2180	{
2181	Assert(i < pPool->cMaxUsers);
2182	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2183	i = paUsers[i].iNext;
2184	} while (i != NIL_PGMPOOL_USER_INDEX);
2185	}
2186	#endif
2187
2188	/*
2189	* Find free a user node.
2190	*/
2191	uint16_t i = pPool->iUserFreeHead;
2192	if (i == NIL_PGMPOOL_USER_INDEX)
2193	{
2194	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2195	if (RT_FAILURE(rc))
2196	return rc;
2197	i = pPool->iUserFreeHead;
2198	}
2199
2200	/*
2201	* Unlink the user node from the free list,
2202	* initialize and insert it into the user list.
2203	*/
2204	pPool->iUserFreeHead = paUsers[i].iNext;
2205	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2206	paUsers[i].iUser = iUser;
2207	paUsers[i].iUserTable = iUserTable;
2208	pPage->iUserHead = i;
2209
2210	/*
2211	* Insert into cache and enable monitoring of the guest page if enabled.
2212	*
2213	* Until we implement caching of all levels, including the CR3 one, we'll
2214	* have to make sure we don't try monitor & cache any recursive reuse of
2215	* a monitored CR3 page. Because all windows versions are doing this we'll
2216	* have to be able to do combined access monitoring, CR3 + PT and
2217	* PD + PT (guest PAE).
2218	*
2219	* Update:
2220	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2221	*/
2222	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2223	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2224	const bool fCanBeMonitored = true;
2225	# else
2226	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2227	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2228	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2229	# endif
2230	# ifdef PGMPOOL_WITH_CACHE
2231	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2232	# endif
2233	if (fCanBeMonitored)
2234	{
2235	# ifdef PGMPOOL_WITH_MONITORING
2236	rc = pgmPoolMonitorInsert(pPool, pPage);
2237	AssertRC(rc);
2238	}
2239	# endif
2240	#endif /* PGMPOOL_WITH_MONITORING */
2241	return rc;
2242	}
2243
2244
2245	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2246	/**
2247	* Adds a user reference to a page.
2248	*
2249	* This will move the page to the head of the
2250	*
2251	* @returns VBox status code.
2252	* @retval VINF_SUCCESS if successfully added.
2253	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2254	* @param pPool The pool.
2255	* @param pPage The cached page.
2256	* @param iUser The user index.
2257	* @param iUserTable The user table.
2258	*/
2259	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2260	{
2261	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2262
2263	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2264
2265	# ifdef VBOX_STRICT
2266	/*
2267	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2268	*/
2269	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2270	{
2271	uint16_t i = pPage->iUserHead;
2272	do
2273	{
2274	Assert(i < pPool->cMaxUsers);
2275	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2276	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2277	i = paUsers[i].iNext;
2278	} while (i != NIL_PGMPOOL_USER_INDEX);
2279	}
2280	# endif
2281
2282	/*
2283	* Allocate a user node.
2284	*/
2285	uint16_t i = pPool->iUserFreeHead;
2286	if (i == NIL_PGMPOOL_USER_INDEX)
2287	{
2288	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2289	if (RT_FAILURE(rc))
2290	return rc;
2291	i = pPool->iUserFreeHead;
2292	}
2293	pPool->iUserFreeHead = paUsers[i].iNext;
2294
2295	/*
2296	* Initialize the user node and insert it.
2297	*/
2298	paUsers[i].iNext = pPage->iUserHead;
2299	paUsers[i].iUser = iUser;
2300	paUsers[i].iUserTable = iUserTable;
2301	pPage->iUserHead = i;
2302
2303	# ifdef PGMPOOL_WITH_CACHE
2304	/*
2305	* Tell the cache to update its replacement stats for this page.
2306	*/
2307	pgmPoolCacheUsed(pPool, pPage);
2308	# endif
2309	return VINF_SUCCESS;
2310	}
2311	# endif /* PGMPOOL_WITH_CACHE */
2312
2313
2314	/**
2315	* Frees a user record associated with a page.
2316	*
2317	* This does not clear the entry in the user table, it simply replaces the
2318	* user record to the chain of free records.
2319	*
2320	* @param pPool The pool.
2321	* @param HCPhys The HC physical address of the shadow page.
2322	* @param iUser The shadow page pool index of the user table.
2323	* @param iUserTable The index into the user table (shadowed).
2324	*/
2325	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2326	{
2327	/*
2328	* Unlink and free the specified user entry.
2329	*/
2330	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2331
2332	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2333	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2334	uint16_t i = pPage->iUserHead;
2335	if ( i != NIL_PGMPOOL_USER_INDEX
2336	&& paUsers[i].iUser == iUser
2337	&& paUsers[i].iUserTable == iUserTable)
2338	{
2339	pPage->iUserHead = paUsers[i].iNext;
2340
2341	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2342	paUsers[i].iNext = pPool->iUserFreeHead;
2343	pPool->iUserFreeHead = i;
2344	return;
2345	}
2346
2347	/* General: Linear search. */
2348	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2349	while (i != NIL_PGMPOOL_USER_INDEX)
2350	{
2351	if ( paUsers[i].iUser == iUser
2352	&& paUsers[i].iUserTable == iUserTable)
2353	{
2354	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2355	paUsers[iPrev].iNext = paUsers[i].iNext;
2356	else
2357	pPage->iUserHead = paUsers[i].iNext;
2358
2359	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2360	paUsers[i].iNext = pPool->iUserFreeHead;
2361	pPool->iUserFreeHead = i;
2362	return;
2363	}
2364	iPrev = i;
2365	i = paUsers[i].iNext;
2366	}
2367
2368	/* Fatal: didn't find it */
2369	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2370	iUser, iUserTable, pPage->GCPhys));
2371	}
2372
2373
2374	/**
2375	* Gets the entry size of a shadow table.
2376	*
2377	* @param enmKind The kind of page.
2378	*
2379	* @returns The size of the entry in bytes. That is, 4 or 8.
2380	* @returns If the kind is not for a table, an assertion is raised and 0 is
2381	* returned.
2382	*/
2383	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2384	{
2385	switch (enmKind)
2386	{
2387	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2388	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2389	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2390	case PGMPOOLKIND_32BIT_PD:
2391	case PGMPOOLKIND_32BIT_PD_PHYS:
2392	return 4;
2393
2394	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2395	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2396	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2397	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2398	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2399	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2400	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2401	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2402	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2403	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2404	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2405	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2406	case PGMPOOLKIND_64BIT_PML4:
2407	case PGMPOOLKIND_PAE_PDPT:
2408	case PGMPOOLKIND_ROOT_NESTED:
2409	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2410	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2411	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2412	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2413	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2414	case PGMPOOLKIND_PAE_PD_PHYS:
2415	case PGMPOOLKIND_PAE_PDPT_PHYS:
2416	return 8;
2417
2418	default:
2419	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2420	}
2421	}
2422
2423
2424	/**
2425	* Gets the entry size of a guest table.
2426	*
2427	* @param enmKind The kind of page.
2428	*
2429	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2430	* @returns If the kind is not for a table, an assertion is raised and 0 is
2431	* returned.
2432	*/
2433	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2434	{
2435	switch (enmKind)
2436	{
2437	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2438	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2439	case PGMPOOLKIND_32BIT_PD:
2440	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2441	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2442	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2443	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2444	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2445	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2446	return 4;
2447
2448	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2449	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2450	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2451	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2452	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2453	case PGMPOOLKIND_64BIT_PML4:
2454	case PGMPOOLKIND_PAE_PDPT:
2455	return 8;
2456
2457	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2458	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2459	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2460	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2461	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2462	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2463	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2464	case PGMPOOLKIND_ROOT_NESTED:
2465	case PGMPOOLKIND_PAE_PD_PHYS:
2466	case PGMPOOLKIND_PAE_PDPT_PHYS:
2467	case PGMPOOLKIND_32BIT_PD_PHYS:
2468	/** @todo can we return 0? (nobody is calling this...) */
2469	AssertFailed();
2470	return 0;
2471
2472	default:
2473	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2474	}
2475	}
2476
2477	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2478
2479	/**
2480	* Scans one shadow page table for mappings of a physical page.
2481	*
2482	* @param pVM The VM handle.
2483	* @param pPhysPage The guest page in question.
2484	* @param iShw The shadow page table.
2485	* @param cRefs The number of references made in that PT.
2486	*/
2487	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2488	{
2489	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2490	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2491
2492	/*
2493	* Assert sanity.
2494	*/
2495	Assert(cRefs == 1);
2496	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2497	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2498
2499	/*
2500	* Then, clear the actual mappings to the page in the shadow PT.
2501	*/
2502	switch (pPage->enmKind)
2503	{
2504	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2505	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2506	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2507	{
2508	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2509	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2510	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2511	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2512	{
2513	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2514	pPT->a[i].u = 0;
2515	cRefs--;
2516	if (!cRefs)
2517	return;
2518	}
2519	#ifdef LOG_ENABLED
2520	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2521	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2522	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2523	{
2524	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2525	pPT->a[i].u = 0;
2526	}
2527	#endif
2528	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2529	break;
2530	}
2531
2532	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2533	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2534	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2535	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2536	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2537	{
2538	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2539	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2540	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2541	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2542	{
2543	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2544	pPT->a[i].u = 0;
2545	cRefs--;
2546	if (!cRefs)
2547	return;
2548	}
2549	#ifdef LOG_ENABLED
2550	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2551	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2552	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2553	{
2554	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2555	pPT->a[i].u = 0;
2556	}
2557	#endif
2558	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2559	break;
2560	}
2561
2562	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2563	{
2564	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2565	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2566	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2567	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2568	{
2569	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2570	pPT->a[i].u = 0;
2571	cRefs--;
2572	if (!cRefs)
2573	return;
2574	}
2575	#ifdef LOG_ENABLED
2576	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2577	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2578	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2579	{
2580	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2581	pPT->a[i].u = 0;
2582	}
2583	#endif
2584	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2585	break;
2586	}
2587
2588	default:
2589	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2590	}
2591	}
2592
2593
2594	/**
2595	* Scans one shadow page table for mappings of a physical page.
2596	*
2597	* @param pVM The VM handle.
2598	* @param pPhysPage The guest page in question.
2599	* @param iShw The shadow page table.
2600	* @param cRefs The number of references made in that PT.
2601	*/
2602	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2603	{
2604	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2605	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2606	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2607	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2608	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2609	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2610	}
2611
2612
2613	/**
2614	* Flushes a list of shadow page tables mapping the same physical page.
2615	*
2616	* @param pVM The VM handle.
2617	* @param pPhysPage The guest page in question.
2618	* @param iPhysExt The physical cross reference extent list to flush.
2619	*/
2620	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2621	{
2622	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2623	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2624	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2625
2626	const uint16_t iPhysExtStart = iPhysExt;
2627	PPGMPOOLPHYSEXT pPhysExt;
2628	do
2629	{
2630	Assert(iPhysExt < pPool->cMaxPhysExts);
2631	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2632	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2633	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2634	{
2635	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2636	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2637	}
2638
2639	/* next */
2640	iPhysExt = pPhysExt->iNext;
2641	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2642
2643	/* insert the list into the free list and clear the ram range entry. */
2644	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2645	pPool->iPhysExtFreeHead = iPhysExtStart;
2646	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2647
2648	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2649	}
2650
2651	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2652
2653	/**
2654	* Flushes all shadow page table mappings of the given guest page.
2655	*
2656	* This is typically called when the host page backing the guest one has been
2657	* replaced or when the page protection was changed due to an access handler.
2658	*
2659	* @returns VBox status code.
2660	* @retval VINF_SUCCESS if all references has been successfully cleared.
2661	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2662	* pool cleaning. FF and sync flags are set.
2663	*
2664	* @param pVM The VM handle.
2665	* @param pPhysPage The guest page in question.
2666	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2667	* flushed, it is NOT touched if this isn't necessary.
2668	* The caller MUST initialized this to @a false.
2669	*/
2670	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2671	{
2672	pgmLock(pVM);
2673	int rc = VINF_SUCCESS;
2674	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2675	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2676	if (u16)
2677	{
2678	/*
2679	* The zero page is currently screwing up the tracking and we'll
2680	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2681	* is defined, zero pages won't normally be mapped. Some kind of solution
2682	* will be needed for this problem of course, but it will have to wait...
2683	*/
2684	if (PGM_PAGE_IS_ZERO(pPhysPage))
2685	rc = VINF_PGM_GCPHYS_ALIASED;
2686	else
2687	{
2688	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2689	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2690	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2691	PVMCPU pVCpu = VMMGetCpu(pVM);
2692	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2693	# endif
2694
2695	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2696	pgmPoolTrackFlushGCPhysPT(pVM,
2697	pPhysPage,
2698	PGMPOOL_TD_GET_IDX(u16),
2699	PGMPOOL_TD_GET_CREFS(u16));
2700	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2701	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2702	else
2703	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2704	*pfFlushTLBs = true;
2705
2706	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2707	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2708	# endif
2709	}
2710	}
2711
2712	#elif defined(PGMPOOL_WITH_CACHE)
2713	if (PGM_PAGE_IS_ZERO(pPhysPage))
2714	rc = VINF_PGM_GCPHYS_ALIASED;
2715	else
2716	{
2717	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2718	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2719	PVMCPU pVCpu = VMMGetCpu(pVM);
2720	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2721	# endif
2722	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2723	if (rc == VINF_SUCCESS)
2724	*pfFlushTLBs = true;
2725	}
2726
2727	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2728	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2729	# endif
2730
2731	#else
2732	rc = VINF_PGM_GCPHYS_ALIASED;
2733	#endif
2734
2735	if (rc == VINF_PGM_GCPHYS_ALIASED)
2736	{
2737	pVM->pgm.s.fGlobalSyncFlags \|= PGM_GLOBAL_SYNC_CLEAR_PGM_POOL;
2738	for (unsigned i=0;i<pVM->cCPUs;i++)
2739	{
2740	PVMCPU pVCpu = &pVM->aCpus[i];
2741	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2742	}
2743	rc = VINF_PGM_SYNC_CR3;
2744	}
2745	pgmUnlock(pVM);
2746	return rc;
2747	}
2748
2749
2750	/**
2751	* Scans all shadow page tables for mappings of a physical page.
2752	*
2753	* This may be slow, but it's most likely more efficient than cleaning
2754	* out the entire page pool / cache.
2755	*
2756	* @returns VBox status code.
2757	* @retval VINF_SUCCESS if all references has been successfully cleared.
2758	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2759	* a page pool cleaning.
2760	*
2761	* @param pVM The VM handle.
2762	* @param pPhysPage The guest page in question.
2763	*/
2764	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2765	{
2766	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2767	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2768	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2769	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2770
2771	#if 1
2772	/*
2773	* There is a limit to what makes sense.
2774	*/
2775	if (pPool->cPresent > 1024)
2776	{
2777	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2778	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2779	return VINF_PGM_GCPHYS_ALIASED;
2780	}
2781	#endif
2782
2783	/*
2784	* Iterate all the pages until we've encountered all that in use.
2785	* This is simple but not quite optimal solution.
2786	*/
2787	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2788	const uint32_t u32 = u64;
2789	unsigned cLeft = pPool->cUsedPages;
2790	unsigned iPage = pPool->cCurPages;
2791	while (--iPage >= PGMPOOL_IDX_FIRST)
2792	{
2793	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2794	if (pPage->GCPhys != NIL_RTGCPHYS)
2795	{
2796	switch (pPage->enmKind)
2797	{
2798	/*
2799	* We only care about shadow page tables.
2800	*/
2801	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2802	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2803	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2804	{
2805	unsigned cPresent = pPage->cPresent;
2806	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2807	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2808	if (pPT->a[i].n.u1Present)
2809	{
2810	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2811	{
2812	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2813	pPT->a[i].u = 0;
2814	}
2815	if (!--cPresent)
2816	break;
2817	}
2818	break;
2819	}
2820
2821	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2822	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2823	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2824	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2825	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2826	{
2827	unsigned cPresent = pPage->cPresent;
2828	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2829	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2830	if (pPT->a[i].n.u1Present)
2831	{
2832	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2833	{
2834	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2835	pPT->a[i].u = 0;
2836	}
2837	if (!--cPresent)
2838	break;
2839	}
2840	break;
2841	}
2842	}
2843	if (!--cLeft)
2844	break;
2845	}
2846	}
2847
2848	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2849	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2850	return VINF_SUCCESS;
2851	}
2852
2853
2854	/**
2855	* Clears the user entry in a user table.
2856	*
2857	* This is used to remove all references to a page when flushing it.
2858	*/
2859	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2860	{
2861	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2862	Assert(pUser->iUser < pPool->cCurPages);
2863	uint32_t iUserTable = pUser->iUserTable;
2864
2865	/*
2866	* Map the user page.
2867	*/
2868	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2869	union
2870	{
2871	uint64_t *pau64;
2872	uint32_t *pau32;
2873	} u;
2874	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2875
2876	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2877
2878	/* Safety precaution in case we change the paging for other modes too in the future. */
2879	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2880
2881	#ifdef VBOX_STRICT
2882	/*
2883	* Some sanity checks.
2884	*/
2885	switch (pUserPage->enmKind)
2886	{
2887	case PGMPOOLKIND_32BIT_PD:
2888	case PGMPOOLKIND_32BIT_PD_PHYS:
2889	Assert(iUserTable < X86_PG_ENTRIES);
2890	break;
2891	case PGMPOOLKIND_PAE_PDPT:
2892	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2893	case PGMPOOLKIND_PAE_PDPT_PHYS:
2894	Assert(iUserTable < 4);
2895	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2896	break;
2897	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2898	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2899	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2900	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2901	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2902	case PGMPOOLKIND_PAE_PD_PHYS:
2903	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2904	break;
2905	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2906	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2907	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2908	break;
2909	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2910	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2911	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2912	break;
2913	case PGMPOOLKIND_64BIT_PML4:
2914	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2915	/* GCPhys >> PAGE_SHIFT is the index here */
2916	break;
2917	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2918	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2919	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2920	break;
2921
2922	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2923	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2924	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2925	break;
2926
2927	case PGMPOOLKIND_ROOT_NESTED:
2928	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2929	break;
2930
2931	default:
2932	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2933	break;
2934	}
2935	#endif /* VBOX_STRICT */
2936
2937	/*
2938	* Clear the entry in the user page.
2939	*/
2940	switch (pUserPage->enmKind)
2941	{
2942	/* 32-bit entries */
2943	case PGMPOOLKIND_32BIT_PD:
2944	case PGMPOOLKIND_32BIT_PD_PHYS:
2945	u.pau32[iUserTable] = 0;
2946	break;
2947
2948	/* 64-bit entries */
2949	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2950	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2951	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2952	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2953	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2954	#if defined(IN_RC)
2955	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
2956	* non-present PDPT will continue to cause page faults.
2957	*/
2958	ASMReloadCR3();
2959	#endif
2960	/* no break */
2961	case PGMPOOLKIND_PAE_PD_PHYS:
2962	case PGMPOOLKIND_PAE_PDPT_PHYS:
2963	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2964	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2965	case PGMPOOLKIND_64BIT_PML4:
2966	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2967	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2968	case PGMPOOLKIND_PAE_PDPT:
2969	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2970	case PGMPOOLKIND_ROOT_NESTED:
2971	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2972	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2973	u.pau64[iUserTable] = 0;
2974	break;
2975
2976	default:
2977	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2978	}
2979	}
2980
2981
2982	/**
2983	* Clears all users of a page.
2984	*/
2985	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2986	{
2987	/*
2988	* Free all the user records.
2989	*/
2990	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
2991
2992	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2993	uint16_t i = pPage->iUserHead;
2994	while (i != NIL_PGMPOOL_USER_INDEX)
2995	{
2996	/* Clear enter in user table. */
2997	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
2998
2999	/* Free it. */
3000	const uint16_t iNext = paUsers[i].iNext;
3001	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3002	paUsers[i].iNext = pPool->iUserFreeHead;
3003	pPool->iUserFreeHead = i;
3004
3005	/* Next. */
3006	i = iNext;
3007	}
3008	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3009	}
3010
3011	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3012
3013	/**
3014	* Allocates a new physical cross reference extent.
3015	*
3016	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3017	* @param pVM The VM handle.
3018	* @param piPhysExt Where to store the phys ext index.
3019	*/
3020	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3021	{
3022	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3023	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3024	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3025	{
3026	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3027	return NULL;
3028	}
3029	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3030	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3031	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3032	*piPhysExt = iPhysExt;
3033	return pPhysExt;
3034	}
3035
3036
3037	/**
3038	* Frees a physical cross reference extent.
3039	*
3040	* @param pVM The VM handle.
3041	* @param iPhysExt The extent to free.
3042	*/
3043	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3044	{
3045	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3046	Assert(iPhysExt < pPool->cMaxPhysExts);
3047	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3048	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3049	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3050	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3051	pPool->iPhysExtFreeHead = iPhysExt;
3052	}
3053
3054
3055	/**
3056	* Frees a physical cross reference extent.
3057	*
3058	* @param pVM The VM handle.
3059	* @param iPhysExt The extent to free.
3060	*/
3061	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3062	{
3063	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3064
3065	const uint16_t iPhysExtStart = iPhysExt;
3066	PPGMPOOLPHYSEXT pPhysExt;
3067	do
3068	{
3069	Assert(iPhysExt < pPool->cMaxPhysExts);
3070	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3071	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3072	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3073
3074	/* next */
3075	iPhysExt = pPhysExt->iNext;
3076	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3077
3078	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3079	pPool->iPhysExtFreeHead = iPhysExtStart;
3080	}
3081
3082
3083	/**
3084	* Insert a reference into a list of physical cross reference extents.
3085	*
3086	* @returns The new tracking data for PGMPAGE.
3087	*
3088	* @param pVM The VM handle.
3089	* @param iPhysExt The physical extent index of the list head.
3090	* @param iShwPT The shadow page table index.
3091	*
3092	*/
3093	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3094	{
3095	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3096	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3097
3098	/* special common case. */
3099	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3100	{
3101	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3102	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3103	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
3104	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3105	}
3106
3107	/* general treatment. */
3108	const uint16_t iPhysExtStart = iPhysExt;
3109	unsigned cMax = 15;
3110	for (;;)
3111	{
3112	Assert(iPhysExt < pPool->cMaxPhysExts);
3113	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3114	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3115	{
3116	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3117	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3118	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3119	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3120	}
3121	if (!--cMax)
3122	{
3123	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3124	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3125	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
3126	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3127	}
3128	}
3129
3130	/* add another extent to the list. */
3131	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3132	if (!pNew)
3133	{
3134	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3135	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3136	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3137	}
3138	pNew->iNext = iPhysExtStart;
3139	pNew->aidx[0] = iShwPT;
3140	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3141	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3142	}
3143
3144
3145	/**
3146	* Add a reference to guest physical page where extents are in use.
3147	*
3148	* @returns The new tracking data for PGMPAGE.
3149	*
3150	* @param pVM The VM handle.
3151	* @param u16 The ram range flags (top 16-bits).
3152	* @param iShwPT The shadow page table index.
3153	*/
3154	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3155	{
3156	pgmLock(pVM);
3157	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3158	{
3159	/*
3160	* Convert to extent list.
3161	*/
3162	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3163	uint16_t iPhysExt;
3164	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3165	if (pPhysExt)
3166	{
3167	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3168	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3169	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3170	pPhysExt->aidx[1] = iShwPT;
3171	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3172	}
3173	else
3174	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3175	}
3176	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3177	{
3178	/*
3179	* Insert into the extent list.
3180	*/
3181	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3182	}
3183	else
3184	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3185	pgmUnlock(pVM);
3186	return u16;
3187	}
3188
3189
3190	/**
3191	* Clear references to guest physical memory.
3192	*
3193	* @param pPool The pool.
3194	* @param pPage The page.
3195	* @param pPhysPage Pointer to the aPages entry in the ram range.
3196	*/
3197	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3198	{
3199	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3200	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3201
3202	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3203	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3204	{
3205	PVM pVM = pPool->CTX_SUFF(pVM);
3206	pgmLock(pVM);
3207
3208	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3209	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3210	do
3211	{
3212	Assert(iPhysExt < pPool->cMaxPhysExts);
3213
3214	/*
3215	* Look for the shadow page and check if it's all freed.
3216	*/
3217	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3218	{
3219	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3220	{
3221	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3222
3223	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3224	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3225	{
3226	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3227	pgmUnlock(pVM);
3228	return;
3229	}
3230
3231	/* we can free the node. */
3232	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3233	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3234	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3235	{
3236	/* lonely node */
3237	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3238	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3239	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3240	}
3241	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3242	{
3243	/* head */
3244	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3245	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3246	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3247	}
3248	else
3249	{
3250	/* in list */
3251	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3252	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3253	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3254	}
3255	iPhysExt = iPhysExtNext;
3256	pgmUnlock(pVM);
3257	return;
3258	}
3259	}
3260
3261	/* next */
3262	iPhysExtPrev = iPhysExt;
3263	iPhysExt = paPhysExts[iPhysExt].iNext;
3264	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3265
3266	pgmUnlock(pVM);
3267	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3268	}
3269	else /* nothing to do */
3270	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3271	}
3272
3273
3274	/**
3275	* Clear references to guest physical memory.
3276	*
3277	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3278	* is assumed to be correct, so the linear search can be skipped and we can assert
3279	* at an earlier point.
3280	*
3281	* @param pPool The pool.
3282	* @param pPage The page.
3283	* @param HCPhys The host physical address corresponding to the guest page.
3284	* @param GCPhys The guest physical address corresponding to HCPhys.
3285	*/
3286	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3287	{
3288	/*
3289	* Walk range list.
3290	*/
3291	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3292	while (pRam)
3293	{
3294	RTGCPHYS off = GCPhys - pRam->GCPhys;
3295	if (off < pRam->cb)
3296	{
3297	/* does it match? */
3298	const unsigned iPage = off >> PAGE_SHIFT;
3299	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3300	#ifdef LOG_ENABLED
3301	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3302	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3303	#endif
3304	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3305	{
3306	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3307	return;
3308	}
3309	break;
3310	}
3311	pRam = pRam->CTX_SUFF(pNext);
3312	}
3313	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3314	}
3315
3316
3317	/**
3318	* Clear references to guest physical memory.
3319	*
3320	* @param pPool The pool.
3321	* @param pPage The page.
3322	* @param HCPhys The host physical address corresponding to the guest page.
3323	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3324	*/
3325	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3326	{
3327	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3328
3329	/*
3330	* Walk range list.
3331	*/
3332	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3333	while (pRam)
3334	{
3335	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3336	if (off < pRam->cb)
3337	{
3338	/* does it match? */
3339	const unsigned iPage = off >> PAGE_SHIFT;
3340	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3341	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3342	{
3343	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3344	return;
3345	}
3346	break;
3347	}
3348	pRam = pRam->CTX_SUFF(pNext);
3349	}
3350
3351	/*
3352	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3353	*/
3354	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3355	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3356	while (pRam)
3357	{
3358	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3359	while (iPage-- > 0)
3360	{
3361	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3362	{
3363	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3364	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3365	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3366	return;
3367	}
3368	}
3369	pRam = pRam->CTX_SUFF(pNext);
3370	}
3371
3372	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3373	}
3374
3375
3376	/**
3377	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3378	*
3379	* @param pPool The pool.
3380	* @param pPage The page.
3381	* @param pShwPT The shadow page table (mapping of the page).
3382	* @param pGstPT The guest page table.
3383	*/
3384	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3385	{
3386	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3387	if (pShwPT->a[i].n.u1Present)
3388	{
3389	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3390	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3391	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3392	if (!--pPage->cPresent)
3393	break;
3394	}
3395	}
3396
3397
3398	/**
3399	* Clear references to guest physical memory in a PAE / 32-bit page table.
3400	*
3401	* @param pPool The pool.
3402	* @param pPage The page.
3403	* @param pShwPT The shadow page table (mapping of the page).
3404	* @param pGstPT The guest page table (just a half one).
3405	*/
3406	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3407	{
3408	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3409	if (pShwPT->a[i].n.u1Present)
3410	{
3411	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3412	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3413	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3414	}
3415	}
3416
3417
3418	/**
3419	* Clear references to guest physical memory in a PAE / PAE page table.
3420	*
3421	* @param pPool The pool.
3422	* @param pPage The page.
3423	* @param pShwPT The shadow page table (mapping of the page).
3424	* @param pGstPT The guest page table.
3425	*/
3426	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3427	{
3428	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3429	if (pShwPT->a[i].n.u1Present)
3430	{
3431	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3432	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3433	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3434	}
3435	}
3436
3437
3438	/**
3439	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3440	*
3441	* @param pPool The pool.
3442	* @param pPage The page.
3443	* @param pShwPT The shadow page table (mapping of the page).
3444	*/
3445	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3446	{
3447	RTGCPHYS GCPhys = pPage->GCPhys;
3448	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3449	if (pShwPT->a[i].n.u1Present)
3450	{
3451	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3452	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3453	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3454	}
3455	}
3456
3457
3458	/**
3459	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3460	*
3461	* @param pPool The pool.
3462	* @param pPage The page.
3463	* @param pShwPT The shadow page table (mapping of the page).
3464	*/
3465	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3466	{
3467	RTGCPHYS GCPhys = pPage->GCPhys;
3468	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3469	if (pShwPT->a[i].n.u1Present)
3470	{
3471	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3472	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3473	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3474	}
3475	}
3476
3477	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3478
3479
3480	/**
3481	* Clear references to shadowed pages in a 32 bits page directory.
3482	*
3483	* @param pPool The pool.
3484	* @param pPage The page.
3485	* @param pShwPD The shadow page directory (mapping of the page).
3486	*/
3487	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3488	{
3489	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3490	{
3491	if ( pShwPD->a[i].n.u1Present
3492	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3493	)
3494	{
3495	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3496	if (pSubPage)
3497	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3498	else
3499	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3500	}
3501	}
3502	}
3503
3504	/**
3505	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3506	*
3507	* @param pPool The pool.
3508	* @param pPage The page.
3509	* @param pShwPD The shadow page directory (mapping of the page).
3510	*/
3511	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3512	{
3513	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3514	{
3515	if ( pShwPD->a[i].n.u1Present
3516	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3517	)
3518	{
3519	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3520	if (pSubPage)
3521	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3522	else
3523	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3524	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3525	}
3526	}
3527	}
3528
3529	/**
3530	* Clear references to shadowed pages in a PAE page directory pointer table.
3531	*
3532	* @param pPool The pool.
3533	* @param pPage The page.
3534	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3535	*/
3536	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3537	{
3538	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3539	{
3540	if ( pShwPDPT->a[i].n.u1Present
3541	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3542	)
3543	{
3544	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3545	if (pSubPage)
3546	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3547	else
3548	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3549	}
3550	}
3551	}
3552
3553
3554	/**
3555	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3556	*
3557	* @param pPool The pool.
3558	* @param pPage The page.
3559	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3560	*/
3561	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3562	{
3563	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3564	{
3565	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3566	if (pShwPDPT->a[i].n.u1Present)
3567	{
3568	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3569	if (pSubPage)
3570	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3571	else
3572	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3573	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3574	}
3575	}
3576	}
3577
3578
3579	/**
3580	* Clear references to shadowed pages in a 64-bit level 4 page table.
3581	*
3582	* @param pPool The pool.
3583	* @param pPage The page.
3584	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3585	*/
3586	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3587	{
3588	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3589	{
3590	if (pShwPML4->a[i].n.u1Present)
3591	{
3592	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3593	if (pSubPage)
3594	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3595	else
3596	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3597	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3598	}
3599	}
3600	}
3601
3602
3603	/**
3604	* Clear references to shadowed pages in an EPT page table.
3605	*
3606	* @param pPool The pool.
3607	* @param pPage The page.
3608	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3609	*/
3610	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3611	{
3612	RTGCPHYS GCPhys = pPage->GCPhys;
3613	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3614	if (pShwPT->a[i].n.u1Present)
3615	{
3616	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3617	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3618	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3619	}
3620	}
3621
3622
3623	/**
3624	* Clear references to shadowed pages in an EPT page directory.
3625	*
3626	* @param pPool The pool.
3627	* @param pPage The page.
3628	* @param pShwPD The shadow page directory (mapping of the page).
3629	*/
3630	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3631	{
3632	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3633	{
3634	if (pShwPD->a[i].n.u1Present)
3635	{
3636	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3637	if (pSubPage)
3638	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3639	else
3640	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3641	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3642	}
3643	}
3644	}
3645
3646
3647	/**
3648	* Clear references to shadowed pages in an EPT page directory pointer table.
3649	*
3650	* @param pPool The pool.
3651	* @param pPage The page.
3652	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3653	*/
3654	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3655	{
3656	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3657	{
3658	if (pShwPDPT->a[i].n.u1Present)
3659	{
3660	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3661	if (pSubPage)
3662	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3663	else
3664	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3665	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3666	}
3667	}
3668	}
3669
3670
3671	/**
3672	* Clears all references made by this page.
3673	*
3674	* This includes other shadow pages and GC physical addresses.
3675	*
3676	* @param pPool The pool.
3677	* @param pPage The page.
3678	*/
3679	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3680	{
3681	/*
3682	* Map the shadow page and take action according to the page kind.
3683	*/
3684	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3685	switch (pPage->enmKind)
3686	{
3687	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3688	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3689	{
3690	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3691	void *pvGst;
3692	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3693	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3694	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3695	break;
3696	}
3697
3698	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3699	{
3700	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3701	void *pvGst;
3702	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3703	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3704	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3705	break;
3706	}
3707
3708	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3709	{
3710	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3711	void *pvGst;
3712	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3713	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3714	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3715	break;
3716	}
3717
3718	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3719	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3720	{
3721	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3722	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3723	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3724	break;
3725	}
3726
3727	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3728	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3729	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3730	{
3731	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3732	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3733	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3734	break;
3735	}
3736
3737	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3738	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3739	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3740	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3741	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3742	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3743	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3744	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3745	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3746	break;
3747	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3748
3749	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3750	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3751	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3752	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3753	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3754	case PGMPOOLKIND_PAE_PD_PHYS:
3755	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3756	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3757	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3758	break;
3759
3760	case PGMPOOLKIND_32BIT_PD_PHYS:
3761	case PGMPOOLKIND_32BIT_PD:
3762	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3763	break;
3764
3765	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3766	case PGMPOOLKIND_PAE_PDPT:
3767	case PGMPOOLKIND_PAE_PDPT_PHYS:
3768	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3769	break;
3770
3771	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3772	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3773	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3774	break;
3775
3776	case PGMPOOLKIND_64BIT_PML4:
3777	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3778	break;
3779
3780	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3781	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3782	break;
3783
3784	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3785	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3786	break;
3787
3788	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3789	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3790	break;
3791
3792	default:
3793	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3794	}
3795
3796	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3797	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3798	ASMMemZeroPage(pvShw);
3799	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3800	pPage->fZeroed = true;
3801	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3802	}
3803
3804	#endif /* PGMPOOL_WITH_USER_TRACKING */
3805	#ifdef IN_RING3
3806	/**
3807	* Flushes the entire cache.
3808	*
3809	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
3810	* and execute this CR3 flush.
3811	*
3812	* @param pPool The pool.
3813	*
3814	* @remark Only used during reset now, we might want to rename and/or move it.
3815	*/
3816	static void pgmPoolFlushAllInt(PPGMPOOL pPool)
3817	{
3818	PVM pVM = pPool->CTX_SUFF(pVM);
3819
3820	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
3821	LogFlow(("pgmPoolFlushAllInt:\n"));
3822
3823	/*
3824	* If there are no pages in the pool, there is nothing to do.
3825	*/
3826	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
3827	{
3828	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3829	return;
3830	}
3831
3832	/*
3833	* Exit the shadow mode since we're going to clear everything,
3834	* including the root page.
3835	*/
3836	/** @todo Need to synchronize this across all VCPUs! */
3837	Assert(pVM->cCPUs == 1);
3838	for (unsigned i=0;i<pVM->cCPUs;i++)
3839	{
3840	PVMCPU pVCpu = &pVM->aCpus[i];
3841	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
3842	}
3843
3844	/*
3845	* Nuke the free list and reinsert all pages into it.
3846	*/
3847	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
3848	{
3849	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3850
3851	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
3852	#ifdef PGMPOOL_WITH_MONITORING
3853	if (pPage->fMonitored)
3854	pgmPoolMonitorFlush(pPool, pPage);
3855	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3856	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3857	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3858	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3859	pPage->cModifications = 0;
3860	#endif
3861	pPage->GCPhys = NIL_RTGCPHYS;
3862	pPage->enmKind = PGMPOOLKIND_FREE;
3863	Assert(pPage->idx == i);
3864	pPage->iNext = i + 1;
3865	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
3866	pPage->fSeenNonGlobal = false;
3867	pPage->fMonitored= false;
3868	pPage->fCached = false;
3869	pPage->fReusedFlushPending = false;
3870	#ifdef PGMPOOL_WITH_USER_TRACKING
3871	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3872	#else
3873	pPage->fCR3Mix = false;
3874	#endif
3875	#ifdef PGMPOOL_WITH_CACHE
3876	pPage->iAgeNext = NIL_PGMPOOL_IDX;
3877	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3878	#endif
3879	pPage->cLocked = 0;
3880	}
3881	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
3882	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
3883	pPool->cUsedPages = 0;
3884
3885	#ifdef PGMPOOL_WITH_USER_TRACKING
3886	/*
3887	* Zap and reinitialize the user records.
3888	*/
3889	pPool->cPresent = 0;
3890	pPool->iUserFreeHead = 0;
3891	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3892	const unsigned cMaxUsers = pPool->cMaxUsers;
3893	for (unsigned i = 0; i < cMaxUsers; i++)
3894	{
3895	paUsers[i].iNext = i + 1;
3896	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3897	paUsers[i].iUserTable = 0xfffffffe;
3898	}
3899	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
3900	#endif
3901
3902	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3903	/*
3904	* Clear all the GCPhys links and rebuild the phys ext free list.
3905	*/
3906	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
3907	pRam;
3908	pRam = pRam->CTX_SUFF(pNext))
3909	{
3910	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3911	while (iPage-- > 0)
3912	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
3913	}
3914
3915	pPool->iPhysExtFreeHead = 0;
3916	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3917	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
3918	for (unsigned i = 0; i < cMaxPhysExts; i++)
3919	{
3920	paPhysExts[i].iNext = i + 1;
3921	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
3922	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
3923	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
3924	}
3925	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3926	#endif
3927
3928	#ifdef PGMPOOL_WITH_MONITORING
3929	/*
3930	* Just zap the modified list.
3931	*/
3932	pPool->cModifiedPages = 0;
3933	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
3934	#endif
3935
3936	#ifdef PGMPOOL_WITH_CACHE
3937	/*
3938	* Clear the GCPhys hash and the age list.
3939	*/
3940	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
3941	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
3942	pPool->iAgeHead = NIL_PGMPOOL_IDX;
3943	pPool->iAgeTail = NIL_PGMPOOL_IDX;
3944	#endif
3945
3946	/*
3947	* Reinsert active pages into the hash and ensure monitoring chains are correct.
3948	*/
3949	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
3950	{
3951	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3952	pPage->iNext = NIL_PGMPOOL_IDX;
3953	#ifdef PGMPOOL_WITH_MONITORING
3954	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3955	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3956	pPage->cModifications = 0;
3957	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
3958	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3959	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3960	if (pPage->fMonitored)
3961	{
3962	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
3963	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
3964	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
3965	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
3966	pPool->pszAccessHandler);
3967	AssertFatalRCSuccess(rc);
3968	# ifdef PGMPOOL_WITH_CACHE
3969	pgmPoolHashInsert(pPool, pPage);
3970	# endif
3971	}
3972	#endif
3973	#ifdef PGMPOOL_WITH_USER_TRACKING
3974	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
3975	#endif
3976	#ifdef PGMPOOL_WITH_CACHE
3977	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
3978	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
3979	#endif
3980	}
3981
3982	for (unsigned i=0;i<pVM->cCPUs;i++)
3983	{
3984	PVMCPU pVCpu = &pVM->aCpus[i];
3985	/*
3986	* Re-enter the shadowing mode and assert Sync CR3 FF.
3987	*/
3988	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
3989	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3990	}
3991
3992	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3993	}
3994
3995	#endif /* IN_RING3 */
3996
3997	/**
3998	* Flushes a pool page.
3999	*
4000	* This moves the page to the free list after removing all user references to it.
4001	* In GC this will cause a CR3 reload if the page is traced back to an active root page.
4002	*
4003	* @returns VBox status code.
4004	* @retval VINF_SUCCESS on success.
4005	* @param pPool The pool.
4006	* @param HCPhys The HC physical address of the shadow page.
4007	*/
4008	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4009	{
4010	PVM pVM = pPool->CTX_SUFF(pVM);
4011
4012	int rc = VINF_SUCCESS;
4013	STAM_PROFILE_START(&pPool->StatFlushPage, f);
4014	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4015	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4016
4017	/*
4018	* Quietly reject any attempts at flushing any of the special root pages.
4019	*/
4020	if (pPage->idx < PGMPOOL_IDX_FIRST)
4021	{
4022	AssertFailed(); /* can no longer happen */
4023	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4024	return VINF_SUCCESS;
4025	}
4026
4027	pgmLock(pVM);
4028
4029	/*
4030	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4031	*/
4032	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4033	{
4034	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4035	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4036	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4037	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4038	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4039	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4040	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4041	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4042	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4043	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4044	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4045	pgmUnlock(pVM);
4046	return VINF_SUCCESS;
4047	}
4048
4049	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4050	/* Start a subset so we won't run out of mapping space. */
4051	PVMCPU pVCpu = VMMGetCpu(pVM);
4052	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4053	#endif
4054
4055	/*
4056	* Mark the page as being in need of a ASMMemZeroPage().
4057	*/
4058	pPage->fZeroed = false;
4059
4060	#ifdef PGMPOOL_WITH_USER_TRACKING
4061	/*
4062	* Clear the page.
4063	*/
4064	pgmPoolTrackClearPageUsers(pPool, pPage);
4065	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4066	pgmPoolTrackDeref(pPool, pPage);
4067	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4068	#endif
4069
4070	#ifdef PGMPOOL_WITH_CACHE
4071	/*
4072	* Flush it from the cache.
4073	*/
4074	pgmPoolCacheFlushPage(pPool, pPage);
4075	#endif /* PGMPOOL_WITH_CACHE */
4076
4077	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4078	/* Heavy stuff done. */
4079	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4080	#endif
4081
4082	#ifdef PGMPOOL_WITH_MONITORING
4083	/*
4084	* Deregistering the monitoring.
4085	*/
4086	if (pPage->fMonitored)
4087	rc = pgmPoolMonitorFlush(pPool, pPage);
4088	#endif
4089
4090	/*
4091	* Free the page.
4092	*/
4093	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4094	pPage->iNext = pPool->iFreeHead;
4095	pPool->iFreeHead = pPage->idx;
4096	pPage->enmKind = PGMPOOLKIND_FREE;
4097	pPage->GCPhys = NIL_RTGCPHYS;
4098	pPage->fReusedFlushPending = false;
4099
4100	pPool->cUsedPages--;
4101	pgmUnlock(pVM);
4102	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4103	return rc;
4104	}
4105
4106
4107	/**
4108	* Frees a usage of a pool page.
4109	*
4110	* The caller is responsible to updating the user table so that it no longer
4111	* references the shadow page.
4112	*
4113	* @param pPool The pool.
4114	* @param HCPhys The HC physical address of the shadow page.
4115	* @param iUser The shadow page pool index of the user table.
4116	* @param iUserTable The index into the user table (shadowed).
4117	*/
4118	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4119	{
4120	PVM pVM = pPool->CTX_SUFF(pVM);
4121
4122	STAM_PROFILE_START(&pPool->StatFree, a);
4123	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4124	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4125	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4126	pgmLock(pVM);
4127	#ifdef PGMPOOL_WITH_USER_TRACKING
4128	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4129	#endif
4130	#ifdef PGMPOOL_WITH_CACHE
4131	if (!pPage->fCached)
4132	#endif
4133	pgmPoolFlushPage(pPool, pPage);
4134	pgmUnlock(pVM);
4135	STAM_PROFILE_STOP(&pPool->StatFree, a);
4136	}
4137
4138
4139	/**
4140	* Makes one or more free page free.
4141	*
4142	* @returns VBox status code.
4143	* @retval VINF_SUCCESS on success.
4144	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4145	*
4146	* @param pPool The pool.
4147	* @param enmKind Page table kind
4148	* @param iUser The user of the page.
4149	*/
4150	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4151	{
4152	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4153
4154	/*
4155	* If the pool isn't full grown yet, expand it.
4156	*/
4157	if ( pPool->cCurPages < pPool->cMaxPages
4158	#if defined(IN_RC)
4159	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4160	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4161	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4162	#endif
4163	)
4164	{
4165	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4166	#ifdef IN_RING3
4167	int rc = PGMR3PoolGrow(pPool->pVMR3);
4168	#else
4169	int rc = CTXALLMID(VMM, CallHost)(pPool->CTX_SUFF(pVM), VMMCALLHOST_PGM_POOL_GROW, 0);
4170	#endif
4171	if (RT_FAILURE(rc))
4172	return rc;
4173	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4174	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4175	return VINF_SUCCESS;
4176	}
4177
4178	#ifdef PGMPOOL_WITH_CACHE
4179	/*
4180	* Free one cached page.
4181	*/
4182	return pgmPoolCacheFreeOne(pPool, iUser);
4183	#else
4184	/*
4185	* Flush the pool.
4186	*
4187	* If we have tracking enabled, it should be possible to come up with
4188	* a cheap replacement strategy...
4189	*/
4190	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4191	AssertCompileFailed();
4192	Assert(!CPUMIsGuestInLongMode(pVM));
4193	pgmPoolFlushAllInt(pPool);
4194	return VERR_PGM_POOL_FLUSHED;
4195	#endif
4196	}
4197
4198
4199	/**
4200	* Allocates a page from the pool.
4201	*
4202	* This page may actually be a cached page and not in need of any processing
4203	* on the callers part.
4204	*
4205	* @returns VBox status code.
4206	* @retval VINF_SUCCESS if a NEW page was allocated.
4207	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4208	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4209	* @param pVM The VM handle.
4210	* @param GCPhys The GC physical address of the page we're gonna shadow.
4211	* For 4MB and 2MB PD entries, it's the first address the
4212	* shadow PT is covering.
4213	* @param enmKind The kind of mapping.
4214	* @param iUser The shadow page pool index of the user table.
4215	* @param iUserTable The index into the user table (shadowed).
4216	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4217	*/
4218	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
4219	{
4220	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4221	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4222	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4223	*ppPage = NULL;
4224	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4225	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4226	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)); */
4227
4228	pgmLock(pVM);
4229
4230	#ifdef PGMPOOL_WITH_CACHE
4231	if (pPool->fCacheEnabled)
4232	{
4233	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, iUser, iUserTable, ppPage);
4234	if (RT_SUCCESS(rc2))
4235	{
4236	pgmUnlock(pVM);
4237	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4238	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4239	return rc2;
4240	}
4241	}
4242	#endif
4243
4244	/*
4245	* Allocate a new one.
4246	*/
4247	int rc = VINF_SUCCESS;
4248	uint16_t iNew = pPool->iFreeHead;
4249	if (iNew == NIL_PGMPOOL_IDX)
4250	{
4251	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4252	if (RT_FAILURE(rc))
4253	{
4254	pgmUnlock(pVM);
4255	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4256	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4257	return rc;
4258	}
4259	iNew = pPool->iFreeHead;
4260	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4261	}
4262
4263	/* unlink the free head */
4264	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4265	pPool->iFreeHead = pPage->iNext;
4266	pPage->iNext = NIL_PGMPOOL_IDX;
4267
4268	/*
4269	* Initialize it.
4270	*/
4271	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4272	pPage->enmKind = enmKind;
4273	pPage->GCPhys = GCPhys;
4274	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4275	pPage->fMonitored = false;
4276	pPage->fCached = false;
4277	pPage->fReusedFlushPending = false;
4278	#ifdef PGMPOOL_WITH_MONITORING
4279	pPage->cModifications = 0;
4280	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4281	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4282	#else
4283	pPage->fCR3Mix = false;
4284	#endif
4285	#ifdef PGMPOOL_WITH_USER_TRACKING
4286	pPage->cPresent = 0;
4287	pPage->iFirstPresent = ~0;
4288
4289	/*
4290	* Insert into the tracking and cache. If this fails, free the page.
4291	*/
4292	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4293	if (RT_FAILURE(rc3))
4294	{
4295	pPool->cUsedPages--;
4296	pPage->enmKind = PGMPOOLKIND_FREE;
4297	pPage->GCPhys = NIL_RTGCPHYS;
4298	pPage->iNext = pPool->iFreeHead;
4299	pPool->iFreeHead = pPage->idx;
4300	pgmUnlock(pVM);
4301	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4302	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4303	return rc3;
4304	}
4305	#endif /* PGMPOOL_WITH_USER_TRACKING */
4306
4307	/*
4308	* Commit the allocation, clear the page and return.
4309	*/
4310	#ifdef VBOX_WITH_STATISTICS
4311	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4312	pPool->cUsedPagesHigh = pPool->cUsedPages;
4313	#endif
4314
4315	if (!pPage->fZeroed)
4316	{
4317	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4318	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4319	ASMMemZeroPage(pv);
4320	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4321	}
4322
4323	*ppPage = pPage;
4324	pgmUnlock(pVM);
4325	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4326	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4327	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4328	return rc;
4329	}
4330
4331
4332	/**
4333	* Frees a usage of a pool page.
4334	*
4335	* @param pVM The VM handle.
4336	* @param HCPhys The HC physical address of the shadow page.
4337	* @param iUser The shadow page pool index of the user table.
4338	* @param iUserTable The index into the user table (shadowed).
4339	*/
4340	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4341	{
4342	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4343	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4344	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4345	}
4346
4347	/**
4348	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4349	*
4350	* @returns Pointer to the shadow page structure.
4351	* @param pPool The pool.
4352	* @param HCPhys The HC physical address of the shadow page.
4353	*/
4354	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4355	{
4356	PVM pVM = pPool->CTX_SUFF(pVM);
4357
4358	/*
4359	* Look up the page.
4360	*/
4361	pgmLock(pVM);
4362	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4363	pgmUnlock(pVM);
4364
4365	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4366	return pPage;
4367	}
4368
4369
4370	#ifdef IN_RING3
4371	/**
4372	* Flushes the entire cache.
4373	*
4374	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4375	* and execute this CR3 flush.
4376	*
4377	* @param pPool The pool.
4378	*/
4379	void pgmPoolFlushAll(PVM pVM)
4380	{
4381	LogFlow(("pgmPoolFlushAll:\n"));
4382	pgmPoolFlushAllInt(pVM->pgm.s.CTX_SUFF(pPool));
4383	}
4384	#endif /* IN_RING3 */
4385
4386	#ifdef LOG_ENABLED
4387	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4388	{
4389	switch(enmKind)
4390	{
4391	case PGMPOOLKIND_INVALID:
4392	return "PGMPOOLKIND_INVALID";
4393	case PGMPOOLKIND_FREE:
4394	return "PGMPOOLKIND_FREE";
4395	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4396	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4397	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4398	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4399	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4400	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4401	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4402	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4403	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4404	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4405	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4406	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4407	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4408	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4409	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4410	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4411	case PGMPOOLKIND_32BIT_PD:
4412	return "PGMPOOLKIND_32BIT_PD";
4413	case PGMPOOLKIND_32BIT_PD_PHYS:
4414	return "PGMPOOLKIND_32BIT_PD_PHYS";
4415	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4416	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4417	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4418	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4419	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4420	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4421	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4422	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4423	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4424	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4425	case PGMPOOLKIND_PAE_PD_PHYS:
4426	return "PGMPOOLKIND_PAE_PD_PHYS";
4427	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4428	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4429	case PGMPOOLKIND_PAE_PDPT:
4430	return "PGMPOOLKIND_PAE_PDPT";
4431	case PGMPOOLKIND_PAE_PDPT_PHYS:
4432	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4433	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4434	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4435	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4436	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4437	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4438	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4439	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4440	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4441	case PGMPOOLKIND_64BIT_PML4:
4442	return "PGMPOOLKIND_64BIT_PML4";
4443	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4444	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4445	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4446	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4447	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4448	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4449	case PGMPOOLKIND_ROOT_NESTED:
4450	return "PGMPOOLKIND_ROOT_NESTED";
4451	}
4452	return "Unknown kind!";
4453	}
4454	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 19690

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