PGMAllPool.cpp@ 19752

Last change on this file since 19752 was 19721, checked in by vboxsync, 16 years ago
Locking assertions
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 160.9 KB

Line
1	/* $Id: PGMAllPool.cpp 19721 2009-05-15 09:17:14Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	__BEGIN_DECLS
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	__END_DECLS
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pCpu The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
249	{
250	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	uShw.pPT->a[iShw].u = 0;
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	uShw.pPTPae->a[iShw].u = 0;
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	uShw.pPDPae->a[iShw+i].u = 0;
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pCpu
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	uShw.pPDPae->a[iShw2].u = 0;
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	uShw.pPTPae->a[iShw].u = 0;
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pCpu
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	uShw.pPTPae->a[iShw2].u = 0;
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	uShw.pPD->a[iShw].u = 0;
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pCpu
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	uShw.pPD->a[iShw2].u = 0;
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	uShw.pPD->a[iShw].u = 0;
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	uShw.pPDPae->a[iShw].u = 0;
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pCpu
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	uShw.pPDPae->a[iShw2].u = 0;
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	uShw.pPDPT->a[iShw].u = 0;
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pCpu
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	uShw.pPDPT->a[iShw2].u = 0;
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	uShw.pPDPae->a[iShw].u = 0;
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pCpu
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	uShw.pPDPae->a[iShw2].u = 0;
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	uShw.pPDPT->a[iShw].u = 0;
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pCpu
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	uShw.pPDPT->a[iShw2].u = 0;
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	uShw.pPML4->a[iShw].u = 0;
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pCpu
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	uShw.pPML4->a[iShw2].u = 0;
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pCpu The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pCpu->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pPage The page in question.
823	* @param pRegFrame Trap register frame.
824	* @param pCpu The disassembly info for the faulting instruction.
825	* @param pvFault The fault address.
826	*
827	* @remark The REP prefix check is left to the caller because of STOSD/W.
828	*/
829	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PPGMPOOLPAGE pPage, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
830	{
831	#ifndef IN_RC
832	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
833	if ( HWACCMHasPendingIrq(pVM)
834	&& (pRegFrame->rsp - pvFault) < 32)
835	{
836	/* Fault caused by stack writes while trying to inject an interrupt event. */
837	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
838	return true;
839	}
840	#else
841	NOREF(pVM); NOREF(pvFault);
842	#endif
843
844	switch (pCpu->pCurInstr->opcode)
845	{
846	/* call implies the actual push of the return address faulted */
847	case OP_CALL:
848	Log4(("pgmPoolMonitorIsReused: CALL\n"));
849	return true;
850	case OP_PUSH:
851	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
852	return true;
853	case OP_PUSHF:
854	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
855	return true;
856	case OP_PUSHA:
857	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
858	return true;
859	case OP_FXSAVE:
860	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
861	return true;
862	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
863	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
864	return true;
865	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
866	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
867	return true;
868	case OP_MOVSWD:
869	case OP_STOSWD:
870	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
871	&& pRegFrame->rcx >= 0x40
872	)
873	{
874	Assert(pCpu->mode == CPUMODE_64BIT);
875
876	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
877	return true;
878	}
879	return false;
880	}
881	if ( (pCpu->param1.flags & USE_REG_GEN32)
882	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
883	{
884	Log4(("pgmPoolMonitorIsReused: ESP\n"));
885	return true;
886	}
887
888	//if (pPage->fCR3Mix)
889	// return false;
890	return false;
891	}
892
893
894	/**
895	* Flushes the page being accessed.
896	*
897	* @returns VBox status code suitable for scheduling.
898	* @param pVM The VM handle.
899	* @param pVCpu The VMCPU handle.
900	* @param pPool The pool.
901	* @param pPage The pool page (head).
902	* @param pCpu The disassembly of the write instruction.
903	* @param pRegFrame The trap register frame.
904	* @param GCPhysFault The fault address as guest physical address.
905	* @param pvFault The fault address.
906	*/
907	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
908	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
909	{
910	/*
911	* First, do the flushing.
912	*/
913	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
914
915	/*
916	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
917	*/
918	uint32_t cbWritten;
919	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
920	if (RT_SUCCESS(rc2))
921	pRegFrame->rip += pCpu->opsize;
922	else if (rc2 == VERR_EM_INTERPRETER)
923	{
924	#ifdef IN_RC
925	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
926	{
927	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
928	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
929	rc = VINF_SUCCESS;
930	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
931	}
932	else
933	#endif
934	{
935	rc = VINF_EM_RAW_EMULATE_INSTR;
936	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
937	}
938	}
939	else
940	rc = rc2;
941
942	/* See use in pgmPoolAccessHandlerSimple(). */
943	PGM_INVL_GUEST_TLBS();
944
945	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
946	return rc;
947
948	}
949
950
951	/**
952	* Handles the STOSD write accesses.
953	*
954	* @returns VBox status code suitable for scheduling.
955	* @param pVM The VM handle.
956	* @param pPool The pool.
957	* @param pPage The pool page (head).
958	* @param pCpu The disassembly of the write instruction.
959	* @param pRegFrame The trap register frame.
960	* @param GCPhysFault The fault address as guest physical address.
961	* @param pvFault The fault address.
962	*/
963	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
964	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
965	{
966	Assert(pCpu->mode == CPUMODE_32BIT);
967
968	Log3(("pgmPoolAccessHandlerSTOSD\n"));
969
970	/*
971	* Increment the modification counter and insert it into the list
972	* of modified pages the first time.
973	*/
974	if (!pPage->cModifications++)
975	pgmPoolMonitorModifiedInsert(pPool, pPage);
976
977	/*
978	* Execute REP STOSD.
979	*
980	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
981	* write situation, meaning that it's safe to write here.
982	*/
983	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
984	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
985	while (pRegFrame->ecx)
986	{
987	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
988	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
989	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
990	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
991	#else
992	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
993	#endif
994	#ifdef IN_RC
995	(uint32_t )pu32 = pRegFrame->eax;
996	#else
997	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
998	#endif
999	pu32 += 4;
1000	GCPhysFault += 4;
1001	pRegFrame->edi += 4;
1002	pRegFrame->ecx--;
1003	}
1004	pRegFrame->rip += pCpu->opsize;
1005
1006	#ifdef IN_RC
1007	/* See use in pgmPoolAccessHandlerSimple(). */
1008	PGM_INVL_GUEST_TLBS();
1009	#endif
1010
1011	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1012	return VINF_SUCCESS;
1013	}
1014
1015
1016	/**
1017	* Handles the simple write accesses.
1018	*
1019	* @returns VBox status code suitable for scheduling.
1020	* @param pVM The VM handle.
1021	* @param pVCpu The VMCPU handle.
1022	* @param pPool The pool.
1023	* @param pPage The pool page (head).
1024	* @param pCpu The disassembly of the write instruction.
1025	* @param pRegFrame The trap register frame.
1026	* @param GCPhysFault The fault address as guest physical address.
1027	* @param pvFault The fault address.
1028	*/
1029	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
1030	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1031	{
1032	Log3(("pgmPoolAccessHandlerSimple\n"));
1033	/*
1034	* Increment the modification counter and insert it into the list
1035	* of modified pages the first time.
1036	*/
1037	if (!pPage->cModifications++)
1038	pgmPoolMonitorModifiedInsert(pPool, pPage);
1039
1040	/*
1041	* Clear all the pages. ASSUMES that pvFault is readable.
1042	*/
1043	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1044	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1045	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1046	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1047	#else
1048	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1049	#endif
1050
1051	/*
1052	* Interpret the instruction.
1053	*/
1054	uint32_t cb;
1055	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
1056	if (RT_SUCCESS(rc))
1057	pRegFrame->rip += pCpu->opsize;
1058	else if (rc == VERR_EM_INTERPRETER)
1059	{
1060	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1061	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
1062	rc = VINF_EM_RAW_EMULATE_INSTR;
1063	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1064	}
1065
1066	#ifdef IN_RC
1067	/*
1068	* Quick hack, with logging enabled we're getting stale
1069	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1070	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1071	* have to be fixed to support this. But that'll have to wait till next week.
1072	*
1073	* An alternative is to keep track of the changed PTEs together with the
1074	* GCPhys from the guest PT. This may proove expensive though.
1075	*
1076	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1077	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1078	*/
1079	PGM_INVL_GUEST_TLBS();
1080	#endif
1081
1082	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1083	return rc;
1084	}
1085
1086	/**
1087	* \#PF Handler callback for PT write accesses.
1088	*
1089	* @returns VBox status code (appropriate for GC return).
1090	* @param pVM VM Handle.
1091	* @param uErrorCode CPU Error code.
1092	* @param pRegFrame Trap register frame.
1093	* NULL on DMA and other non CPU access.
1094	* @param pvFault The fault address (cr2).
1095	* @param GCPhysFault The GC physical address corresponding to pvFault.
1096	* @param pvUser User argument.
1097	*/
1098	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1099	{
1100	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1101	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1102	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1103	PVMCPU pVCpu = VMMGetCpu(pVM);
1104
1105	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1106
1107	/*
1108	* We should ALWAYS have the list head as user parameter. This
1109	* is because we use that page to record the changes.
1110	*/
1111	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1112
1113	/*
1114	* Disassemble the faulting instruction.
1115	*/
1116	DISCPUSTATE Cpu;
1117	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
1118	AssertRCReturn(rc, rc);
1119
1120	pgmLock(pVM);
1121
1122	/*
1123	* Check if it's worth dealing with.
1124	*/
1125	bool fReused = false;
1126	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1127	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1128	)
1129	&& !(fReused = pgmPoolMonitorIsReused(pVM, pPage, pRegFrame, &Cpu, pvFault))
1130	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1131	{
1132	/*
1133	* Simple instructions, no REP prefix.
1134	*/
1135	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1136	{
1137	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1138	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1139	pgmUnlock(pVM);
1140	return rc;
1141	}
1142
1143	/*
1144	* Windows is frequently doing small memset() operations (netio test 4k+).
1145	* We have to deal with these or we'll kill the cache and performance.
1146	*/
1147	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1148	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1149	&& pRegFrame->ecx <= 0x20
1150	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1151	&& !((uintptr_t)pvFault & 3)
1152	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1153	&& Cpu.mode == CPUMODE_32BIT
1154	&& Cpu.opmode == CPUMODE_32BIT
1155	&& Cpu.addrmode == CPUMODE_32BIT
1156	&& Cpu.prefix == PREFIX_REP
1157	&& !pRegFrame->eflags.Bits.u1DF
1158	)
1159	{
1160	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1161	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1162	pgmUnlock(pVM);
1163	return rc;
1164	}
1165
1166	/* REP prefix, don't bother. */
1167	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1168	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1169	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1170	}
1171
1172	/*
1173	* Not worth it, so flush it.
1174	*
1175	* If we considered it to be reused, don't go back to ring-3
1176	* to emulate failed instructions since we usually cannot
1177	* interpret then. This may be a bit risky, in which case
1178	* the reuse detection must be fixed.
1179	*/
1180	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1181	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1182	rc = VINF_SUCCESS;
1183	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1184	pgmUnlock(pVM);
1185	return rc;
1186	}
1187
1188	# endif /* !IN_RING3 */
1189	#endif /* PGMPOOL_WITH_MONITORING */
1190
1191	#ifdef PGMPOOL_WITH_CACHE
1192
1193	/**
1194	* Inserts a page into the GCPhys hash table.
1195	*
1196	* @param pPool The pool.
1197	* @param pPage The page.
1198	*/
1199	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1200	{
1201	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1202	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1203	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1204	pPage->iNext = pPool->aiHash[iHash];
1205	pPool->aiHash[iHash] = pPage->idx;
1206	}
1207
1208
1209	/**
1210	* Removes a page from the GCPhys hash table.
1211	*
1212	* @param pPool The pool.
1213	* @param pPage The page.
1214	*/
1215	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1216	{
1217	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1218	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1219	if (pPool->aiHash[iHash] == pPage->idx)
1220	pPool->aiHash[iHash] = pPage->iNext;
1221	else
1222	{
1223	uint16_t iPrev = pPool->aiHash[iHash];
1224	for (;;)
1225	{
1226	const int16_t i = pPool->aPages[iPrev].iNext;
1227	if (i == pPage->idx)
1228	{
1229	pPool->aPages[iPrev].iNext = pPage->iNext;
1230	break;
1231	}
1232	if (i == NIL_PGMPOOL_IDX)
1233	{
1234	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1235	break;
1236	}
1237	iPrev = i;
1238	}
1239	}
1240	pPage->iNext = NIL_PGMPOOL_IDX;
1241	}
1242
1243
1244	/**
1245	* Frees up one cache page.
1246	*
1247	* @returns VBox status code.
1248	* @retval VINF_SUCCESS on success.
1249	* @param pPool The pool.
1250	* @param iUser The user index.
1251	*/
1252	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1253	{
1254	#ifndef IN_RC
1255	const PVM pVM = pPool->CTX_SUFF(pVM);
1256	#endif
1257	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1258	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1259
1260	/*
1261	* Select one page from the tail of the age list.
1262	*/
1263	PPGMPOOLPAGE pPage;
1264	for (unsigned iLoop = 0; ; iLoop++)
1265	{
1266	uint16_t iToFree = pPool->iAgeTail;
1267	if (iToFree == iUser)
1268	iToFree = pPool->aPages[iToFree].iAgePrev;
1269	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1270	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1271	{
1272	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1273	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1274	{
1275	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1276	continue;
1277	iToFree = i;
1278	break;
1279	}
1280	}
1281	*/
1282	Assert(iToFree != iUser);
1283	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1284	pPage = &pPool->aPages[iToFree];
1285
1286	/*
1287	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1288	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1289	*/
1290	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1291	break;
1292	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1293	pgmPoolCacheUsed(pPool, pPage);
1294	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1295	}
1296
1297	/*
1298	* Found a usable page, flush it and return.
1299	*/
1300	int rc = pgmPoolFlushPage(pPool, pPage);
1301	if (rc == VINF_SUCCESS)
1302	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1303	return rc;
1304	}
1305
1306
1307	/**
1308	* Checks if a kind mismatch is really a page being reused
1309	* or if it's just normal remappings.
1310	*
1311	* @returns true if reused and the cached page (enmKind1) should be flushed
1312	* @returns false if not reused.
1313	* @param enmKind1 The kind of the cached page.
1314	* @param enmKind2 The kind of the requested page.
1315	*/
1316	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1317	{
1318	switch (enmKind1)
1319	{
1320	/*
1321	* Never reuse them. There is no remapping in non-paging mode.
1322	*/
1323	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1324	case PGMPOOLKIND_32BIT_PD_PHYS:
1325	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1326	case PGMPOOLKIND_PAE_PD_PHYS:
1327	case PGMPOOLKIND_PAE_PDPT_PHYS:
1328	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1329	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1330	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1331	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1332	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1333	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1334	return false;
1335
1336	/*
1337	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1338	*/
1339	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1340	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1341	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1342	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1343	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1344	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1345	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1346	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1347	case PGMPOOLKIND_32BIT_PD:
1348	case PGMPOOLKIND_PAE_PDPT:
1349	switch (enmKind2)
1350	{
1351	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1352	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1353	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1354	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1355	case PGMPOOLKIND_64BIT_PML4:
1356	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1357	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1358	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1359	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1360	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1361	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1362	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1363	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1364	return true;
1365	default:
1366	return false;
1367	}
1368
1369	/*
1370	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1371	*/
1372	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1373	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1374	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1375	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1376	case PGMPOOLKIND_64BIT_PML4:
1377	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1378	switch (enmKind2)
1379	{
1380	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1381	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1382	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1383	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1384	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1385	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1386	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1387	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1388	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1389	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1390	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1391	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1392	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1393	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1394	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1395	return true;
1396	default:
1397	return false;
1398	}
1399
1400	/*
1401	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1402	*/
1403	case PGMPOOLKIND_ROOT_NESTED:
1404	return false;
1405
1406	default:
1407	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1408	}
1409	}
1410
1411
1412	/**
1413	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1414	*
1415	* @returns VBox status code.
1416	* @retval VINF_PGM_CACHED_PAGE on success.
1417	* @retval VERR_FILE_NOT_FOUND if not found.
1418	* @param pPool The pool.
1419	* @param GCPhys The GC physical address of the page we're gonna shadow.
1420	* @param enmKind The kind of mapping.
1421	* @param iUser The shadow page pool index of the user table.
1422	* @param iUserTable The index into the user table (shadowed).
1423	* @param ppPage Where to store the pointer to the page.
1424	*/
1425	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1426	{
1427	#ifndef IN_RC
1428	const PVM pVM = pPool->CTX_SUFF(pVM);
1429	#endif
1430	/*
1431	* Look up the GCPhys in the hash.
1432	*/
1433	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1434	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1435	if (i != NIL_PGMPOOL_IDX)
1436	{
1437	do
1438	{
1439	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1440	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1441	if (pPage->GCPhys == GCPhys)
1442	{
1443	if ((PGMPOOLKIND)pPage->enmKind == enmKind)
1444	{
1445	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1446	* doesn't flush it in case there are no more free use records.
1447	*/
1448	pgmPoolCacheUsed(pPool, pPage);
1449
1450	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1451	if (RT_SUCCESS(rc))
1452	{
1453	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1454	*ppPage = pPage;
1455	STAM_COUNTER_INC(&pPool->StatCacheHits);
1456	return VINF_PGM_CACHED_PAGE;
1457	}
1458	return rc;
1459	}
1460
1461	/*
1462	* The kind is different. In some cases we should now flush the page
1463	* as it has been reused, but in most cases this is normal remapping
1464	* of PDs as PT or big pages using the GCPhys field in a slightly
1465	* different way than the other kinds.
1466	*/
1467	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1468	{
1469	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1470	pgmPoolFlushPage(pPool, pPage);
1471	PGM_INVL_GUEST_TLBS(); /* see PT handler. */
1472	break;
1473	}
1474	}
1475
1476	/* next */
1477	i = pPage->iNext;
1478	} while (i != NIL_PGMPOOL_IDX);
1479	}
1480
1481	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1482	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1483	return VERR_FILE_NOT_FOUND;
1484	}
1485
1486
1487	/**
1488	* Inserts a page into the cache.
1489	*
1490	* @param pPool The pool.
1491	* @param pPage The cached page.
1492	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1493	*/
1494	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1495	{
1496	/*
1497	* Insert into the GCPhys hash if the page is fit for that.
1498	*/
1499	Assert(!pPage->fCached);
1500	if (fCanBeCached)
1501	{
1502	pPage->fCached = true;
1503	pgmPoolHashInsert(pPool, pPage);
1504	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1505	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1506	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1507	}
1508	else
1509	{
1510	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1511	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1512	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1513	}
1514
1515	/*
1516	* Insert at the head of the age list.
1517	*/
1518	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1519	pPage->iAgeNext = pPool->iAgeHead;
1520	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1521	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1522	else
1523	pPool->iAgeTail = pPage->idx;
1524	pPool->iAgeHead = pPage->idx;
1525	}
1526
1527
1528	/**
1529	* Flushes a cached page.
1530	*
1531	* @param pPool The pool.
1532	* @param pPage The cached page.
1533	*/
1534	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1535	{
1536	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1537
1538	/*
1539	* Remove the page from the hash.
1540	*/
1541	if (pPage->fCached)
1542	{
1543	pPage->fCached = false;
1544	pgmPoolHashRemove(pPool, pPage);
1545	}
1546	else
1547	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1548
1549	/*
1550	* Remove it from the age list.
1551	*/
1552	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1553	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1554	else
1555	pPool->iAgeTail = pPage->iAgePrev;
1556	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1557	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1558	else
1559	pPool->iAgeHead = pPage->iAgeNext;
1560	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1561	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1562	}
1563
1564	#endif /* PGMPOOL_WITH_CACHE */
1565	#ifdef PGMPOOL_WITH_MONITORING
1566
1567	/**
1568	* Looks for pages sharing the monitor.
1569	*
1570	* @returns Pointer to the head page.
1571	* @returns NULL if not found.
1572	* @param pPool The Pool
1573	* @param pNewPage The page which is going to be monitored.
1574	*/
1575	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1576	{
1577	#ifdef PGMPOOL_WITH_CACHE
1578	/*
1579	* Look up the GCPhys in the hash.
1580	*/
1581	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1582	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1583	if (i == NIL_PGMPOOL_IDX)
1584	return NULL;
1585	do
1586	{
1587	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1588	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1589	&& pPage != pNewPage)
1590	{
1591	switch (pPage->enmKind)
1592	{
1593	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1594	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1595	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1596	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1597	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1598	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1599	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1600	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1601	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1602	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1603	case PGMPOOLKIND_64BIT_PML4:
1604	case PGMPOOLKIND_32BIT_PD:
1605	case PGMPOOLKIND_PAE_PDPT:
1606	{
1607	/* find the head */
1608	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1609	{
1610	Assert(pPage->iMonitoredPrev != pPage->idx);
1611	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1612	}
1613	return pPage;
1614	}
1615
1616	/* ignore, no monitoring. */
1617	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1618	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1619	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1620	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1621	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1622	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1623	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1624	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1625	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1626	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1627	case PGMPOOLKIND_ROOT_NESTED:
1628	case PGMPOOLKIND_PAE_PD_PHYS:
1629	case PGMPOOLKIND_PAE_PDPT_PHYS:
1630	case PGMPOOLKIND_32BIT_PD_PHYS:
1631	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1632	break;
1633	default:
1634	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1635	}
1636	}
1637
1638	/* next */
1639	i = pPage->iNext;
1640	} while (i != NIL_PGMPOOL_IDX);
1641	#endif
1642	return NULL;
1643	}
1644
1645
1646	/**
1647	* Enabled write monitoring of a guest page.
1648	*
1649	* @returns VBox status code.
1650	* @retval VINF_SUCCESS on success.
1651	* @param pPool The pool.
1652	* @param pPage The cached page.
1653	*/
1654	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1655	{
1656	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1657
1658	/*
1659	* Filter out the relevant kinds.
1660	*/
1661	switch (pPage->enmKind)
1662	{
1663	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1664	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1665	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1666	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1667	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1668	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1669	case PGMPOOLKIND_64BIT_PML4:
1670	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1671	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1672	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1673	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1674	case PGMPOOLKIND_32BIT_PD:
1675	case PGMPOOLKIND_PAE_PDPT:
1676	break;
1677
1678	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1679	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1680	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1681	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1682	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1683	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1684	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1685	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1686	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1687	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1688	case PGMPOOLKIND_ROOT_NESTED:
1689	/* Nothing to monitor here. */
1690	return VINF_SUCCESS;
1691
1692	case PGMPOOLKIND_32BIT_PD_PHYS:
1693	case PGMPOOLKIND_PAE_PDPT_PHYS:
1694	case PGMPOOLKIND_PAE_PD_PHYS:
1695	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1696	/* Nothing to monitor here. */
1697	return VINF_SUCCESS;
1698	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1699	break;
1700	#else
1701	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1702	#endif
1703	default:
1704	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1705	}
1706
1707	/*
1708	* Install handler.
1709	*/
1710	int rc;
1711	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1712	if (pPageHead)
1713	{
1714	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1715	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1716	pPage->iMonitoredPrev = pPageHead->idx;
1717	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1718	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1719	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1720	pPageHead->iMonitoredNext = pPage->idx;
1721	rc = VINF_SUCCESS;
1722	}
1723	else
1724	{
1725	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1726	PVM pVM = pPool->CTX_SUFF(pVM);
1727	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1728	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1729	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1730	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1731	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1732	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1733	pPool->pszAccessHandler);
1734	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1735	* the heap size should suffice. */
1736	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1737	Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1738	}
1739	pPage->fMonitored = true;
1740	return rc;
1741	}
1742
1743
1744	/**
1745	* Disables write monitoring of a guest page.
1746	*
1747	* @returns VBox status code.
1748	* @retval VINF_SUCCESS on success.
1749	* @param pPool The pool.
1750	* @param pPage The cached page.
1751	*/
1752	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1753	{
1754	/*
1755	* Filter out the relevant kinds.
1756	*/
1757	switch (pPage->enmKind)
1758	{
1759	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1760	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1761	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1762	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1763	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1764	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1765	case PGMPOOLKIND_64BIT_PML4:
1766	case PGMPOOLKIND_32BIT_PD:
1767	case PGMPOOLKIND_PAE_PDPT:
1768	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1769	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1770	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1771	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1772	break;
1773
1774	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1775	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1776	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1777	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1778	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1779	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1780	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1781	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1782	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1783	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1784	case PGMPOOLKIND_ROOT_NESTED:
1785	case PGMPOOLKIND_PAE_PD_PHYS:
1786	case PGMPOOLKIND_PAE_PDPT_PHYS:
1787	case PGMPOOLKIND_32BIT_PD_PHYS:
1788	/* Nothing to monitor here. */
1789	return VINF_SUCCESS;
1790
1791	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1792	break;
1793	#endif
1794	default:
1795	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1796	}
1797
1798	/*
1799	* Remove the page from the monitored list or uninstall it if last.
1800	*/
1801	const PVM pVM = pPool->CTX_SUFF(pVM);
1802	int rc;
1803	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1804	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1805	{
1806	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1807	{
1808	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1809	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1810	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1811	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1812	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1813	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1814	pPool->pszAccessHandler);
1815	AssertFatalRCSuccess(rc);
1816	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1817	}
1818	else
1819	{
1820	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1821	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1822	{
1823	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1824	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1825	}
1826	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1827	rc = VINF_SUCCESS;
1828	}
1829	}
1830	else
1831	{
1832	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1833	AssertFatalRC(rc);
1834	AssertMsg(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3),
1835	("%#x %#x\n", pVM->pgm.s.fGlobalSyncFlags, pVM->fGlobalForcedActions));
1836	}
1837	pPage->fMonitored = false;
1838
1839	/*
1840	* Remove it from the list of modified pages (if in it).
1841	*/
1842	pgmPoolMonitorModifiedRemove(pPool, pPage);
1843
1844	return rc;
1845	}
1846
1847
1848	/**
1849	* Inserts the page into the list of modified pages.
1850	*
1851	* @param pPool The pool.
1852	* @param pPage The page.
1853	*/
1854	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1855	{
1856	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1857	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1858	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1859	&& pPool->iModifiedHead != pPage->idx,
1860	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1861	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1862	pPool->iModifiedHead, pPool->cModifiedPages));
1863
1864	pPage->iModifiedNext = pPool->iModifiedHead;
1865	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1866	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1867	pPool->iModifiedHead = pPage->idx;
1868	pPool->cModifiedPages++;
1869	#ifdef VBOX_WITH_STATISTICS
1870	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1871	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1872	#endif
1873	}
1874
1875
1876	/**
1877	* Removes the page from the list of modified pages and resets the
1878	* moficiation counter.
1879	*
1880	* @param pPool The pool.
1881	* @param pPage The page which is believed to be in the list of modified pages.
1882	*/
1883	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1884	{
1885	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1886	if (pPool->iModifiedHead == pPage->idx)
1887	{
1888	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1889	pPool->iModifiedHead = pPage->iModifiedNext;
1890	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1891	{
1892	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1893	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1894	}
1895	pPool->cModifiedPages--;
1896	}
1897	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1898	{
1899	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1900	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1901	{
1902	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1903	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1904	}
1905	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1906	pPool->cModifiedPages--;
1907	}
1908	else
1909	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1910	pPage->cModifications = 0;
1911	}
1912
1913
1914	/**
1915	* Zaps the list of modified pages, resetting their modification counters in the process.
1916	*
1917	* @param pVM The VM handle.
1918	*/
1919	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1920	{
1921	pgmLock(pVM);
1922	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1923	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1924
1925	unsigned cPages = 0; NOREF(cPages);
1926	uint16_t idx = pPool->iModifiedHead;
1927	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1928	while (idx != NIL_PGMPOOL_IDX)
1929	{
1930	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1931	idx = pPage->iModifiedNext;
1932	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1933	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1934	pPage->cModifications = 0;
1935	Assert(++cPages);
1936	}
1937	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1938	pPool->cModifiedPages = 0;
1939	pgmUnlock(pVM);
1940	}
1941
1942
1943	#ifdef IN_RING3
1944	/**
1945	* Callback to clear all shadow pages and clear all modification counters.
1946	*
1947	* @returns VBox status code.
1948	* @param pVM The VM handle.
1949	* @param pvUser Unused parameter
1950	* @remark Should only be used when monitoring is available, thus placed in
1951	* the PGMPOOL_WITH_MONITORING #ifdef.
1952	*/
1953	DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, void *pvUser)
1954	{
1955	NOREF(pvUser);
1956	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1957	STAM_PROFILE_START(&pPool->StatClearAll, c);
1958	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1959
1960	pgmLock(pVM);
1961
1962	/*
1963	* Iterate all the pages until we've encountered all that in use.
1964	* This is simple but not quite optimal solution.
1965	*/
1966	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1967	unsigned cLeft = pPool->cUsedPages;
1968	unsigned iPage = pPool->cCurPages;
1969	while (--iPage >= PGMPOOL_IDX_FIRST)
1970	{
1971	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1972	if (pPage->GCPhys != NIL_RTGCPHYS)
1973	{
1974	switch (pPage->enmKind)
1975	{
1976	/*
1977	* We only care about shadow page tables.
1978	*/
1979	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1980	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1981	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1982	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1983	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1984	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1985	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1986	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1987	{
1988	#ifdef PGMPOOL_WITH_USER_TRACKING
1989	if (pPage->cPresent)
1990	#endif
1991	{
1992	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1993	STAM_PROFILE_START(&pPool->StatZeroPage, z);
1994	ASMMemZeroPage(pvShw);
1995	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
1996	#ifdef PGMPOOL_WITH_USER_TRACKING
1997	pPage->cPresent = 0;
1998	pPage->iFirstPresent = ~0;
1999	#endif
2000	}
2001	}
2002	/* fall thru */
2003
2004	default:
2005	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2006	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2007	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2008	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2009	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2010	pPage->cModifications = 0;
2011	break;
2012
2013	}
2014	if (!--cLeft)
2015	break;
2016	}
2017	}
2018
2019	/* swipe the special pages too. */
2020	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2021	{
2022	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2023	if (pPage->GCPhys != NIL_RTGCPHYS)
2024	{
2025	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2026	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2027	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2028	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2029	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2030	pPage->cModifications = 0;
2031	}
2032	}
2033
2034	#ifndef DEBUG_michael
2035	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2036	#endif
2037	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2038	pPool->cModifiedPages = 0;
2039
2040	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2041	/*
2042	* Clear all the GCPhys links and rebuild the phys ext free list.
2043	*/
2044	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2045	pRam;
2046	pRam = pRam->CTX_SUFF(pNext))
2047	{
2048	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2049	while (iPage-- > 0)
2050	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2051	}
2052
2053	pPool->iPhysExtFreeHead = 0;
2054	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2055	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2056	for (unsigned i = 0; i < cMaxPhysExts; i++)
2057	{
2058	paPhysExts[i].iNext = i + 1;
2059	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2060	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2061	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2062	}
2063	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2064	#endif
2065
2066	pPool->cPresent = 0;
2067	pgmUnlock(pVM);
2068	PGM_INVL_GUEST_TLBS();
2069	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2070	return VINF_SUCCESS;
2071	}
2072	#endif /* IN_RING3 */
2073
2074
2075	/**
2076	* Handle SyncCR3 pool tasks
2077	*
2078	* @returns VBox status code.
2079	* @retval VINF_SUCCESS if successfully added.
2080	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2081	* @param pVM The VM handle.
2082	* @remark Should only be used when monitoring is available, thus placed in
2083	* the PGMPOOL_WITH_MONITORING #ifdef.
2084	*/
2085	int pgmPoolSyncCR3(PVM pVM)
2086	{
2087	LogFlow(("pgmPoolSyncCR3\n"));
2088	/*
2089	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2090	* Occasionally we will have to clear all the shadow page tables because we wanted
2091	* to monitor a page which was mapped by too many shadowed page tables. This operation
2092	* sometimes refered to as a 'lightweight flush'.
2093	*/
2094	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2095	if (ASMBitTestAndClear(&pVM->pgm.s.fGlobalSyncFlags, PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT))
2096	{
2097	VMMR3AtomicExecuteHandler(pVM, pgmPoolClearAll, NULL);
2098	# else /* !IN_RING3 */
2099	if (pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)
2100	{
2101	LogFlow(("SyncCR3: PGM_GLOBAL_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2102	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2103	return VINF_PGM_SYNC_CR3;
2104	# endif /* !IN_RING3 */
2105	}
2106	else
2107	pgmPoolMonitorModifiedClearAll(pVM);
2108
2109	return VINF_SUCCESS;
2110	}
2111
2112	#endif /* PGMPOOL_WITH_MONITORING */
2113	#ifdef PGMPOOL_WITH_USER_TRACKING
2114
2115	/**
2116	* Frees up at least one user entry.
2117	*
2118	* @returns VBox status code.
2119	* @retval VINF_SUCCESS if successfully added.
2120	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2121	* @param pPool The pool.
2122	* @param iUser The user index.
2123	*/
2124	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2125	{
2126	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2127	#ifdef PGMPOOL_WITH_CACHE
2128	/*
2129	* Just free cached pages in a braindead fashion.
2130	*/
2131	/** @todo walk the age list backwards and free the first with usage. */
2132	int rc = VINF_SUCCESS;
2133	do
2134	{
2135	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2136	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2137	rc = rc2;
2138	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2139	return rc;
2140	#else
2141	/*
2142	* Lazy approach.
2143	*/
2144	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2145	AssertCompileFailed();
2146	Assert(!CPUMIsGuestInLongMode(pVM));
2147	pgmPoolFlushAllInt(pPool);
2148	return VERR_PGM_POOL_FLUSHED;
2149	#endif
2150	}
2151
2152
2153	/**
2154	* Inserts a page into the cache.
2155	*
2156	* This will create user node for the page, insert it into the GCPhys
2157	* hash, and insert it into the age list.
2158	*
2159	* @returns VBox status code.
2160	* @retval VINF_SUCCESS if successfully added.
2161	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2162	* @param pPool The pool.
2163	* @param pPage The cached page.
2164	* @param GCPhys The GC physical address of the page we're gonna shadow.
2165	* @param iUser The user index.
2166	* @param iUserTable The user table index.
2167	*/
2168	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2169	{
2170	int rc = VINF_SUCCESS;
2171	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2172
2173	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2174
2175	#ifdef VBOX_STRICT
2176	/*
2177	* Check that the entry doesn't already exists.
2178	*/
2179	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2180	{
2181	uint16_t i = pPage->iUserHead;
2182	do
2183	{
2184	Assert(i < pPool->cMaxUsers);
2185	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2186	i = paUsers[i].iNext;
2187	} while (i != NIL_PGMPOOL_USER_INDEX);
2188	}
2189	#endif
2190
2191	/*
2192	* Find free a user node.
2193	*/
2194	uint16_t i = pPool->iUserFreeHead;
2195	if (i == NIL_PGMPOOL_USER_INDEX)
2196	{
2197	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2198	if (RT_FAILURE(rc))
2199	return rc;
2200	i = pPool->iUserFreeHead;
2201	}
2202
2203	/*
2204	* Unlink the user node from the free list,
2205	* initialize and insert it into the user list.
2206	*/
2207	pPool->iUserFreeHead = paUsers[i].iNext;
2208	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2209	paUsers[i].iUser = iUser;
2210	paUsers[i].iUserTable = iUserTable;
2211	pPage->iUserHead = i;
2212
2213	/*
2214	* Insert into cache and enable monitoring of the guest page if enabled.
2215	*
2216	* Until we implement caching of all levels, including the CR3 one, we'll
2217	* have to make sure we don't try monitor & cache any recursive reuse of
2218	* a monitored CR3 page. Because all windows versions are doing this we'll
2219	* have to be able to do combined access monitoring, CR3 + PT and
2220	* PD + PT (guest PAE).
2221	*
2222	* Update:
2223	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2224	*/
2225	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2226	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2227	const bool fCanBeMonitored = true;
2228	# else
2229	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2230	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2231	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2232	# endif
2233	# ifdef PGMPOOL_WITH_CACHE
2234	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2235	# endif
2236	if (fCanBeMonitored)
2237	{
2238	# ifdef PGMPOOL_WITH_MONITORING
2239	rc = pgmPoolMonitorInsert(pPool, pPage);
2240	AssertRC(rc);
2241	}
2242	# endif
2243	#endif /* PGMPOOL_WITH_MONITORING */
2244	return rc;
2245	}
2246
2247
2248	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2249	/**
2250	* Adds a user reference to a page.
2251	*
2252	* This will move the page to the head of the
2253	*
2254	* @returns VBox status code.
2255	* @retval VINF_SUCCESS if successfully added.
2256	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2257	* @param pPool The pool.
2258	* @param pPage The cached page.
2259	* @param iUser The user index.
2260	* @param iUserTable The user table.
2261	*/
2262	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2263	{
2264	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2265
2266	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2267
2268	# ifdef VBOX_STRICT
2269	/*
2270	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2271	*/
2272	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2273	{
2274	uint16_t i = pPage->iUserHead;
2275	do
2276	{
2277	Assert(i < pPool->cMaxUsers);
2278	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2279	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2280	i = paUsers[i].iNext;
2281	} while (i != NIL_PGMPOOL_USER_INDEX);
2282	}
2283	# endif
2284
2285	/*
2286	* Allocate a user node.
2287	*/
2288	uint16_t i = pPool->iUserFreeHead;
2289	if (i == NIL_PGMPOOL_USER_INDEX)
2290	{
2291	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2292	if (RT_FAILURE(rc))
2293	return rc;
2294	i = pPool->iUserFreeHead;
2295	}
2296	pPool->iUserFreeHead = paUsers[i].iNext;
2297
2298	/*
2299	* Initialize the user node and insert it.
2300	*/
2301	paUsers[i].iNext = pPage->iUserHead;
2302	paUsers[i].iUser = iUser;
2303	paUsers[i].iUserTable = iUserTable;
2304	pPage->iUserHead = i;
2305
2306	# ifdef PGMPOOL_WITH_CACHE
2307	/*
2308	* Tell the cache to update its replacement stats for this page.
2309	*/
2310	pgmPoolCacheUsed(pPool, pPage);
2311	# endif
2312	return VINF_SUCCESS;
2313	}
2314	# endif /* PGMPOOL_WITH_CACHE */
2315
2316
2317	/**
2318	* Frees a user record associated with a page.
2319	*
2320	* This does not clear the entry in the user table, it simply replaces the
2321	* user record to the chain of free records.
2322	*
2323	* @param pPool The pool.
2324	* @param HCPhys The HC physical address of the shadow page.
2325	* @param iUser The shadow page pool index of the user table.
2326	* @param iUserTable The index into the user table (shadowed).
2327	*/
2328	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2329	{
2330	/*
2331	* Unlink and free the specified user entry.
2332	*/
2333	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2334
2335	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2336	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2337	uint16_t i = pPage->iUserHead;
2338	if ( i != NIL_PGMPOOL_USER_INDEX
2339	&& paUsers[i].iUser == iUser
2340	&& paUsers[i].iUserTable == iUserTable)
2341	{
2342	pPage->iUserHead = paUsers[i].iNext;
2343
2344	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2345	paUsers[i].iNext = pPool->iUserFreeHead;
2346	pPool->iUserFreeHead = i;
2347	return;
2348	}
2349
2350	/* General: Linear search. */
2351	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2352	while (i != NIL_PGMPOOL_USER_INDEX)
2353	{
2354	if ( paUsers[i].iUser == iUser
2355	&& paUsers[i].iUserTable == iUserTable)
2356	{
2357	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2358	paUsers[iPrev].iNext = paUsers[i].iNext;
2359	else
2360	pPage->iUserHead = paUsers[i].iNext;
2361
2362	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2363	paUsers[i].iNext = pPool->iUserFreeHead;
2364	pPool->iUserFreeHead = i;
2365	return;
2366	}
2367	iPrev = i;
2368	i = paUsers[i].iNext;
2369	}
2370
2371	/* Fatal: didn't find it */
2372	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2373	iUser, iUserTable, pPage->GCPhys));
2374	}
2375
2376
2377	/**
2378	* Gets the entry size of a shadow table.
2379	*
2380	* @param enmKind The kind of page.
2381	*
2382	* @returns The size of the entry in bytes. That is, 4 or 8.
2383	* @returns If the kind is not for a table, an assertion is raised and 0 is
2384	* returned.
2385	*/
2386	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2387	{
2388	switch (enmKind)
2389	{
2390	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2391	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2392	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2393	case PGMPOOLKIND_32BIT_PD:
2394	case PGMPOOLKIND_32BIT_PD_PHYS:
2395	return 4;
2396
2397	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2398	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2399	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2400	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2401	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2402	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2403	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2404	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2405	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2406	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2407	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2408	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2409	case PGMPOOLKIND_64BIT_PML4:
2410	case PGMPOOLKIND_PAE_PDPT:
2411	case PGMPOOLKIND_ROOT_NESTED:
2412	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2413	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2414	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2415	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2416	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2417	case PGMPOOLKIND_PAE_PD_PHYS:
2418	case PGMPOOLKIND_PAE_PDPT_PHYS:
2419	return 8;
2420
2421	default:
2422	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2423	}
2424	}
2425
2426
2427	/**
2428	* Gets the entry size of a guest table.
2429	*
2430	* @param enmKind The kind of page.
2431	*
2432	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2433	* @returns If the kind is not for a table, an assertion is raised and 0 is
2434	* returned.
2435	*/
2436	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2437	{
2438	switch (enmKind)
2439	{
2440	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2441	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2442	case PGMPOOLKIND_32BIT_PD:
2443	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2444	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2445	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2446	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2447	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2448	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2449	return 4;
2450
2451	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2452	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2453	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2454	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2455	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2456	case PGMPOOLKIND_64BIT_PML4:
2457	case PGMPOOLKIND_PAE_PDPT:
2458	return 8;
2459
2460	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2461	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2462	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2463	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2464	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2465	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2466	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2467	case PGMPOOLKIND_ROOT_NESTED:
2468	case PGMPOOLKIND_PAE_PD_PHYS:
2469	case PGMPOOLKIND_PAE_PDPT_PHYS:
2470	case PGMPOOLKIND_32BIT_PD_PHYS:
2471	/** @todo can we return 0? (nobody is calling this...) */
2472	AssertFailed();
2473	return 0;
2474
2475	default:
2476	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2477	}
2478	}
2479
2480	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2481
2482	/**
2483	* Scans one shadow page table for mappings of a physical page.
2484	*
2485	* @param pVM The VM handle.
2486	* @param pPhysPage The guest page in question.
2487	* @param iShw The shadow page table.
2488	* @param cRefs The number of references made in that PT.
2489	*/
2490	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2491	{
2492	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2493	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2494
2495	/*
2496	* Assert sanity.
2497	*/
2498	Assert(cRefs == 1);
2499	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2500	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2501
2502	/*
2503	* Then, clear the actual mappings to the page in the shadow PT.
2504	*/
2505	switch (pPage->enmKind)
2506	{
2507	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2508	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2509	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2510	{
2511	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2512	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2513	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2514	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2515	{
2516	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2517	pPT->a[i].u = 0;
2518	cRefs--;
2519	if (!cRefs)
2520	return;
2521	}
2522	#ifdef LOG_ENABLED
2523	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2524	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2525	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2526	{
2527	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2528	pPT->a[i].u = 0;
2529	}
2530	#endif
2531	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2532	break;
2533	}
2534
2535	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2536	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2537	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2538	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2539	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2540	{
2541	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2542	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2543	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2544	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2545	{
2546	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2547	pPT->a[i].u = 0;
2548	cRefs--;
2549	if (!cRefs)
2550	return;
2551	}
2552	#ifdef LOG_ENABLED
2553	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2554	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2555	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2556	{
2557	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2558	pPT->a[i].u = 0;
2559	}
2560	#endif
2561	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2562	break;
2563	}
2564
2565	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2566	{
2567	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2568	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2569	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2570	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2571	{
2572	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2573	pPT->a[i].u = 0;
2574	cRefs--;
2575	if (!cRefs)
2576	return;
2577	}
2578	#ifdef LOG_ENABLED
2579	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2580	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2581	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2582	{
2583	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2584	pPT->a[i].u = 0;
2585	}
2586	#endif
2587	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2588	break;
2589	}
2590
2591	default:
2592	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2593	}
2594	}
2595
2596
2597	/**
2598	* Scans one shadow page table for mappings of a physical page.
2599	*
2600	* @param pVM The VM handle.
2601	* @param pPhysPage The guest page in question.
2602	* @param iShw The shadow page table.
2603	* @param cRefs The number of references made in that PT.
2604	*/
2605	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2606	{
2607	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2608	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2609	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2610	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2611	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2612	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2613	}
2614
2615
2616	/**
2617	* Flushes a list of shadow page tables mapping the same physical page.
2618	*
2619	* @param pVM The VM handle.
2620	* @param pPhysPage The guest page in question.
2621	* @param iPhysExt The physical cross reference extent list to flush.
2622	*/
2623	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2624	{
2625	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2626	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2627	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2628
2629	const uint16_t iPhysExtStart = iPhysExt;
2630	PPGMPOOLPHYSEXT pPhysExt;
2631	do
2632	{
2633	Assert(iPhysExt < pPool->cMaxPhysExts);
2634	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2635	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2636	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2637	{
2638	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2639	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2640	}
2641
2642	/* next */
2643	iPhysExt = pPhysExt->iNext;
2644	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2645
2646	/* insert the list into the free list and clear the ram range entry. */
2647	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2648	pPool->iPhysExtFreeHead = iPhysExtStart;
2649	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2650
2651	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2652	}
2653
2654	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2655
2656	/**
2657	* Flushes all shadow page table mappings of the given guest page.
2658	*
2659	* This is typically called when the host page backing the guest one has been
2660	* replaced or when the page protection was changed due to an access handler.
2661	*
2662	* @returns VBox status code.
2663	* @retval VINF_SUCCESS if all references has been successfully cleared.
2664	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2665	* pool cleaning. FF and sync flags are set.
2666	*
2667	* @param pVM The VM handle.
2668	* @param pPhysPage The guest page in question.
2669	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2670	* flushed, it is NOT touched if this isn't necessary.
2671	* The caller MUST initialized this to @a false.
2672	*/
2673	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2674	{
2675	pgmLock(pVM);
2676	int rc = VINF_SUCCESS;
2677	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2678	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2679	if (u16)
2680	{
2681	/*
2682	* The zero page is currently screwing up the tracking and we'll
2683	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2684	* is defined, zero pages won't normally be mapped. Some kind of solution
2685	* will be needed for this problem of course, but it will have to wait...
2686	*/
2687	if (PGM_PAGE_IS_ZERO(pPhysPage))
2688	rc = VINF_PGM_GCPHYS_ALIASED;
2689	else
2690	{
2691	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2692	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2693	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2694	PVMCPU pVCpu = VMMGetCpu(pVM);
2695	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2696	# endif
2697
2698	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2699	pgmPoolTrackFlushGCPhysPT(pVM,
2700	pPhysPage,
2701	PGMPOOL_TD_GET_IDX(u16),
2702	PGMPOOL_TD_GET_CREFS(u16));
2703	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2704	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2705	else
2706	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2707	*pfFlushTLBs = true;
2708
2709	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2710	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2711	# endif
2712	}
2713	}
2714
2715	#elif defined(PGMPOOL_WITH_CACHE)
2716	if (PGM_PAGE_IS_ZERO(pPhysPage))
2717	rc = VINF_PGM_GCPHYS_ALIASED;
2718	else
2719	{
2720	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2721	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2722	PVMCPU pVCpu = VMMGetCpu(pVM);
2723	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2724	# endif
2725	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2726	if (rc == VINF_SUCCESS)
2727	*pfFlushTLBs = true;
2728	}
2729
2730	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2731	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2732	# endif
2733
2734	#else
2735	rc = VINF_PGM_GCPHYS_ALIASED;
2736	#endif
2737
2738	if (rc == VINF_PGM_GCPHYS_ALIASED)
2739	{
2740	pVM->pgm.s.fGlobalSyncFlags \|= PGM_GLOBAL_SYNC_CLEAR_PGM_POOL;
2741	for (unsigned i=0;i<pVM->cCPUs;i++)
2742	{
2743	PVMCPU pVCpu = &pVM->aCpus[i];
2744	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2745	}
2746	rc = VINF_PGM_SYNC_CR3;
2747	}
2748	pgmUnlock(pVM);
2749	return rc;
2750	}
2751
2752
2753	/**
2754	* Scans all shadow page tables for mappings of a physical page.
2755	*
2756	* This may be slow, but it's most likely more efficient than cleaning
2757	* out the entire page pool / cache.
2758	*
2759	* @returns VBox status code.
2760	* @retval VINF_SUCCESS if all references has been successfully cleared.
2761	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2762	* a page pool cleaning.
2763	*
2764	* @param pVM The VM handle.
2765	* @param pPhysPage The guest page in question.
2766	*/
2767	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2768	{
2769	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2770	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2771	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2772	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2773
2774	#if 1
2775	/*
2776	* There is a limit to what makes sense.
2777	*/
2778	if (pPool->cPresent > 1024)
2779	{
2780	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2781	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2782	return VINF_PGM_GCPHYS_ALIASED;
2783	}
2784	#endif
2785
2786	/*
2787	* Iterate all the pages until we've encountered all that in use.
2788	* This is simple but not quite optimal solution.
2789	*/
2790	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2791	const uint32_t u32 = u64;
2792	unsigned cLeft = pPool->cUsedPages;
2793	unsigned iPage = pPool->cCurPages;
2794	while (--iPage >= PGMPOOL_IDX_FIRST)
2795	{
2796	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2797	if (pPage->GCPhys != NIL_RTGCPHYS)
2798	{
2799	switch (pPage->enmKind)
2800	{
2801	/*
2802	* We only care about shadow page tables.
2803	*/
2804	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2805	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2806	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2807	{
2808	unsigned cPresent = pPage->cPresent;
2809	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2810	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2811	if (pPT->a[i].n.u1Present)
2812	{
2813	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2814	{
2815	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2816	pPT->a[i].u = 0;
2817	}
2818	if (!--cPresent)
2819	break;
2820	}
2821	break;
2822	}
2823
2824	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2825	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2826	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2827	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2828	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2829	{
2830	unsigned cPresent = pPage->cPresent;
2831	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2832	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2833	if (pPT->a[i].n.u1Present)
2834	{
2835	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2836	{
2837	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2838	pPT->a[i].u = 0;
2839	}
2840	if (!--cPresent)
2841	break;
2842	}
2843	break;
2844	}
2845	}
2846	if (!--cLeft)
2847	break;
2848	}
2849	}
2850
2851	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2852	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2853	return VINF_SUCCESS;
2854	}
2855
2856
2857	/**
2858	* Clears the user entry in a user table.
2859	*
2860	* This is used to remove all references to a page when flushing it.
2861	*/
2862	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2863	{
2864	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2865	Assert(pUser->iUser < pPool->cCurPages);
2866	uint32_t iUserTable = pUser->iUserTable;
2867
2868	/*
2869	* Map the user page.
2870	*/
2871	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2872	union
2873	{
2874	uint64_t *pau64;
2875	uint32_t *pau32;
2876	} u;
2877	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2878
2879	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2880
2881	/* Safety precaution in case we change the paging for other modes too in the future. */
2882	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2883
2884	#ifdef VBOX_STRICT
2885	/*
2886	* Some sanity checks.
2887	*/
2888	switch (pUserPage->enmKind)
2889	{
2890	case PGMPOOLKIND_32BIT_PD:
2891	case PGMPOOLKIND_32BIT_PD_PHYS:
2892	Assert(iUserTable < X86_PG_ENTRIES);
2893	break;
2894	case PGMPOOLKIND_PAE_PDPT:
2895	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2896	case PGMPOOLKIND_PAE_PDPT_PHYS:
2897	Assert(iUserTable < 4);
2898	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2899	break;
2900	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2901	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2902	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2903	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2904	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2905	case PGMPOOLKIND_PAE_PD_PHYS:
2906	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2907	break;
2908	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2909	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2910	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2911	break;
2912	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2913	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2914	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2915	break;
2916	case PGMPOOLKIND_64BIT_PML4:
2917	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2918	/* GCPhys >> PAGE_SHIFT is the index here */
2919	break;
2920	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2921	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2922	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2923	break;
2924
2925	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2926	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2927	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2928	break;
2929
2930	case PGMPOOLKIND_ROOT_NESTED:
2931	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2932	break;
2933
2934	default:
2935	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2936	break;
2937	}
2938	#endif /* VBOX_STRICT */
2939
2940	/*
2941	* Clear the entry in the user page.
2942	*/
2943	switch (pUserPage->enmKind)
2944	{
2945	/* 32-bit entries */
2946	case PGMPOOLKIND_32BIT_PD:
2947	case PGMPOOLKIND_32BIT_PD_PHYS:
2948	u.pau32[iUserTable] = 0;
2949	break;
2950
2951	/* 64-bit entries */
2952	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2953	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2954	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2955	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2956	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2957	#if defined(IN_RC)
2958	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
2959	* non-present PDPT will continue to cause page faults.
2960	*/
2961	ASMReloadCR3();
2962	#endif
2963	/* no break */
2964	case PGMPOOLKIND_PAE_PD_PHYS:
2965	case PGMPOOLKIND_PAE_PDPT_PHYS:
2966	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2967	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2968	case PGMPOOLKIND_64BIT_PML4:
2969	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2970	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2971	case PGMPOOLKIND_PAE_PDPT:
2972	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2973	case PGMPOOLKIND_ROOT_NESTED:
2974	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2975	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2976	u.pau64[iUserTable] = 0;
2977	break;
2978
2979	default:
2980	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2981	}
2982	}
2983
2984
2985	/**
2986	* Clears all users of a page.
2987	*/
2988	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2989	{
2990	/*
2991	* Free all the user records.
2992	*/
2993	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
2994
2995	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2996	uint16_t i = pPage->iUserHead;
2997	while (i != NIL_PGMPOOL_USER_INDEX)
2998	{
2999	/* Clear enter in user table. */
3000	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3001
3002	/* Free it. */
3003	const uint16_t iNext = paUsers[i].iNext;
3004	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3005	paUsers[i].iNext = pPool->iUserFreeHead;
3006	pPool->iUserFreeHead = i;
3007
3008	/* Next. */
3009	i = iNext;
3010	}
3011	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3012	}
3013
3014	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3015
3016	/**
3017	* Allocates a new physical cross reference extent.
3018	*
3019	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3020	* @param pVM The VM handle.
3021	* @param piPhysExt Where to store the phys ext index.
3022	*/
3023	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3024	{
3025	Assert(PGMIsLockOwner(pVM));
3026	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3027	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3028	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3029	{
3030	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3031	return NULL;
3032	}
3033	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3034	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3035	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3036	*piPhysExt = iPhysExt;
3037	return pPhysExt;
3038	}
3039
3040
3041	/**
3042	* Frees a physical cross reference extent.
3043	*
3044	* @param pVM The VM handle.
3045	* @param iPhysExt The extent to free.
3046	*/
3047	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3048	{
3049	Assert(PGMIsLockOwner(pVM));
3050	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3051	Assert(iPhysExt < pPool->cMaxPhysExts);
3052	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3053	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3054	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3055	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3056	pPool->iPhysExtFreeHead = iPhysExt;
3057	}
3058
3059
3060	/**
3061	* Frees a physical cross reference extent.
3062	*
3063	* @param pVM The VM handle.
3064	* @param iPhysExt The extent to free.
3065	*/
3066	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3067	{
3068	Assert(PGMIsLockOwner(pVM));
3069	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3070
3071	const uint16_t iPhysExtStart = iPhysExt;
3072	PPGMPOOLPHYSEXT pPhysExt;
3073	do
3074	{
3075	Assert(iPhysExt < pPool->cMaxPhysExts);
3076	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3077	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3078	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3079
3080	/* next */
3081	iPhysExt = pPhysExt->iNext;
3082	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3083
3084	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3085	pPool->iPhysExtFreeHead = iPhysExtStart;
3086	}
3087
3088
3089	/**
3090	* Insert a reference into a list of physical cross reference extents.
3091	*
3092	* @returns The new tracking data for PGMPAGE.
3093	*
3094	* @param pVM The VM handle.
3095	* @param iPhysExt The physical extent index of the list head.
3096	* @param iShwPT The shadow page table index.
3097	*
3098	*/
3099	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3100	{
3101	Assert(PGMIsLockOwner(pVM));
3102	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3103	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3104
3105	/* special common case. */
3106	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3107	{
3108	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3109	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3110	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
3111	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3112	}
3113
3114	/* general treatment. */
3115	const uint16_t iPhysExtStart = iPhysExt;
3116	unsigned cMax = 15;
3117	for (;;)
3118	{
3119	Assert(iPhysExt < pPool->cMaxPhysExts);
3120	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3121	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3122	{
3123	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3124	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3125	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3126	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3127	}
3128	if (!--cMax)
3129	{
3130	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3131	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3132	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
3133	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3134	}
3135	}
3136
3137	/* add another extent to the list. */
3138	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3139	if (!pNew)
3140	{
3141	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3142	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3143	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3144	}
3145	pNew->iNext = iPhysExtStart;
3146	pNew->aidx[0] = iShwPT;
3147	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3148	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3149	}
3150
3151
3152	/**
3153	* Add a reference to guest physical page where extents are in use.
3154	*
3155	* @returns The new tracking data for PGMPAGE.
3156	*
3157	* @param pVM The VM handle.
3158	* @param u16 The ram range flags (top 16-bits).
3159	* @param iShwPT The shadow page table index.
3160	*/
3161	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3162	{
3163	pgmLock(pVM);
3164	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3165	{
3166	/*
3167	* Convert to extent list.
3168	*/
3169	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3170	uint16_t iPhysExt;
3171	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3172	if (pPhysExt)
3173	{
3174	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3175	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3176	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3177	pPhysExt->aidx[1] = iShwPT;
3178	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3179	}
3180	else
3181	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3182	}
3183	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3184	{
3185	/*
3186	* Insert into the extent list.
3187	*/
3188	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3189	}
3190	else
3191	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3192	pgmUnlock(pVM);
3193	return u16;
3194	}
3195
3196
3197	/**
3198	* Clear references to guest physical memory.
3199	*
3200	* @param pPool The pool.
3201	* @param pPage The page.
3202	* @param pPhysPage Pointer to the aPages entry in the ram range.
3203	*/
3204	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3205	{
3206	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3207	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3208
3209	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3210	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3211	{
3212	PVM pVM = pPool->CTX_SUFF(pVM);
3213	pgmLock(pVM);
3214
3215	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3216	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3217	do
3218	{
3219	Assert(iPhysExt < pPool->cMaxPhysExts);
3220
3221	/*
3222	* Look for the shadow page and check if it's all freed.
3223	*/
3224	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3225	{
3226	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3227	{
3228	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3229
3230	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3231	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3232	{
3233	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3234	pgmUnlock(pVM);
3235	return;
3236	}
3237
3238	/* we can free the node. */
3239	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3240	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3241	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3242	{
3243	/* lonely node */
3244	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3245	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3246	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3247	}
3248	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3249	{
3250	/* head */
3251	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3252	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3253	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3254	}
3255	else
3256	{
3257	/* in list */
3258	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3259	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3260	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3261	}
3262	iPhysExt = iPhysExtNext;
3263	pgmUnlock(pVM);
3264	return;
3265	}
3266	}
3267
3268	/* next */
3269	iPhysExtPrev = iPhysExt;
3270	iPhysExt = paPhysExts[iPhysExt].iNext;
3271	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3272
3273	pgmUnlock(pVM);
3274	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3275	}
3276	else /* nothing to do */
3277	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3278	}
3279
3280
3281	/**
3282	* Clear references to guest physical memory.
3283	*
3284	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3285	* is assumed to be correct, so the linear search can be skipped and we can assert
3286	* at an earlier point.
3287	*
3288	* @param pPool The pool.
3289	* @param pPage The page.
3290	* @param HCPhys The host physical address corresponding to the guest page.
3291	* @param GCPhys The guest physical address corresponding to HCPhys.
3292	*/
3293	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3294	{
3295	/*
3296	* Walk range list.
3297	*/
3298	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3299	while (pRam)
3300	{
3301	RTGCPHYS off = GCPhys - pRam->GCPhys;
3302	if (off < pRam->cb)
3303	{
3304	/* does it match? */
3305	const unsigned iPage = off >> PAGE_SHIFT;
3306	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3307	#ifdef LOG_ENABLED
3308	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3309	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3310	#endif
3311	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3312	{
3313	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3314	return;
3315	}
3316	break;
3317	}
3318	pRam = pRam->CTX_SUFF(pNext);
3319	}
3320	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3321	}
3322
3323
3324	/**
3325	* Clear references to guest physical memory.
3326	*
3327	* @param pPool The pool.
3328	* @param pPage The page.
3329	* @param HCPhys The host physical address corresponding to the guest page.
3330	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3331	*/
3332	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3333	{
3334	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3335
3336	/*
3337	* Walk range list.
3338	*/
3339	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3340	while (pRam)
3341	{
3342	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3343	if (off < pRam->cb)
3344	{
3345	/* does it match? */
3346	const unsigned iPage = off >> PAGE_SHIFT;
3347	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3348	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3349	{
3350	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3351	return;
3352	}
3353	break;
3354	}
3355	pRam = pRam->CTX_SUFF(pNext);
3356	}
3357
3358	/*
3359	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3360	*/
3361	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3362	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3363	while (pRam)
3364	{
3365	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3366	while (iPage-- > 0)
3367	{
3368	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3369	{
3370	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3371	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3372	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3373	return;
3374	}
3375	}
3376	pRam = pRam->CTX_SUFF(pNext);
3377	}
3378
3379	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3380	}
3381
3382
3383	/**
3384	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3385	*
3386	* @param pPool The pool.
3387	* @param pPage The page.
3388	* @param pShwPT The shadow page table (mapping of the page).
3389	* @param pGstPT The guest page table.
3390	*/
3391	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3392	{
3393	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3394	if (pShwPT->a[i].n.u1Present)
3395	{
3396	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3397	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3398	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3399	if (!--pPage->cPresent)
3400	break;
3401	}
3402	}
3403
3404
3405	/**
3406	* Clear references to guest physical memory in a PAE / 32-bit page table.
3407	*
3408	* @param pPool The pool.
3409	* @param pPage The page.
3410	* @param pShwPT The shadow page table (mapping of the page).
3411	* @param pGstPT The guest page table (just a half one).
3412	*/
3413	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3414	{
3415	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3416	if (pShwPT->a[i].n.u1Present)
3417	{
3418	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3419	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3420	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3421	}
3422	}
3423
3424
3425	/**
3426	* Clear references to guest physical memory in a PAE / PAE page table.
3427	*
3428	* @param pPool The pool.
3429	* @param pPage The page.
3430	* @param pShwPT The shadow page table (mapping of the page).
3431	* @param pGstPT The guest page table.
3432	*/
3433	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3434	{
3435	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3436	if (pShwPT->a[i].n.u1Present)
3437	{
3438	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3439	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3440	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3441	}
3442	}
3443
3444
3445	/**
3446	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3447	*
3448	* @param pPool The pool.
3449	* @param pPage The page.
3450	* @param pShwPT The shadow page table (mapping of the page).
3451	*/
3452	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3453	{
3454	RTGCPHYS GCPhys = pPage->GCPhys;
3455	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3456	if (pShwPT->a[i].n.u1Present)
3457	{
3458	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3459	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3460	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3461	}
3462	}
3463
3464
3465	/**
3466	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3467	*
3468	* @param pPool The pool.
3469	* @param pPage The page.
3470	* @param pShwPT The shadow page table (mapping of the page).
3471	*/
3472	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3473	{
3474	RTGCPHYS GCPhys = pPage->GCPhys;
3475	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3476	if (pShwPT->a[i].n.u1Present)
3477	{
3478	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3479	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3480	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3481	}
3482	}
3483
3484	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3485
3486
3487	/**
3488	* Clear references to shadowed pages in a 32 bits page directory.
3489	*
3490	* @param pPool The pool.
3491	* @param pPage The page.
3492	* @param pShwPD The shadow page directory (mapping of the page).
3493	*/
3494	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3495	{
3496	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3497	{
3498	if ( pShwPD->a[i].n.u1Present
3499	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3500	)
3501	{
3502	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3503	if (pSubPage)
3504	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3505	else
3506	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3507	}
3508	}
3509	}
3510
3511	/**
3512	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3513	*
3514	* @param pPool The pool.
3515	* @param pPage The page.
3516	* @param pShwPD The shadow page directory (mapping of the page).
3517	*/
3518	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3519	{
3520	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3521	{
3522	if ( pShwPD->a[i].n.u1Present
3523	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3524	)
3525	{
3526	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3527	if (pSubPage)
3528	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3529	else
3530	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3531	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3532	}
3533	}
3534	}
3535
3536	/**
3537	* Clear references to shadowed pages in a PAE page directory pointer table.
3538	*
3539	* @param pPool The pool.
3540	* @param pPage The page.
3541	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3542	*/
3543	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3544	{
3545	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3546	{
3547	if ( pShwPDPT->a[i].n.u1Present
3548	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3549	)
3550	{
3551	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3552	if (pSubPage)
3553	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3554	else
3555	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3556	}
3557	}
3558	}
3559
3560
3561	/**
3562	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3563	*
3564	* @param pPool The pool.
3565	* @param pPage The page.
3566	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3567	*/
3568	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3569	{
3570	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3571	{
3572	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3573	if (pShwPDPT->a[i].n.u1Present)
3574	{
3575	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3576	if (pSubPage)
3577	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3578	else
3579	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3580	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3581	}
3582	}
3583	}
3584
3585
3586	/**
3587	* Clear references to shadowed pages in a 64-bit level 4 page table.
3588	*
3589	* @param pPool The pool.
3590	* @param pPage The page.
3591	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3592	*/
3593	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3594	{
3595	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3596	{
3597	if (pShwPML4->a[i].n.u1Present)
3598	{
3599	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3600	if (pSubPage)
3601	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3602	else
3603	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3604	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3605	}
3606	}
3607	}
3608
3609
3610	/**
3611	* Clear references to shadowed pages in an EPT page table.
3612	*
3613	* @param pPool The pool.
3614	* @param pPage The page.
3615	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3616	*/
3617	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3618	{
3619	RTGCPHYS GCPhys = pPage->GCPhys;
3620	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3621	if (pShwPT->a[i].n.u1Present)
3622	{
3623	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3624	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3625	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3626	}
3627	}
3628
3629
3630	/**
3631	* Clear references to shadowed pages in an EPT page directory.
3632	*
3633	* @param pPool The pool.
3634	* @param pPage The page.
3635	* @param pShwPD The shadow page directory (mapping of the page).
3636	*/
3637	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3638	{
3639	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3640	{
3641	if (pShwPD->a[i].n.u1Present)
3642	{
3643	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3644	if (pSubPage)
3645	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3646	else
3647	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3648	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3649	}
3650	}
3651	}
3652
3653
3654	/**
3655	* Clear references to shadowed pages in an EPT page directory pointer table.
3656	*
3657	* @param pPool The pool.
3658	* @param pPage The page.
3659	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3660	*/
3661	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3662	{
3663	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3664	{
3665	if (pShwPDPT->a[i].n.u1Present)
3666	{
3667	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3668	if (pSubPage)
3669	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3670	else
3671	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3672	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3673	}
3674	}
3675	}
3676
3677
3678	/**
3679	* Clears all references made by this page.
3680	*
3681	* This includes other shadow pages and GC physical addresses.
3682	*
3683	* @param pPool The pool.
3684	* @param pPage The page.
3685	*/
3686	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3687	{
3688	/*
3689	* Map the shadow page and take action according to the page kind.
3690	*/
3691	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3692	switch (pPage->enmKind)
3693	{
3694	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3695	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3696	{
3697	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3698	void *pvGst;
3699	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3700	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3701	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3702	break;
3703	}
3704
3705	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3706	{
3707	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3708	void *pvGst;
3709	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3710	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3711	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3712	break;
3713	}
3714
3715	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3716	{
3717	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3718	void *pvGst;
3719	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3720	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3721	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3722	break;
3723	}
3724
3725	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3726	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3727	{
3728	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3729	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3730	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3731	break;
3732	}
3733
3734	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3735	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3736	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3737	{
3738	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3739	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3740	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3741	break;
3742	}
3743
3744	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3745	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3746	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3747	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3748	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3749	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3750	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3751	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3752	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3753	break;
3754	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3755
3756	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3757	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3758	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3759	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3760	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3761	case PGMPOOLKIND_PAE_PD_PHYS:
3762	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3763	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3764	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3765	break;
3766
3767	case PGMPOOLKIND_32BIT_PD_PHYS:
3768	case PGMPOOLKIND_32BIT_PD:
3769	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3770	break;
3771
3772	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3773	case PGMPOOLKIND_PAE_PDPT:
3774	case PGMPOOLKIND_PAE_PDPT_PHYS:
3775	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3776	break;
3777
3778	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3779	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3780	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3781	break;
3782
3783	case PGMPOOLKIND_64BIT_PML4:
3784	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3785	break;
3786
3787	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3788	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3789	break;
3790
3791	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3792	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3793	break;
3794
3795	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3796	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3797	break;
3798
3799	default:
3800	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3801	}
3802
3803	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3804	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3805	ASMMemZeroPage(pvShw);
3806	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3807	pPage->fZeroed = true;
3808	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3809	}
3810
3811	#endif /* PGMPOOL_WITH_USER_TRACKING */
3812	#ifdef IN_RING3
3813	/**
3814	* Flushes the entire cache.
3815	*
3816	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
3817	* and execute this CR3 flush.
3818	*
3819	* @param pPool The pool.
3820	*
3821	* @remark Only used during reset now, we might want to rename and/or move it.
3822	*/
3823	static void pgmPoolFlushAllInt(PPGMPOOL pPool)
3824	{
3825	PVM pVM = pPool->CTX_SUFF(pVM);
3826
3827	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
3828	LogFlow(("pgmPoolFlushAllInt:\n"));
3829
3830	/*
3831	* If there are no pages in the pool, there is nothing to do.
3832	*/
3833	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
3834	{
3835	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
3836	return;
3837	}
3838
3839	/*
3840	* Exit the shadow mode since we're going to clear everything,
3841	* including the root page.
3842	*/
3843	/** @todo Need to synchronize this across all VCPUs! */
3844	Assert(pVM->cCPUs == 1);
3845	for (unsigned i=0;i<pVM->cCPUs;i++)
3846	{
3847	PVMCPU pVCpu = &pVM->aCpus[i];
3848	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
3849	}
3850
3851	/*
3852	* Nuke the free list and reinsert all pages into it.
3853	*/
3854	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
3855	{
3856	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3857
3858	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
3859	#ifdef PGMPOOL_WITH_MONITORING
3860	if (pPage->fMonitored)
3861	pgmPoolMonitorFlush(pPool, pPage);
3862	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3863	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3864	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3865	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3866	pPage->cModifications = 0;
3867	#endif
3868	pPage->GCPhys = NIL_RTGCPHYS;
3869	pPage->enmKind = PGMPOOLKIND_FREE;
3870	Assert(pPage->idx == i);
3871	pPage->iNext = i + 1;
3872	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
3873	pPage->fSeenNonGlobal = false;
3874	pPage->fMonitored= false;
3875	pPage->fCached = false;
3876	pPage->fReusedFlushPending = false;
3877	#ifdef PGMPOOL_WITH_USER_TRACKING
3878	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3879	#else
3880	pPage->fCR3Mix = false;
3881	#endif
3882	#ifdef PGMPOOL_WITH_CACHE
3883	pPage->iAgeNext = NIL_PGMPOOL_IDX;
3884	pPage->iAgePrev = NIL_PGMPOOL_IDX;
3885	#endif
3886	pPage->cLocked = 0;
3887	}
3888	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
3889	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
3890	pPool->cUsedPages = 0;
3891
3892	#ifdef PGMPOOL_WITH_USER_TRACKING
3893	/*
3894	* Zap and reinitialize the user records.
3895	*/
3896	pPool->cPresent = 0;
3897	pPool->iUserFreeHead = 0;
3898	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3899	const unsigned cMaxUsers = pPool->cMaxUsers;
3900	for (unsigned i = 0; i < cMaxUsers; i++)
3901	{
3902	paUsers[i].iNext = i + 1;
3903	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3904	paUsers[i].iUserTable = 0xfffffffe;
3905	}
3906	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
3907	#endif
3908
3909	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3910	/*
3911	* Clear all the GCPhys links and rebuild the phys ext free list.
3912	*/
3913	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
3914	pRam;
3915	pRam = pRam->CTX_SUFF(pNext))
3916	{
3917	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3918	while (iPage-- > 0)
3919	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
3920	}
3921
3922	pPool->iPhysExtFreeHead = 0;
3923	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3924	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
3925	for (unsigned i = 0; i < cMaxPhysExts; i++)
3926	{
3927	paPhysExts[i].iNext = i + 1;
3928	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
3929	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
3930	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
3931	}
3932	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3933	#endif
3934
3935	#ifdef PGMPOOL_WITH_MONITORING
3936	/*
3937	* Just zap the modified list.
3938	*/
3939	pPool->cModifiedPages = 0;
3940	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
3941	#endif
3942
3943	#ifdef PGMPOOL_WITH_CACHE
3944	/*
3945	* Clear the GCPhys hash and the age list.
3946	*/
3947	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
3948	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
3949	pPool->iAgeHead = NIL_PGMPOOL_IDX;
3950	pPool->iAgeTail = NIL_PGMPOOL_IDX;
3951	#endif
3952
3953	/*
3954	* Reinsert active pages into the hash and ensure monitoring chains are correct.
3955	*/
3956	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
3957	{
3958	PPGMPOOLPAGE pPage = &pPool->aPages[i];
3959	pPage->iNext = NIL_PGMPOOL_IDX;
3960	#ifdef PGMPOOL_WITH_MONITORING
3961	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
3962	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
3963	pPage->cModifications = 0;
3964	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
3965	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
3966	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
3967	if (pPage->fMonitored)
3968	{
3969	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
3970	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
3971	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
3972	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
3973	pPool->pszAccessHandler);
3974	AssertFatalRCSuccess(rc);
3975	# ifdef PGMPOOL_WITH_CACHE
3976	pgmPoolHashInsert(pPool, pPage);
3977	# endif
3978	}
3979	#endif
3980	#ifdef PGMPOOL_WITH_USER_TRACKING
3981	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
3982	#endif
3983	#ifdef PGMPOOL_WITH_CACHE
3984	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
3985	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
3986	#endif
3987	}
3988
3989	for (unsigned i=0;i<pVM->cCPUs;i++)
3990	{
3991	PVMCPU pVCpu = &pVM->aCpus[i];
3992	/*
3993	* Re-enter the shadowing mode and assert Sync CR3 FF.
3994	*/
3995	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
3996	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3997	}
3998
3999	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4000	}
4001
4002	#endif /* IN_RING3 */
4003
4004	/**
4005	* Flushes a pool page.
4006	*
4007	* This moves the page to the free list after removing all user references to it.
4008	* In GC this will cause a CR3 reload if the page is traced back to an active root page.
4009	*
4010	* @returns VBox status code.
4011	* @retval VINF_SUCCESS on success.
4012	* @param pPool The pool.
4013	* @param HCPhys The HC physical address of the shadow page.
4014	*/
4015	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4016	{
4017	PVM pVM = pPool->CTX_SUFF(pVM);
4018
4019	int rc = VINF_SUCCESS;
4020	STAM_PROFILE_START(&pPool->StatFlushPage, f);
4021	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4022	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4023
4024	/*
4025	* Quietly reject any attempts at flushing any of the special root pages.
4026	*/
4027	if (pPage->idx < PGMPOOL_IDX_FIRST)
4028	{
4029	AssertFailed(); /* can no longer happen */
4030	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4031	return VINF_SUCCESS;
4032	}
4033
4034	pgmLock(pVM);
4035
4036	/*
4037	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4038	*/
4039	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4040	{
4041	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4042	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4043	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4044	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4045	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4046	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4047	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4048	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4049	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4050	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4051	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4052	pgmUnlock(pVM);
4053	return VINF_SUCCESS;
4054	}
4055
4056	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4057	/* Start a subset so we won't run out of mapping space. */
4058	PVMCPU pVCpu = VMMGetCpu(pVM);
4059	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4060	#endif
4061
4062	/*
4063	* Mark the page as being in need of a ASMMemZeroPage().
4064	*/
4065	pPage->fZeroed = false;
4066
4067	#ifdef PGMPOOL_WITH_USER_TRACKING
4068	/*
4069	* Clear the page.
4070	*/
4071	pgmPoolTrackClearPageUsers(pPool, pPage);
4072	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4073	pgmPoolTrackDeref(pPool, pPage);
4074	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4075	#endif
4076
4077	#ifdef PGMPOOL_WITH_CACHE
4078	/*
4079	* Flush it from the cache.
4080	*/
4081	pgmPoolCacheFlushPage(pPool, pPage);
4082	#endif /* PGMPOOL_WITH_CACHE */
4083
4084	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4085	/* Heavy stuff done. */
4086	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4087	#endif
4088
4089	#ifdef PGMPOOL_WITH_MONITORING
4090	/*
4091	* Deregistering the monitoring.
4092	*/
4093	if (pPage->fMonitored)
4094	rc = pgmPoolMonitorFlush(pPool, pPage);
4095	#endif
4096
4097	/*
4098	* Free the page.
4099	*/
4100	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4101	pPage->iNext = pPool->iFreeHead;
4102	pPool->iFreeHead = pPage->idx;
4103	pPage->enmKind = PGMPOOLKIND_FREE;
4104	pPage->GCPhys = NIL_RTGCPHYS;
4105	pPage->fReusedFlushPending = false;
4106
4107	pPool->cUsedPages--;
4108	pgmUnlock(pVM);
4109	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4110	return rc;
4111	}
4112
4113
4114	/**
4115	* Frees a usage of a pool page.
4116	*
4117	* The caller is responsible to updating the user table so that it no longer
4118	* references the shadow page.
4119	*
4120	* @param pPool The pool.
4121	* @param HCPhys The HC physical address of the shadow page.
4122	* @param iUser The shadow page pool index of the user table.
4123	* @param iUserTable The index into the user table (shadowed).
4124	*/
4125	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4126	{
4127	PVM pVM = pPool->CTX_SUFF(pVM);
4128
4129	STAM_PROFILE_START(&pPool->StatFree, a);
4130	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4131	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4132	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4133	pgmLock(pVM);
4134	#ifdef PGMPOOL_WITH_USER_TRACKING
4135	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4136	#endif
4137	#ifdef PGMPOOL_WITH_CACHE
4138	if (!pPage->fCached)
4139	#endif
4140	pgmPoolFlushPage(pPool, pPage);
4141	pgmUnlock(pVM);
4142	STAM_PROFILE_STOP(&pPool->StatFree, a);
4143	}
4144
4145
4146	/**
4147	* Makes one or more free page free.
4148	*
4149	* @returns VBox status code.
4150	* @retval VINF_SUCCESS on success.
4151	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4152	*
4153	* @param pPool The pool.
4154	* @param enmKind Page table kind
4155	* @param iUser The user of the page.
4156	*/
4157	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4158	{
4159	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4160
4161	/*
4162	* If the pool isn't full grown yet, expand it.
4163	*/
4164	if ( pPool->cCurPages < pPool->cMaxPages
4165	#if defined(IN_RC)
4166	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4167	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4168	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4169	#endif
4170	)
4171	{
4172	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4173	#ifdef IN_RING3
4174	int rc = PGMR3PoolGrow(pPool->pVMR3);
4175	#else
4176	int rc = CTXALLMID(VMM, CallHost)(pPool->CTX_SUFF(pVM), VMMCALLHOST_PGM_POOL_GROW, 0);
4177	#endif
4178	if (RT_FAILURE(rc))
4179	return rc;
4180	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4181	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4182	return VINF_SUCCESS;
4183	}
4184
4185	#ifdef PGMPOOL_WITH_CACHE
4186	/*
4187	* Free one cached page.
4188	*/
4189	return pgmPoolCacheFreeOne(pPool, iUser);
4190	#else
4191	/*
4192	* Flush the pool.
4193	*
4194	* If we have tracking enabled, it should be possible to come up with
4195	* a cheap replacement strategy...
4196	*/
4197	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4198	AssertCompileFailed();
4199	Assert(!CPUMIsGuestInLongMode(pVM));
4200	pgmPoolFlushAllInt(pPool);
4201	return VERR_PGM_POOL_FLUSHED;
4202	#endif
4203	}
4204
4205
4206	/**
4207	* Allocates a page from the pool.
4208	*
4209	* This page may actually be a cached page and not in need of any processing
4210	* on the callers part.
4211	*
4212	* @returns VBox status code.
4213	* @retval VINF_SUCCESS if a NEW page was allocated.
4214	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4215	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4216	* @param pVM The VM handle.
4217	* @param GCPhys The GC physical address of the page we're gonna shadow.
4218	* For 4MB and 2MB PD entries, it's the first address the
4219	* shadow PT is covering.
4220	* @param enmKind The kind of mapping.
4221	* @param iUser The shadow page pool index of the user table.
4222	* @param iUserTable The index into the user table (shadowed).
4223	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4224	*/
4225	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
4226	{
4227	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4228	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4229	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4230	*ppPage = NULL;
4231	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4232	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4233	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)); */
4234
4235	pgmLock(pVM);
4236
4237	#ifdef PGMPOOL_WITH_CACHE
4238	if (pPool->fCacheEnabled)
4239	{
4240	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, iUser, iUserTable, ppPage);
4241	if (RT_SUCCESS(rc2))
4242	{
4243	pgmUnlock(pVM);
4244	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4245	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4246	return rc2;
4247	}
4248	}
4249	#endif
4250
4251	/*
4252	* Allocate a new one.
4253	*/
4254	int rc = VINF_SUCCESS;
4255	uint16_t iNew = pPool->iFreeHead;
4256	if (iNew == NIL_PGMPOOL_IDX)
4257	{
4258	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4259	if (RT_FAILURE(rc))
4260	{
4261	pgmUnlock(pVM);
4262	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4263	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4264	return rc;
4265	}
4266	iNew = pPool->iFreeHead;
4267	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4268	}
4269
4270	/* unlink the free head */
4271	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4272	pPool->iFreeHead = pPage->iNext;
4273	pPage->iNext = NIL_PGMPOOL_IDX;
4274
4275	/*
4276	* Initialize it.
4277	*/
4278	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4279	pPage->enmKind = enmKind;
4280	pPage->GCPhys = GCPhys;
4281	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4282	pPage->fMonitored = false;
4283	pPage->fCached = false;
4284	pPage->fReusedFlushPending = false;
4285	#ifdef PGMPOOL_WITH_MONITORING
4286	pPage->cModifications = 0;
4287	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4288	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4289	#else
4290	pPage->fCR3Mix = false;
4291	#endif
4292	#ifdef PGMPOOL_WITH_USER_TRACKING
4293	pPage->cPresent = 0;
4294	pPage->iFirstPresent = ~0;
4295
4296	/*
4297	* Insert into the tracking and cache. If this fails, free the page.
4298	*/
4299	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4300	if (RT_FAILURE(rc3))
4301	{
4302	pPool->cUsedPages--;
4303	pPage->enmKind = PGMPOOLKIND_FREE;
4304	pPage->GCPhys = NIL_RTGCPHYS;
4305	pPage->iNext = pPool->iFreeHead;
4306	pPool->iFreeHead = pPage->idx;
4307	pgmUnlock(pVM);
4308	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4309	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4310	return rc3;
4311	}
4312	#endif /* PGMPOOL_WITH_USER_TRACKING */
4313
4314	/*
4315	* Commit the allocation, clear the page and return.
4316	*/
4317	#ifdef VBOX_WITH_STATISTICS
4318	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4319	pPool->cUsedPagesHigh = pPool->cUsedPages;
4320	#endif
4321
4322	if (!pPage->fZeroed)
4323	{
4324	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4325	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4326	ASMMemZeroPage(pv);
4327	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4328	}
4329
4330	*ppPage = pPage;
4331	pgmUnlock(pVM);
4332	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4333	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4334	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4335	return rc;
4336	}
4337
4338
4339	/**
4340	* Frees a usage of a pool page.
4341	*
4342	* @param pVM The VM handle.
4343	* @param HCPhys The HC physical address of the shadow page.
4344	* @param iUser The shadow page pool index of the user table.
4345	* @param iUserTable The index into the user table (shadowed).
4346	*/
4347	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4348	{
4349	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4350	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4351	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4352	}
4353
4354	/**
4355	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4356	*
4357	* @returns Pointer to the shadow page structure.
4358	* @param pPool The pool.
4359	* @param HCPhys The HC physical address of the shadow page.
4360	*/
4361	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4362	{
4363	PVM pVM = pPool->CTX_SUFF(pVM);
4364
4365	/*
4366	* Look up the page.
4367	*/
4368	pgmLock(pVM);
4369	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4370	pgmUnlock(pVM);
4371
4372	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4373	return pPage;
4374	}
4375
4376
4377	#ifdef IN_RING3
4378	/**
4379	* Flushes the entire cache.
4380	*
4381	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4382	* and execute this CR3 flush.
4383	*
4384	* @param pPool The pool.
4385	*/
4386	void pgmPoolFlushAll(PVM pVM)
4387	{
4388	LogFlow(("pgmPoolFlushAll:\n"));
4389	pgmPoolFlushAllInt(pVM->pgm.s.CTX_SUFF(pPool));
4390	}
4391	#endif /* IN_RING3 */
4392
4393	#ifdef LOG_ENABLED
4394	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4395	{
4396	switch(enmKind)
4397	{
4398	case PGMPOOLKIND_INVALID:
4399	return "PGMPOOLKIND_INVALID";
4400	case PGMPOOLKIND_FREE:
4401	return "PGMPOOLKIND_FREE";
4402	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4403	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4404	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4405	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4406	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4407	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4408	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4409	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4410	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4411	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4412	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4413	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4414	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4415	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4416	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4417	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4418	case PGMPOOLKIND_32BIT_PD:
4419	return "PGMPOOLKIND_32BIT_PD";
4420	case PGMPOOLKIND_32BIT_PD_PHYS:
4421	return "PGMPOOLKIND_32BIT_PD_PHYS";
4422	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4423	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4424	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4425	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4426	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4427	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4428	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4429	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4430	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4431	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4432	case PGMPOOLKIND_PAE_PD_PHYS:
4433	return "PGMPOOLKIND_PAE_PD_PHYS";
4434	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4435	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4436	case PGMPOOLKIND_PAE_PDPT:
4437	return "PGMPOOLKIND_PAE_PDPT";
4438	case PGMPOOLKIND_PAE_PDPT_PHYS:
4439	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4440	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4441	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4442	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4443	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4444	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4445	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4446	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4447	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4448	case PGMPOOLKIND_64BIT_PML4:
4449	return "PGMPOOLKIND_64BIT_PML4";
4450	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4451	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4452	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4453	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4454	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4455	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4456	case PGMPOOLKIND_ROOT_NESTED:
4457	return "PGMPOOLKIND_ROOT_NESTED";
4458	}
4459	return "Unknown kind!";
4460	}
4461	#endif /* LOG_ENABLED*/

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 19752

Download in other formats: