PGMAllPool.cpp@ 22336

Last change on this file since 22336 was 22336, checked in by vboxsync, 15 years ago
Moved check for changed pgm pool page up.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 163.5 KB

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1	/* $Id: PGMAllPool.cpp 22336 2009-08-19 08:14:20Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	RT_C_DECLS_BEGIN
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	RT_C_DECLS_END
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pDis The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pDis)
249	{
250	AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%#x (idx=%#x)\n", pPage->iMonitoredPrev, pPage->idx));
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = pDis ? pgmPoolDisasWriteSize(pDis) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pDis
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pDis
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pDis
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pDis
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pDis
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pDis
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pDis
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pDis
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pDis The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pDis->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pRegFrame Trap register frame.
823	* @param pDis The disassembly info for the faulting instruction.
824	* @param pvFault The fault address.
825	*
826	* @remark The REP prefix check is left to the caller because of STOSD/W.
827	*/
828	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
829	{
830	#ifndef IN_RC
831	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
832	if ( HWACCMHasPendingIrq(pVM)
833	&& (pRegFrame->rsp - pvFault) < 32)
834	{
835	/* Fault caused by stack writes while trying to inject an interrupt event. */
836	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
837	return true;
838	}
839	#else
840	NOREF(pVM); NOREF(pvFault);
841	#endif
842
843	switch (pDis->pCurInstr->opcode)
844	{
845	/* call implies the actual push of the return address faulted */
846	case OP_CALL:
847	Log4(("pgmPoolMonitorIsReused: CALL\n"));
848	return true;
849	case OP_PUSH:
850	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
851	return true;
852	case OP_PUSHF:
853	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
854	return true;
855	case OP_PUSHA:
856	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
857	return true;
858	case OP_FXSAVE:
859	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
860	return true;
861	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
862	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
863	return true;
864	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
865	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
866	return true;
867	case OP_MOVSWD:
868	case OP_STOSWD:
869	if ( pDis->prefix == (PREFIX_REP\|PREFIX_REX)
870	&& pRegFrame->rcx >= 0x40
871	)
872	{
873	Assert(pDis->mode == CPUMODE_64BIT);
874
875	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
876	return true;
877	}
878	return false;
879	}
880	if ( (pDis->param1.flags & USE_REG_GEN32)
881	&& (pDis->param1.base.reg_gen == USE_REG_ESP))
882	{
883	Log4(("pgmPoolMonitorIsReused: ESP\n"));
884	return true;
885	}
886
887	return false;
888	}
889
890
891	/**
892	* Flushes the page being accessed.
893	*
894	* @returns VBox status code suitable for scheduling.
895	* @param pVM The VM handle.
896	* @param pVCpu The VMCPU handle.
897	* @param pPool The pool.
898	* @param pPage The pool page (head).
899	* @param pDis The disassembly of the write instruction.
900	* @param pRegFrame The trap register frame.
901	* @param GCPhysFault The fault address as guest physical address.
902	* @param pvFault The fault address.
903	*/
904	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
905	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
906	{
907	/*
908	* First, do the flushing.
909	*/
910	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
911
912	/*
913	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
914	*/
915	uint32_t cbWritten;
916	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten);
917	if (RT_SUCCESS(rc2))
918	pRegFrame->rip += pDis->opsize;
919	else if (rc2 == VERR_EM_INTERPRETER)
920	{
921	#ifdef IN_RC
922	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
923	{
924	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
925	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
926	rc = VINF_SUCCESS;
927	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
928	}
929	else
930	#endif
931	{
932	rc = VINF_EM_RAW_EMULATE_INSTR;
933	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
934	}
935	}
936	else
937	rc = rc2;
938
939	/* See use in pgmPoolAccessHandlerSimple(). */
940	PGM_INVL_VCPU_TLBS(pVCpu);
941
942	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
943	return rc;
944
945	}
946
947
948	/**
949	* Handles the STOSD write accesses.
950	*
951	* @returns VBox status code suitable for scheduling.
952	* @param pVM The VM handle.
953	* @param pPool The pool.
954	* @param pPage The pool page (head).
955	* @param pDis The disassembly of the write instruction.
956	* @param pRegFrame The trap register frame.
957	* @param GCPhysFault The fault address as guest physical address.
958	* @param pvFault The fault address.
959	*/
960	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
961	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
962	{
963	unsigned uIncrement;
964
965	Assert(pDis->mode == CPUMODE_32BIT \|\| pDis->mode == CPUMODE_64BIT);
966	Assert(pRegFrame->rcx <= 0x20);
967
968	if (pDis->mode == CPUMODE_32BIT)
969	uIncrement = 4;
970	else
971	uIncrement = 8;
972
973	Log3(("pgmPoolAccessHandlerSTOSD\n"));
974
975	/*
976	* Increment the modification counter and insert it into the list
977	* of modified pages the first time.
978	*/
979	if (!pPage->cModifications++)
980	pgmPoolMonitorModifiedInsert(pPool, pPage);
981
982	/*
983	* Execute REP STOSD.
984	*
985	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
986	* write situation, meaning that it's safe to write here.
987	*/
988	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
989	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
990	while (pRegFrame->rcx)
991	{
992	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
993	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
994	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
995	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
996	#else
997	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
998	#endif
999	#ifdef IN_RC
1000	(uint32_t )pu32 = pRegFrame->eax;
1001	#else
1002	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
1003	#endif
1004	pu32 += uIncrement;
1005	GCPhysFault += uIncrement;
1006	pRegFrame->rdi += uIncrement;
1007	pRegFrame->rcx--;
1008	}
1009	pRegFrame->rip += pDis->opsize;
1010
1011	#ifdef IN_RC
1012	/* See use in pgmPoolAccessHandlerSimple(). */
1013	PGM_INVL_VCPU_TLBS(pVCpu);
1014	#endif
1015
1016	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1017	return VINF_SUCCESS;
1018	}
1019
1020
1021	/**
1022	* Handles the simple write accesses.
1023	*
1024	* @returns VBox status code suitable for scheduling.
1025	* @param pVM The VM handle.
1026	* @param pVCpu The VMCPU handle.
1027	* @param pPool The pool.
1028	* @param pPage The pool page (head).
1029	* @param pDis The disassembly of the write instruction.
1030	* @param pRegFrame The trap register frame.
1031	* @param GCPhysFault The fault address as guest physical address.
1032	* @param pvFault The fault address.
1033	*/
1034	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
1035	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1036	{
1037	Log3(("pgmPoolAccessHandlerSimple\n"));
1038	/*
1039	* Increment the modification counter and insert it into the list
1040	* of modified pages the first time.
1041	*/
1042	if (!pPage->cModifications++)
1043	pgmPoolMonitorModifiedInsert(pPool, pPage);
1044
1045	/*
1046	* Clear all the pages. ASSUMES that pvFault is readable.
1047	*/
1048	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1049	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1050	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1051	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1052	#else
1053	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1054	#endif
1055
1056	/*
1057	* Interpret the instruction.
1058	*/
1059	uint32_t cb;
1060	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb);
1061	if (RT_SUCCESS(rc))
1062	pRegFrame->rip += pDis->opsize;
1063	else if (rc == VERR_EM_INTERPRETER)
1064	{
1065	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1066	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
1067	rc = VINF_EM_RAW_EMULATE_INSTR;
1068	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1069	}
1070
1071	#ifdef IN_RC
1072	/*
1073	* Quick hack, with logging enabled we're getting stale
1074	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1075	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1076	* have to be fixed to support this. But that'll have to wait till next week.
1077	*
1078	* An alternative is to keep track of the changed PTEs together with the
1079	* GCPhys from the guest PT. This may proove expensive though.
1080	*
1081	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1082	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1083	*/
1084	PGM_INVL_VCPU_TLBS(pVCpu);
1085	#endif
1086
1087	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1088	return rc;
1089	}
1090
1091	/**
1092	* \#PF Handler callback for PT write accesses.
1093	*
1094	* @returns VBox status code (appropriate for GC return).
1095	* @param pVM VM Handle.
1096	* @param uErrorCode CPU Error code.
1097	* @param pRegFrame Trap register frame.
1098	* NULL on DMA and other non CPU access.
1099	* @param pvFault The fault address (cr2).
1100	* @param GCPhysFault The GC physical address corresponding to pvFault.
1101	* @param pvUser User argument.
1102	*/
1103	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1104	{
1105	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1106	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1107	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1108	PVMCPU pVCpu = VMMGetCpu(pVM);
1109
1110	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1111
1112	pgmLock(pVM);
1113	if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1114	{
1115	/* Pool page changed while we were waiting for the lock; ignore. */
1116	Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1117	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1118	pgmUnlock(pVM);
1119	return VINF_SUCCESS;
1120	}
1121
1122	/*
1123	* Disassemble the faulting instruction.
1124	*/
1125	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1126	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1127	AssertReturnStmt(rc == VINF_SUCCESS, pgmUnlock(pVM), rc);
1128
1129	Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1130
1131	/*
1132	* We should ALWAYS have the list head as user parameter. This
1133	* is because we use that page to record the changes.
1134	*/
1135	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1136
1137	/*
1138	* Check if it's worth dealing with.
1139	*/
1140	bool fReused = false;
1141	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1142	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1143	)
1144	&& !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, pDis, pvFault))
1145	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1146	{
1147	/*
1148	* Simple instructions, no REP prefix.
1149	*/
1150	if (!(pDis->prefix & (PREFIX_REP \| PREFIX_REPNE)))
1151	{
1152	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1153	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1154	pgmUnlock(pVM);
1155	return rc;
1156	}
1157
1158	/*
1159	* Windows is frequently doing small memset() operations (netio test 4k+).
1160	* We have to deal with these or we'll kill the cache and performance.
1161	*/
1162	if ( pDis->pCurInstr->opcode == OP_STOSWD
1163	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1164	&& !pRegFrame->eflags.Bits.u1DF
1165	&& pDis->opmode == pDis->mode
1166	&& pDis->addrmode == pDis->mode)
1167	{
1168	bool fValidStosd = false;
1169
1170	if ( pDis->mode == CPUMODE_32BIT
1171	&& pDis->prefix == PREFIX_REP
1172	&& pRegFrame->ecx <= 0x20
1173	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1174	&& !((uintptr_t)pvFault & 3)
1175	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1176	)
1177	{
1178	fValidStosd = true;
1179	pRegFrame->rcx &= 0xffffffff; /* paranoia */
1180	}
1181	else
1182	if ( pDis->mode == CPUMODE_64BIT
1183	&& pDis->prefix == (PREFIX_REP \| PREFIX_REX)
1184	&& pRegFrame->rcx <= 0x20
1185	&& pRegFrame->rcx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1186	&& !((uintptr_t)pvFault & 3)
1187	&& (pRegFrame->rax == 0 \|\| pRegFrame->rax == 0x80) /* the two values observed. */
1188	)
1189	{
1190	fValidStosd = true;
1191	}
1192
1193	if (fValidStosd)
1194	{
1195	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1196	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1197	pgmUnlock(pVM);
1198	return rc;
1199	}
1200	}
1201
1202	/* REP prefix, don't bother. */
1203	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1204	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1205	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1206	}
1207
1208	/*
1209	* Not worth it, so flush it.
1210	*
1211	* If we considered it to be reused, don't go back to ring-3
1212	* to emulate failed instructions since we usually cannot
1213	* interpret then. This may be a bit risky, in which case
1214	* the reuse detection must be fixed.
1215	*/
1216	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1217	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1218	rc = VINF_SUCCESS;
1219	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1220	pgmUnlock(pVM);
1221	return rc;
1222	}
1223
1224	# endif /* !IN_RING3 */
1225	#endif /* PGMPOOL_WITH_MONITORING */
1226
1227	#ifdef PGMPOOL_WITH_CACHE
1228
1229	/**
1230	* Inserts a page into the GCPhys hash table.
1231	*
1232	* @param pPool The pool.
1233	* @param pPage The page.
1234	*/
1235	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1236	{
1237	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1238	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1239	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1240	pPage->iNext = pPool->aiHash[iHash];
1241	pPool->aiHash[iHash] = pPage->idx;
1242	}
1243
1244
1245	/**
1246	* Removes a page from the GCPhys hash table.
1247	*
1248	* @param pPool The pool.
1249	* @param pPage The page.
1250	*/
1251	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1252	{
1253	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1254	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1255	if (pPool->aiHash[iHash] == pPage->idx)
1256	pPool->aiHash[iHash] = pPage->iNext;
1257	else
1258	{
1259	uint16_t iPrev = pPool->aiHash[iHash];
1260	for (;;)
1261	{
1262	const int16_t i = pPool->aPages[iPrev].iNext;
1263	if (i == pPage->idx)
1264	{
1265	pPool->aPages[iPrev].iNext = pPage->iNext;
1266	break;
1267	}
1268	if (i == NIL_PGMPOOL_IDX)
1269	{
1270	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1271	break;
1272	}
1273	iPrev = i;
1274	}
1275	}
1276	pPage->iNext = NIL_PGMPOOL_IDX;
1277	}
1278
1279
1280	/**
1281	* Frees up one cache page.
1282	*
1283	* @returns VBox status code.
1284	* @retval VINF_SUCCESS on success.
1285	* @param pPool The pool.
1286	* @param iUser The user index.
1287	*/
1288	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1289	{
1290	#ifndef IN_RC
1291	const PVM pVM = pPool->CTX_SUFF(pVM);
1292	#endif
1293	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1294	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1295
1296	/*
1297	* Select one page from the tail of the age list.
1298	*/
1299	PPGMPOOLPAGE pPage;
1300	for (unsigned iLoop = 0; ; iLoop++)
1301	{
1302	uint16_t iToFree = pPool->iAgeTail;
1303	if (iToFree == iUser)
1304	iToFree = pPool->aPages[iToFree].iAgePrev;
1305	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1306	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1307	{
1308	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1309	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1310	{
1311	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1312	continue;
1313	iToFree = i;
1314	break;
1315	}
1316	}
1317	*/
1318	Assert(iToFree != iUser);
1319	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1320	pPage = &pPool->aPages[iToFree];
1321
1322	/*
1323	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1324	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1325	*/
1326	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1327	break;
1328	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1329	pgmPoolCacheUsed(pPool, pPage);
1330	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1331	}
1332
1333	/*
1334	* Found a usable page, flush it and return.
1335	*/
1336	int rc = pgmPoolFlushPage(pPool, pPage);
1337	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
1338	if (rc == VINF_SUCCESS)
1339	PGM_INVL_ALL_VCPU_TLBS(pVM);
1340	return rc;
1341	}
1342
1343
1344	/**
1345	* Checks if a kind mismatch is really a page being reused
1346	* or if it's just normal remappings.
1347	*
1348	* @returns true if reused and the cached page (enmKind1) should be flushed
1349	* @returns false if not reused.
1350	* @param enmKind1 The kind of the cached page.
1351	* @param enmKind2 The kind of the requested page.
1352	*/
1353	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1354	{
1355	switch (enmKind1)
1356	{
1357	/*
1358	* Never reuse them. There is no remapping in non-paging mode.
1359	*/
1360	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1361	case PGMPOOLKIND_32BIT_PD_PHYS:
1362	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1363	case PGMPOOLKIND_PAE_PD_PHYS:
1364	case PGMPOOLKIND_PAE_PDPT_PHYS:
1365	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1366	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1367	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1368	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1369	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1370	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1371	return false;
1372
1373	/*
1374	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1375	*/
1376	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1377	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1378	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1379	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1380	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1381	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1382	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1383	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1384	case PGMPOOLKIND_32BIT_PD:
1385	case PGMPOOLKIND_PAE_PDPT:
1386	switch (enmKind2)
1387	{
1388	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1390	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1391	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1392	case PGMPOOLKIND_64BIT_PML4:
1393	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1394	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1395	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1396	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1397	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1398	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1399	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1400	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1401	return true;
1402	default:
1403	return false;
1404	}
1405
1406	/*
1407	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1408	*/
1409	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1410	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1411	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1412	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1413	case PGMPOOLKIND_64BIT_PML4:
1414	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1415	switch (enmKind2)
1416	{
1417	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1418	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1419	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1420	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1421	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1422	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1423	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1424	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1425	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1426	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1427	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1428	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1429	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1430	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1431	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1432	return true;
1433	default:
1434	return false;
1435	}
1436
1437	/*
1438	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1439	*/
1440	case PGMPOOLKIND_ROOT_NESTED:
1441	return false;
1442
1443	default:
1444	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1445	}
1446	}
1447
1448
1449	/**
1450	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1451	*
1452	* @returns VBox status code.
1453	* @retval VINF_PGM_CACHED_PAGE on success.
1454	* @retval VERR_FILE_NOT_FOUND if not found.
1455	* @param pPool The pool.
1456	* @param GCPhys The GC physical address of the page we're gonna shadow.
1457	* @param enmKind The kind of mapping.
1458	* @param enmAccess Access type for the mapping (only relevant for big pages)
1459	* @param iUser The shadow page pool index of the user table.
1460	* @param iUserTable The index into the user table (shadowed).
1461	* @param ppPage Where to store the pointer to the page.
1462	*/
1463	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1464	{
1465	#ifndef IN_RC
1466	const PVM pVM = pPool->CTX_SUFF(pVM);
1467	#endif
1468	/*
1469	* Look up the GCPhys in the hash.
1470	*/
1471	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1472	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1473	if (i != NIL_PGMPOOL_IDX)
1474	{
1475	do
1476	{
1477	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1478	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1479	if (pPage->GCPhys == GCPhys)
1480	{
1481	if ( (PGMPOOLKIND)pPage->enmKind == enmKind
1482	&& (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
1483	{
1484	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1485	* doesn't flush it in case there are no more free use records.
1486	*/
1487	pgmPoolCacheUsed(pPool, pPage);
1488
1489	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1490	if (RT_SUCCESS(rc))
1491	{
1492	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1493	*ppPage = pPage;
1494	STAM_COUNTER_INC(&pPool->StatCacheHits);
1495	return VINF_PGM_CACHED_PAGE;
1496	}
1497	return rc;
1498	}
1499
1500	if ((PGMPOOLKIND)pPage->enmKind != enmKind)
1501	{
1502	/*
1503	* The kind is different. In some cases we should now flush the page
1504	* as it has been reused, but in most cases this is normal remapping
1505	* of PDs as PT or big pages using the GCPhys field in a slightly
1506	* different way than the other kinds.
1507	*/
1508	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1509	{
1510	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1511	pgmPoolFlushPage(pPool, pPage);
1512	PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
1513	break;
1514	}
1515	}
1516	}
1517
1518	/* next */
1519	i = pPage->iNext;
1520	} while (i != NIL_PGMPOOL_IDX);
1521	}
1522
1523	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1524	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1525	return VERR_FILE_NOT_FOUND;
1526	}
1527
1528
1529	/**
1530	* Inserts a page into the cache.
1531	*
1532	* @param pPool The pool.
1533	* @param pPage The cached page.
1534	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1535	*/
1536	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1537	{
1538	/*
1539	* Insert into the GCPhys hash if the page is fit for that.
1540	*/
1541	Assert(!pPage->fCached);
1542	if (fCanBeCached)
1543	{
1544	pPage->fCached = true;
1545	pgmPoolHashInsert(pPool, pPage);
1546	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1547	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1548	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1549	}
1550	else
1551	{
1552	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1553	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1554	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1555	}
1556
1557	/*
1558	* Insert at the head of the age list.
1559	*/
1560	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1561	pPage->iAgeNext = pPool->iAgeHead;
1562	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1563	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1564	else
1565	pPool->iAgeTail = pPage->idx;
1566	pPool->iAgeHead = pPage->idx;
1567	}
1568
1569
1570	/**
1571	* Flushes a cached page.
1572	*
1573	* @param pPool The pool.
1574	* @param pPage The cached page.
1575	*/
1576	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1577	{
1578	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1579
1580	/*
1581	* Remove the page from the hash.
1582	*/
1583	if (pPage->fCached)
1584	{
1585	pPage->fCached = false;
1586	pgmPoolHashRemove(pPool, pPage);
1587	}
1588	else
1589	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1590
1591	/*
1592	* Remove it from the age list.
1593	*/
1594	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1595	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1596	else
1597	pPool->iAgeTail = pPage->iAgePrev;
1598	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1599	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1600	else
1601	pPool->iAgeHead = pPage->iAgeNext;
1602	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1603	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1604	}
1605
1606	#endif /* PGMPOOL_WITH_CACHE */
1607	#ifdef PGMPOOL_WITH_MONITORING
1608
1609	/**
1610	* Looks for pages sharing the monitor.
1611	*
1612	* @returns Pointer to the head page.
1613	* @returns NULL if not found.
1614	* @param pPool The Pool
1615	* @param pNewPage The page which is going to be monitored.
1616	*/
1617	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1618	{
1619	#ifdef PGMPOOL_WITH_CACHE
1620	/*
1621	* Look up the GCPhys in the hash.
1622	*/
1623	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1624	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1625	if (i == NIL_PGMPOOL_IDX)
1626	return NULL;
1627	do
1628	{
1629	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1630	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1631	&& pPage != pNewPage)
1632	{
1633	switch (pPage->enmKind)
1634	{
1635	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1636	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1637	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1638	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1639	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1640	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1641	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1642	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1643	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1644	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1645	case PGMPOOLKIND_64BIT_PML4:
1646	case PGMPOOLKIND_32BIT_PD:
1647	case PGMPOOLKIND_PAE_PDPT:
1648	{
1649	/* find the head */
1650	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1651	{
1652	Assert(pPage->iMonitoredPrev != pPage->idx);
1653	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1654	}
1655	return pPage;
1656	}
1657
1658	/* ignore, no monitoring. */
1659	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1660	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1661	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1662	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1663	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1664	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1665	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1666	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1667	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1668	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1669	case PGMPOOLKIND_ROOT_NESTED:
1670	case PGMPOOLKIND_PAE_PD_PHYS:
1671	case PGMPOOLKIND_PAE_PDPT_PHYS:
1672	case PGMPOOLKIND_32BIT_PD_PHYS:
1673	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1674	break;
1675	default:
1676	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1677	}
1678	}
1679
1680	/* next */
1681	i = pPage->iNext;
1682	} while (i != NIL_PGMPOOL_IDX);
1683	#endif
1684	return NULL;
1685	}
1686
1687
1688	/**
1689	* Enabled write monitoring of a guest page.
1690	*
1691	* @returns VBox status code.
1692	* @retval VINF_SUCCESS on success.
1693	* @param pPool The pool.
1694	* @param pPage The cached page.
1695	*/
1696	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1697	{
1698	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1699
1700	/*
1701	* Filter out the relevant kinds.
1702	*/
1703	switch (pPage->enmKind)
1704	{
1705	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1706	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1707	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1708	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1709	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1710	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1711	case PGMPOOLKIND_64BIT_PML4:
1712	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1713	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1714	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1715	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1716	case PGMPOOLKIND_32BIT_PD:
1717	case PGMPOOLKIND_PAE_PDPT:
1718	break;
1719
1720	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1721	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1722	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1723	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1724	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1725	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1726	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1727	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1728	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1729	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1730	case PGMPOOLKIND_ROOT_NESTED:
1731	/* Nothing to monitor here. */
1732	return VINF_SUCCESS;
1733
1734	case PGMPOOLKIND_32BIT_PD_PHYS:
1735	case PGMPOOLKIND_PAE_PDPT_PHYS:
1736	case PGMPOOLKIND_PAE_PD_PHYS:
1737	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1738	/* Nothing to monitor here. */
1739	return VINF_SUCCESS;
1740	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1741	break;
1742	#else
1743	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1744	#endif
1745	default:
1746	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1747	}
1748
1749	/*
1750	* Install handler.
1751	*/
1752	int rc;
1753	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1754	if (pPageHead)
1755	{
1756	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1757	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1758	pPage->iMonitoredPrev = pPageHead->idx;
1759	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1760	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1761	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1762	pPageHead->iMonitoredNext = pPage->idx;
1763	rc = VINF_SUCCESS;
1764	}
1765	else
1766	{
1767	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1768	PVM pVM = pPool->CTX_SUFF(pVM);
1769	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1770	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1771	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1772	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1773	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1774	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1775	pPool->pszAccessHandler);
1776	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1777	* the heap size should suffice. */
1778	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1779	Assert(!(VMMGetCpu(pVM)->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1780	}
1781	pPage->fMonitored = true;
1782	return rc;
1783	}
1784
1785
1786	/**
1787	* Disables write monitoring of a guest page.
1788	*
1789	* @returns VBox status code.
1790	* @retval VINF_SUCCESS on success.
1791	* @param pPool The pool.
1792	* @param pPage The cached page.
1793	*/
1794	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1795	{
1796	/*
1797	* Filter out the relevant kinds.
1798	*/
1799	switch (pPage->enmKind)
1800	{
1801	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1802	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1803	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1804	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1805	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1806	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1807	case PGMPOOLKIND_64BIT_PML4:
1808	case PGMPOOLKIND_32BIT_PD:
1809	case PGMPOOLKIND_PAE_PDPT:
1810	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1811	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1812	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1813	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1814	break;
1815
1816	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1817	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1818	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1819	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1820	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1821	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1822	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1823	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1824	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1825	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1826	case PGMPOOLKIND_ROOT_NESTED:
1827	case PGMPOOLKIND_PAE_PD_PHYS:
1828	case PGMPOOLKIND_PAE_PDPT_PHYS:
1829	case PGMPOOLKIND_32BIT_PD_PHYS:
1830	/* Nothing to monitor here. */
1831	return VINF_SUCCESS;
1832
1833	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1834	break;
1835	#endif
1836	default:
1837	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1838	}
1839
1840	/*
1841	* Remove the page from the monitored list or uninstall it if last.
1842	*/
1843	const PVM pVM = pPool->CTX_SUFF(pVM);
1844	int rc;
1845	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1846	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1847	{
1848	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1849	{
1850	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1851	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1852	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1853	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1854	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1855	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1856	pPool->pszAccessHandler);
1857	AssertFatalRCSuccess(rc);
1858	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1859	}
1860	else
1861	{
1862	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1863	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1864	{
1865	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1866	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1867	}
1868	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1869	rc = VINF_SUCCESS;
1870	}
1871	}
1872	else
1873	{
1874	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1875	AssertFatalRC(rc);
1876	#ifdef VBOX_STRICT
1877	PVMCPU pVCpu = VMMGetCpu(pVM);
1878	#endif
1879	AssertMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
1880	("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
1881	}
1882	pPage->fMonitored = false;
1883
1884	/*
1885	* Remove it from the list of modified pages (if in it).
1886	*/
1887	pgmPoolMonitorModifiedRemove(pPool, pPage);
1888
1889	return rc;
1890	}
1891
1892
1893	/**
1894	* Inserts the page into the list of modified pages.
1895	*
1896	* @param pPool The pool.
1897	* @param pPage The page.
1898	*/
1899	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1900	{
1901	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1902	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1903	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1904	&& pPool->iModifiedHead != pPage->idx,
1905	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1906	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1907	pPool->iModifiedHead, pPool->cModifiedPages));
1908
1909	pPage->iModifiedNext = pPool->iModifiedHead;
1910	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1911	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1912	pPool->iModifiedHead = pPage->idx;
1913	pPool->cModifiedPages++;
1914	#ifdef VBOX_WITH_STATISTICS
1915	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1916	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1917	#endif
1918	}
1919
1920
1921	/**
1922	* Removes the page from the list of modified pages and resets the
1923	* moficiation counter.
1924	*
1925	* @param pPool The pool.
1926	* @param pPage The page which is believed to be in the list of modified pages.
1927	*/
1928	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1929	{
1930	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1931	if (pPool->iModifiedHead == pPage->idx)
1932	{
1933	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1934	pPool->iModifiedHead = pPage->iModifiedNext;
1935	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1936	{
1937	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1938	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1939	}
1940	pPool->cModifiedPages--;
1941	}
1942	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1943	{
1944	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1945	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1946	{
1947	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1948	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1949	}
1950	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1951	pPool->cModifiedPages--;
1952	}
1953	else
1954	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1955	pPage->cModifications = 0;
1956	}
1957
1958
1959	/**
1960	* Zaps the list of modified pages, resetting their modification counters in the process.
1961	*
1962	* @param pVM The VM handle.
1963	*/
1964	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1965	{
1966	pgmLock(pVM);
1967	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1968	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1969
1970	unsigned cPages = 0; NOREF(cPages);
1971	uint16_t idx = pPool->iModifiedHead;
1972	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1973	while (idx != NIL_PGMPOOL_IDX)
1974	{
1975	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1976	idx = pPage->iModifiedNext;
1977	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1978	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1979	pPage->cModifications = 0;
1980	Assert(++cPages);
1981	}
1982	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1983	pPool->cModifiedPages = 0;
1984	pgmUnlock(pVM);
1985	}
1986
1987
1988	#ifdef IN_RING3
1989	/**
1990	* Callback to clear all shadow pages and clear all modification counters.
1991	*
1992	* @returns VBox status code.
1993	* @param pVM The VM handle.
1994	* @param pVCpu The VMCPU for the EMT we're being called on. Unused.
1995	* @param pvUser Unused parameter.
1996	*
1997	* @remark Should only be used when monitoring is available, thus placed in
1998	* the PGMPOOL_WITH_MONITORING \#ifdef.
1999	*/
2000	DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, PVMCPU pVCpu, void *pvUser)
2001	{
2002	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2003	STAM_PROFILE_START(&pPool->StatClearAll, c);
2004	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
2005	NOREF(pvUser); NOREF(pVCpu);
2006
2007	pgmLock(pVM);
2008
2009	/*
2010	* Iterate all the pages until we've encountered all that in use.
2011	* This is simple but not quite optimal solution.
2012	*/
2013	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
2014	unsigned cLeft = pPool->cUsedPages;
2015	unsigned iPage = pPool->cCurPages;
2016	while (--iPage >= PGMPOOL_IDX_FIRST)
2017	{
2018	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2019	if (pPage->GCPhys != NIL_RTGCPHYS)
2020	{
2021	switch (pPage->enmKind)
2022	{
2023	/*
2024	* We only care about shadow page tables.
2025	*/
2026	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2027	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2028	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2029	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2030	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2031	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2032	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2033	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2034	{
2035	#ifdef PGMPOOL_WITH_USER_TRACKING
2036	if (pPage->cPresent)
2037	#endif
2038	{
2039	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
2040	STAM_PROFILE_START(&pPool->StatZeroPage, z);
2041	ASMMemZeroPage(pvShw);
2042	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
2043	#ifdef PGMPOOL_WITH_USER_TRACKING
2044	pPage->cPresent = 0;
2045	pPage->iFirstPresent = ~0;
2046	#endif
2047	}
2048	}
2049	/* fall thru */
2050
2051	default:
2052	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2053	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2054	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2055	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2056	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2057	pPage->cModifications = 0;
2058	break;
2059
2060	}
2061	if (!--cLeft)
2062	break;
2063	}
2064	}
2065
2066	/* swipe the special pages too. */
2067	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2068	{
2069	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2070	if (pPage->GCPhys != NIL_RTGCPHYS)
2071	{
2072	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2073	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2074	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2075	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2076	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2077	pPage->cModifications = 0;
2078	}
2079	}
2080
2081	#ifndef DEBUG_michael
2082	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2083	#endif
2084	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2085	pPool->cModifiedPages = 0;
2086
2087	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2088	/*
2089	* Clear all the GCPhys links and rebuild the phys ext free list.
2090	*/
2091	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2092	pRam;
2093	pRam = pRam->CTX_SUFF(pNext))
2094	{
2095	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2096	while (iPage-- > 0)
2097	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2098	}
2099
2100	pPool->iPhysExtFreeHead = 0;
2101	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2102	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2103	for (unsigned i = 0; i < cMaxPhysExts; i++)
2104	{
2105	paPhysExts[i].iNext = i + 1;
2106	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2107	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2108	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2109	}
2110	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2111	#endif
2112
2113	/* Clear the PGM_SYNC_CLEAR_PGM_POOL flag on all VCPUs to prevent redundant flushes. */
2114	for (unsigned idCpu = 0; idCpu < pVM->cCPUs; idCpu++)
2115	{
2116	PVMCPU pVCpu = &pVM->aCpus[idCpu];
2117
2118	pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2119	}
2120
2121	pPool->cPresent = 0;
2122	pgmUnlock(pVM);
2123	PGM_INVL_ALL_VCPU_TLBS(pVM);
2124	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2125	return VINF_SUCCESS;
2126	}
2127	#endif /* IN_RING3 */
2128
2129
2130	/**
2131	* Handle SyncCR3 pool tasks
2132	*
2133	* @returns VBox status code.
2134	* @retval VINF_SUCCESS if successfully added.
2135	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2136	* @param pVCpu The VMCPU handle.
2137	* @remark Should only be used when monitoring is available, thus placed in
2138	* the PGMPOOL_WITH_MONITORING #ifdef.
2139	*/
2140	int pgmPoolSyncCR3(PVMCPU pVCpu)
2141	{
2142	PVM pVM = pVCpu->CTX_SUFF(pVM);
2143	LogFlow(("pgmPoolSyncCR3\n"));
2144
2145	/*
2146	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2147	* Occasionally we will have to clear all the shadow page tables because we wanted
2148	* to monitor a page which was mapped by too many shadowed page tables. This operation
2149	* sometimes refered to as a 'lightweight flush'.
2150	*/
2151	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2152	if (ASMBitTestAndClear(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_CLEAR_PGM_POOL_BIT))
2153	{
2154	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmPoolClearAll, NULL);
2155	AssertRC(rc);
2156	}
2157	# else /* !IN_RING3 */
2158	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2159	{
2160	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2161	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2162	return VINF_PGM_SYNC_CR3;
2163	}
2164	# endif /* !IN_RING3 */
2165	else
2166	pgmPoolMonitorModifiedClearAll(pVM);
2167
2168	return VINF_SUCCESS;
2169	}
2170
2171	#endif /* PGMPOOL_WITH_MONITORING */
2172	#ifdef PGMPOOL_WITH_USER_TRACKING
2173
2174	/**
2175	* Frees up at least one user entry.
2176	*
2177	* @returns VBox status code.
2178	* @retval VINF_SUCCESS if successfully added.
2179	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2180	* @param pPool The pool.
2181	* @param iUser The user index.
2182	*/
2183	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2184	{
2185	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2186	#ifdef PGMPOOL_WITH_CACHE
2187	/*
2188	* Just free cached pages in a braindead fashion.
2189	*/
2190	/** @todo walk the age list backwards and free the first with usage. */
2191	int rc = VINF_SUCCESS;
2192	do
2193	{
2194	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2195	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2196	rc = rc2;
2197	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2198	return rc;
2199	#else
2200	/*
2201	* Lazy approach.
2202	*/
2203	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2204	AssertCompileFailed();
2205	Assert(!CPUMIsGuestInLongMode(pVM));
2206	pgmPoolFlushAllInt(pPool);
2207	return VERR_PGM_POOL_FLUSHED;
2208	#endif
2209	}
2210
2211
2212	/**
2213	* Inserts a page into the cache.
2214	*
2215	* This will create user node for the page, insert it into the GCPhys
2216	* hash, and insert it into the age list.
2217	*
2218	* @returns VBox status code.
2219	* @retval VINF_SUCCESS if successfully added.
2220	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2221	* @param pPool The pool.
2222	* @param pPage The cached page.
2223	* @param GCPhys The GC physical address of the page we're gonna shadow.
2224	* @param iUser The user index.
2225	* @param iUserTable The user table index.
2226	*/
2227	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2228	{
2229	int rc = VINF_SUCCESS;
2230	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2231
2232	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2233
2234	#ifdef VBOX_STRICT
2235	/*
2236	* Check that the entry doesn't already exists.
2237	*/
2238	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2239	{
2240	uint16_t i = pPage->iUserHead;
2241	do
2242	{
2243	Assert(i < pPool->cMaxUsers);
2244	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2245	i = paUsers[i].iNext;
2246	} while (i != NIL_PGMPOOL_USER_INDEX);
2247	}
2248	#endif
2249
2250	/*
2251	* Find free a user node.
2252	*/
2253	uint16_t i = pPool->iUserFreeHead;
2254	if (i == NIL_PGMPOOL_USER_INDEX)
2255	{
2256	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2257	if (RT_FAILURE(rc))
2258	return rc;
2259	i = pPool->iUserFreeHead;
2260	}
2261
2262	/*
2263	* Unlink the user node from the free list,
2264	* initialize and insert it into the user list.
2265	*/
2266	pPool->iUserFreeHead = paUsers[i].iNext;
2267	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2268	paUsers[i].iUser = iUser;
2269	paUsers[i].iUserTable = iUserTable;
2270	pPage->iUserHead = i;
2271
2272	/*
2273	* Insert into cache and enable monitoring of the guest page if enabled.
2274	*
2275	* Until we implement caching of all levels, including the CR3 one, we'll
2276	* have to make sure we don't try monitor & cache any recursive reuse of
2277	* a monitored CR3 page. Because all windows versions are doing this we'll
2278	* have to be able to do combined access monitoring, CR3 + PT and
2279	* PD + PT (guest PAE).
2280	*
2281	* Update:
2282	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2283	*/
2284	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2285	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2286	const bool fCanBeMonitored = true;
2287	# else
2288	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2289	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2290	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2291	# endif
2292	# ifdef PGMPOOL_WITH_CACHE
2293	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2294	# endif
2295	if (fCanBeMonitored)
2296	{
2297	# ifdef PGMPOOL_WITH_MONITORING
2298	rc = pgmPoolMonitorInsert(pPool, pPage);
2299	AssertRC(rc);
2300	}
2301	# endif
2302	#endif /* PGMPOOL_WITH_MONITORING */
2303	return rc;
2304	}
2305
2306
2307	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2308	/**
2309	* Adds a user reference to a page.
2310	*
2311	* This will move the page to the head of the
2312	*
2313	* @returns VBox status code.
2314	* @retval VINF_SUCCESS if successfully added.
2315	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2316	* @param pPool The pool.
2317	* @param pPage The cached page.
2318	* @param iUser The user index.
2319	* @param iUserTable The user table.
2320	*/
2321	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2322	{
2323	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2324
2325	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2326
2327	# ifdef VBOX_STRICT
2328	/*
2329	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2330	*/
2331	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2332	{
2333	uint16_t i = pPage->iUserHead;
2334	do
2335	{
2336	Assert(i < pPool->cMaxUsers);
2337	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2338	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2339	i = paUsers[i].iNext;
2340	} while (i != NIL_PGMPOOL_USER_INDEX);
2341	}
2342	# endif
2343
2344	/*
2345	* Allocate a user node.
2346	*/
2347	uint16_t i = pPool->iUserFreeHead;
2348	if (i == NIL_PGMPOOL_USER_INDEX)
2349	{
2350	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2351	if (RT_FAILURE(rc))
2352	return rc;
2353	i = pPool->iUserFreeHead;
2354	}
2355	pPool->iUserFreeHead = paUsers[i].iNext;
2356
2357	/*
2358	* Initialize the user node and insert it.
2359	*/
2360	paUsers[i].iNext = pPage->iUserHead;
2361	paUsers[i].iUser = iUser;
2362	paUsers[i].iUserTable = iUserTable;
2363	pPage->iUserHead = i;
2364
2365	# ifdef PGMPOOL_WITH_CACHE
2366	/*
2367	* Tell the cache to update its replacement stats for this page.
2368	*/
2369	pgmPoolCacheUsed(pPool, pPage);
2370	# endif
2371	return VINF_SUCCESS;
2372	}
2373	# endif /* PGMPOOL_WITH_CACHE */
2374
2375
2376	/**
2377	* Frees a user record associated with a page.
2378	*
2379	* This does not clear the entry in the user table, it simply replaces the
2380	* user record to the chain of free records.
2381	*
2382	* @param pPool The pool.
2383	* @param HCPhys The HC physical address of the shadow page.
2384	* @param iUser The shadow page pool index of the user table.
2385	* @param iUserTable The index into the user table (shadowed).
2386	*/
2387	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2388	{
2389	/*
2390	* Unlink and free the specified user entry.
2391	*/
2392	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2393
2394	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2395	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2396	uint16_t i = pPage->iUserHead;
2397	if ( i != NIL_PGMPOOL_USER_INDEX
2398	&& paUsers[i].iUser == iUser
2399	&& paUsers[i].iUserTable == iUserTable)
2400	{
2401	pPage->iUserHead = paUsers[i].iNext;
2402
2403	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2404	paUsers[i].iNext = pPool->iUserFreeHead;
2405	pPool->iUserFreeHead = i;
2406	return;
2407	}
2408
2409	/* General: Linear search. */
2410	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2411	while (i != NIL_PGMPOOL_USER_INDEX)
2412	{
2413	if ( paUsers[i].iUser == iUser
2414	&& paUsers[i].iUserTable == iUserTable)
2415	{
2416	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2417	paUsers[iPrev].iNext = paUsers[i].iNext;
2418	else
2419	pPage->iUserHead = paUsers[i].iNext;
2420
2421	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2422	paUsers[i].iNext = pPool->iUserFreeHead;
2423	pPool->iUserFreeHead = i;
2424	return;
2425	}
2426	iPrev = i;
2427	i = paUsers[i].iNext;
2428	}
2429
2430	/* Fatal: didn't find it */
2431	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2432	iUser, iUserTable, pPage->GCPhys));
2433	}
2434
2435
2436	/**
2437	* Gets the entry size of a shadow table.
2438	*
2439	* @param enmKind The kind of page.
2440	*
2441	* @returns The size of the entry in bytes. That is, 4 or 8.
2442	* @returns If the kind is not for a table, an assertion is raised and 0 is
2443	* returned.
2444	*/
2445	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2446	{
2447	switch (enmKind)
2448	{
2449	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2450	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2451	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2452	case PGMPOOLKIND_32BIT_PD:
2453	case PGMPOOLKIND_32BIT_PD_PHYS:
2454	return 4;
2455
2456	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2457	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2458	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2459	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2460	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2461	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2462	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2463	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2464	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2465	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2466	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2467	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2468	case PGMPOOLKIND_64BIT_PML4:
2469	case PGMPOOLKIND_PAE_PDPT:
2470	case PGMPOOLKIND_ROOT_NESTED:
2471	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2472	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2473	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2474	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2475	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2476	case PGMPOOLKIND_PAE_PD_PHYS:
2477	case PGMPOOLKIND_PAE_PDPT_PHYS:
2478	return 8;
2479
2480	default:
2481	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2482	}
2483	}
2484
2485
2486	/**
2487	* Gets the entry size of a guest table.
2488	*
2489	* @param enmKind The kind of page.
2490	*
2491	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2492	* @returns If the kind is not for a table, an assertion is raised and 0 is
2493	* returned.
2494	*/
2495	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2496	{
2497	switch (enmKind)
2498	{
2499	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2500	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2501	case PGMPOOLKIND_32BIT_PD:
2502	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2503	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2504	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2505	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2506	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2507	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2508	return 4;
2509
2510	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2511	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2512	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2513	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2514	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2515	case PGMPOOLKIND_64BIT_PML4:
2516	case PGMPOOLKIND_PAE_PDPT:
2517	return 8;
2518
2519	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2520	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2521	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2522	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2523	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2524	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2525	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2526	case PGMPOOLKIND_ROOT_NESTED:
2527	case PGMPOOLKIND_PAE_PD_PHYS:
2528	case PGMPOOLKIND_PAE_PDPT_PHYS:
2529	case PGMPOOLKIND_32BIT_PD_PHYS:
2530	/** @todo can we return 0? (nobody is calling this...) */
2531	AssertFailed();
2532	return 0;
2533
2534	default:
2535	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2536	}
2537	}
2538
2539	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2540
2541	/**
2542	* Scans one shadow page table for mappings of a physical page.
2543	*
2544	* @param pVM The VM handle.
2545	* @param pPhysPage The guest page in question.
2546	* @param iShw The shadow page table.
2547	* @param cRefs The number of references made in that PT.
2548	*/
2549	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2550	{
2551	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2552	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2553
2554	/*
2555	* Assert sanity.
2556	*/
2557	Assert(cRefs == 1);
2558	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2559	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2560
2561	/*
2562	* Then, clear the actual mappings to the page in the shadow PT.
2563	*/
2564	switch (pPage->enmKind)
2565	{
2566	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2567	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2568	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2569	{
2570	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2571	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2572	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2573	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2574	{
2575	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2576	pPT->a[i].u = 0;
2577	cRefs--;
2578	if (!cRefs)
2579	return;
2580	}
2581	#ifdef LOG_ENABLED
2582	Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2583	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2584	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2585	{
2586	Log(("i=%d cRefs=%d\n", i, cRefs--));
2587	}
2588	#endif
2589	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2590	break;
2591	}
2592
2593	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2594	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2595	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2596	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2597	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2598	{
2599	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2600	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2601	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2602	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2603	{
2604	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2605	pPT->a[i].u = 0;
2606	cRefs--;
2607	if (!cRefs)
2608	return;
2609	}
2610	#ifdef LOG_ENABLED
2611	Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2612	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2613	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2614	{
2615	Log(("i=%d cRefs=%d\n", i, cRefs--));
2616	}
2617	#endif
2618	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2619	break;
2620	}
2621
2622	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2623	{
2624	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2625	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2626	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2627	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2628	{
2629	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2630	pPT->a[i].u = 0;
2631	cRefs--;
2632	if (!cRefs)
2633	return;
2634	}
2635	#ifdef LOG_ENABLED
2636	Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2637	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2638	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2639	{
2640	Log(("i=%d cRefs=%d\n", i, cRefs--));
2641	}
2642	#endif
2643	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2644	break;
2645	}
2646
2647	default:
2648	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2649	}
2650	}
2651
2652
2653	/**
2654	* Scans one shadow page table for mappings of a physical page.
2655	*
2656	* @param pVM The VM handle.
2657	* @param pPhysPage The guest page in question.
2658	* @param iShw The shadow page table.
2659	* @param cRefs The number of references made in that PT.
2660	*/
2661	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2662	{
2663	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2664	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2665	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2666	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2667	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2668	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2669	}
2670
2671
2672	/**
2673	* Flushes a list of shadow page tables mapping the same physical page.
2674	*
2675	* @param pVM The VM handle.
2676	* @param pPhysPage The guest page in question.
2677	* @param iPhysExt The physical cross reference extent list to flush.
2678	*/
2679	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2680	{
2681	Assert(PGMIsLockOwner(pVM));
2682	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2683	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2684	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2685
2686	const uint16_t iPhysExtStart = iPhysExt;
2687	PPGMPOOLPHYSEXT pPhysExt;
2688	do
2689	{
2690	Assert(iPhysExt < pPool->cMaxPhysExts);
2691	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2692	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2693	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2694	{
2695	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2696	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2697	}
2698
2699	/* next */
2700	iPhysExt = pPhysExt->iNext;
2701	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2702
2703	/* insert the list into the free list and clear the ram range entry. */
2704	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2705	pPool->iPhysExtFreeHead = iPhysExtStart;
2706	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2707
2708	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2709	}
2710
2711	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2712
2713	/**
2714	* Flushes all shadow page table mappings of the given guest page.
2715	*
2716	* This is typically called when the host page backing the guest one has been
2717	* replaced or when the page protection was changed due to an access handler.
2718	*
2719	* @returns VBox status code.
2720	* @retval VINF_SUCCESS if all references has been successfully cleared.
2721	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2722	* pool cleaning. FF and sync flags are set.
2723	*
2724	* @param pVM The VM handle.
2725	* @param pPhysPage The guest page in question.
2726	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2727	* flushed, it is NOT touched if this isn't necessary.
2728	* The caller MUST initialized this to @a false.
2729	*/
2730	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2731	{
2732	PVMCPU pVCpu = VMMGetCpu(pVM);
2733	pgmLock(pVM);
2734	int rc = VINF_SUCCESS;
2735	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2736	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2737	if (u16)
2738	{
2739	/*
2740	* The zero page is currently screwing up the tracking and we'll
2741	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2742	* is defined, zero pages won't normally be mapped. Some kind of solution
2743	* will be needed for this problem of course, but it will have to wait...
2744	*/
2745	if (PGM_PAGE_IS_ZERO(pPhysPage))
2746	rc = VINF_PGM_GCPHYS_ALIASED;
2747	else
2748	{
2749	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2750	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2751	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2752	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2753	# endif
2754
2755	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2756	pgmPoolTrackFlushGCPhysPT(pVM,
2757	pPhysPage,
2758	PGMPOOL_TD_GET_IDX(u16),
2759	PGMPOOL_TD_GET_CREFS(u16));
2760	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2761	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2762	else
2763	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2764	*pfFlushTLBs = true;
2765
2766	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2767	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2768	# endif
2769	}
2770	}
2771
2772	#elif defined(PGMPOOL_WITH_CACHE)
2773	if (PGM_PAGE_IS_ZERO(pPhysPage))
2774	rc = VINF_PGM_GCPHYS_ALIASED;
2775	else
2776	{
2777	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2778	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2779	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2780	# endif
2781	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2782	if (rc == VINF_SUCCESS)
2783	*pfFlushTLBs = true;
2784	}
2785
2786	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2787	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2788	# endif
2789
2790	#else
2791	rc = VINF_PGM_GCPHYS_ALIASED;
2792	#endif
2793
2794	if (rc == VINF_PGM_GCPHYS_ALIASED)
2795	{
2796	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
2797	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2798	rc = VINF_PGM_SYNC_CR3;
2799	}
2800	pgmUnlock(pVM);
2801	return rc;
2802	}
2803
2804
2805	/**
2806	* Scans all shadow page tables for mappings of a physical page.
2807	*
2808	* This may be slow, but it's most likely more efficient than cleaning
2809	* out the entire page pool / cache.
2810	*
2811	* @returns VBox status code.
2812	* @retval VINF_SUCCESS if all references has been successfully cleared.
2813	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2814	* a page pool cleaning.
2815	*
2816	* @param pVM The VM handle.
2817	* @param pPhysPage The guest page in question.
2818	*/
2819	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2820	{
2821	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2822	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2823	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2824	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2825
2826	#if 1
2827	/*
2828	* There is a limit to what makes sense.
2829	*/
2830	if (pPool->cPresent > 1024)
2831	{
2832	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2833	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2834	return VINF_PGM_GCPHYS_ALIASED;
2835	}
2836	#endif
2837
2838	/*
2839	* Iterate all the pages until we've encountered all that in use.
2840	* This is simple but not quite optimal solution.
2841	*/
2842	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2843	const uint32_t u32 = u64;
2844	unsigned cLeft = pPool->cUsedPages;
2845	unsigned iPage = pPool->cCurPages;
2846	while (--iPage >= PGMPOOL_IDX_FIRST)
2847	{
2848	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2849	if (pPage->GCPhys != NIL_RTGCPHYS)
2850	{
2851	switch (pPage->enmKind)
2852	{
2853	/*
2854	* We only care about shadow page tables.
2855	*/
2856	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2857	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2858	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2859	{
2860	unsigned cPresent = pPage->cPresent;
2861	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2862	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2863	if (pPT->a[i].n.u1Present)
2864	{
2865	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2866	{
2867	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2868	pPT->a[i].u = 0;
2869	}
2870	if (!--cPresent)
2871	break;
2872	}
2873	break;
2874	}
2875
2876	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2877	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2878	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2879	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2880	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2881	{
2882	unsigned cPresent = pPage->cPresent;
2883	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2884	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2885	if (pPT->a[i].n.u1Present)
2886	{
2887	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2888	{
2889	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2890	pPT->a[i].u = 0;
2891	}
2892	if (!--cPresent)
2893	break;
2894	}
2895	break;
2896	}
2897	}
2898	if (!--cLeft)
2899	break;
2900	}
2901	}
2902
2903	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2904	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2905	return VINF_SUCCESS;
2906	}
2907
2908
2909	/**
2910	* Clears the user entry in a user table.
2911	*
2912	* This is used to remove all references to a page when flushing it.
2913	*/
2914	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2915	{
2916	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2917	Assert(pUser->iUser < pPool->cCurPages);
2918	uint32_t iUserTable = pUser->iUserTable;
2919
2920	/*
2921	* Map the user page.
2922	*/
2923	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2924	union
2925	{
2926	uint64_t *pau64;
2927	uint32_t *pau32;
2928	} u;
2929	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2930
2931	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2932
2933	/* Safety precaution in case we change the paging for other modes too in the future. */
2934	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2935
2936	#ifdef VBOX_STRICT
2937	/*
2938	* Some sanity checks.
2939	*/
2940	switch (pUserPage->enmKind)
2941	{
2942	case PGMPOOLKIND_32BIT_PD:
2943	case PGMPOOLKIND_32BIT_PD_PHYS:
2944	Assert(iUserTable < X86_PG_ENTRIES);
2945	break;
2946	case PGMPOOLKIND_PAE_PDPT:
2947	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2948	case PGMPOOLKIND_PAE_PDPT_PHYS:
2949	Assert(iUserTable < 4);
2950	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2951	break;
2952	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2953	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2954	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2955	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2956	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2957	case PGMPOOLKIND_PAE_PD_PHYS:
2958	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2959	break;
2960	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2961	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2962	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2963	break;
2964	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2965	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2966	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2967	break;
2968	case PGMPOOLKIND_64BIT_PML4:
2969	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2970	/* GCPhys >> PAGE_SHIFT is the index here */
2971	break;
2972	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2973	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2974	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2975	break;
2976
2977	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2978	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2979	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2980	break;
2981
2982	case PGMPOOLKIND_ROOT_NESTED:
2983	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2984	break;
2985
2986	default:
2987	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2988	break;
2989	}
2990	#endif /* VBOX_STRICT */
2991
2992	/*
2993	* Clear the entry in the user page.
2994	*/
2995	switch (pUserPage->enmKind)
2996	{
2997	/* 32-bit entries */
2998	case PGMPOOLKIND_32BIT_PD:
2999	case PGMPOOLKIND_32BIT_PD_PHYS:
3000	u.pau32[iUserTable] = 0;
3001	break;
3002
3003	/* 64-bit entries */
3004	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3005	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3006	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3007	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3008	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3009	#if defined(IN_RC)
3010	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
3011	* non-present PDPT will continue to cause page faults.
3012	*/
3013	ASMReloadCR3();
3014	#endif
3015	/* no break */
3016	case PGMPOOLKIND_PAE_PD_PHYS:
3017	case PGMPOOLKIND_PAE_PDPT_PHYS:
3018	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3019	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3020	case PGMPOOLKIND_64BIT_PML4:
3021	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3022	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3023	case PGMPOOLKIND_PAE_PDPT:
3024	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3025	case PGMPOOLKIND_ROOT_NESTED:
3026	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3027	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3028	u.pau64[iUserTable] = 0;
3029	break;
3030
3031	default:
3032	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3033	}
3034	}
3035
3036
3037	/**
3038	* Clears all users of a page.
3039	*/
3040	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3041	{
3042	/*
3043	* Free all the user records.
3044	*/
3045	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3046
3047	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3048	uint16_t i = pPage->iUserHead;
3049	while (i != NIL_PGMPOOL_USER_INDEX)
3050	{
3051	/* Clear enter in user table. */
3052	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3053
3054	/* Free it. */
3055	const uint16_t iNext = paUsers[i].iNext;
3056	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3057	paUsers[i].iNext = pPool->iUserFreeHead;
3058	pPool->iUserFreeHead = i;
3059
3060	/* Next. */
3061	i = iNext;
3062	}
3063	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3064	}
3065
3066	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3067
3068	/**
3069	* Allocates a new physical cross reference extent.
3070	*
3071	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3072	* @param pVM The VM handle.
3073	* @param piPhysExt Where to store the phys ext index.
3074	*/
3075	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3076	{
3077	Assert(PGMIsLockOwner(pVM));
3078	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3079	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3080	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3081	{
3082	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3083	return NULL;
3084	}
3085	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3086	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3087	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3088	*piPhysExt = iPhysExt;
3089	return pPhysExt;
3090	}
3091
3092
3093	/**
3094	* Frees a physical cross reference extent.
3095	*
3096	* @param pVM The VM handle.
3097	* @param iPhysExt The extent to free.
3098	*/
3099	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3100	{
3101	Assert(PGMIsLockOwner(pVM));
3102	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3103	Assert(iPhysExt < pPool->cMaxPhysExts);
3104	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3105	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3106	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3107	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3108	pPool->iPhysExtFreeHead = iPhysExt;
3109	}
3110
3111
3112	/**
3113	* Frees a physical cross reference extent.
3114	*
3115	* @param pVM The VM handle.
3116	* @param iPhysExt The extent to free.
3117	*/
3118	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3119	{
3120	Assert(PGMIsLockOwner(pVM));
3121	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3122
3123	const uint16_t iPhysExtStart = iPhysExt;
3124	PPGMPOOLPHYSEXT pPhysExt;
3125	do
3126	{
3127	Assert(iPhysExt < pPool->cMaxPhysExts);
3128	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3129	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3130	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3131
3132	/* next */
3133	iPhysExt = pPhysExt->iNext;
3134	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3135
3136	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3137	pPool->iPhysExtFreeHead = iPhysExtStart;
3138	}
3139
3140
3141	/**
3142	* Insert a reference into a list of physical cross reference extents.
3143	*
3144	* @returns The new tracking data for PGMPAGE.
3145	*
3146	* @param pVM The VM handle.
3147	* @param iPhysExt The physical extent index of the list head.
3148	* @param iShwPT The shadow page table index.
3149	*
3150	*/
3151	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3152	{
3153	Assert(PGMIsLockOwner(pVM));
3154	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3155	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3156
3157	/* special common case. */
3158	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3159	{
3160	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3161	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3162	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d}\n", iPhysExt, iShwPT));
3163	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3164	}
3165
3166	/* general treatment. */
3167	const uint16_t iPhysExtStart = iPhysExt;
3168	unsigned cMax = 15;
3169	for (;;)
3170	{
3171	Assert(iPhysExt < pPool->cMaxPhysExts);
3172	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3173	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3174	{
3175	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3176	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3177	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3178	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3179	}
3180	if (!--cMax)
3181	{
3182	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3183	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3184	LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3185	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3186	}
3187	}
3188
3189	/* add another extent to the list. */
3190	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3191	if (!pNew)
3192	{
3193	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3194	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3195	LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3196	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3197	}
3198	pNew->iNext = iPhysExtStart;
3199	pNew->aidx[0] = iShwPT;
3200	LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3201	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3202	}
3203
3204
3205	/**
3206	* Add a reference to guest physical page where extents are in use.
3207	*
3208	* @returns The new tracking data for PGMPAGE.
3209	*
3210	* @param pVM The VM handle.
3211	* @param u16 The ram range flags (top 16-bits).
3212	* @param iShwPT The shadow page table index.
3213	*/
3214	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3215	{
3216	pgmLock(pVM);
3217	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3218	{
3219	/*
3220	* Convert to extent list.
3221	*/
3222	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3223	uint16_t iPhysExt;
3224	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3225	if (pPhysExt)
3226	{
3227	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3228	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3229	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3230	pPhysExt->aidx[1] = iShwPT;
3231	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3232	}
3233	else
3234	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3235	}
3236	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3237	{
3238	/*
3239	* Insert into the extent list.
3240	*/
3241	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3242	}
3243	else
3244	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3245	pgmUnlock(pVM);
3246	return u16;
3247	}
3248
3249
3250	/**
3251	* Clear references to guest physical memory.
3252	*
3253	* @param pPool The pool.
3254	* @param pPage The page.
3255	* @param pPhysPage Pointer to the aPages entry in the ram range.
3256	*/
3257	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3258	{
3259	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3260	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3261
3262	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3263	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3264	{
3265	PVM pVM = pPool->CTX_SUFF(pVM);
3266	pgmLock(pVM);
3267
3268	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3269	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3270	do
3271	{
3272	Assert(iPhysExt < pPool->cMaxPhysExts);
3273
3274	/*
3275	* Look for the shadow page and check if it's all freed.
3276	*/
3277	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3278	{
3279	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3280	{
3281	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3282
3283	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3284	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3285	{
3286	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3287	pgmUnlock(pVM);
3288	return;
3289	}
3290
3291	/* we can free the node. */
3292	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3293	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3294	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3295	{
3296	/* lonely node */
3297	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3298	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3299	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3300	}
3301	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3302	{
3303	/* head */
3304	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3305	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3306	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3307	}
3308	else
3309	{
3310	/* in list */
3311	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3312	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3313	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3314	}
3315	iPhysExt = iPhysExtNext;
3316	pgmUnlock(pVM);
3317	return;
3318	}
3319	}
3320
3321	/* next */
3322	iPhysExtPrev = iPhysExt;
3323	iPhysExt = paPhysExts[iPhysExt].iNext;
3324	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3325
3326	pgmUnlock(pVM);
3327	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3328	}
3329	else /* nothing to do */
3330	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3331	}
3332
3333
3334	/**
3335	* Clear references to guest physical memory.
3336	*
3337	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3338	* is assumed to be correct, so the linear search can be skipped and we can assert
3339	* at an earlier point.
3340	*
3341	* @param pPool The pool.
3342	* @param pPage The page.
3343	* @param HCPhys The host physical address corresponding to the guest page.
3344	* @param GCPhys The guest physical address corresponding to HCPhys.
3345	*/
3346	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3347	{
3348	/*
3349	* Walk range list.
3350	*/
3351	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3352	while (pRam)
3353	{
3354	RTGCPHYS off = GCPhys - pRam->GCPhys;
3355	if (off < pRam->cb)
3356	{
3357	/* does it match? */
3358	const unsigned iPage = off >> PAGE_SHIFT;
3359	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3360	#ifdef LOG_ENABLED
3361	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3362	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3363	#endif
3364	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3365	{
3366	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3367	return;
3368	}
3369	break;
3370	}
3371	pRam = pRam->CTX_SUFF(pNext);
3372	}
3373	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3374	}
3375
3376
3377	/**
3378	* Clear references to guest physical memory.
3379	*
3380	* @param pPool The pool.
3381	* @param pPage The page.
3382	* @param HCPhys The host physical address corresponding to the guest page.
3383	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3384	*/
3385	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3386	{
3387	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3388
3389	/*
3390	* Walk range list.
3391	*/
3392	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3393	while (pRam)
3394	{
3395	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3396	if (off < pRam->cb)
3397	{
3398	/* does it match? */
3399	const unsigned iPage = off >> PAGE_SHIFT;
3400	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3401	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3402	{
3403	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3404	return;
3405	}
3406	break;
3407	}
3408	pRam = pRam->CTX_SUFF(pNext);
3409	}
3410
3411	/*
3412	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3413	*/
3414	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3415	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3416	while (pRam)
3417	{
3418	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3419	while (iPage-- > 0)
3420	{
3421	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3422	{
3423	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3424	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3425	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3426	return;
3427	}
3428	}
3429	pRam = pRam->CTX_SUFF(pNext);
3430	}
3431
3432	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3433	}
3434
3435
3436	/**
3437	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3438	*
3439	* @param pPool The pool.
3440	* @param pPage The page.
3441	* @param pShwPT The shadow page table (mapping of the page).
3442	* @param pGstPT The guest page table.
3443	*/
3444	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3445	{
3446	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3447	if (pShwPT->a[i].n.u1Present)
3448	{
3449	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3450	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3451	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3452	if (!--pPage->cPresent)
3453	break;
3454	}
3455	}
3456
3457
3458	/**
3459	* Clear references to guest physical memory in a PAE / 32-bit page table.
3460	*
3461	* @param pPool The pool.
3462	* @param pPage The page.
3463	* @param pShwPT The shadow page table (mapping of the page).
3464	* @param pGstPT The guest page table (just a half one).
3465	*/
3466	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3467	{
3468	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3469	if (pShwPT->a[i].n.u1Present)
3470	{
3471	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3472	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3473	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3474	}
3475	}
3476
3477
3478	/**
3479	* Clear references to guest physical memory in a PAE / PAE page table.
3480	*
3481	* @param pPool The pool.
3482	* @param pPage The page.
3483	* @param pShwPT The shadow page table (mapping of the page).
3484	* @param pGstPT The guest page table.
3485	*/
3486	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3487	{
3488	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3489	if (pShwPT->a[i].n.u1Present)
3490	{
3491	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3492	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3493	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3494	}
3495	}
3496
3497
3498	/**
3499	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3500	*
3501	* @param pPool The pool.
3502	* @param pPage The page.
3503	* @param pShwPT The shadow page table (mapping of the page).
3504	*/
3505	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3506	{
3507	RTGCPHYS GCPhys = pPage->GCPhys;
3508	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3509	if (pShwPT->a[i].n.u1Present)
3510	{
3511	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3512	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3513	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3514	}
3515	}
3516
3517
3518	/**
3519	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3520	*
3521	* @param pPool The pool.
3522	* @param pPage The page.
3523	* @param pShwPT The shadow page table (mapping of the page).
3524	*/
3525	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3526	{
3527	RTGCPHYS GCPhys = pPage->GCPhys;
3528	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3529	if (pShwPT->a[i].n.u1Present)
3530	{
3531	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3532	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3533	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3534	}
3535	}
3536
3537	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3538
3539
3540	/**
3541	* Clear references to shadowed pages in a 32 bits page directory.
3542	*
3543	* @param pPool The pool.
3544	* @param pPage The page.
3545	* @param pShwPD The shadow page directory (mapping of the page).
3546	*/
3547	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3548	{
3549	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3550	{
3551	if ( pShwPD->a[i].n.u1Present
3552	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3553	)
3554	{
3555	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3556	if (pSubPage)
3557	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3558	else
3559	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3560	}
3561	}
3562	}
3563
3564	/**
3565	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3566	*
3567	* @param pPool The pool.
3568	* @param pPage The page.
3569	* @param pShwPD The shadow page directory (mapping of the page).
3570	*/
3571	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3572	{
3573	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3574	{
3575	if ( pShwPD->a[i].n.u1Present
3576	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3577	)
3578	{
3579	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3580	if (pSubPage)
3581	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3582	else
3583	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3584	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3585	}
3586	}
3587	}
3588
3589	/**
3590	* Clear references to shadowed pages in a PAE page directory pointer table.
3591	*
3592	* @param pPool The pool.
3593	* @param pPage The page.
3594	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3595	*/
3596	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3597	{
3598	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3599	{
3600	if ( pShwPDPT->a[i].n.u1Present
3601	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3602	)
3603	{
3604	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3605	if (pSubPage)
3606	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3607	else
3608	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3609	}
3610	}
3611	}
3612
3613
3614	/**
3615	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3616	*
3617	* @param pPool The pool.
3618	* @param pPage The page.
3619	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3620	*/
3621	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3622	{
3623	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3624	{
3625	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3626	if (pShwPDPT->a[i].n.u1Present)
3627	{
3628	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3629	if (pSubPage)
3630	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3631	else
3632	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3633	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3634	}
3635	}
3636	}
3637
3638
3639	/**
3640	* Clear references to shadowed pages in a 64-bit level 4 page table.
3641	*
3642	* @param pPool The pool.
3643	* @param pPage The page.
3644	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3645	*/
3646	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3647	{
3648	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3649	{
3650	if (pShwPML4->a[i].n.u1Present)
3651	{
3652	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3653	if (pSubPage)
3654	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3655	else
3656	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3657	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3658	}
3659	}
3660	}
3661
3662
3663	/**
3664	* Clear references to shadowed pages in an EPT page table.
3665	*
3666	* @param pPool The pool.
3667	* @param pPage The page.
3668	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3669	*/
3670	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3671	{
3672	RTGCPHYS GCPhys = pPage->GCPhys;
3673	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3674	if (pShwPT->a[i].n.u1Present)
3675	{
3676	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3677	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3678	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3679	}
3680	}
3681
3682
3683	/**
3684	* Clear references to shadowed pages in an EPT page directory.
3685	*
3686	* @param pPool The pool.
3687	* @param pPage The page.
3688	* @param pShwPD The shadow page directory (mapping of the page).
3689	*/
3690	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3691	{
3692	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3693	{
3694	if (pShwPD->a[i].n.u1Present)
3695	{
3696	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3697	if (pSubPage)
3698	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3699	else
3700	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3701	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3702	}
3703	}
3704	}
3705
3706
3707	/**
3708	* Clear references to shadowed pages in an EPT page directory pointer table.
3709	*
3710	* @param pPool The pool.
3711	* @param pPage The page.
3712	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3713	*/
3714	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3715	{
3716	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3717	{
3718	if (pShwPDPT->a[i].n.u1Present)
3719	{
3720	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3721	if (pSubPage)
3722	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3723	else
3724	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3725	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3726	}
3727	}
3728	}
3729
3730
3731	/**
3732	* Clears all references made by this page.
3733	*
3734	* This includes other shadow pages and GC physical addresses.
3735	*
3736	* @param pPool The pool.
3737	* @param pPage The page.
3738	*/
3739	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3740	{
3741	/*
3742	* Map the shadow page and take action according to the page kind.
3743	*/
3744	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3745	switch (pPage->enmKind)
3746	{
3747	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3748	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3749	{
3750	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3751	void *pvGst;
3752	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3753	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3754	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3755	break;
3756	}
3757
3758	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3759	{
3760	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3761	void *pvGst;
3762	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3763	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3764	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3765	break;
3766	}
3767
3768	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3769	{
3770	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3771	void *pvGst;
3772	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3773	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3774	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3775	break;
3776	}
3777
3778	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3779	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3780	{
3781	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3782	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3783	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3784	break;
3785	}
3786
3787	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3788	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3789	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3790	{
3791	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3792	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3793	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3794	break;
3795	}
3796
3797	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3798	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3799	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3800	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3801	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3802	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3803	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3804	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3805	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3806	break;
3807	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3808
3809	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3810	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3811	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3812	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3813	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3814	case PGMPOOLKIND_PAE_PD_PHYS:
3815	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3816	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3817	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3818	break;
3819
3820	case PGMPOOLKIND_32BIT_PD_PHYS:
3821	case PGMPOOLKIND_32BIT_PD:
3822	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3823	break;
3824
3825	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3826	case PGMPOOLKIND_PAE_PDPT:
3827	case PGMPOOLKIND_PAE_PDPT_PHYS:
3828	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3829	break;
3830
3831	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3832	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3833	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3834	break;
3835
3836	case PGMPOOLKIND_64BIT_PML4:
3837	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3838	break;
3839
3840	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3841	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3842	break;
3843
3844	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3845	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3846	break;
3847
3848	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3849	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3850	break;
3851
3852	default:
3853	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3854	}
3855
3856	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3857	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3858	ASMMemZeroPage(pvShw);
3859	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3860	pPage->fZeroed = true;
3861	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3862	}
3863	#endif /* PGMPOOL_WITH_USER_TRACKING */
3864
3865	/**
3866	* Flushes a pool page.
3867	*
3868	* This moves the page to the free list after removing all user references to it.
3869	*
3870	* @returns VBox status code.
3871	* @retval VINF_SUCCESS on success.
3872	* @param pPool The pool.
3873	* @param HCPhys The HC physical address of the shadow page.
3874	*/
3875	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3876	{
3877	PVM pVM = pPool->CTX_SUFF(pVM);
3878
3879	int rc = VINF_SUCCESS;
3880	STAM_PROFILE_START(&pPool->StatFlushPage, f);
3881	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
3882	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
3883
3884	/*
3885	* Quietly reject any attempts at flushing any of the special root pages.
3886	*/
3887	if (pPage->idx < PGMPOOL_IDX_FIRST)
3888	{
3889	AssertFailed(); /* can no longer happen */
3890	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3891	return VINF_SUCCESS;
3892	}
3893
3894	pgmLock(pVM);
3895
3896	/*
3897	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
3898	*/
3899	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
3900	{
3901	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
3902	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
3903	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
3904	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
3905	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3906	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
3907	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
3908	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
3909	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
3910	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
3911	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3912	pgmUnlock(pVM);
3913	return VINF_SUCCESS;
3914	}
3915
3916	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3917	/* Start a subset so we won't run out of mapping space. */
3918	PVMCPU pVCpu = VMMGetCpu(pVM);
3919	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3920	#endif
3921
3922	/*
3923	* Mark the page as being in need of a ASMMemZeroPage().
3924	*/
3925	pPage->fZeroed = false;
3926
3927	#ifdef PGMPOOL_WITH_USER_TRACKING
3928	/*
3929	* Clear the page.
3930	*/
3931	pgmPoolTrackClearPageUsers(pPool, pPage);
3932	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
3933	pgmPoolTrackDeref(pPool, pPage);
3934	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
3935	#endif
3936
3937	#ifdef PGMPOOL_WITH_CACHE
3938	/*
3939	* Flush it from the cache.
3940	*/
3941	pgmPoolCacheFlushPage(pPool, pPage);
3942	#endif /* PGMPOOL_WITH_CACHE */
3943
3944	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3945	/* Heavy stuff done. */
3946	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3947	#endif
3948
3949	#ifdef PGMPOOL_WITH_MONITORING
3950	/*
3951	* Deregistering the monitoring.
3952	*/
3953	if (pPage->fMonitored)
3954	rc = pgmPoolMonitorFlush(pPool, pPage);
3955	#endif
3956
3957	/*
3958	* Free the page.
3959	*/
3960	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
3961	pPage->iNext = pPool->iFreeHead;
3962	pPool->iFreeHead = pPage->idx;
3963	pPage->enmKind = PGMPOOLKIND_FREE;
3964	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
3965	pPage->GCPhys = NIL_RTGCPHYS;
3966	pPage->fReusedFlushPending = false;
3967
3968	pPool->cUsedPages--;
3969	pgmUnlock(pVM);
3970	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
3971	return rc;
3972	}
3973
3974
3975	/**
3976	* Frees a usage of a pool page.
3977	*
3978	* The caller is responsible to updating the user table so that it no longer
3979	* references the shadow page.
3980	*
3981	* @param pPool The pool.
3982	* @param HCPhys The HC physical address of the shadow page.
3983	* @param iUser The shadow page pool index of the user table.
3984	* @param iUserTable The index into the user table (shadowed).
3985	*/
3986	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
3987	{
3988	PVM pVM = pPool->CTX_SUFF(pVM);
3989
3990	STAM_PROFILE_START(&pPool->StatFree, a);
3991	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
3992	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
3993	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
3994	pgmLock(pVM);
3995	#ifdef PGMPOOL_WITH_USER_TRACKING
3996	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
3997	#endif
3998	#ifdef PGMPOOL_WITH_CACHE
3999	if (!pPage->fCached)
4000	#endif
4001	pgmPoolFlushPage(pPool, pPage);
4002	pgmUnlock(pVM);
4003	STAM_PROFILE_STOP(&pPool->StatFree, a);
4004	}
4005
4006
4007	/**
4008	* Makes one or more free page free.
4009	*
4010	* @returns VBox status code.
4011	* @retval VINF_SUCCESS on success.
4012	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4013	*
4014	* @param pPool The pool.
4015	* @param enmKind Page table kind
4016	* @param iUser The user of the page.
4017	*/
4018	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4019	{
4020	PVM pVM = pPool->CTX_SUFF(pVM);
4021
4022	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4023
4024	/*
4025	* If the pool isn't full grown yet, expand it.
4026	*/
4027	if ( pPool->cCurPages < pPool->cMaxPages
4028	#if defined(IN_RC)
4029	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4030	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4031	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4032	#endif
4033	)
4034	{
4035	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4036	#ifdef IN_RING3
4037	int rc = PGMR3PoolGrow(pVM);
4038	#else
4039	int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4040	#endif
4041	if (RT_FAILURE(rc))
4042	return rc;
4043	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4044	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4045	return VINF_SUCCESS;
4046	}
4047
4048	#ifdef PGMPOOL_WITH_CACHE
4049	/*
4050	* Free one cached page.
4051	*/
4052	return pgmPoolCacheFreeOne(pPool, iUser);
4053	#else
4054	/*
4055	* Flush the pool.
4056	*
4057	* If we have tracking enabled, it should be possible to come up with
4058	* a cheap replacement strategy...
4059	*/
4060	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4061	AssertCompileFailed();
4062	Assert(!CPUMIsGuestInLongMode(pVM));
4063	pgmPoolFlushAllInt(pPool);
4064	return VERR_PGM_POOL_FLUSHED;
4065	#endif
4066	}
4067
4068	/**
4069	* Allocates a page from the pool.
4070	*
4071	* This page may actually be a cached page and not in need of any processing
4072	* on the callers part.
4073	*
4074	* @returns VBox status code.
4075	* @retval VINF_SUCCESS if a NEW page was allocated.
4076	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4077	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4078	* @param pVM The VM handle.
4079	* @param GCPhys The GC physical address of the page we're gonna shadow.
4080	* For 4MB and 2MB PD entries, it's the first address the
4081	* shadow PT is covering.
4082	* @param enmKind The kind of mapping.
4083	* @param enmAccess Access type for the mapping (only relevant for big pages)
4084	* @param iUser The shadow page pool index of the user table.
4085	* @param iUserTable The index into the user table (shadowed).
4086	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4087	* @param fLockPage Lock the page
4088	*/
4089	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage)
4090	{
4091	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4092	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4093	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4094	*ppPage = NULL;
4095	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4096	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4097	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4098
4099	pgmLock(pVM);
4100
4101	#ifdef PGMPOOL_WITH_CACHE
4102	if (pPool->fCacheEnabled)
4103	{
4104	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4105	if (RT_SUCCESS(rc2))
4106	{
4107	if (fLockPage)
4108	pgmPoolLockPage(pPool, *ppPage);
4109	pgmUnlock(pVM);
4110	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4111	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4112	return rc2;
4113	}
4114	}
4115	#endif
4116
4117	/*
4118	* Allocate a new one.
4119	*/
4120	int rc = VINF_SUCCESS;
4121	uint16_t iNew = pPool->iFreeHead;
4122	if (iNew == NIL_PGMPOOL_IDX)
4123	{
4124	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4125	if (RT_FAILURE(rc))
4126	{
4127	pgmUnlock(pVM);
4128	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4129	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4130	return rc;
4131	}
4132	iNew = pPool->iFreeHead;
4133	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4134	}
4135
4136	/* unlink the free head */
4137	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4138	pPool->iFreeHead = pPage->iNext;
4139	pPage->iNext = NIL_PGMPOOL_IDX;
4140
4141	/*
4142	* Initialize it.
4143	*/
4144	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4145	pPage->enmKind = enmKind;
4146	pPage->enmAccess = enmAccess;
4147	pPage->GCPhys = GCPhys;
4148	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4149	pPage->fMonitored = false;
4150	pPage->fCached = false;
4151	pPage->fReusedFlushPending = false;
4152	#ifdef PGMPOOL_WITH_MONITORING
4153	pPage->cModifications = 0;
4154	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4155	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4156	#else
4157	pPage->fCR3Mix = false;
4158	#endif
4159	#ifdef PGMPOOL_WITH_USER_TRACKING
4160	pPage->cPresent = 0;
4161	pPage->iFirstPresent = ~0;
4162
4163	/*
4164	* Insert into the tracking and cache. If this fails, free the page.
4165	*/
4166	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4167	if (RT_FAILURE(rc3))
4168	{
4169	pPool->cUsedPages--;
4170	pPage->enmKind = PGMPOOLKIND_FREE;
4171	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4172	pPage->GCPhys = NIL_RTGCPHYS;
4173	pPage->iNext = pPool->iFreeHead;
4174	pPool->iFreeHead = pPage->idx;
4175	pgmUnlock(pVM);
4176	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4177	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4178	return rc3;
4179	}
4180	#endif /* PGMPOOL_WITH_USER_TRACKING */
4181
4182	/*
4183	* Commit the allocation, clear the page and return.
4184	*/
4185	#ifdef VBOX_WITH_STATISTICS
4186	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4187	pPool->cUsedPagesHigh = pPool->cUsedPages;
4188	#endif
4189
4190	if (!pPage->fZeroed)
4191	{
4192	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4193	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4194	ASMMemZeroPage(pv);
4195	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4196	}
4197
4198	*ppPage = pPage;
4199	if (fLockPage)
4200	pgmPoolLockPage(pPool, pPage);
4201	pgmUnlock(pVM);
4202	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4203	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4204	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4205	return rc;
4206	}
4207
4208
4209	/**
4210	* Frees a usage of a pool page.
4211	*
4212	* @param pVM The VM handle.
4213	* @param HCPhys The HC physical address of the shadow page.
4214	* @param iUser The shadow page pool index of the user table.
4215	* @param iUserTable The index into the user table (shadowed).
4216	*/
4217	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4218	{
4219	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4220	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4221	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4222	}
4223
4224	/**
4225	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4226	*
4227	* @returns Pointer to the shadow page structure.
4228	* @param pPool The pool.
4229	* @param HCPhys The HC physical address of the shadow page.
4230	*/
4231	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4232	{
4233	PVM pVM = pPool->CTX_SUFF(pVM);
4234
4235	Assert(PGMIsLockOwner(pVM));
4236
4237	/*
4238	* Look up the page.
4239	*/
4240	pgmLock(pVM);
4241	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4242	pgmUnlock(pVM);
4243
4244	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4245	return pPage;
4246	}
4247
4248
4249	#ifdef IN_RING3
4250	/**
4251	* Flushes the entire cache.
4252	*
4253	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4254	* and execute this CR3 flush.
4255	*
4256	* @param pPool The pool.
4257	*/
4258	void pgmR3PoolReset(PVM pVM)
4259	{
4260	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4261
4262	Assert(PGMIsLockOwner(pVM));
4263	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
4264	LogFlow(("pgmPoolFlushAllInt:\n"));
4265
4266	/*
4267	* If there are no pages in the pool, there is nothing to do.
4268	*/
4269	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
4270	{
4271	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4272	return;
4273	}
4274
4275	/*
4276	* Exit the shadow mode since we're going to clear everything,
4277	* including the root page.
4278	*/
4279	for (unsigned i=0;i<pVM->cCPUs;i++)
4280	{
4281	PVMCPU pVCpu = &pVM->aCpus[i];
4282	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4283	}
4284
4285	/*
4286	* Nuke the free list and reinsert all pages into it.
4287	*/
4288	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
4289	{
4290	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4291
4292	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
4293	#ifdef PGMPOOL_WITH_MONITORING
4294	if (pPage->fMonitored)
4295	pgmPoolMonitorFlush(pPool, pPage);
4296	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4297	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4298	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4299	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4300	pPage->cModifications = 0;
4301	#endif
4302	pPage->GCPhys = NIL_RTGCPHYS;
4303	pPage->enmKind = PGMPOOLKIND_FREE;
4304	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4305	Assert(pPage->idx == i);
4306	pPage->iNext = i + 1;
4307	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
4308	pPage->fSeenNonGlobal = false;
4309	pPage->fMonitored = false;
4310	pPage->fCached = false;
4311	pPage->fReusedFlushPending = false;
4312	#ifdef PGMPOOL_WITH_USER_TRACKING
4313	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
4314	#else
4315	pPage->fCR3Mix = false;
4316	#endif
4317	#ifdef PGMPOOL_WITH_CACHE
4318	pPage->iAgeNext = NIL_PGMPOOL_IDX;
4319	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4320	#endif
4321	pPage->cLocked = 0;
4322	}
4323	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
4324	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
4325	pPool->cUsedPages = 0;
4326
4327	#ifdef PGMPOOL_WITH_USER_TRACKING
4328	/*
4329	* Zap and reinitialize the user records.
4330	*/
4331	pPool->cPresent = 0;
4332	pPool->iUserFreeHead = 0;
4333	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
4334	const unsigned cMaxUsers = pPool->cMaxUsers;
4335	for (unsigned i = 0; i < cMaxUsers; i++)
4336	{
4337	paUsers[i].iNext = i + 1;
4338	paUsers[i].iUser = NIL_PGMPOOL_IDX;
4339	paUsers[i].iUserTable = 0xfffffffe;
4340	}
4341	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
4342	#endif
4343
4344	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4345	/*
4346	* Clear all the GCPhys links and rebuild the phys ext free list.
4347	*/
4348	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
4349	pRam;
4350	pRam = pRam->CTX_SUFF(pNext))
4351	{
4352	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4353	while (iPage-- > 0)
4354	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
4355	}
4356
4357	pPool->iPhysExtFreeHead = 0;
4358	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4359	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
4360	for (unsigned i = 0; i < cMaxPhysExts; i++)
4361	{
4362	paPhysExts[i].iNext = i + 1;
4363	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
4364	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
4365	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
4366	}
4367	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
4368	#endif
4369
4370	#ifdef PGMPOOL_WITH_MONITORING
4371	/*
4372	* Just zap the modified list.
4373	*/
4374	pPool->cModifiedPages = 0;
4375	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
4376	#endif
4377
4378	#ifdef PGMPOOL_WITH_CACHE
4379	/*
4380	* Clear the GCPhys hash and the age list.
4381	*/
4382	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
4383	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
4384	pPool->iAgeHead = NIL_PGMPOOL_IDX;
4385	pPool->iAgeTail = NIL_PGMPOOL_IDX;
4386	#endif
4387
4388	/*
4389	* Reinsert active pages into the hash and ensure monitoring chains are correct.
4390	*/
4391	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
4392	{
4393	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4394	pPage->iNext = NIL_PGMPOOL_IDX;
4395	#ifdef PGMPOOL_WITH_MONITORING
4396	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4397	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4398	pPage->cModifications = 0;
4399	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
4400	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4401	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4402	if (pPage->fMonitored)
4403	{
4404	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
4405	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
4406	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
4407	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
4408	pPool->pszAccessHandler);
4409	AssertFatalRCSuccess(rc);
4410	# ifdef PGMPOOL_WITH_CACHE
4411	pgmPoolHashInsert(pPool, pPage);
4412	# endif
4413	}
4414	#endif
4415	#ifdef PGMPOOL_WITH_USER_TRACKING
4416	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
4417	#endif
4418	#ifdef PGMPOOL_WITH_CACHE
4419	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
4420	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
4421	#endif
4422	}
4423
4424	for (unsigned i=0;i<pVM->cCPUs;i++)
4425	{
4426	PVMCPU pVCpu = &pVM->aCpus[i];
4427	/*
4428	* Re-enter the shadowing mode and assert Sync CR3 FF.
4429	*/
4430	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
4431	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4432	}
4433
4434	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4435	}
4436	#endif /* IN_RING3 */
4437
4438	#ifdef LOG_ENABLED
4439	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4440	{
4441	switch(enmKind)
4442	{
4443	case PGMPOOLKIND_INVALID:
4444	return "PGMPOOLKIND_INVALID";
4445	case PGMPOOLKIND_FREE:
4446	return "PGMPOOLKIND_FREE";
4447	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4448	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4449	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4450	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4451	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4452	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4453	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4454	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4455	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4456	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4457	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4458	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4459	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4460	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4461	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4462	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4463	case PGMPOOLKIND_32BIT_PD:
4464	return "PGMPOOLKIND_32BIT_PD";
4465	case PGMPOOLKIND_32BIT_PD_PHYS:
4466	return "PGMPOOLKIND_32BIT_PD_PHYS";
4467	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4468	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4469	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4470	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4471	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4472	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4473	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4474	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4475	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4476	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4477	case PGMPOOLKIND_PAE_PD_PHYS:
4478	return "PGMPOOLKIND_PAE_PD_PHYS";
4479	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4480	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4481	case PGMPOOLKIND_PAE_PDPT:
4482	return "PGMPOOLKIND_PAE_PDPT";
4483	case PGMPOOLKIND_PAE_PDPT_PHYS:
4484	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4485	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4486	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4487	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4488	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4489	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4490	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4491	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4492	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4493	case PGMPOOLKIND_64BIT_PML4:
4494	return "PGMPOOLKIND_64BIT_PML4";
4495	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4496	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4497	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4498	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4499	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4500	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4501	case PGMPOOLKIND_ROOT_NESTED:
4502	return "PGMPOOLKIND_ROOT_NESTED";
4503	}
4504	return "Unknown kind!";
4505	}
4506	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 22336

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