VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 23121

Last change on this file since 23121 was 23121, checked in by vboxsync, 16 years ago

Paging updates:

  • use the dirty page handling after fewer writes
  • don't always invalidate PTEs in pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs; just flipping the X86_PTE_W bit is sufficient
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 194.2 KB
Line 
1/* $Id: PGMAllPool.cpp 23121 2009-09-18 11:12:52Z vboxsync $ */
2/** @file
3 * PGM Shadow Page Pool.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_POOL
27#include <VBox/pgm.h>
28#include <VBox/mm.h>
29#include <VBox/em.h>
30#include <VBox/cpum.h>
31#ifdef IN_RC
32# include <VBox/patm.h>
33#endif
34#include "PGMInternal.h"
35#include <VBox/vm.h>
36#include <VBox/disopcode.h>
37#include <VBox/hwacc_vmx.h>
38
39#include <VBox/log.h>
40#include <VBox/err.h>
41#include <iprt/asm.h>
42#include <iprt/string.h>
43
44
45/*******************************************************************************
46* Internal Functions *
47*******************************************************************************/
48RT_C_DECLS_BEGIN
49static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50#ifdef PGMPOOL_WITH_USER_TRACKING
51DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54#endif
55#ifdef PGMPOOL_WITH_CACHE
56static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
57#endif
58#ifdef PGMPOOL_WITH_MONITORING
59static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
60#endif
61#ifndef IN_RING3
62DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
63#endif
64#ifdef LOG_ENABLED
65static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
66#endif
67
68int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
69PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
70void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
71void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
72
73RT_C_DECLS_END
74
75
76/**
77 * Checks if the specified page pool kind is for a 4MB or 2MB guest page.
78 *
79 * @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
80 * @param enmKind The page kind.
81 */
82DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
83{
84 switch (enmKind)
85 {
86 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
87 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
88 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
89 return true;
90 default:
91 return false;
92 }
93}
94
95/** @def PGMPOOL_PAGE_2_LOCKED_PTR
96 * Maps a pool page pool into the current context and lock it (RC only).
97 *
98 * @returns VBox status code.
99 * @param pVM The VM handle.
100 * @param pPage The pool page.
101 *
102 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
103 * small page window employeed by that function. Be careful.
104 * @remark There is no need to assert on the result.
105 */
106#if defined(IN_RC)
107DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
108{
109 void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
110
111 /* Make sure the dynamic mapping will not be reused. */
112 if (pv)
113 PGMDynLockHCPage(pVM, (uint8_t *)pv);
114
115 return pv;
116}
117#else
118# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
119#endif
120
121/** @def PGMPOOL_UNLOCK_PTR
122 * Unlock a previously locked dynamic caching (RC only).
123 *
124 * @returns VBox status code.
125 * @param pVM The VM handle.
126 * @param pPage The pool page.
127 *
128 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
129 * small page window employeed by that function. Be careful.
130 * @remark There is no need to assert on the result.
131 */
132#if defined(IN_RC)
133DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
134{
135 if (pvPage)
136 PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
137}
138#else
139# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
140#endif
141
142
143#ifdef PGMPOOL_WITH_MONITORING
144/**
145 * Determin the size of a write instruction.
146 * @returns number of bytes written.
147 * @param pDis The disassembler state.
148 */
149static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
150{
151 /*
152 * This is very crude and possibly wrong for some opcodes,
153 * but since it's not really supposed to be called we can
154 * probably live with that.
155 */
156 return DISGetParamSize(pDis, &pDis->param1);
157}
158
159
160/**
161 * Flushes a chain of pages sharing the same access monitor.
162 *
163 * @returns VBox status code suitable for scheduling.
164 * @param pPool The pool.
165 * @param pPage A page in the chain.
166 */
167int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
168{
169 LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
170
171 /*
172 * Find the list head.
173 */
174 uint16_t idx = pPage->idx;
175 if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
176 {
177 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
178 {
179 idx = pPage->iMonitoredPrev;
180 Assert(idx != pPage->idx);
181 pPage = &pPool->aPages[idx];
182 }
183 }
184
185 /*
186 * Iterate the list flushing each shadow page.
187 */
188 int rc = VINF_SUCCESS;
189 for (;;)
190 {
191 idx = pPage->iMonitoredNext;
192 Assert(idx != pPage->idx);
193 if (pPage->idx >= PGMPOOL_IDX_FIRST)
194 {
195 int rc2 = pgmPoolFlushPage(pPool, pPage);
196 AssertRC(rc2);
197 }
198 /* next */
199 if (idx == NIL_PGMPOOL_IDX)
200 break;
201 pPage = &pPool->aPages[idx];
202 }
203 return rc;
204}
205
206
207/**
208 * Wrapper for getting the current context pointer to the entry being modified.
209 *
210 * @returns VBox status code suitable for scheduling.
211 * @param pVM VM Handle.
212 * @param pvDst Destination address
213 * @param pvSrc Source guest virtual address.
214 * @param GCPhysSrc The source guest physical address.
215 * @param cb Size of data to read
216 */
217DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
218{
219#if defined(IN_RING3)
220 memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
221 return VINF_SUCCESS;
222#else
223 /* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
224 return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
225#endif
226}
227
228/**
229 * Process shadow entries before they are changed by the guest.
230 *
231 * For PT entries we will clear them. For PD entries, we'll simply check
232 * for mapping conflicts and set the SyncCR3 FF if found.
233 *
234 * @param pVCpu VMCPU handle
235 * @param pPool The pool.
236 * @param pPage The head page.
237 * @param GCPhysFault The guest physical fault address.
238 * @param uAddress In R0 and GC this is the guest context fault address (flat).
239 * In R3 this is the host context 'fault' address.
240 * @param pDis The disassembler state for figuring out the write size.
241 * This need not be specified if the caller knows we won't do cross entry accesses.
242 */
243void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pDis)
244{
245 AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%#x (idx=%#x)\n", pPage->iMonitoredPrev, pPage->idx));
246 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
247 const unsigned cbWrite = pDis ? pgmPoolDisasWriteSize(pDis) : 0;
248 PVM pVM = pPool->CTX_SUFF(pVM);
249
250 LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, cbWrite));
251
252 for (;;)
253 {
254 union
255 {
256 void *pv;
257 PX86PT pPT;
258 PX86PTPAE pPTPae;
259 PX86PD pPD;
260 PX86PDPAE pPDPae;
261 PX86PDPT pPDPT;
262 PX86PML4 pPML4;
263 } uShw;
264
265 LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
266
267 uShw.pv = NULL;
268 switch (pPage->enmKind)
269 {
270 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
271 {
272 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
273 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
274 const unsigned iShw = off / sizeof(X86PTE);
275 LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
276 if (uShw.pPT->a[iShw].n.u1Present)
277 {
278# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
279 X86PTE GstPte;
280
281 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
282 AssertRC(rc);
283 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
284 pgmPoolTracDerefGCPhysHint(pPool, pPage,
285 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
286 GstPte.u & X86_PTE_PG_MASK);
287# endif
288 ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
289 }
290 break;
291 }
292
293 /* page/2 sized */
294 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
295 {
296 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
297 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298 if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299 {
300 const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301 LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302 if (uShw.pPTPae->a[iShw].n.u1Present)
303 {
304# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305 X86PTE GstPte;
306 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307 AssertRC(rc);
308
309 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310 pgmPoolTracDerefGCPhysHint(pPool, pPage,
311 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312 GstPte.u & X86_PTE_PG_MASK);
313# endif
314 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
315 }
316 }
317 break;
318 }
319
320 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324 {
325 unsigned iGst = off / sizeof(X86PDE);
326 unsigned iShwPdpt = iGst / 256;
327 unsigned iShw = (iGst % 256) * 2;
328 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330 LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
332 if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
333 {
334 for (unsigned i = 0; i < 2; i++)
335 {
336# ifndef IN_RING0
337 if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
338 {
339 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
340 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
341 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
342 break;
343 }
344 else
345# endif /* !IN_RING0 */
346 if (uShw.pPDPae->a[iShw+i].n.u1Present)
347 {
348 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
349 pgmPoolFree(pVM,
350 uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
351 pPage->idx,
352 iShw + i);
353 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
354 }
355
356 /* paranoia / a bit assumptive. */
357 if ( pDis
358 && (off & 3)
359 && (off & 3) + cbWrite > 4)
360 {
361 const unsigned iShw2 = iShw + 2 + i;
362 if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
363 {
364# ifndef IN_RING0
365 if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
366 {
367 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
368 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
369 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
370 break;
371 }
372 else
373# endif /* !IN_RING0 */
374 if (uShw.pPDPae->a[iShw2].n.u1Present)
375 {
376 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
377 pgmPoolFree(pVM,
378 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
379 pPage->idx,
380 iShw2);
381 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
382 }
383 }
384 }
385 }
386 }
387 break;
388 }
389
390 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
391 {
392 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
393 const unsigned iShw = off / sizeof(X86PTEPAE);
394 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
395 if (uShw.pPTPae->a[iShw].n.u1Present)
396 {
397# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
398 X86PTEPAE GstPte;
399 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
400 AssertRC(rc);
401
402 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
403 pgmPoolTracDerefGCPhysHint(pPool, pPage,
404 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
405 GstPte.u & X86_PTE_PAE_PG_MASK);
406# endif
407 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
408 }
409
410 /* paranoia / a bit assumptive. */
411 if ( pDis
412 && (off & 7)
413 && (off & 7) + cbWrite > sizeof(X86PTEPAE))
414 {
415 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
416 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
417
418 if (uShw.pPTPae->a[iShw2].n.u1Present)
419 {
420# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
421 X86PTEPAE GstPte;
422# ifdef IN_RING3
423 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424# else
425 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
426# endif
427 AssertRC(rc);
428 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
429 pgmPoolTracDerefGCPhysHint(pPool, pPage,
430 uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
431 GstPte.u & X86_PTE_PAE_PG_MASK);
432# endif
433 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
434 }
435 }
436 break;
437 }
438
439 case PGMPOOLKIND_32BIT_PD:
440 {
441 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
442 const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
443
444 LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
445 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
446# ifndef IN_RING0
447 if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
448 {
449 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
450 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
451 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
452 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
453 break;
454 }
455# endif /* !IN_RING0 */
456# ifndef IN_RING0
457 else
458# endif /* !IN_RING0 */
459 {
460 if (uShw.pPD->a[iShw].n.u1Present)
461 {
462 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
463 pgmPoolFree(pVM,
464 uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
465 pPage->idx,
466 iShw);
467 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
468 }
469 }
470 /* paranoia / a bit assumptive. */
471 if ( pDis
472 && (off & 3)
473 && (off & 3) + cbWrite > sizeof(X86PTE))
474 {
475 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
476 if ( iShw2 != iShw
477 && iShw2 < RT_ELEMENTS(uShw.pPD->a))
478 {
479# ifndef IN_RING0
480 if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
481 {
482 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
483 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
484 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
485 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
486 break;
487 }
488# endif /* !IN_RING0 */
489# ifndef IN_RING0
490 else
491# endif /* !IN_RING0 */
492 {
493 if (uShw.pPD->a[iShw2].n.u1Present)
494 {
495 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
496 pgmPoolFree(pVM,
497 uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
498 pPage->idx,
499 iShw2);
500 ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
501 }
502 }
503 }
504 }
505#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
506 if ( uShw.pPD->a[iShw].n.u1Present
507 && !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
508 {
509 LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
510# ifdef IN_RC /* TLB load - we're pushing things a bit... */
511 ASMProbeReadByte(pvAddress);
512# endif
513 pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
514 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
515 }
516#endif
517 break;
518 }
519
520 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
521 {
522 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
523 const unsigned iShw = off / sizeof(X86PDEPAE);
524 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
525#ifndef IN_RING0
526 if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
527 {
528 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
529 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
530 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
531 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
532 break;
533 }
534#endif /* !IN_RING0 */
535 /*
536 * Causes trouble when the guest uses a PDE to refer to the whole page table level
537 * structure. (Invalidate here; faults later on when it tries to change the page
538 * table entries -> recheck; probably only applies to the RC case.)
539 */
540# ifndef IN_RING0
541 else
542# endif /* !IN_RING0 */
543 {
544 if (uShw.pPDPae->a[iShw].n.u1Present)
545 {
546 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
547 pgmPoolFree(pVM,
548 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
549 pPage->idx,
550 iShw);
551 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
552 }
553 }
554 /* paranoia / a bit assumptive. */
555 if ( pDis
556 && (off & 7)
557 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
558 {
559 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
560 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
561
562#ifndef IN_RING0
563 if ( iShw2 != iShw
564 && uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
565 {
566 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
567 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
568 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
569 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
570 break;
571 }
572#endif /* !IN_RING0 */
573# ifndef IN_RING0
574 else
575# endif /* !IN_RING0 */
576 if (uShw.pPDPae->a[iShw2].n.u1Present)
577 {
578 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
579 pgmPoolFree(pVM,
580 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
581 pPage->idx,
582 iShw2);
583 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
584 }
585 }
586 break;
587 }
588
589 case PGMPOOLKIND_PAE_PDPT:
590 {
591 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
592 /*
593 * Hopefully this doesn't happen very often:
594 * - touching unused parts of the page
595 * - messing with the bits of pd pointers without changing the physical address
596 */
597 /* PDPT roots are not page aligned; 32 byte only! */
598 const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
599
600 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
601 const unsigned iShw = offPdpt / sizeof(X86PDPE);
602 if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
603 {
604# ifndef IN_RING0
605 if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
606 {
607 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
608 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
609 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
610 LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
611 break;
612 }
613# endif /* !IN_RING0 */
614# ifndef IN_RING0
615 else
616# endif /* !IN_RING0 */
617 if (uShw.pPDPT->a[iShw].n.u1Present)
618 {
619 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
620 pgmPoolFree(pVM,
621 uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
622 pPage->idx,
623 iShw);
624 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
625 }
626
627 /* paranoia / a bit assumptive. */
628 if ( pDis
629 && (offPdpt & 7)
630 && (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
631 {
632 const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
633 if ( iShw2 != iShw
634 && iShw2 < X86_PG_PAE_PDPE_ENTRIES)
635 {
636# ifndef IN_RING0
637 if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
638 {
639 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
640 STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
641 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
642 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
643 break;
644 }
645# endif /* !IN_RING0 */
646# ifndef IN_RING0
647 else
648# endif /* !IN_RING0 */
649 if (uShw.pPDPT->a[iShw2].n.u1Present)
650 {
651 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
652 pgmPoolFree(pVM,
653 uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
654 pPage->idx,
655 iShw2);
656 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
657 }
658 }
659 }
660 }
661 break;
662 }
663
664#ifndef IN_RC
665 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
666 {
667 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
668 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
669 const unsigned iShw = off / sizeof(X86PDEPAE);
670 Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
671 if (uShw.pPDPae->a[iShw].n.u1Present)
672 {
673 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
674 pgmPoolFree(pVM,
675 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
676 pPage->idx,
677 iShw);
678 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
679 }
680 /* paranoia / a bit assumptive. */
681 if ( pDis
682 && (off & 7)
683 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
684 {
685 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
686 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
687
688 Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
689 if (uShw.pPDPae->a[iShw2].n.u1Present)
690 {
691 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
692 pgmPoolFree(pVM,
693 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
694 pPage->idx,
695 iShw2);
696 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
697 }
698 }
699 break;
700 }
701
702 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
703 {
704 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
705 /*
706 * Hopefully this doesn't happen very often:
707 * - messing with the bits of pd pointers without changing the physical address
708 */
709 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
710 {
711 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
712 const unsigned iShw = off / sizeof(X86PDPE);
713 if (uShw.pPDPT->a[iShw].n.u1Present)
714 {
715 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
716 pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
717 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
718 }
719 /* paranoia / a bit assumptive. */
720 if ( pDis
721 && (off & 7)
722 && (off & 7) + cbWrite > sizeof(X86PDPE))
723 {
724 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
725 if (uShw.pPDPT->a[iShw2].n.u1Present)
726 {
727 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
728 pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
729 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
730 }
731 }
732 }
733 break;
734 }
735
736 case PGMPOOLKIND_64BIT_PML4:
737 {
738 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
739 /*
740 * Hopefully this doesn't happen very often:
741 * - messing with the bits of pd pointers without changing the physical address
742 */
743 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
744 {
745 uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
746 const unsigned iShw = off / sizeof(X86PDPE);
747 if (uShw.pPML4->a[iShw].n.u1Present)
748 {
749 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
750 pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
751 ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
752 }
753 /* paranoia / a bit assumptive. */
754 if ( pDis
755 && (off & 7)
756 && (off & 7) + cbWrite > sizeof(X86PDPE))
757 {
758 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
759 if (uShw.pPML4->a[iShw2].n.u1Present)
760 {
761 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
762 pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
763 ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
764 }
765 }
766 }
767 break;
768 }
769#endif /* IN_RING0 */
770
771 default:
772 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
773 }
774 PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
775
776 /* next */
777 if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
778 return;
779 pPage = &pPool->aPages[pPage->iMonitoredNext];
780 }
781}
782
783# ifndef IN_RING3
784/**
785 * Checks if a access could be a fork operation in progress.
786 *
787 * Meaning, that the guest is setting up the parent process for Copy-On-Write.
788 *
789 * @returns true if it's likly that we're forking, otherwise false.
790 * @param pPool The pool.
791 * @param pDis The disassembled instruction.
792 * @param offFault The access offset.
793 */
794DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
795{
796 /*
797 * i386 linux is using btr to clear X86_PTE_RW.
798 * The functions involved are (2.6.16 source inspection):
799 * clear_bit
800 * ptep_set_wrprotect
801 * copy_one_pte
802 * copy_pte_range
803 * copy_pmd_range
804 * copy_pud_range
805 * copy_page_range
806 * dup_mmap
807 * dup_mm
808 * copy_mm
809 * copy_process
810 * do_fork
811 */
812 if ( pDis->pCurInstr->opcode == OP_BTR
813 && !(offFault & 4)
814 /** @todo Validate that the bit index is X86_PTE_RW. */
815 )
816 {
817 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
818 return true;
819 }
820 return false;
821}
822
823
824/**
825 * Determine whether the page is likely to have been reused.
826 *
827 * @returns true if we consider the page as being reused for a different purpose.
828 * @returns false if we consider it to still be a paging page.
829 * @param pVM VM Handle.
830 * @param pVCpu VMCPU Handle.
831 * @param pRegFrame Trap register frame.
832 * @param pDis The disassembly info for the faulting instruction.
833 * @param pvFault The fault address.
834 *
835 * @remark The REP prefix check is left to the caller because of STOSD/W.
836 */
837DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
838{
839#ifndef IN_RC
840 /** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
841 if ( HWACCMHasPendingIrq(pVM)
842 && (pRegFrame->rsp - pvFault) < 32)
843 {
844 /* Fault caused by stack writes while trying to inject an interrupt event. */
845 Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
846 return true;
847 }
848#else
849 NOREF(pVM); NOREF(pvFault);
850#endif
851
852 LogFlow(("Reused instr %RGv %d at %RGv param1.flags=%x param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.flags, pDis->param1.base.reg_gen));
853
854 /* Non-supervisor mode write means it's used for something else. */
855 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
856 return true;
857
858 switch (pDis->pCurInstr->opcode)
859 {
860 /* call implies the actual push of the return address faulted */
861 case OP_CALL:
862 Log4(("pgmPoolMonitorIsReused: CALL\n"));
863 return true;
864 case OP_PUSH:
865 Log4(("pgmPoolMonitorIsReused: PUSH\n"));
866 return true;
867 case OP_PUSHF:
868 Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
869 return true;
870 case OP_PUSHA:
871 Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
872 return true;
873 case OP_FXSAVE:
874 Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
875 return true;
876 case OP_MOVNTI: /* solaris - block_zero_no_xmm */
877 Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
878 return true;
879 case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
880 Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
881 return true;
882 case OP_MOVSWD:
883 case OP_STOSWD:
884 if ( pDis->prefix == (PREFIX_REP|PREFIX_REX)
885 && pRegFrame->rcx >= 0x40
886 )
887 {
888 Assert(pDis->mode == CPUMODE_64BIT);
889
890 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
891 return true;
892 }
893 return false;
894 }
895 if ( ( (pDis->param1.flags & USE_REG_GEN32)
896 || (pDis->param1.flags & USE_REG_GEN64))
897 && (pDis->param1.base.reg_gen == USE_REG_ESP))
898 {
899 Log4(("pgmPoolMonitorIsReused: ESP\n"));
900 return true;
901 }
902
903 return false;
904}
905
906/**
907 * Flushes the page being accessed.
908 *
909 * @returns VBox status code suitable for scheduling.
910 * @param pVM The VM handle.
911 * @param pVCpu The VMCPU handle.
912 * @param pPool The pool.
913 * @param pPage The pool page (head).
914 * @param pDis The disassembly of the write instruction.
915 * @param pRegFrame The trap register frame.
916 * @param GCPhysFault The fault address as guest physical address.
917 * @param pvFault The fault address.
918 */
919static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
920 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
921{
922 /*
923 * First, do the flushing.
924 */
925 int rc = pgmPoolMonitorChainFlush(pPool, pPage);
926
927 /*
928 * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). Must do this in raw mode (!); XP boot will fail otherwise
929 */
930 uint32_t cbWritten;
931 int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten);
932 if (RT_SUCCESS(rc2))
933 pRegFrame->rip += pDis->opsize;
934 else if (rc2 == VERR_EM_INTERPRETER)
935 {
936#ifdef IN_RC
937 if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
938 {
939 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
940 pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
941 rc = VINF_SUCCESS;
942 STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
943 }
944 else
945#endif
946 {
947 rc = VINF_EM_RAW_EMULATE_INSTR;
948 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
949 }
950 }
951 else
952 rc = rc2;
953
954 /* See use in pgmPoolAccessHandlerSimple(). */
955 PGM_INVL_VCPU_TLBS(pVCpu);
956 LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
957 return rc;
958}
959
960/**
961 * Handles the STOSD write accesses.
962 *
963 * @returns VBox status code suitable for scheduling.
964 * @param pVM The VM handle.
965 * @param pPool The pool.
966 * @param pPage The pool page (head).
967 * @param pDis The disassembly of the write instruction.
968 * @param pRegFrame The trap register frame.
969 * @param GCPhysFault The fault address as guest physical address.
970 * @param pvFault The fault address.
971 */
972DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
973 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
974{
975 unsigned uIncrement = pDis->param1.size;
976
977 Assert(pDis->mode == CPUMODE_32BIT || pDis->mode == CPUMODE_64BIT);
978 Assert(pRegFrame->rcx <= 0x20);
979
980#ifdef VBOX_STRICT
981 if (pDis->opmode == CPUMODE_32BIT)
982 Assert(uIncrement == 4);
983 else
984 Assert(uIncrement == 8);
985#endif
986
987 Log3(("pgmPoolAccessHandlerSTOSD\n"));
988
989 /*
990 * Increment the modification counter and insert it into the list
991 * of modified pages the first time.
992 */
993 if (!pPage->cModifications++)
994 pgmPoolMonitorModifiedInsert(pPool, pPage);
995
996 /*
997 * Execute REP STOSD.
998 *
999 * This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
1000 * write situation, meaning that it's safe to write here.
1001 */
1002 PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
1003 RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
1004 while (pRegFrame->rcx)
1005 {
1006#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1007 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1008 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
1009 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1010#else
1011 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
1012#endif
1013#ifdef IN_RC
1014 *(uint32_t *)pu32 = pRegFrame->eax;
1015#else
1016 PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
1017#endif
1018 pu32 += uIncrement;
1019 GCPhysFault += uIncrement;
1020 pRegFrame->rdi += uIncrement;
1021 pRegFrame->rcx--;
1022 }
1023 pRegFrame->rip += pDis->opsize;
1024
1025#ifdef IN_RC
1026 /* See use in pgmPoolAccessHandlerSimple(). */
1027 PGM_INVL_VCPU_TLBS(pVCpu);
1028#endif
1029
1030 LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1031 return VINF_SUCCESS;
1032}
1033
1034
1035/**
1036 * Handles the simple write accesses.
1037 *
1038 * @returns VBox status code suitable for scheduling.
1039 * @param pVM The VM handle.
1040 * @param pVCpu The VMCPU handle.
1041 * @param pPool The pool.
1042 * @param pPage The pool page (head).
1043 * @param pDis The disassembly of the write instruction.
1044 * @param pRegFrame The trap register frame.
1045 * @param GCPhysFault The fault address as guest physical address.
1046 * @param pvFault The fault address.
1047 * @param pfReused Reused state (out)
1048 */
1049DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
1050 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
1051{
1052 Log3(("pgmPoolAccessHandlerSimple\n"));
1053 /*
1054 * Increment the modification counter and insert it into the list
1055 * of modified pages the first time.
1056 */
1057 if (!pPage->cModifications++)
1058 pgmPoolMonitorModifiedInsert(pPool, pPage);
1059
1060 /*
1061 * Clear all the pages. ASSUMES that pvFault is readable.
1062 */
1063#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1064 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1065 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1066 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1067#else
1068 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pDis);
1069#endif
1070
1071 /*
1072 * Interpret the instruction.
1073 */
1074 uint32_t cb;
1075 int rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb);
1076 if (RT_SUCCESS(rc))
1077 pRegFrame->rip += pDis->opsize;
1078 else if (rc == VERR_EM_INTERPRETER)
1079 {
1080 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1081 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
1082 rc = VINF_EM_RAW_EMULATE_INSTR;
1083 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1084 }
1085
1086#if 0 /* experimental code */
1087 if (rc == VINF_SUCCESS)
1088 {
1089 switch (pPage->enmKind)
1090 {
1091 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1092 {
1093 X86PTEPAE GstPte;
1094 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1095 AssertRC(rc);
1096
1097 /* Check the new value written by the guest. If present and with a bogus physical address, then
1098 * it's fairly safe to assume the guest is reusing the PT.
1099 */
1100 if (GstPte.n.u1Present)
1101 {
1102 RTHCPHYS HCPhys = -1;
1103 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1104 if (rc != VINF_SUCCESS)
1105 {
1106 *pfReused = true;
1107 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1108 }
1109 }
1110 break;
1111 }
1112 }
1113 }
1114#endif
1115
1116#ifdef IN_RC
1117 /*
1118 * Quick hack, with logging enabled we're getting stale
1119 * code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1120 * Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1121 * have to be fixed to support this. But that'll have to wait till next week.
1122 *
1123 * An alternative is to keep track of the changed PTEs together with the
1124 * GCPhys from the guest PT. This may proove expensive though.
1125 *
1126 * At the moment, it's VITAL that it's done AFTER the instruction interpreting
1127 * because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1128 */
1129 PGM_INVL_VCPU_TLBS(pVCpu);
1130#endif
1131
1132 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1133 return rc;
1134}
1135
1136/**
1137 * \#PF Handler callback for PT write accesses.
1138 *
1139 * @returns VBox status code (appropriate for GC return).
1140 * @param pVM VM Handle.
1141 * @param uErrorCode CPU Error code.
1142 * @param pRegFrame Trap register frame.
1143 * NULL on DMA and other non CPU access.
1144 * @param pvFault The fault address (cr2).
1145 * @param GCPhysFault The GC physical address corresponding to pvFault.
1146 * @param pvUser User argument.
1147 */
1148DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1149{
1150 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1151 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1152 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1153 PVMCPU pVCpu = VMMGetCpu(pVM);
1154 unsigned cMaxModifications;
1155 bool fForcedFlush = false;
1156
1157 LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1158
1159 pgmLock(pVM);
1160 if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1161 {
1162 /* Pool page changed while we were waiting for the lock; ignore. */
1163 Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1164 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1165 pgmUnlock(pVM);
1166 return VINF_SUCCESS;
1167 }
1168
1169 /*
1170 * Disassemble the faulting instruction.
1171 */
1172 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1173 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1174 AssertReturnStmt(rc == VINF_SUCCESS, pgmUnlock(pVM), rc);
1175
1176 Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1177
1178 /*
1179 * We should ALWAYS have the list head as user parameter. This
1180 * is because we use that page to record the changes.
1181 */
1182 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1183#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1184 Assert(!pPage->fDirty);
1185#endif
1186
1187#ifdef IN_RING0
1188 /* Maximum nr of modifications depends on the page type. */
1189 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1190 cMaxModifications = 4;
1191 else
1192 cMaxModifications = 24;
1193#else
1194 cMaxModifications = 48;
1195#endif
1196
1197 /*
1198 * Incremental page table updates should weight more than random ones.
1199 * (Only applies when started from offset 0)
1200 */
1201 pVCpu->pgm.s.cPoolAccessHandler++;
1202 if ( pPage->pvLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1203 && pPage->pvLastAccessHandlerRip < pRegFrame->rip + 0x40
1204 && pvFault == (pPage->pvLastAccessHandlerFault + pDis->param1.size)
1205 && pVCpu->pgm.s.cPoolAccessHandler == (pPage->cLastAccessHandlerCount + 1))
1206 {
1207 Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1208 pPage->cModifications = pPage->cModifications * 2;
1209 pPage->pvLastAccessHandlerFault = pvFault;
1210 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1211 if (pPage->cModifications >= cMaxModifications)
1212 {
1213 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1214 fForcedFlush = true;
1215 }
1216 }
1217
1218 if (pPage->cModifications >= cMaxModifications)
1219 Log(("Mod overflow %VGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1220
1221 /*
1222 * Check if it's worth dealing with.
1223 */
1224 bool fReused = false;
1225 bool fNotReusedNotForking = false;
1226 if ( ( pPage->cModifications < cMaxModifications /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
1227 || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1228 )
1229 && !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1230 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1231 {
1232 /*
1233 * Simple instructions, no REP prefix.
1234 */
1235 if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE)))
1236 {
1237 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1238 if (fReused)
1239 goto flushPage;
1240
1241 /* A mov instruction to change the first page table entry will be remembered so we can detect
1242 * full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1243 */
1244 if ( rc == VINF_SUCCESS
1245 && pDis->pCurInstr->opcode == OP_MOV
1246 && (pvFault & PAGE_OFFSET_MASK) == 0)
1247 {
1248 pPage->pvLastAccessHandlerFault = pvFault;
1249 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1250 pPage->pvLastAccessHandlerRip = pRegFrame->rip;
1251 /* Make sure we don't kick out a page too quickly. */
1252 if (pPage->cModifications > 8)
1253 pPage->cModifications = 2;
1254 }
1255 else
1256 if (pPage->pvLastAccessHandlerFault == pvFault)
1257 {
1258 /* ignore the 2nd write to this page table entry. */
1259 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1260 }
1261 else
1262 {
1263 pPage->pvLastAccessHandlerFault = 0;
1264 pPage->pvLastAccessHandlerRip = 0;
1265 }
1266
1267 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1268 pgmUnlock(pVM);
1269 return rc;
1270 }
1271
1272 /*
1273 * Windows is frequently doing small memset() operations (netio test 4k+).
1274 * We have to deal with these or we'll kill the cache and performance.
1275 */
1276 if ( pDis->pCurInstr->opcode == OP_STOSWD
1277 && !pRegFrame->eflags.Bits.u1DF
1278 && pDis->opmode == pDis->mode
1279 && pDis->addrmode == pDis->mode)
1280 {
1281 bool fValidStosd = false;
1282
1283 if ( pDis->mode == CPUMODE_32BIT
1284 && pDis->prefix == PREFIX_REP
1285 && pRegFrame->ecx <= 0x20
1286 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1287 && !((uintptr_t)pvFault & 3)
1288 && (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */
1289 )
1290 {
1291 fValidStosd = true;
1292 pRegFrame->rcx &= 0xffffffff; /* paranoia */
1293 }
1294 else
1295 if ( pDis->mode == CPUMODE_64BIT
1296 && pDis->prefix == (PREFIX_REP | PREFIX_REX)
1297 && pRegFrame->rcx <= 0x20
1298 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1299 && !((uintptr_t)pvFault & 7)
1300 && (pRegFrame->rax == 0 || pRegFrame->rax == 0x80) /* the two values observed. */
1301 )
1302 {
1303 fValidStosd = true;
1304 }
1305
1306 if (fValidStosd)
1307 {
1308 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1309 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1310 pgmUnlock(pVM);
1311 return rc;
1312 }
1313 }
1314
1315 /* REP prefix, don't bother. */
1316 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1317 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1318 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1319 fNotReusedNotForking = true;
1320 }
1321
1322#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1323 /* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1324 * leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1325 */
1326 if ( pPage->cModifications >= cMaxModifications
1327 && !fForcedFlush
1328 && pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1329 && ( fNotReusedNotForking
1330 || ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1331 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1332 )
1333 )
1334 {
1335 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
1336 Assert(pPage->fDirty == false);
1337
1338 /* Flush any monitored duplicates as we will disable write protection. */
1339 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1340 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1341 {
1342 PPGMPOOLPAGE pPageHead = pPage;
1343
1344 /* Find the monitor head. */
1345 while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1346 pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1347
1348 while (pPageHead)
1349 {
1350 unsigned idxNext = pPageHead->iMonitoredNext;
1351
1352 if (pPageHead != pPage)
1353 {
1354 STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1355 Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1356 int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1357 AssertRC(rc2);
1358 }
1359
1360 if (idxNext == NIL_PGMPOOL_IDX)
1361 break;
1362
1363 pPageHead = &pPool->aPages[idxNext];
1364 }
1365 }
1366
1367 /* The flushing above might fail for locked pages, so double check. */
1368 if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1369 && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1370 {
1371 pgmPoolAddDirtyPage(pVM, pPool, pPage);
1372
1373 /* Temporarily allow write access to the page table again. */
1374 rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys, pPage->GCPhys);
1375 if (rc == VINF_SUCCESS)
1376 {
1377 rc = PGMShwModifyPage(pVCpu, pvFault, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
1378 AssertMsg(rc == VINF_SUCCESS
1379 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1380 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1381 || rc == VERR_PAGE_NOT_PRESENT,
1382 ("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1383
1384 pPage->pvDirtyFault = pvFault;
1385
1386 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1387 pgmUnlock(pVM);
1388 return rc;
1389 }
1390 }
1391 }
1392#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1393
1394 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1395flushPage:
1396 /*
1397 * Not worth it, so flush it.
1398 *
1399 * If we considered it to be reused, don't go back to ring-3
1400 * to emulate failed instructions since we usually cannot
1401 * interpret then. This may be a bit risky, in which case
1402 * the reuse detection must be fixed.
1403 */
1404 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1405 if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1406 rc = VINF_SUCCESS;
1407 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1408 pgmUnlock(pVM);
1409 return rc;
1410}
1411
1412# endif /* !IN_RING3 */
1413
1414# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1415
1416# ifdef VBOX_STRICT
1417/**
1418 * Check references to guest physical memory in a PAE / PAE page table.
1419 *
1420 * @param pPool The pool.
1421 * @param pPage The page.
1422 * @param pShwPT The shadow page table (mapping of the page).
1423 * @param pGstPT The guest page table.
1424 */
1425DECLINLINE(void) pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
1426{
1427 unsigned cErrors = 0;
1428 int LastRc;
1429 unsigned LastPTE;
1430 RTHCPHYS LastHCPhys;
1431
1432#ifdef VBOX_STRICT
1433 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1434 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1435#endif
1436 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1437 {
1438 if (pShwPT->a[i].n.u1Present)
1439 {
1440 RTHCPHYS HCPhys = -1;
1441 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1442 if ( rc != VINF_SUCCESS
1443 || (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys)
1444 {
1445 RTHCPHYS HCPhysPT = -1;
1446 Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1447 LastPTE = i;
1448 LastRc = rc;
1449 LastHCPhys = HCPhys;
1450 cErrors++;
1451
1452 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pPage->GCPhys, &HCPhysPT);
1453 AssertRC(rc);
1454
1455 for (unsigned i = 0; i < pPool->cCurPages; i++)
1456 {
1457 PPGMPOOLPAGE pTempPage = &pPool->aPages[i];
1458
1459 if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1460 {
1461 PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pTempPage);
1462
1463 for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1464 {
1465 if ( pShwPT2->a[j].n.u1Present
1466 && pShwPT2->a[j].n.u1Write
1467 && ((pShwPT2->a[j].u & X86_PTE_PAE_PG_MASK) == HCPhysPT))
1468 {
1469 Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, pShwPT->a[j].u, pShwPT2->a[j].u));
1470 }
1471 }
1472 }
1473 }
1474 }
1475 }
1476 }
1477 AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, pShwPT->a[LastPTE].u, LastHCPhys));
1478}
1479# endif /* VBOX_STRICT */
1480
1481/**
1482 * Clear references to guest physical memory in a PAE / PAE page table.
1483 *
1484 * @returns nr of changed PTEs
1485 * @param pPool The pool.
1486 * @param pPage The page.
1487 * @param pShwPT The shadow page table (mapping of the page).
1488 * @param pGstPT The guest page table.
1489 * @param pOldGstPT The old cached guest page table.
1490 * @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1491 * @param pfFlush Flush reused page table (out)
1492 */
1493DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT, PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1494{
1495 unsigned cChanged = 0;
1496
1497#ifdef VBOX_STRICT
1498 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1499 AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1500#endif
1501 *pfFlush = false;
1502
1503 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1504 {
1505 /* Check the new value written by the guest. If present and with a bogus physical address, then
1506 * it's fairly safe to assume the guest is reusing the PT.
1507 */
1508 if ( fAllowRemoval
1509 && pGstPT->a[i].n.u1Present)
1510 {
1511 if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1512 {
1513 *pfFlush = true;
1514 return ++cChanged;
1515 }
1516 }
1517 if (pShwPT->a[i].n.u1Present)
1518 {
1519 /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1520 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1521 {
1522#ifdef VBOX_STRICT
1523 RTHCPHYS HCPhys = -1;
1524 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1525 AssertMsg(rc == VINF_SUCCESS && (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1526#endif
1527 uint64_t uHostAttr = pShwPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1528 bool fHostRW = !!(pShwPT->a[i].u & X86_PTE_RW);
1529 uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1530 bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1531
1532 if ( uHostAttr == uGuestAttr
1533 && fHostRW <= fGuestRW)
1534 continue;
1535 }
1536 cChanged++;
1537 /* Something was changed, so flush it. */
1538 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1539 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1540 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
1541 ASMAtomicWriteSize(&pShwPT->a[i].u, 0);
1542 }
1543 }
1544 return cChanged;
1545}
1546
1547
1548/**
1549 * Flush a dirty page
1550 *
1551 * @param pVM VM Handle.
1552 * @param pPool The pool.
1553 * @param idxSlot Dirty array slot index
1554 * @param fAllowRemoval Allow a reused page table to be removed
1555 */
1556static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1557{
1558 PPGMPOOLPAGE pPage;
1559 unsigned idxPage;
1560
1561 Assert(idxSlot < RT_ELEMENTS(pPool->aIdxDirtyPages));
1562 if (pPool->aIdxDirtyPages[idxSlot] == NIL_PGMPOOL_IDX)
1563 return;
1564
1565 idxPage = pPool->aIdxDirtyPages[idxSlot];
1566 AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1567 pPage = &pPool->aPages[idxPage];
1568 Assert(pPage->idx == idxPage);
1569 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1570
1571 AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1572 Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1573
1574 /* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1575 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys);
1576 Assert(rc == VINF_SUCCESS);
1577 pPage->fDirty = false;
1578
1579#ifdef VBOX_STRICT
1580 uint64_t fFlags = 0;
1581 RTHCPHYS HCPhys;
1582 rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys);
1583 AssertMsg( ( rc == VINF_SUCCESS
1584 && (!(fFlags & X86_PTE_RW) || HCPhys != pPage->Core.Key))
1585 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1586 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1587 || rc == VERR_PAGE_NOT_PRESENT,
1588 ("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags));
1589#endif
1590
1591 /* Flush those PTEs that have changed. */
1592 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1593 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1594 void *pvGst;
1595 bool fFlush;
1596 rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1597 unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst, (PCX86PTPAE)&pPool->aDirtyPages[idxSlot][0], fAllowRemoval, &fFlush);
1598 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1599 /** Note: we might want to consider keeping the dirty page active in case there were many changes. */
1600
1601 /* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1602 Assert(pPage->cModifications);
1603 if (cChanges < 4)
1604 pPage->cModifications = 1; /* must use > 0 here */
1605 else
1606 pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1607
1608 STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1609 if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages))
1610 pPool->idxFreeDirtyPage = idxSlot;
1611
1612 pPool->cDirtyPages--;
1613 pPool->aIdxDirtyPages[idxSlot] = NIL_PGMPOOL_IDX;
1614 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1615 if (fFlush)
1616 {
1617 Assert(fAllowRemoval);
1618 Log(("Flush reused page table!\n"));
1619 pgmPoolFlushPage(pPool, pPage);
1620 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1621 }
1622 else
1623 Log(("Removed dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1624}
1625
1626# ifndef IN_RING3
1627/**
1628 * Add a new dirty page
1629 *
1630 * @param pVM VM Handle.
1631 * @param pPool The pool.
1632 * @param pPage The page.
1633 */
1634void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1635{
1636 unsigned idxFree;
1637
1638 Assert(PGMIsLocked(pVM));
1639 AssertCompile(RT_ELEMENTS(pPool->aIdxDirtyPages) == 8 || RT_ELEMENTS(pPool->aIdxDirtyPages) == 16);
1640 Assert(!pPage->fDirty);
1641
1642 idxFree = pPool->idxFreeDirtyPage;
1643 Assert(idxFree < RT_ELEMENTS(pPool->aIdxDirtyPages));
1644 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1645
1646 if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aIdxDirtyPages))
1647 {
1648 STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1649 pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1650 }
1651 Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages));
1652 AssertMsg(pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1653
1654 Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1655
1656 /* Make a copy of the guest page table as we require valid GCPhys addresses when removing
1657 * references to physical pages. (the HCPhys linear lookup is *extremely* expensive!)
1658 */
1659 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
1660 void *pvGst;
1661 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1662 memcpy(&pPool->aDirtyPages[idxFree][0], pvGst, PAGE_SIZE);
1663#ifdef VBOX_STRICT
1664 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1665#endif
1666
1667 STAM_COUNTER_INC(&pPool->StatDirtyPage);
1668 pPage->fDirty = true;
1669 pPage->idxDirty = idxFree;
1670 pPool->aIdxDirtyPages[idxFree] = pPage->idx;
1671 pPool->cDirtyPages++;
1672
1673 pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1674 if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages)
1675 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1676 {
1677 unsigned i;
1678 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1679 {
1680 idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1681 if (pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX)
1682 {
1683 pPool->idxFreeDirtyPage = idxFree;
1684 break;
1685 }
1686 }
1687 Assert(i != RT_ELEMENTS(pPool->aIdxDirtyPages));
1688 }
1689
1690 Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages) || pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX);
1691 return;
1692}
1693# endif /* !IN_RING3 */
1694
1695/**
1696 * Check if the specified page is dirty (not write monitored)
1697 *
1698 * @return dirty or not
1699 * @param pVM VM Handle.
1700 * @param GCPhys Guest physical address
1701 */
1702bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1703{
1704 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1705 Assert(PGMIsLocked(pVM));
1706 if (!pPool->cDirtyPages)
1707 return false;
1708
1709 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1710
1711 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1712 {
1713 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1714 {
1715 PPGMPOOLPAGE pPage;
1716 unsigned idxPage = pPool->aIdxDirtyPages[i];
1717
1718 pPage = &pPool->aPages[idxPage];
1719 if (pPage->GCPhys == GCPhys)
1720 return true;
1721 }
1722 }
1723 return false;
1724}
1725
1726/**
1727 * Reset all dirty pages by reinstating page monitoring.
1728 *
1729 * @param pVM VM Handle.
1730 */
1731void pgmPoolResetDirtyPages(PVM pVM)
1732{
1733 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1734 Assert(PGMIsLocked(pVM));
1735 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1736
1737 if (!pPool->cDirtyPages)
1738 return;
1739
1740 Log(("pgmPoolResetDirtyPages\n"));
1741 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1742 pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1743
1744 pPool->idxFreeDirtyPage = 0;
1745 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1746 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1747 {
1748 unsigned i;
1749 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1750 {
1751 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1752 {
1753 pPool->idxFreeDirtyPage = i;
1754 break;
1755 }
1756 }
1757 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1758 }
1759
1760 Assert(pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX || pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages));
1761 return;
1762}
1763# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1764#endif /* PGMPOOL_WITH_MONITORING */
1765
1766#ifdef PGMPOOL_WITH_CACHE
1767
1768/**
1769 * Inserts a page into the GCPhys hash table.
1770 *
1771 * @param pPool The pool.
1772 * @param pPage The page.
1773 */
1774DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1775{
1776 Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1777 Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1778 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1779 pPage->iNext = pPool->aiHash[iHash];
1780 pPool->aiHash[iHash] = pPage->idx;
1781}
1782
1783
1784/**
1785 * Removes a page from the GCPhys hash table.
1786 *
1787 * @param pPool The pool.
1788 * @param pPage The page.
1789 */
1790DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1791{
1792 Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1793 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1794 if (pPool->aiHash[iHash] == pPage->idx)
1795 pPool->aiHash[iHash] = pPage->iNext;
1796 else
1797 {
1798 uint16_t iPrev = pPool->aiHash[iHash];
1799 for (;;)
1800 {
1801 const int16_t i = pPool->aPages[iPrev].iNext;
1802 if (i == pPage->idx)
1803 {
1804 pPool->aPages[iPrev].iNext = pPage->iNext;
1805 break;
1806 }
1807 if (i == NIL_PGMPOOL_IDX)
1808 {
1809 AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1810 break;
1811 }
1812 iPrev = i;
1813 }
1814 }
1815 pPage->iNext = NIL_PGMPOOL_IDX;
1816}
1817
1818
1819/**
1820 * Frees up one cache page.
1821 *
1822 * @returns VBox status code.
1823 * @retval VINF_SUCCESS on success.
1824 * @param pPool The pool.
1825 * @param iUser The user index.
1826 */
1827static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1828{
1829#ifndef IN_RC
1830 const PVM pVM = pPool->CTX_SUFF(pVM);
1831#endif
1832 Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1833 STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1834
1835 /*
1836 * Select one page from the tail of the age list.
1837 */
1838 PPGMPOOLPAGE pPage;
1839 for (unsigned iLoop = 0; ; iLoop++)
1840 {
1841 uint16_t iToFree = pPool->iAgeTail;
1842 if (iToFree == iUser)
1843 iToFree = pPool->aPages[iToFree].iAgePrev;
1844/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1845 if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1846 {
1847 uint16_t i = pPool->aPages[iToFree].iAgePrev;
1848 for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1849 {
1850 if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1851 continue;
1852 iToFree = i;
1853 break;
1854 }
1855 }
1856*/
1857 Assert(iToFree != iUser);
1858 AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1859 pPage = &pPool->aPages[iToFree];
1860
1861 /*
1862 * Reject any attempts at flushing the currently active shadow CR3 mapping.
1863 * Call pgmPoolCacheUsed to move the page to the head of the age list.
1864 */
1865 if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1866 break;
1867 LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1868 pgmPoolCacheUsed(pPool, pPage);
1869 AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1870 }
1871
1872 /*
1873 * Found a usable page, flush it and return.
1874 */
1875 return pgmPoolFlushPage(pPool, pPage);
1876}
1877
1878
1879/**
1880 * Checks if a kind mismatch is really a page being reused
1881 * or if it's just normal remappings.
1882 *
1883 * @returns true if reused and the cached page (enmKind1) should be flushed
1884 * @returns false if not reused.
1885 * @param enmKind1 The kind of the cached page.
1886 * @param enmKind2 The kind of the requested page.
1887 */
1888static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1889{
1890 switch (enmKind1)
1891 {
1892 /*
1893 * Never reuse them. There is no remapping in non-paging mode.
1894 */
1895 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1896 case PGMPOOLKIND_32BIT_PD_PHYS:
1897 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1898 case PGMPOOLKIND_PAE_PD_PHYS:
1899 case PGMPOOLKIND_PAE_PDPT_PHYS:
1900 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1901 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1902 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1903 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1904 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1905 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1906 return false;
1907
1908 /*
1909 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1910 */
1911 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1912 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1913 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1914 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1915 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1916 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1917 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1918 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1919 case PGMPOOLKIND_32BIT_PD:
1920 case PGMPOOLKIND_PAE_PDPT:
1921 switch (enmKind2)
1922 {
1923 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1924 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1925 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1926 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1927 case PGMPOOLKIND_64BIT_PML4:
1928 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1929 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1930 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1931 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1932 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1933 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1934 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1935 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1936 return true;
1937 default:
1938 return false;
1939 }
1940
1941 /*
1942 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1943 */
1944 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1945 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1946 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1947 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1948 case PGMPOOLKIND_64BIT_PML4:
1949 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1950 switch (enmKind2)
1951 {
1952 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1953 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1954 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1955 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1956 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1957 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1958 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1959 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1960 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1961 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1962 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1963 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1964 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1965 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1966 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1967 return true;
1968 default:
1969 return false;
1970 }
1971
1972 /*
1973 * These cannot be flushed, and it's common to reuse the PDs as PTs.
1974 */
1975 case PGMPOOLKIND_ROOT_NESTED:
1976 return false;
1977
1978 default:
1979 AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1980 }
1981}
1982
1983
1984/**
1985 * Attempts to satisfy a pgmPoolAlloc request from the cache.
1986 *
1987 * @returns VBox status code.
1988 * @retval VINF_PGM_CACHED_PAGE on success.
1989 * @retval VERR_FILE_NOT_FOUND if not found.
1990 * @param pPool The pool.
1991 * @param GCPhys The GC physical address of the page we're gonna shadow.
1992 * @param enmKind The kind of mapping.
1993 * @param enmAccess Access type for the mapping (only relevant for big pages)
1994 * @param iUser The shadow page pool index of the user table.
1995 * @param iUserTable The index into the user table (shadowed).
1996 * @param ppPage Where to store the pointer to the page.
1997 */
1998static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1999{
2000#ifndef IN_RC
2001 const PVM pVM = pPool->CTX_SUFF(pVM);
2002#endif
2003 /*
2004 * Look up the GCPhys in the hash.
2005 */
2006 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2007 Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2008 if (i != NIL_PGMPOOL_IDX)
2009 {
2010 do
2011 {
2012 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2013 Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2014 if (pPage->GCPhys == GCPhys)
2015 {
2016 if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2017 && (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
2018 {
2019 /* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2020 * doesn't flush it in case there are no more free use records.
2021 */
2022 pgmPoolCacheUsed(pPool, pPage);
2023
2024 int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2025 if (RT_SUCCESS(rc))
2026 {
2027 Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2028 *ppPage = pPage;
2029 if (pPage->cModifications)
2030 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2031 STAM_COUNTER_INC(&pPool->StatCacheHits);
2032 return VINF_PGM_CACHED_PAGE;
2033 }
2034 return rc;
2035 }
2036
2037 if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2038 {
2039 /*
2040 * The kind is different. In some cases we should now flush the page
2041 * as it has been reused, but in most cases this is normal remapping
2042 * of PDs as PT or big pages using the GCPhys field in a slightly
2043 * different way than the other kinds.
2044 */
2045 if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2046 {
2047 STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2048 pgmPoolFlushPage(pPool, pPage);
2049 break;
2050 }
2051 }
2052 }
2053
2054 /* next */
2055 i = pPage->iNext;
2056 } while (i != NIL_PGMPOOL_IDX);
2057 }
2058
2059 Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2060 STAM_COUNTER_INC(&pPool->StatCacheMisses);
2061 return VERR_FILE_NOT_FOUND;
2062}
2063
2064
2065/**
2066 * Inserts a page into the cache.
2067 *
2068 * @param pPool The pool.
2069 * @param pPage The cached page.
2070 * @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2071 */
2072static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2073{
2074 /*
2075 * Insert into the GCPhys hash if the page is fit for that.
2076 */
2077 Assert(!pPage->fCached);
2078 if (fCanBeCached)
2079 {
2080 pPage->fCached = true;
2081 pgmPoolHashInsert(pPool, pPage);
2082 Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2083 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2084 STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2085 }
2086 else
2087 {
2088 Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2089 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2090 STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2091 }
2092
2093 /*
2094 * Insert at the head of the age list.
2095 */
2096 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2097 pPage->iAgeNext = pPool->iAgeHead;
2098 if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2099 pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2100 else
2101 pPool->iAgeTail = pPage->idx;
2102 pPool->iAgeHead = pPage->idx;
2103}
2104
2105
2106/**
2107 * Flushes a cached page.
2108 *
2109 * @param pPool The pool.
2110 * @param pPage The cached page.
2111 */
2112static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2113{
2114 Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2115
2116 /*
2117 * Remove the page from the hash.
2118 */
2119 if (pPage->fCached)
2120 {
2121 pPage->fCached = false;
2122 pgmPoolHashRemove(pPool, pPage);
2123 }
2124 else
2125 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2126
2127 /*
2128 * Remove it from the age list.
2129 */
2130 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2131 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2132 else
2133 pPool->iAgeTail = pPage->iAgePrev;
2134 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2135 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2136 else
2137 pPool->iAgeHead = pPage->iAgeNext;
2138 pPage->iAgeNext = NIL_PGMPOOL_IDX;
2139 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2140}
2141
2142#endif /* PGMPOOL_WITH_CACHE */
2143#ifdef PGMPOOL_WITH_MONITORING
2144
2145/**
2146 * Looks for pages sharing the monitor.
2147 *
2148 * @returns Pointer to the head page.
2149 * @returns NULL if not found.
2150 * @param pPool The Pool
2151 * @param pNewPage The page which is going to be monitored.
2152 */
2153static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2154{
2155#ifdef PGMPOOL_WITH_CACHE
2156 /*
2157 * Look up the GCPhys in the hash.
2158 */
2159 RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2160 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2161 if (i == NIL_PGMPOOL_IDX)
2162 return NULL;
2163 do
2164 {
2165 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2166 if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2167 && pPage != pNewPage)
2168 {
2169 switch (pPage->enmKind)
2170 {
2171 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2172 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2173 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2174 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2175 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2176 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2177 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2178 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2179 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2180 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2181 case PGMPOOLKIND_64BIT_PML4:
2182 case PGMPOOLKIND_32BIT_PD:
2183 case PGMPOOLKIND_PAE_PDPT:
2184 {
2185 /* find the head */
2186 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2187 {
2188 Assert(pPage->iMonitoredPrev != pPage->idx);
2189 pPage = &pPool->aPages[pPage->iMonitoredPrev];
2190 }
2191 return pPage;
2192 }
2193
2194 /* ignore, no monitoring. */
2195 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2196 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2197 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2198 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2199 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2200 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2201 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2202 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2203 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2204 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2205 case PGMPOOLKIND_ROOT_NESTED:
2206 case PGMPOOLKIND_PAE_PD_PHYS:
2207 case PGMPOOLKIND_PAE_PDPT_PHYS:
2208 case PGMPOOLKIND_32BIT_PD_PHYS:
2209 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2210 break;
2211 default:
2212 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2213 }
2214 }
2215
2216 /* next */
2217 i = pPage->iNext;
2218 } while (i != NIL_PGMPOOL_IDX);
2219#endif
2220 return NULL;
2221}
2222
2223
2224/**
2225 * Enabled write monitoring of a guest page.
2226 *
2227 * @returns VBox status code.
2228 * @retval VINF_SUCCESS on success.
2229 * @param pPool The pool.
2230 * @param pPage The cached page.
2231 */
2232static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2233{
2234 LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
2235
2236 /*
2237 * Filter out the relevant kinds.
2238 */
2239 switch (pPage->enmKind)
2240 {
2241 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2242 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2243 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2244 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2245 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2246 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2247 case PGMPOOLKIND_64BIT_PML4:
2248 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2249 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2250 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2251 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2252 case PGMPOOLKIND_32BIT_PD:
2253 case PGMPOOLKIND_PAE_PDPT:
2254 break;
2255
2256 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2257 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2258 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2259 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2260 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2261 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2262 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2263 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2264 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2265 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2266 case PGMPOOLKIND_ROOT_NESTED:
2267 /* Nothing to monitor here. */
2268 return VINF_SUCCESS;
2269
2270 case PGMPOOLKIND_32BIT_PD_PHYS:
2271 case PGMPOOLKIND_PAE_PDPT_PHYS:
2272 case PGMPOOLKIND_PAE_PD_PHYS:
2273 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2274 /* Nothing to monitor here. */
2275 return VINF_SUCCESS;
2276#ifdef PGMPOOL_WITH_MIXED_PT_CR3
2277 break;
2278#else
2279 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2280#endif
2281 default:
2282 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2283 }
2284
2285 /*
2286 * Install handler.
2287 */
2288 int rc;
2289 PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2290 if (pPageHead)
2291 {
2292 Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2293 Assert(pPageHead->iMonitoredPrev != pPage->idx);
2294
2295#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2296 if (pPageHead->fDirty)
2297 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirty, false /* do not remove */);
2298#endif
2299
2300 pPage->iMonitoredPrev = pPageHead->idx;
2301 pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2302 if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2303 pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2304 pPageHead->iMonitoredNext = pPage->idx;
2305 rc = VINF_SUCCESS;
2306 }
2307 else
2308 {
2309 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2310 PVM pVM = pPool->CTX_SUFF(pVM);
2311 const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2312 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2313 GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
2314 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2315 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2316 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2317 pPool->pszAccessHandler);
2318 /** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2319 * the heap size should suffice. */
2320 AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2321 Assert(!(VMMGetCpu(pVM)->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
2322 }
2323 pPage->fMonitored = true;
2324 return rc;
2325}
2326
2327
2328/**
2329 * Disables write monitoring of a guest page.
2330 *
2331 * @returns VBox status code.
2332 * @retval VINF_SUCCESS on success.
2333 * @param pPool The pool.
2334 * @param pPage The cached page.
2335 */
2336static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2337{
2338 /*
2339 * Filter out the relevant kinds.
2340 */
2341 switch (pPage->enmKind)
2342 {
2343 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2344 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2345 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2346 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2347 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2348 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2349 case PGMPOOLKIND_64BIT_PML4:
2350 case PGMPOOLKIND_32BIT_PD:
2351 case PGMPOOLKIND_PAE_PDPT:
2352 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2353 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2354 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2355 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2356 break;
2357
2358 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2359 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2360 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2361 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2362 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2363 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2364 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2365 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2366 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2367 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2368 case PGMPOOLKIND_ROOT_NESTED:
2369 case PGMPOOLKIND_PAE_PD_PHYS:
2370 case PGMPOOLKIND_PAE_PDPT_PHYS:
2371 case PGMPOOLKIND_32BIT_PD_PHYS:
2372 /* Nothing to monitor here. */
2373 return VINF_SUCCESS;
2374
2375#ifdef PGMPOOL_WITH_MIXED_PT_CR3
2376 break;
2377#endif
2378 default:
2379 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2380 }
2381
2382 /*
2383 * Remove the page from the monitored list or uninstall it if last.
2384 */
2385 const PVM pVM = pPool->CTX_SUFF(pVM);
2386 int rc;
2387 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2388 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2389 {
2390 if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2391 {
2392 PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2393 pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2394 rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
2395 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2396 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2397 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2398 pPool->pszAccessHandler);
2399 AssertFatalRCSuccess(rc);
2400 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2401 }
2402 else
2403 {
2404 pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2405 if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2406 {
2407 pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2408 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2409 }
2410 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2411 rc = VINF_SUCCESS;
2412 }
2413 }
2414 else
2415 {
2416 rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
2417 AssertFatalRC(rc);
2418#ifdef VBOX_STRICT
2419 PVMCPU pVCpu = VMMGetCpu(pVM);
2420#endif
2421 AssertMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2422 ("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2423 }
2424 pPage->fMonitored = false;
2425
2426 /*
2427 * Remove it from the list of modified pages (if in it).
2428 */
2429 pgmPoolMonitorModifiedRemove(pPool, pPage);
2430
2431 return rc;
2432}
2433
2434
2435/**
2436 * Inserts the page into the list of modified pages.
2437 *
2438 * @param pPool The pool.
2439 * @param pPage The page.
2440 */
2441void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2442{
2443 Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2444 AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2445 && pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2446 && pPool->iModifiedHead != pPage->idx,
2447 ("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2448 pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2449 pPool->iModifiedHead, pPool->cModifiedPages));
2450
2451 pPage->iModifiedNext = pPool->iModifiedHead;
2452 if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2453 pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2454 pPool->iModifiedHead = pPage->idx;
2455 pPool->cModifiedPages++;
2456#ifdef VBOX_WITH_STATISTICS
2457 if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2458 pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2459#endif
2460}
2461
2462
2463/**
2464 * Removes the page from the list of modified pages and resets the
2465 * moficiation counter.
2466 *
2467 * @param pPool The pool.
2468 * @param pPage The page which is believed to be in the list of modified pages.
2469 */
2470static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2471{
2472 Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2473 if (pPool->iModifiedHead == pPage->idx)
2474 {
2475 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2476 pPool->iModifiedHead = pPage->iModifiedNext;
2477 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2478 {
2479 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2480 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2481 }
2482 pPool->cModifiedPages--;
2483 }
2484 else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2485 {
2486 pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2487 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2488 {
2489 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2490 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2491 }
2492 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2493 pPool->cModifiedPages--;
2494 }
2495 else
2496 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2497 pPage->cModifications = 0;
2498}
2499
2500
2501/**
2502 * Zaps the list of modified pages, resetting their modification counters in the process.
2503 *
2504 * @param pVM The VM handle.
2505 */
2506static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2507{
2508 pgmLock(pVM);
2509 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2510 LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2511
2512 unsigned cPages = 0; NOREF(cPages);
2513
2514#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2515 pgmPoolResetDirtyPages(pVM);
2516#endif
2517
2518 uint16_t idx = pPool->iModifiedHead;
2519 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2520 while (idx != NIL_PGMPOOL_IDX)
2521 {
2522 PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2523 idx = pPage->iModifiedNext;
2524 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2525 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2526 pPage->cModifications = 0;
2527 Assert(++cPages);
2528 }
2529 AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2530 pPool->cModifiedPages = 0;
2531 pgmUnlock(pVM);
2532}
2533
2534
2535#ifdef IN_RING3
2536/**
2537 * Callback to clear all shadow pages and clear all modification counters.
2538 *
2539 * @returns VBox status code.
2540 * @param pVM The VM handle.
2541 * @param pVCpu The VMCPU for the EMT we're being called on. Unused.
2542 * @param pvUser Unused parameter.
2543 *
2544 * @remark Should only be used when monitoring is available, thus placed in
2545 * the PGMPOOL_WITH_MONITORING \#ifdef.
2546 */
2547DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, PVMCPU pVCpu, void *pvUser)
2548{
2549 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2550 STAM_PROFILE_START(&pPool->StatClearAll, c);
2551 LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
2552 NOREF(pvUser); NOREF(pVCpu);
2553
2554 pgmLock(pVM);
2555
2556#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2557 pgmPoolResetDirtyPages(pVM);
2558#endif
2559
2560 /*
2561 * Iterate all the pages until we've encountered all that in use.
2562 * This is simple but not quite optimal solution.
2563 */
2564 unsigned cModifiedPages = 0; NOREF(cModifiedPages);
2565 unsigned cLeft = pPool->cUsedPages;
2566 unsigned iPage = pPool->cCurPages;
2567 while (--iPage >= PGMPOOL_IDX_FIRST)
2568 {
2569 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2570 if (pPage->GCPhys != NIL_RTGCPHYS)
2571 {
2572 switch (pPage->enmKind)
2573 {
2574 /*
2575 * We only care about shadow page tables.
2576 */
2577 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2578 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2579 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2580 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2581 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2582 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2583 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2584 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2585 {
2586#ifdef PGMPOOL_WITH_USER_TRACKING
2587 if (pPage->cPresent)
2588#endif
2589 {
2590 void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
2591 STAM_PROFILE_START(&pPool->StatZeroPage, z);
2592 ASMMemZeroPage(pvShw);
2593 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
2594#ifdef PGMPOOL_WITH_USER_TRACKING
2595 pPage->cPresent = 0;
2596 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
2597#endif
2598 }
2599#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2600 else
2601 Assert(!pPage->fDirty);
2602#endif
2603 }
2604 /* fall thru */
2605
2606 default:
2607#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2608 Assert(!pPage->fDirty);
2609#endif
2610 Assert(!pPage->cModifications || ++cModifiedPages);
2611 Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX || pPage->cModifications);
2612 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX || pPage->cModifications);
2613 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2614 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2615 pPage->cModifications = 0;
2616 break;
2617
2618 }
2619 if (!--cLeft)
2620 break;
2621 }
2622 }
2623
2624 /* swipe the special pages too. */
2625 for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2626 {
2627 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2628 if (pPage->GCPhys != NIL_RTGCPHYS)
2629 {
2630 Assert(!pPage->cModifications || ++cModifiedPages);
2631 Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX || pPage->cModifications);
2632 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX || pPage->cModifications);
2633 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2634 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2635 pPage->cModifications = 0;
2636 }
2637 }
2638
2639#ifndef DEBUG_michael
2640 AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2641#endif
2642 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2643 pPool->cModifiedPages = 0;
2644
2645#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2646 /*
2647 * Clear all the GCPhys links and rebuild the phys ext free list.
2648 */
2649 for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2650 pRam;
2651 pRam = pRam->CTX_SUFF(pNext))
2652 {
2653 unsigned iPage = pRam->cb >> PAGE_SHIFT;
2654 while (iPage-- > 0)
2655 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2656 }
2657
2658 pPool->iPhysExtFreeHead = 0;
2659 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2660 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2661 for (unsigned i = 0; i < cMaxPhysExts; i++)
2662 {
2663 paPhysExts[i].iNext = i + 1;
2664 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2665 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2666 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2667 }
2668 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2669#endif
2670
2671#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2672 /* Clear all dirty pages. */
2673 pPool->idxFreeDirtyPage = 0;
2674 pPool->cDirtyPages = 0;
2675 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
2676 pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
2677#endif
2678
2679 /* Clear the PGM_SYNC_CLEAR_PGM_POOL flag on all VCPUs to prevent redundant flushes. */
2680 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2681 {
2682 PVMCPU pVCpu = &pVM->aCpus[idCpu];
2683 pVCpu->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2684 }
2685
2686 pPool->cPresent = 0;
2687 pgmUnlock(pVM);
2688 PGM_INVL_ALL_VCPU_TLBS(pVM);
2689 STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2690 return VINF_SUCCESS;
2691}
2692#endif /* IN_RING3 */
2693
2694
2695/**
2696 * Handle SyncCR3 pool tasks
2697 *
2698 * @returns VBox status code.
2699 * @retval VINF_SUCCESS if successfully added.
2700 * @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2701 * @param pVCpu The VMCPU handle.
2702 * @remark Should only be used when monitoring is available, thus placed in
2703 * the PGMPOOL_WITH_MONITORING #ifdef.
2704 */
2705int pgmPoolSyncCR3(PVMCPU pVCpu)
2706{
2707 PVM pVM = pVCpu->CTX_SUFF(pVM);
2708 LogFlow(("pgmPoolSyncCR3\n"));
2709
2710 /*
2711 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2712 * Occasionally we will have to clear all the shadow page tables because we wanted
2713 * to monitor a page which was mapped by too many shadowed page tables. This operation
2714 * sometimes refered to as a 'lightweight flush'.
2715 */
2716# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2717 if (ASMBitTestAndClear(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_CLEAR_PGM_POOL_BIT))
2718 {
2719 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONCE, pgmPoolClearAll, NULL);
2720 AssertRC(rc);
2721 }
2722# else /* !IN_RING3 */
2723 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2724 {
2725 LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2726 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2727 return VINF_PGM_SYNC_CR3;
2728 }
2729# endif /* !IN_RING3 */
2730 else
2731 pgmPoolMonitorModifiedClearAll(pVM);
2732
2733 return VINF_SUCCESS;
2734}
2735
2736#endif /* PGMPOOL_WITH_MONITORING */
2737#ifdef PGMPOOL_WITH_USER_TRACKING
2738
2739/**
2740 * Frees up at least one user entry.
2741 *
2742 * @returns VBox status code.
2743 * @retval VINF_SUCCESS if successfully added.
2744 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2745 * @param pPool The pool.
2746 * @param iUser The user index.
2747 */
2748static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2749{
2750 STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2751#ifdef PGMPOOL_WITH_CACHE
2752 /*
2753 * Just free cached pages in a braindead fashion.
2754 */
2755 /** @todo walk the age list backwards and free the first with usage. */
2756 int rc = VINF_SUCCESS;
2757 do
2758 {
2759 int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2760 if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2761 rc = rc2;
2762 } while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2763 return rc;
2764#else
2765 /*
2766 * Lazy approach.
2767 */
2768 /* @todo This path no longer works (CR3 root pages will be flushed)!! */
2769 AssertCompileFailed();
2770 Assert(!CPUMIsGuestInLongMode(pVM));
2771 pgmPoolFlushAllInt(pPool);
2772 return VERR_PGM_POOL_FLUSHED;
2773#endif
2774}
2775
2776
2777/**
2778 * Inserts a page into the cache.
2779 *
2780 * This will create user node for the page, insert it into the GCPhys
2781 * hash, and insert it into the age list.
2782 *
2783 * @returns VBox status code.
2784 * @retval VINF_SUCCESS if successfully added.
2785 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2786 * @param pPool The pool.
2787 * @param pPage The cached page.
2788 * @param GCPhys The GC physical address of the page we're gonna shadow.
2789 * @param iUser The user index.
2790 * @param iUserTable The user table index.
2791 */
2792DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2793{
2794 int rc = VINF_SUCCESS;
2795 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2796
2797 LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2798
2799#ifdef VBOX_STRICT
2800 /*
2801 * Check that the entry doesn't already exists.
2802 */
2803 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2804 {
2805 uint16_t i = pPage->iUserHead;
2806 do
2807 {
2808 Assert(i < pPool->cMaxUsers);
2809 AssertMsg(paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2810 i = paUsers[i].iNext;
2811 } while (i != NIL_PGMPOOL_USER_INDEX);
2812 }
2813#endif
2814
2815 /*
2816 * Find free a user node.
2817 */
2818 uint16_t i = pPool->iUserFreeHead;
2819 if (i == NIL_PGMPOOL_USER_INDEX)
2820 {
2821 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2822 if (RT_FAILURE(rc))
2823 return rc;
2824 i = pPool->iUserFreeHead;
2825 }
2826
2827 /*
2828 * Unlink the user node from the free list,
2829 * initialize and insert it into the user list.
2830 */
2831 pPool->iUserFreeHead = paUsers[i].iNext;
2832 paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2833 paUsers[i].iUser = iUser;
2834 paUsers[i].iUserTable = iUserTable;
2835 pPage->iUserHead = i;
2836
2837 /*
2838 * Insert into cache and enable monitoring of the guest page if enabled.
2839 *
2840 * Until we implement caching of all levels, including the CR3 one, we'll
2841 * have to make sure we don't try monitor & cache any recursive reuse of
2842 * a monitored CR3 page. Because all windows versions are doing this we'll
2843 * have to be able to do combined access monitoring, CR3 + PT and
2844 * PD + PT (guest PAE).
2845 *
2846 * Update:
2847 * We're now cooperating with the CR3 monitor if an uncachable page is found.
2848 */
2849#if defined(PGMPOOL_WITH_MONITORING) || defined(PGMPOOL_WITH_CACHE)
2850# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2851 const bool fCanBeMonitored = true;
2852# else
2853 bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2854 || (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2855 || pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2856# endif
2857# ifdef PGMPOOL_WITH_CACHE
2858 pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2859# endif
2860 if (fCanBeMonitored)
2861 {
2862# ifdef PGMPOOL_WITH_MONITORING
2863 rc = pgmPoolMonitorInsert(pPool, pPage);
2864 AssertRC(rc);
2865 }
2866# endif
2867#endif /* PGMPOOL_WITH_MONITORING */
2868 return rc;
2869}
2870
2871
2872# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2873/**
2874 * Adds a user reference to a page.
2875 *
2876 * This will move the page to the head of the
2877 *
2878 * @returns VBox status code.
2879 * @retval VINF_SUCCESS if successfully added.
2880 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2881 * @param pPool The pool.
2882 * @param pPage The cached page.
2883 * @param iUser The user index.
2884 * @param iUserTable The user table.
2885 */
2886static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2887{
2888 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2889
2890 Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2891
2892# ifdef VBOX_STRICT
2893 /*
2894 * Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2895 */
2896 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2897 {
2898 uint16_t i = pPage->iUserHead;
2899 do
2900 {
2901 Assert(i < pPool->cMaxUsers);
2902 AssertMsg(iUser != PGMPOOL_IDX_PD || iUser != PGMPOOL_IDX_PDPT || iUser != PGMPOOL_IDX_NESTED_ROOT || iUser != PGMPOOL_IDX_AMD64_CR3 ||
2903 paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2904 i = paUsers[i].iNext;
2905 } while (i != NIL_PGMPOOL_USER_INDEX);
2906 }
2907# endif
2908
2909 /*
2910 * Allocate a user node.
2911 */
2912 uint16_t i = pPool->iUserFreeHead;
2913 if (i == NIL_PGMPOOL_USER_INDEX)
2914 {
2915 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2916 if (RT_FAILURE(rc))
2917 return rc;
2918 i = pPool->iUserFreeHead;
2919 }
2920 pPool->iUserFreeHead = paUsers[i].iNext;
2921
2922 /*
2923 * Initialize the user node and insert it.
2924 */
2925 paUsers[i].iNext = pPage->iUserHead;
2926 paUsers[i].iUser = iUser;
2927 paUsers[i].iUserTable = iUserTable;
2928 pPage->iUserHead = i;
2929
2930# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2931 if (pPage->fDirty)
2932 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirty, false /* do not remove */);
2933# endif
2934
2935# ifdef PGMPOOL_WITH_CACHE
2936 /*
2937 * Tell the cache to update its replacement stats for this page.
2938 */
2939 pgmPoolCacheUsed(pPool, pPage);
2940# endif
2941 return VINF_SUCCESS;
2942}
2943# endif /* PGMPOOL_WITH_CACHE */
2944
2945
2946/**
2947 * Frees a user record associated with a page.
2948 *
2949 * This does not clear the entry in the user table, it simply replaces the
2950 * user record to the chain of free records.
2951 *
2952 * @param pPool The pool.
2953 * @param HCPhys The HC physical address of the shadow page.
2954 * @param iUser The shadow page pool index of the user table.
2955 * @param iUserTable The index into the user table (shadowed).
2956 */
2957static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2958{
2959 /*
2960 * Unlink and free the specified user entry.
2961 */
2962 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2963
2964 Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2965 /* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2966 uint16_t i = pPage->iUserHead;
2967 if ( i != NIL_PGMPOOL_USER_INDEX
2968 && paUsers[i].iUser == iUser
2969 && paUsers[i].iUserTable == iUserTable)
2970 {
2971 pPage->iUserHead = paUsers[i].iNext;
2972
2973 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2974 paUsers[i].iNext = pPool->iUserFreeHead;
2975 pPool->iUserFreeHead = i;
2976 return;
2977 }
2978
2979 /* General: Linear search. */
2980 uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2981 while (i != NIL_PGMPOOL_USER_INDEX)
2982 {
2983 if ( paUsers[i].iUser == iUser
2984 && paUsers[i].iUserTable == iUserTable)
2985 {
2986 if (iPrev != NIL_PGMPOOL_USER_INDEX)
2987 paUsers[iPrev].iNext = paUsers[i].iNext;
2988 else
2989 pPage->iUserHead = paUsers[i].iNext;
2990
2991 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2992 paUsers[i].iNext = pPool->iUserFreeHead;
2993 pPool->iUserFreeHead = i;
2994 return;
2995 }
2996 iPrev = i;
2997 i = paUsers[i].iNext;
2998 }
2999
3000 /* Fatal: didn't find it */
3001 AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
3002 iUser, iUserTable, pPage->GCPhys));
3003}
3004
3005
3006/**
3007 * Gets the entry size of a shadow table.
3008 *
3009 * @param enmKind The kind of page.
3010 *
3011 * @returns The size of the entry in bytes. That is, 4 or 8.
3012 * @returns If the kind is not for a table, an assertion is raised and 0 is
3013 * returned.
3014 */
3015DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
3016{
3017 switch (enmKind)
3018 {
3019 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3020 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3021 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3022 case PGMPOOLKIND_32BIT_PD:
3023 case PGMPOOLKIND_32BIT_PD_PHYS:
3024 return 4;
3025
3026 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3027 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3028 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3029 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3030 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3031 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3032 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3033 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3034 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3035 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3036 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3037 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3038 case PGMPOOLKIND_64BIT_PML4:
3039 case PGMPOOLKIND_PAE_PDPT:
3040 case PGMPOOLKIND_ROOT_NESTED:
3041 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3042 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3043 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3044 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3045 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3046 case PGMPOOLKIND_PAE_PD_PHYS:
3047 case PGMPOOLKIND_PAE_PDPT_PHYS:
3048 return 8;
3049
3050 default:
3051 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3052 }
3053}
3054
3055
3056/**
3057 * Gets the entry size of a guest table.
3058 *
3059 * @param enmKind The kind of page.
3060 *
3061 * @returns The size of the entry in bytes. That is, 0, 4 or 8.
3062 * @returns If the kind is not for a table, an assertion is raised and 0 is
3063 * returned.
3064 */
3065DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
3066{
3067 switch (enmKind)
3068 {
3069 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3070 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3071 case PGMPOOLKIND_32BIT_PD:
3072 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3073 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3074 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3075 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3076 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3077 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3078 return 4;
3079
3080 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3081 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3082 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3083 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3084 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3085 case PGMPOOLKIND_64BIT_PML4:
3086 case PGMPOOLKIND_PAE_PDPT:
3087 return 8;
3088
3089 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3090 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3091 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3092 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3093 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3094 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3095 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3096 case PGMPOOLKIND_ROOT_NESTED:
3097 case PGMPOOLKIND_PAE_PD_PHYS:
3098 case PGMPOOLKIND_PAE_PDPT_PHYS:
3099 case PGMPOOLKIND_32BIT_PD_PHYS:
3100 /** @todo can we return 0? (nobody is calling this...) */
3101 AssertFailed();
3102 return 0;
3103
3104 default:
3105 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3106 }
3107}
3108
3109#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3110
3111/**
3112 * Scans one shadow page table for mappings of a physical page.
3113 *
3114 * @returns true/false indicating removal of all relevant PTEs
3115 * @param pVM The VM handle.
3116 * @param pPhysPage The guest page in question.
3117 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3118 * @param iShw The shadow page table.
3119 * @param cRefs The number of references made in that PT.
3120 * @param pfKeptPTEs Flag indicating removal of all relevant PTEs (out)
3121 */
3122static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
3123{
3124 LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
3125 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3126 bool bRet = false;
3127
3128 /*
3129 * Assert sanity.
3130 */
3131 Assert(cRefs == 1);
3132 AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
3133 PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
3134
3135 /*
3136 * Then, clear the actual mappings to the page in the shadow PT.
3137 */
3138 switch (pPage->enmKind)
3139 {
3140 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3141 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3142 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3143 {
3144 const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3145 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3146 uint32_t u32AndMask, u32OrMask;
3147
3148 u32AndMask = 0;
3149 u32OrMask = 0;
3150
3151 if (!fFlushPTEs)
3152 {
3153 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3154 {
3155 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3156 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3157 u32OrMask = X86_PTE_RW;
3158 u32AndMask = UINT32_MAX;
3159 bRet = true;
3160 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3161 break;
3162
3163 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3164 u32OrMask = 0;
3165 u32AndMask = ~X86_PTE_RW;
3166 bRet = true;
3167 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3168 break;
3169 default:
3170 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3171 break;
3172 }
3173 }
3174 else
3175 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3176
3177 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3178 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3179 {
3180 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
3181 pPT->a[i].u = (pPT->a[i].u & u32AndMask) | u32OrMask;
3182 cRefs--;
3183 if (!cRefs)
3184 return bRet;
3185 }
3186#ifdef LOG_ENABLED
3187 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3188 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3189 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3190 {
3191 Log(("i=%d cRefs=%d\n", i, cRefs--));
3192 }
3193#endif
3194 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3195 break;
3196 }
3197
3198 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3199 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3200 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3201 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3202 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3203 {
3204 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3205 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3206 uint64_t u64AndMask, u64OrMask;
3207
3208 u64OrMask = 0;
3209 u64AndMask = 0;
3210 if (!fFlushPTEs)
3211 {
3212 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3213 {
3214 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3215 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3216 u64OrMask = X86_PTE_RW;
3217 u64AndMask = UINT64_MAX;
3218 bRet = true;
3219 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3220 break;
3221
3222 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3223 u64OrMask = 0;
3224 u64AndMask = ~((uint64_t)X86_PTE_RW);
3225 bRet = true;
3226 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3227 break;
3228
3229 default:
3230 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3231 break;
3232 }
3233 }
3234 else
3235 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3236
3237 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3238 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3239 {
3240 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3241 pPT->a[i].u = (pPT->a[i].u & u64AndMask) | u64OrMask;
3242 cRefs--;
3243 if (!cRefs)
3244 return bRet;
3245 }
3246#ifdef LOG_ENABLED
3247 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3248 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3249 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3250 {
3251 Log(("i=%d cRefs=%d\n", i, cRefs--));
3252 }
3253#endif
3254 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
3255 break;
3256 }
3257
3258 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3259 {
3260 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3261 PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3262 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3263 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3264 {
3265 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
3266 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3267 pPT->a[i].u = 0;
3268 cRefs--;
3269 if (!cRefs)
3270 return bRet;
3271 }
3272#ifdef LOG_ENABLED
3273 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3274 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3275 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3276 {
3277 Log(("i=%d cRefs=%d\n", i, cRefs--));
3278 }
3279#endif
3280 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3281 break;
3282 }
3283
3284 default:
3285 AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3286 }
3287 return bRet;
3288}
3289
3290
3291/**
3292 * Scans one shadow page table for mappings of a physical page.
3293 *
3294 * @param pVM The VM handle.
3295 * @param pPhysPage The guest page in question.
3296 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3297 * @param iShw The shadow page table.
3298 * @param cRefs The number of references made in that PT.
3299 */
3300static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
3301{
3302 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3303
3304 LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
3305 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3306 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, cRefs);
3307 if (!fKeptPTEs)
3308 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3309 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3310}
3311
3312
3313/**
3314 * Flushes a list of shadow page tables mapping the same physical page.
3315 *
3316 * @param pVM The VM handle.
3317 * @param pPhysPage The guest page in question.
3318 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3319 * @param iPhysExt The physical cross reference extent list to flush.
3320 */
3321static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3322{
3323 Assert(PGMIsLockOwner(pVM));
3324 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3325 bool fKeepList = false;
3326
3327 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3328 LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3329
3330 const uint16_t iPhysExtStart = iPhysExt;
3331 PPGMPOOLPHYSEXT pPhysExt;
3332 do
3333 {
3334 Assert(iPhysExt < pPool->cMaxPhysExts);
3335 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3336 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3337 {
3338 if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3339 {
3340 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], 1);
3341 if (!fKeptPTEs)
3342 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3343 else
3344 fKeepList = true;
3345 }
3346 }
3347 /* next */
3348 iPhysExt = pPhysExt->iNext;
3349 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3350
3351 if (!fKeepList)
3352 {
3353 /* insert the list into the free list and clear the ram range entry. */
3354 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3355 pPool->iPhysExtFreeHead = iPhysExtStart;
3356 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3357 }
3358
3359 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3360}
3361
3362#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3363
3364/**
3365 * Flushes all shadow page table mappings of the given guest page.
3366 *
3367 * This is typically called when the host page backing the guest one has been
3368 * replaced or when the page protection was changed due to an access handler.
3369 *
3370 * @returns VBox status code.
3371 * @retval VINF_SUCCESS if all references has been successfully cleared.
3372 * @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3373 * pool cleaning. FF and sync flags are set.
3374 *
3375 * @param pVM The VM handle.
3376 * @param pPhysPage The guest page in question.
3377 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3378 * @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3379 * flushed, it is NOT touched if this isn't necessary.
3380 * The caller MUST initialized this to @a false.
3381 */
3382int pgmPoolTrackUpdateGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3383{
3384 PVMCPU pVCpu = VMMGetCpu(pVM);
3385 pgmLock(pVM);
3386 int rc = VINF_SUCCESS;
3387#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3388 const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3389 if (u16)
3390 {
3391 /*
3392 * The zero page is currently screwing up the tracking and we'll
3393 * have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3394 * is defined, zero pages won't normally be mapped. Some kind of solution
3395 * will be needed for this problem of course, but it will have to wait...
3396 */
3397 if (PGM_PAGE_IS_ZERO(pPhysPage))
3398 rc = VINF_PGM_GCPHYS_ALIASED;
3399 else
3400 {
3401# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3402 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3403 pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3404 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3405# endif
3406
3407 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3408 pgmPoolTrackFlushGCPhysPT(pVM,
3409 pPhysPage,
3410 fFlushPTEs,
3411 PGMPOOL_TD_GET_IDX(u16),
3412 PGMPOOL_TD_GET_CREFS(u16));
3413 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3414 pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3415 else
3416 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3417 *pfFlushTLBs = true;
3418
3419# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3420 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3421# endif
3422 }
3423 }
3424
3425#elif defined(PGMPOOL_WITH_CACHE)
3426 if (PGM_PAGE_IS_ZERO(pPhysPage))
3427 rc = VINF_PGM_GCPHYS_ALIASED;
3428 else
3429 {
3430# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3431 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kills the pool otherwise. */
3432 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3433# endif
3434 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3435 if (rc == VINF_SUCCESS)
3436 *pfFlushTLBs = true;
3437 }
3438
3439# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3440 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3441# endif
3442
3443#else
3444 rc = VINF_PGM_GCPHYS_ALIASED;
3445#endif
3446
3447 if (rc == VINF_PGM_GCPHYS_ALIASED)
3448 {
3449 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3450 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3451 rc = VINF_PGM_SYNC_CR3;
3452 }
3453 pgmUnlock(pVM);
3454 return rc;
3455}
3456
3457
3458/**
3459 * Scans all shadow page tables for mappings of a physical page.
3460 *
3461 * This may be slow, but it's most likely more efficient than cleaning
3462 * out the entire page pool / cache.
3463 *
3464 * @returns VBox status code.
3465 * @retval VINF_SUCCESS if all references has been successfully cleared.
3466 * @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3467 * a page pool cleaning.
3468 *
3469 * @param pVM The VM handle.
3470 * @param pPhysPage The guest page in question.
3471 */
3472int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3473{
3474 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3475 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3476 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3477 pPool->cUsedPages, pPool->cPresent, pPhysPage));
3478
3479#if 1
3480 /*
3481 * There is a limit to what makes sense.
3482 */
3483 if (pPool->cPresent > 1024)
3484 {
3485 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3486 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3487 return VINF_PGM_GCPHYS_ALIASED;
3488 }
3489#endif
3490
3491 /*
3492 * Iterate all the pages until we've encountered all that in use.
3493 * This is simple but not quite optimal solution.
3494 */
3495 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3496 const uint32_t u32 = u64;
3497 unsigned cLeft = pPool->cUsedPages;
3498 unsigned iPage = pPool->cCurPages;
3499 while (--iPage >= PGMPOOL_IDX_FIRST)
3500 {
3501 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3502 if (pPage->GCPhys != NIL_RTGCPHYS)
3503 {
3504 switch (pPage->enmKind)
3505 {
3506 /*
3507 * We only care about shadow page tables.
3508 */
3509 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3510 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3511 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3512 {
3513 unsigned cPresent = pPage->cPresent;
3514 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3515 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3516 if (pPT->a[i].n.u1Present)
3517 {
3518 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3519 {
3520 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3521 pPT->a[i].u = 0;
3522 }
3523 if (!--cPresent)
3524 break;
3525 }
3526 break;
3527 }
3528
3529 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3530 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3531 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3532 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3533 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3534 {
3535 unsigned cPresent = pPage->cPresent;
3536 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3537 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3538 if (pPT->a[i].n.u1Present)
3539 {
3540 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3541 {
3542 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3543 pPT->a[i].u = 0;
3544 }
3545 if (!--cPresent)
3546 break;
3547 }
3548 break;
3549 }
3550 }
3551 if (!--cLeft)
3552 break;
3553 }
3554 }
3555
3556 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3557 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3558 return VINF_SUCCESS;
3559}
3560
3561
3562/**
3563 * Clears the user entry in a user table.
3564 *
3565 * This is used to remove all references to a page when flushing it.
3566 */
3567static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3568{
3569 Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3570 Assert(pUser->iUser < pPool->cCurPages);
3571 uint32_t iUserTable = pUser->iUserTable;
3572
3573 /*
3574 * Map the user page.
3575 */
3576 PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3577 union
3578 {
3579 uint64_t *pau64;
3580 uint32_t *pau32;
3581 } u;
3582 u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3583
3584 LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3585
3586 /* Safety precaution in case we change the paging for other modes too in the future. */
3587 Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
3588
3589#ifdef VBOX_STRICT
3590 /*
3591 * Some sanity checks.
3592 */
3593 switch (pUserPage->enmKind)
3594 {
3595 case PGMPOOLKIND_32BIT_PD:
3596 case PGMPOOLKIND_32BIT_PD_PHYS:
3597 Assert(iUserTable < X86_PG_ENTRIES);
3598 break;
3599 case PGMPOOLKIND_PAE_PDPT:
3600 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3601 case PGMPOOLKIND_PAE_PDPT_PHYS:
3602 Assert(iUserTable < 4);
3603 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3604 break;
3605 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3606 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3607 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3608 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3609 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3610 case PGMPOOLKIND_PAE_PD_PHYS:
3611 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3612 break;
3613 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3614 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3615 Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3616 break;
3617 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3618 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3619 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3620 break;
3621 case PGMPOOLKIND_64BIT_PML4:
3622 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3623 /* GCPhys >> PAGE_SHIFT is the index here */
3624 break;
3625 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3626 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3627 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3628 break;
3629
3630 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3631 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3632 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3633 break;
3634
3635 case PGMPOOLKIND_ROOT_NESTED:
3636 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3637 break;
3638
3639 default:
3640 AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3641 break;
3642 }
3643#endif /* VBOX_STRICT */
3644
3645 /*
3646 * Clear the entry in the user page.
3647 */
3648 switch (pUserPage->enmKind)
3649 {
3650 /* 32-bit entries */
3651 case PGMPOOLKIND_32BIT_PD:
3652 case PGMPOOLKIND_32BIT_PD_PHYS:
3653 u.pau32[iUserTable] = 0;
3654 break;
3655
3656 /* 64-bit entries */
3657 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3658 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3659 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3660 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3661 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3662#if defined(IN_RC)
3663 /* In 32 bits PAE mode we *must* invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
3664 * non-present PDPT will continue to cause page faults.
3665 */
3666 ASMReloadCR3();
3667#endif
3668 /* no break */
3669 case PGMPOOLKIND_PAE_PD_PHYS:
3670 case PGMPOOLKIND_PAE_PDPT_PHYS:
3671 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3672 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3673 case PGMPOOLKIND_64BIT_PML4:
3674 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3675 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3676 case PGMPOOLKIND_PAE_PDPT:
3677 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3678 case PGMPOOLKIND_ROOT_NESTED:
3679 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3680 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3681 u.pau64[iUserTable] = 0;
3682 break;
3683
3684 default:
3685 AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3686 }
3687}
3688
3689
3690/**
3691 * Clears all users of a page.
3692 */
3693static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3694{
3695 /*
3696 * Free all the user records.
3697 */
3698 LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3699
3700 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3701 uint16_t i = pPage->iUserHead;
3702 while (i != NIL_PGMPOOL_USER_INDEX)
3703 {
3704 /* Clear enter in user table. */
3705 pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3706
3707 /* Free it. */
3708 const uint16_t iNext = paUsers[i].iNext;
3709 paUsers[i].iUser = NIL_PGMPOOL_IDX;
3710 paUsers[i].iNext = pPool->iUserFreeHead;
3711 pPool->iUserFreeHead = i;
3712
3713 /* Next. */
3714 i = iNext;
3715 }
3716 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3717}
3718
3719#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3720
3721/**
3722 * Allocates a new physical cross reference extent.
3723 *
3724 * @returns Pointer to the allocated extent on success. NULL if we're out of them.
3725 * @param pVM The VM handle.
3726 * @param piPhysExt Where to store the phys ext index.
3727 */
3728PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3729{
3730 Assert(PGMIsLockOwner(pVM));
3731 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3732 uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3733 if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3734 {
3735 STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3736 return NULL;
3737 }
3738 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3739 pPool->iPhysExtFreeHead = pPhysExt->iNext;
3740 pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3741 *piPhysExt = iPhysExt;
3742 return pPhysExt;
3743}
3744
3745
3746/**
3747 * Frees a physical cross reference extent.
3748 *
3749 * @param pVM The VM handle.
3750 * @param iPhysExt The extent to free.
3751 */
3752void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3753{
3754 Assert(PGMIsLockOwner(pVM));
3755 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3756 Assert(iPhysExt < pPool->cMaxPhysExts);
3757 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3758 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3759 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3760 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3761 pPool->iPhysExtFreeHead = iPhysExt;
3762}
3763
3764
3765/**
3766 * Frees a physical cross reference extent.
3767 *
3768 * @param pVM The VM handle.
3769 * @param iPhysExt The extent to free.
3770 */
3771void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3772{
3773 Assert(PGMIsLockOwner(pVM));
3774 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3775
3776 const uint16_t iPhysExtStart = iPhysExt;
3777 PPGMPOOLPHYSEXT pPhysExt;
3778 do
3779 {
3780 Assert(iPhysExt < pPool->cMaxPhysExts);
3781 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3782 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3783 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3784
3785 /* next */
3786 iPhysExt = pPhysExt->iNext;
3787 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3788
3789 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3790 pPool->iPhysExtFreeHead = iPhysExtStart;
3791}
3792
3793
3794/**
3795 * Insert a reference into a list of physical cross reference extents.
3796 *
3797 * @returns The new tracking data for PGMPAGE.
3798 *
3799 * @param pVM The VM handle.
3800 * @param iPhysExt The physical extent index of the list head.
3801 * @param iShwPT The shadow page table index.
3802 *
3803 */
3804static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3805{
3806 Assert(PGMIsLockOwner(pVM));
3807 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3808 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3809
3810 /* special common case. */
3811 if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3812 {
3813 paPhysExts[iPhysExt].aidx[2] = iShwPT;
3814 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3815 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d}\n", iPhysExt, iShwPT));
3816 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3817 }
3818
3819 /* general treatment. */
3820 const uint16_t iPhysExtStart = iPhysExt;
3821 unsigned cMax = 15;
3822 for (;;)
3823 {
3824 Assert(iPhysExt < pPool->cMaxPhysExts);
3825 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3826 if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3827 {
3828 paPhysExts[iPhysExt].aidx[i] = iShwPT;
3829 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3830 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3831 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3832 }
3833 if (!--cMax)
3834 {
3835 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3836 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3837 LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3838 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3839 }
3840 }
3841
3842 /* add another extent to the list. */
3843 PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3844 if (!pNew)
3845 {
3846 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3847 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3848 LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3849 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3850 }
3851 pNew->iNext = iPhysExtStart;
3852 pNew->aidx[0] = iShwPT;
3853 LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3854 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3855}
3856
3857
3858/**
3859 * Add a reference to guest physical page where extents are in use.
3860 *
3861 * @returns The new tracking data for PGMPAGE.
3862 *
3863 * @param pVM The VM handle.
3864 * @param u16 The ram range flags (top 16-bits).
3865 * @param iShwPT The shadow page table index.
3866 */
3867uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3868{
3869 pgmLock(pVM);
3870 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3871 {
3872 /*
3873 * Convert to extent list.
3874 */
3875 Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3876 uint16_t iPhysExt;
3877 PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3878 if (pPhysExt)
3879 {
3880 LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3881 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3882 pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3883 pPhysExt->aidx[1] = iShwPT;
3884 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3885 }
3886 else
3887 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3888 }
3889 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3890 {
3891 /*
3892 * Insert into the extent list.
3893 */
3894 u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3895 }
3896 else
3897 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3898 pgmUnlock(pVM);
3899 return u16;
3900}
3901
3902
3903/**
3904 * Clear references to guest physical memory.
3905 *
3906 * @param pPool The pool.
3907 * @param pPage The page.
3908 * @param pPhysPage Pointer to the aPages entry in the ram range.
3909 */
3910void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3911{
3912 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3913 AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3914
3915 uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3916 if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3917 {
3918 PVM pVM = pPool->CTX_SUFF(pVM);
3919 pgmLock(pVM);
3920
3921 uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3922 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3923 do
3924 {
3925 Assert(iPhysExt < pPool->cMaxPhysExts);
3926
3927 /*
3928 * Look for the shadow page and check if it's all freed.
3929 */
3930 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3931 {
3932 if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3933 {
3934 paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3935
3936 for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3937 if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3938 {
3939 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3940 pgmUnlock(pVM);
3941 return;
3942 }
3943
3944 /* we can free the node. */
3945 const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3946 if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3947 && iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3948 {
3949 /* lonely node */
3950 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3951 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3952 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3953 }
3954 else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3955 {
3956 /* head */
3957 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3958 PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3959 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3960 }
3961 else
3962 {
3963 /* in list */
3964 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3965 paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3966 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3967 }
3968 iPhysExt = iPhysExtNext;
3969 pgmUnlock(pVM);
3970 return;
3971 }
3972 }
3973
3974 /* next */
3975 iPhysExtPrev = iPhysExt;
3976 iPhysExt = paPhysExts[iPhysExt].iNext;
3977 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3978
3979 pgmUnlock(pVM);
3980 AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3981 }
3982 else /* nothing to do */
3983 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3984}
3985
3986
3987/**
3988 * Clear references to guest physical memory.
3989 *
3990 * This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3991 * is assumed to be correct, so the linear search can be skipped and we can assert
3992 * at an earlier point.
3993 *
3994 * @param pPool The pool.
3995 * @param pPage The page.
3996 * @param HCPhys The host physical address corresponding to the guest page.
3997 * @param GCPhys The guest physical address corresponding to HCPhys.
3998 */
3999static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
4000{
4001 /*
4002 * Walk range list.
4003 */
4004 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4005 while (pRam)
4006 {
4007 RTGCPHYS off = GCPhys - pRam->GCPhys;
4008 if (off < pRam->cb)
4009 {
4010 /* does it match? */
4011 const unsigned iPage = off >> PAGE_SHIFT;
4012 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4013#ifdef LOG_ENABLED
4014RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
4015Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
4016#endif
4017 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4018 {
4019 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
4020 return;
4021 }
4022 break;
4023 }
4024 pRam = pRam->CTX_SUFF(pNext);
4025 }
4026 AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4027}
4028
4029
4030/**
4031 * Clear references to guest physical memory.
4032 *
4033 * @param pPool The pool.
4034 * @param pPage The page.
4035 * @param HCPhys The host physical address corresponding to the guest page.
4036 * @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4037 */
4038void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
4039{
4040 Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4041
4042 /*
4043 * Walk range list.
4044 */
4045 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4046 while (pRam)
4047 {
4048 RTGCPHYS off = GCPhysHint - pRam->GCPhys;
4049 if (off < pRam->cb)
4050 {
4051 /* does it match? */
4052 const unsigned iPage = off >> PAGE_SHIFT;
4053 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4054 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4055 {
4056 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
4057 return;
4058 }
4059 break;
4060 }
4061 pRam = pRam->CTX_SUFF(pNext);
4062 }
4063
4064 /*
4065 * Damn, the hint didn't work. We'll have to do an expensive linear search.
4066 */
4067 STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4068 pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4069 while (pRam)
4070 {
4071 unsigned iPage = pRam->cb >> PAGE_SHIFT;
4072 while (iPage-- > 0)
4073 {
4074 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4075 {
4076 Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4077 HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4078 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
4079 return;
4080 }
4081 }
4082 pRam = pRam->CTX_SUFF(pNext);
4083 }
4084
4085 AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
4086}
4087
4088
4089/**
4090 * Clear references to guest physical memory in a 32-bit / 32-bit page table.
4091 *
4092 * @param pPool The pool.
4093 * @param pPage The page.
4094 * @param pShwPT The shadow page table (mapping of the page).
4095 * @param pGstPT The guest page table.
4096 */
4097DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4098{
4099 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4100 if (pShwPT->a[i].n.u1Present)
4101 {
4102 Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4103 i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4104 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
4105 if (!--pPage->cPresent)
4106 break;
4107 }
4108}
4109
4110
4111/**
4112 * Clear references to guest physical memory in a PAE / 32-bit page table.
4113 *
4114 * @param pPool The pool.
4115 * @param pPage The page.
4116 * @param pShwPT The shadow page table (mapping of the page).
4117 * @param pGstPT The guest page table (just a half one).
4118 */
4119DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
4120{
4121 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4122 if (pShwPT->a[i].n.u1Present)
4123 {
4124 Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4125 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4126 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
4127 if (!--pPage->cPresent)
4128 break;
4129 }
4130}
4131
4132
4133/**
4134 * Clear references to guest physical memory in a PAE / PAE page table.
4135 *
4136 * @param pPool The pool.
4137 * @param pPage The page.
4138 * @param pShwPT The shadow page table (mapping of the page).
4139 * @param pGstPT The guest page table.
4140 */
4141DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
4142{
4143 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4144 if (pShwPT->a[i].n.u1Present)
4145 {
4146 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4147 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4148 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
4149 if (!--pPage->cPresent)
4150 break;
4151 }
4152}
4153
4154
4155/**
4156 * Clear references to guest physical memory in a 32-bit / 4MB page table.
4157 *
4158 * @param pPool The pool.
4159 * @param pPage The page.
4160 * @param pShwPT The shadow page table (mapping of the page).
4161 */
4162DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4163{
4164 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4165 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4166 if (pShwPT->a[i].n.u1Present)
4167 {
4168 Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4169 i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4170 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
4171 if (!--pPage->cPresent)
4172 break;
4173 }
4174}
4175
4176
4177/**
4178 * Clear references to guest physical memory in a PAE / 2/4MB page table.
4179 *
4180 * @param pPool The pool.
4181 * @param pPage The page.
4182 * @param pShwPT The shadow page table (mapping of the page).
4183 */
4184DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
4185{
4186 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4187 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4188 if (pShwPT->a[i].n.u1Present)
4189 {
4190 Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4191 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
4192 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
4193 if (!--pPage->cPresent)
4194 break;
4195 }
4196}
4197
4198
4199/**
4200 * Clear references to shadowed pages in an EPT page table.
4201 *
4202 * @param pPool The pool.
4203 * @param pPage The page.
4204 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4205 */
4206DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4207{
4208 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4209 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4210 if (pShwPT->a[i].n.u1Present)
4211 {
4212 Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4213 i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4214 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
4215 if (!--pPage->cPresent)
4216 break;
4217 }
4218}
4219
4220#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4221
4222
4223/**
4224 * Clear references to shadowed pages in a 32 bits page directory.
4225 *
4226 * @param pPool The pool.
4227 * @param pPage The page.
4228 * @param pShwPD The shadow page directory (mapping of the page).
4229 */
4230DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4231{
4232 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4233 {
4234 if ( pShwPD->a[i].n.u1Present
4235 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4236 )
4237 {
4238 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4239 if (pSubPage)
4240 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4241 else
4242 AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4243 }
4244 }
4245}
4246
4247/**
4248 * Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4249 *
4250 * @param pPool The pool.
4251 * @param pPage The page.
4252 * @param pShwPD The shadow page directory (mapping of the page).
4253 */
4254DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4255{
4256 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4257 {
4258 if ( pShwPD->a[i].n.u1Present
4259 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4260 )
4261 {
4262 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4263 if (pSubPage)
4264 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4265 else
4266 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4267 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4268 }
4269 }
4270}
4271
4272/**
4273 * Clear references to shadowed pages in a PAE page directory pointer table.
4274 *
4275 * @param pPool The pool.
4276 * @param pPage The page.
4277 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4278 */
4279DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4280{
4281 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4282 {
4283 if ( pShwPDPT->a[i].n.u1Present
4284 && !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4285 )
4286 {
4287 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4288 if (pSubPage)
4289 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4290 else
4291 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4292 }
4293 }
4294}
4295
4296
4297/**
4298 * Clear references to shadowed pages in a 64-bit page directory pointer table.
4299 *
4300 * @param pPool The pool.
4301 * @param pPage The page.
4302 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4303 */
4304DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4305{
4306 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4307 {
4308 Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
4309 if (pShwPDPT->a[i].n.u1Present)
4310 {
4311 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4312 if (pSubPage)
4313 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4314 else
4315 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4316 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4317 }
4318 }
4319}
4320
4321
4322/**
4323 * Clear references to shadowed pages in a 64-bit level 4 page table.
4324 *
4325 * @param pPool The pool.
4326 * @param pPage The page.
4327 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4328 */
4329DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4330{
4331 for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4332 {
4333 if (pShwPML4->a[i].n.u1Present)
4334 {
4335 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4336 if (pSubPage)
4337 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4338 else
4339 AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4340 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4341 }
4342 }
4343}
4344
4345
4346/**
4347 * Clear references to shadowed pages in an EPT page directory.
4348 *
4349 * @param pPool The pool.
4350 * @param pPage The page.
4351 * @param pShwPD The shadow page directory (mapping of the page).
4352 */
4353DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4354{
4355 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4356 {
4357 if (pShwPD->a[i].n.u1Present)
4358 {
4359 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4360 if (pSubPage)
4361 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4362 else
4363 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4364 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4365 }
4366 }
4367}
4368
4369
4370/**
4371 * Clear references to shadowed pages in an EPT page directory pointer table.
4372 *
4373 * @param pPool The pool.
4374 * @param pPage The page.
4375 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4376 */
4377DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4378{
4379 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4380 {
4381 if (pShwPDPT->a[i].n.u1Present)
4382 {
4383 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4384 if (pSubPage)
4385 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4386 else
4387 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4388 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4389 }
4390 }
4391}
4392
4393
4394/**
4395 * Clears all references made by this page.
4396 *
4397 * This includes other shadow pages and GC physical addresses.
4398 *
4399 * @param pPool The pool.
4400 * @param pPage The page.
4401 */
4402static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4403{
4404 /*
4405 * Map the shadow page and take action according to the page kind.
4406 */
4407 void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
4408 switch (pPage->enmKind)
4409 {
4410#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4411 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4412 {
4413 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4414 void *pvGst;
4415 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4416 pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4417 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4418 break;
4419 }
4420
4421 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4422 {
4423 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4424 void *pvGst;
4425 int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4426 pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
4427 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4428 break;
4429 }
4430
4431 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4432 {
4433 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4434 void *pvGst;
4435 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4436 pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
4437 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4438 break;
4439 }
4440
4441 case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4442 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4443 {
4444 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4445 pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4446 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4447 break;
4448 }
4449
4450 case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4451 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4452 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4453 {
4454 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4455 pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
4456 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4457 break;
4458 }
4459
4460#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
4461 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4462 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4463 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4464 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4465 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4466 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4467 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4468 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4469 break;
4470#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
4471
4472 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4473 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4474 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4475 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4476 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4477 case PGMPOOLKIND_PAE_PD_PHYS:
4478 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4479 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4480 pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4481 break;
4482
4483 case PGMPOOLKIND_32BIT_PD_PHYS:
4484 case PGMPOOLKIND_32BIT_PD:
4485 pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4486 break;
4487
4488 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4489 case PGMPOOLKIND_PAE_PDPT:
4490 case PGMPOOLKIND_PAE_PDPT_PHYS:
4491 pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4492 break;
4493
4494 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4495 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4496 pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4497 break;
4498
4499 case PGMPOOLKIND_64BIT_PML4:
4500 pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4501 break;
4502
4503 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4504 pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4505 break;
4506
4507 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4508 pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4509 break;
4510
4511 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4512 pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4513 break;
4514
4515 default:
4516 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4517 }
4518
4519 /* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4520 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4521 ASMMemZeroPage(pvShw);
4522 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4523 pPage->fZeroed = true;
4524 PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
4525}
4526#endif /* PGMPOOL_WITH_USER_TRACKING */
4527
4528/**
4529 * Flushes a pool page.
4530 *
4531 * This moves the page to the free list after removing all user references to it.
4532 *
4533 * @returns VBox status code.
4534 * @retval VINF_SUCCESS on success.
4535 * @param pPool The pool.
4536 * @param HCPhys The HC physical address of the shadow page.
4537 */
4538int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4539{
4540 PVM pVM = pPool->CTX_SUFF(pVM);
4541
4542 int rc = VINF_SUCCESS;
4543 STAM_PROFILE_START(&pPool->StatFlushPage, f);
4544 LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4545 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4546
4547 /*
4548 * Quietly reject any attempts at flushing any of the special root pages.
4549 */
4550 if (pPage->idx < PGMPOOL_IDX_FIRST)
4551 {
4552 AssertFailed(); /* can no longer happen */
4553 Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4554 return VINF_SUCCESS;
4555 }
4556
4557 pgmLock(pVM);
4558
4559 /*
4560 * Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4561 */
4562 if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4563 {
4564 AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4565 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4566 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4567 || pPage->enmKind == PGMPOOLKIND_32BIT_PD
4568 || pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4569 || pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4570 || pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4571 || pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4572 || pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4573 ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4574 Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4575 pgmUnlock(pVM);
4576 return VINF_SUCCESS;
4577 }
4578
4579#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4580 /* Start a subset so we won't run out of mapping space. */
4581 PVMCPU pVCpu = VMMGetCpu(pVM);
4582 uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
4583#endif
4584
4585 /*
4586 * Mark the page as being in need of an ASMMemZeroPage().
4587 */
4588 pPage->fZeroed = false;
4589
4590#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4591 if (pPage->fDirty)
4592 pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirty, false /* do not remove */);
4593#endif
4594
4595#ifdef PGMPOOL_WITH_USER_TRACKING
4596 /*
4597 * Clear the page.
4598 */
4599 pgmPoolTrackClearPageUsers(pPool, pPage);
4600 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4601 pgmPoolTrackDeref(pPool, pPage);
4602 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4603#endif
4604
4605#ifdef PGMPOOL_WITH_CACHE
4606 /*
4607 * Flush it from the cache.
4608 */
4609 pgmPoolCacheFlushPage(pPool, pPage);
4610#endif /* PGMPOOL_WITH_CACHE */
4611
4612#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4613 /* Heavy stuff done. */
4614 PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
4615#endif
4616
4617#ifdef PGMPOOL_WITH_MONITORING
4618 /*
4619 * Deregistering the monitoring.
4620 */
4621 if (pPage->fMonitored)
4622 rc = pgmPoolMonitorFlush(pPool, pPage);
4623#endif
4624
4625 /*
4626 * Free the page.
4627 */
4628 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4629 pPage->iNext = pPool->iFreeHead;
4630 pPool->iFreeHead = pPage->idx;
4631 pPage->enmKind = PGMPOOLKIND_FREE;
4632 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4633 pPage->GCPhys = NIL_RTGCPHYS;
4634 pPage->fReusedFlushPending = false;
4635
4636 pPool->cUsedPages--;
4637 pgmUnlock(pVM);
4638 STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4639 return rc;
4640}
4641
4642
4643/**
4644 * Frees a usage of a pool page.
4645 *
4646 * The caller is responsible to updating the user table so that it no longer
4647 * references the shadow page.
4648 *
4649 * @param pPool The pool.
4650 * @param HCPhys The HC physical address of the shadow page.
4651 * @param iUser The shadow page pool index of the user table.
4652 * @param iUserTable The index into the user table (shadowed).
4653 */
4654void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4655{
4656 PVM pVM = pPool->CTX_SUFF(pVM);
4657
4658 STAM_PROFILE_START(&pPool->StatFree, a);
4659 LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4660 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4661 Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4662 pgmLock(pVM);
4663#ifdef PGMPOOL_WITH_USER_TRACKING
4664 pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4665#endif
4666#ifdef PGMPOOL_WITH_CACHE
4667 if (!pPage->fCached)
4668#endif
4669 pgmPoolFlushPage(pPool, pPage);
4670 pgmUnlock(pVM);
4671 STAM_PROFILE_STOP(&pPool->StatFree, a);
4672}
4673
4674
4675/**
4676 * Makes one or more free page free.
4677 *
4678 * @returns VBox status code.
4679 * @retval VINF_SUCCESS on success.
4680 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4681 *
4682 * @param pPool The pool.
4683 * @param enmKind Page table kind
4684 * @param iUser The user of the page.
4685 */
4686static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4687{
4688 PVM pVM = pPool->CTX_SUFF(pVM);
4689
4690 LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4691
4692 /*
4693 * If the pool isn't full grown yet, expand it.
4694 */
4695 if ( pPool->cCurPages < pPool->cMaxPages
4696#if defined(IN_RC)
4697 /* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4698 && enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4699 && (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD || enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4700#endif
4701 )
4702 {
4703 STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4704#ifdef IN_RING3
4705 int rc = PGMR3PoolGrow(pVM);
4706#else
4707 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4708#endif
4709 if (RT_FAILURE(rc))
4710 return rc;
4711 STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4712 if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4713 return VINF_SUCCESS;
4714 }
4715
4716#ifdef PGMPOOL_WITH_CACHE
4717 /*
4718 * Free one cached page.
4719 */
4720 return pgmPoolCacheFreeOne(pPool, iUser);
4721#else
4722 /*
4723 * Flush the pool.
4724 *
4725 * If we have tracking enabled, it should be possible to come up with
4726 * a cheap replacement strategy...
4727 */
4728 /* @todo This path no longer works (CR3 root pages will be flushed)!! */
4729 AssertCompileFailed();
4730 Assert(!CPUMIsGuestInLongMode(pVM));
4731 pgmPoolFlushAllInt(pPool);
4732 return VERR_PGM_POOL_FLUSHED;
4733#endif
4734}
4735
4736/**
4737 * Allocates a page from the pool.
4738 *
4739 * This page may actually be a cached page and not in need of any processing
4740 * on the callers part.
4741 *
4742 * @returns VBox status code.
4743 * @retval VINF_SUCCESS if a NEW page was allocated.
4744 * @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4745 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4746 * @param pVM The VM handle.
4747 * @param GCPhys The GC physical address of the page we're gonna shadow.
4748 * For 4MB and 2MB PD entries, it's the first address the
4749 * shadow PT is covering.
4750 * @param enmKind The kind of mapping.
4751 * @param enmAccess Access type for the mapping (only relevant for big pages)
4752 * @param iUser The shadow page pool index of the user table.
4753 * @param iUserTable The index into the user table (shadowed).
4754 * @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4755 * @param fLockPage Lock the page
4756 */
4757int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage)
4758{
4759 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4760 STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4761 LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4762 *ppPage = NULL;
4763 /** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4764 * (TRPMR3SyncIDT) because of FF priority. Try fix that?
4765 * Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4766
4767 pgmLock(pVM);
4768
4769#ifdef PGMPOOL_WITH_CACHE
4770 if (pPool->fCacheEnabled)
4771 {
4772 int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4773 if (RT_SUCCESS(rc2))
4774 {
4775 if (fLockPage)
4776 pgmPoolLockPage(pPool, *ppPage);
4777 pgmUnlock(pVM);
4778 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4779 LogFlow(("pgmPoolAlloc: cached returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, *ppPage, (*ppPage)->Core.Key, (*ppPage)->idx));
4780 return rc2;
4781 }
4782 }
4783#endif
4784
4785 /*
4786 * Allocate a new one.
4787 */
4788 int rc = VINF_SUCCESS;
4789 uint16_t iNew = pPool->iFreeHead;
4790 if (iNew == NIL_PGMPOOL_IDX)
4791 {
4792 rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4793 if (RT_FAILURE(rc))
4794 {
4795 pgmUnlock(pVM);
4796 Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4797 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4798 return rc;
4799 }
4800 iNew = pPool->iFreeHead;
4801 AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4802 }
4803
4804 /* unlink the free head */
4805 PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4806 pPool->iFreeHead = pPage->iNext;
4807 pPage->iNext = NIL_PGMPOOL_IDX;
4808
4809 /*
4810 * Initialize it.
4811 */
4812 pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4813 pPage->enmKind = enmKind;
4814 pPage->enmAccess = enmAccess;
4815 pPage->GCPhys = GCPhys;
4816 pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4817 pPage->fMonitored = false;
4818 pPage->fCached = false;
4819#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4820 pPage->fDirty = false;
4821#endif
4822 pPage->fReusedFlushPending = false;
4823#ifdef PGMPOOL_WITH_MONITORING
4824 pPage->cModifications = 0;
4825 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4826 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4827#else
4828 pPage->fCR3Mix = false;
4829#endif
4830#ifdef PGMPOOL_WITH_USER_TRACKING
4831 pPage->cPresent = 0;
4832 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
4833 pPage->pvLastAccessHandlerFault = 0;
4834 pPage->cLastAccessHandlerCount = 0;
4835 pPage->pvLastAccessHandlerRip = 0;
4836
4837 /*
4838 * Insert into the tracking and cache. If this fails, free the page.
4839 */
4840 int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4841 if (RT_FAILURE(rc3))
4842 {
4843 pPool->cUsedPages--;
4844 pPage->enmKind = PGMPOOLKIND_FREE;
4845 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4846 pPage->GCPhys = NIL_RTGCPHYS;
4847 pPage->iNext = pPool->iFreeHead;
4848 pPool->iFreeHead = pPage->idx;
4849 pgmUnlock(pVM);
4850 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4851 Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4852 return rc3;
4853 }
4854#endif /* PGMPOOL_WITH_USER_TRACKING */
4855
4856 /*
4857 * Commit the allocation, clear the page and return.
4858 */
4859#ifdef VBOX_WITH_STATISTICS
4860 if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4861 pPool->cUsedPagesHigh = pPool->cUsedPages;
4862#endif
4863
4864 if (!pPage->fZeroed)
4865 {
4866 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4867 void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4868 ASMMemZeroPage(pv);
4869 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4870 }
4871
4872 *ppPage = pPage;
4873 if (fLockPage)
4874 pgmPoolLockPage(pPool, pPage);
4875 pgmUnlock(pVM);
4876 LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4877 rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4878 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4879 return rc;
4880}
4881
4882
4883/**
4884 * Frees a usage of a pool page.
4885 *
4886 * @param pVM The VM handle.
4887 * @param HCPhys The HC physical address of the shadow page.
4888 * @param iUser The shadow page pool index of the user table.
4889 * @param iUserTable The index into the user table (shadowed).
4890 */
4891void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4892{
4893 LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4894 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4895 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4896}
4897
4898/**
4899 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4900 *
4901 * @returns Pointer to the shadow page structure.
4902 * @param pPool The pool.
4903 * @param HCPhys The HC physical address of the shadow page.
4904 */
4905PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4906{
4907 PVM pVM = pPool->CTX_SUFF(pVM);
4908
4909 Assert(PGMIsLockOwner(pVM));
4910
4911 /*
4912 * Look up the page.
4913 */
4914 pgmLock(pVM);
4915 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4916 pgmUnlock(pVM);
4917
4918 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4919 return pPage;
4920}
4921
4922#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
4923/**
4924 * Flush the specified page if present
4925 *
4926 * @param pVM The VM handle.
4927 * @param GCPhys Guest physical address of the page to flush
4928 */
4929void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
4930{
4931#ifdef PGMPOOL_WITH_CACHE
4932 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4933
4934 VM_ASSERT_EMT(pVM);
4935
4936 /*
4937 * Look up the GCPhys in the hash.
4938 */
4939 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
4940 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
4941 if (i == NIL_PGMPOOL_IDX)
4942 return;
4943
4944 do
4945 {
4946 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4947 if (pPage->GCPhys - GCPhys < PAGE_SIZE)
4948 {
4949 switch (pPage->enmKind)
4950 {
4951 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4952 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4953 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4954 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4955 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4956 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4957 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4958 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4959 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4960 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4961 case PGMPOOLKIND_64BIT_PML4:
4962 case PGMPOOLKIND_32BIT_PD:
4963 case PGMPOOLKIND_PAE_PDPT:
4964 {
4965 Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
4966#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4967 if (pPage->fDirty)
4968 STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
4969 else
4970#endif
4971 STAM_COUNTER_INC(&pPool->StatForceFlushPage);
4972 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
4973 pgmPoolMonitorChainFlush(pPool, pPage);
4974 return;
4975 }
4976
4977 /* ignore, no monitoring. */
4978 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4979 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4980 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4981 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4982 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4983 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4984 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4985 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4986 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4987 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4988 case PGMPOOLKIND_ROOT_NESTED:
4989 case PGMPOOLKIND_PAE_PD_PHYS:
4990 case PGMPOOLKIND_PAE_PDPT_PHYS:
4991 case PGMPOOLKIND_32BIT_PD_PHYS:
4992 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4993 break;
4994
4995 default:
4996 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
4997 }
4998 }
4999
5000 /* next */
5001 i = pPage->iNext;
5002 } while (i != NIL_PGMPOOL_IDX);
5003#endif
5004 return;
5005}
5006#endif /* IN_RING3 */
5007
5008#ifdef IN_RING3
5009/**
5010 * Flushes the entire cache.
5011 *
5012 * It will assert a global CR3 flush (FF) and assumes the caller is aware of this
5013 * and execute this CR3 flush.
5014 *
5015 * @param pPool The pool.
5016 */
5017void pgmR3PoolReset(PVM pVM)
5018{
5019 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5020
5021 Assert(PGMIsLockOwner(pVM));
5022 STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
5023 LogFlow(("pgmPoolFlushAllInt:\n"));
5024
5025 /*
5026 * If there are no pages in the pool, there is nothing to do.
5027 */
5028 if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5029 {
5030 STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
5031 return;
5032 }
5033
5034 /*
5035 * Exit the shadow mode since we're going to clear everything,
5036 * including the root page.
5037 */
5038 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5039 {
5040 PVMCPU pVCpu = &pVM->aCpus[i];
5041 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
5042 }
5043
5044 /*
5045 * Nuke the free list and reinsert all pages into it.
5046 */
5047 for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5048 {
5049 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5050
5051 Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
5052#ifdef PGMPOOL_WITH_MONITORING
5053 if (pPage->fMonitored)
5054 pgmPoolMonitorFlush(pPool, pPage);
5055 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5056 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5057 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5058 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5059 pPage->cModifications = 0;
5060#endif
5061 pPage->GCPhys = NIL_RTGCPHYS;
5062 pPage->enmKind = PGMPOOLKIND_FREE;
5063 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5064 Assert(pPage->idx == i);
5065 pPage->iNext = i + 1;
5066 pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5067 pPage->fSeenNonGlobal = false;
5068 pPage->fMonitored = false;
5069#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5070 pPage->fDirty = false;
5071#endif
5072 pPage->fCached = false;
5073 pPage->fReusedFlushPending = false;
5074#ifdef PGMPOOL_WITH_USER_TRACKING
5075 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5076#else
5077 pPage->fCR3Mix = false;
5078#endif
5079#ifdef PGMPOOL_WITH_CACHE
5080 pPage->iAgeNext = NIL_PGMPOOL_IDX;
5081 pPage->iAgePrev = NIL_PGMPOOL_IDX;
5082#endif
5083 pPage->cLocked = 0;
5084 }
5085 pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5086 pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5087 pPool->cUsedPages = 0;
5088
5089#ifdef PGMPOOL_WITH_USER_TRACKING
5090 /*
5091 * Zap and reinitialize the user records.
5092 */
5093 pPool->cPresent = 0;
5094 pPool->iUserFreeHead = 0;
5095 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5096 const unsigned cMaxUsers = pPool->cMaxUsers;
5097 for (unsigned i = 0; i < cMaxUsers; i++)
5098 {
5099 paUsers[i].iNext = i + 1;
5100 paUsers[i].iUser = NIL_PGMPOOL_IDX;
5101 paUsers[i].iUserTable = 0xfffffffe;
5102 }
5103 paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5104#endif
5105
5106#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
5107 /*
5108 * Clear all the GCPhys links and rebuild the phys ext free list.
5109 */
5110 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
5111 pRam;
5112 pRam = pRam->CTX_SUFF(pNext))
5113 {
5114 unsigned iPage = pRam->cb >> PAGE_SHIFT;
5115 while (iPage-- > 0)
5116 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
5117 }
5118
5119 pPool->iPhysExtFreeHead = 0;
5120 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5121 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5122 for (unsigned i = 0; i < cMaxPhysExts; i++)
5123 {
5124 paPhysExts[i].iNext = i + 1;
5125 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5126 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5127 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5128 }
5129 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5130#endif
5131
5132#ifdef PGMPOOL_WITH_MONITORING
5133 /*
5134 * Just zap the modified list.
5135 */
5136 pPool->cModifiedPages = 0;
5137 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5138#endif
5139
5140#ifdef PGMPOOL_WITH_CACHE
5141 /*
5142 * Clear the GCPhys hash and the age list.
5143 */
5144 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5145 pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5146 pPool->iAgeHead = NIL_PGMPOOL_IDX;
5147 pPool->iAgeTail = NIL_PGMPOOL_IDX;
5148#endif
5149
5150#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5151 /* Clear all dirty pages. */
5152 pPool->idxFreeDirtyPage = 0;
5153 pPool->cDirtyPages = 0;
5154 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
5155 pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
5156#endif
5157
5158 /*
5159 * Reinsert active pages into the hash and ensure monitoring chains are correct.
5160 */
5161 for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
5162 {
5163 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5164 pPage->iNext = NIL_PGMPOOL_IDX;
5165#ifdef PGMPOOL_WITH_MONITORING
5166 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5167 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5168 pPage->cModifications = 0;
5169 /* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
5170 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5171 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5172 if (pPage->fMonitored)
5173 {
5174 int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
5175 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
5176 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
5177 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
5178 pPool->pszAccessHandler);
5179 AssertFatalRCSuccess(rc);
5180# ifdef PGMPOOL_WITH_CACHE
5181 pgmPoolHashInsert(pPool, pPage);
5182# endif
5183 }
5184#endif
5185#ifdef PGMPOOL_WITH_USER_TRACKING
5186 Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
5187#endif
5188#ifdef PGMPOOL_WITH_CACHE
5189 Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
5190 Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
5191#endif
5192 }
5193
5194 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5195 {
5196 /*
5197 * Re-enter the shadowing mode and assert Sync CR3 FF.
5198 */
5199 PVMCPU pVCpu = &pVM->aCpus[i];
5200 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5201 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5202 }
5203
5204 STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
5205}
5206#endif /* IN_RING3 */
5207
5208#ifdef LOG_ENABLED
5209static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5210{
5211 switch(enmKind)
5212 {
5213 case PGMPOOLKIND_INVALID:
5214 return "PGMPOOLKIND_INVALID";
5215 case PGMPOOLKIND_FREE:
5216 return "PGMPOOLKIND_FREE";
5217 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5218 return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5219 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5220 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5221 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5222 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5223 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5224 return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5225 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5226 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5227 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5228 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5229 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5230 return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5231 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5232 return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5233 case PGMPOOLKIND_32BIT_PD:
5234 return "PGMPOOLKIND_32BIT_PD";
5235 case PGMPOOLKIND_32BIT_PD_PHYS:
5236 return "PGMPOOLKIND_32BIT_PD_PHYS";
5237 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5238 return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5239 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5240 return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5241 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5242 return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5243 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5244 return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5245 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5246 return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5247 case PGMPOOLKIND_PAE_PD_PHYS:
5248 return "PGMPOOLKIND_PAE_PD_PHYS";
5249 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5250 return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5251 case PGMPOOLKIND_PAE_PDPT:
5252 return "PGMPOOLKIND_PAE_PDPT";
5253 case PGMPOOLKIND_PAE_PDPT_PHYS:
5254 return "PGMPOOLKIND_PAE_PDPT_PHYS";
5255 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5256 return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5257 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5258 return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5259 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5260 return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5261 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5262 return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5263 case PGMPOOLKIND_64BIT_PML4:
5264 return "PGMPOOLKIND_64BIT_PML4";
5265 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5266 return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5267 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5268 return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5269 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5270 return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5271 case PGMPOOLKIND_ROOT_NESTED:
5272 return "PGMPOOLKIND_ROOT_NESTED";
5273 }
5274 return "Unknown kind!";
5275}
5276#endif /* LOG_ENABLED*/
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette