PGMAllPool.cpp@ 31463

Last change on this file since 31463 was 31446, checked in by vboxsync, 14 years ago
PGMAllPool.cpp: Added lots more PGM_DYNMAP_UNUSED_HINT_VM calls to avoid running out of mapping space.
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File size: 197.8 KB

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1	/* $Id: PGMAllPool.cpp 31446 2010-08-07 21:13:53Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_POOL
23	#include <VBox/pgm.h>
24	#include <VBox/mm.h>
25	#include <VBox/em.h>
26	#include <VBox/cpum.h>
27	#ifdef IN_RC
28	# include <VBox/patm.h>
29	#endif
30	#include "../PGMInternal.h"
31	#include <VBox/vm.h>
32	#include "../PGMInline.h"
33	#include <VBox/disopcode.h>
34	#include <VBox/hwacc_vmx.h>
35
36	#include <VBox/log.h>
37	#include <VBox/err.h>
38	#include <iprt/asm.h>
39	#include <iprt/asm-amd64-x86.h>
40	#include <iprt/string.h>
41
42
43	/*******************************************************************************
44	* Internal Functions *
45	*******************************************************************************/
46	RT_C_DECLS_BEGIN
47	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
48	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
49	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
50	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
51	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
52	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
53	#ifndef IN_RING3
54	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
55	#endif
56	#ifdef LOG_ENABLED
57	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
58	#endif
59	#if defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)
60	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT);
61	#endif
62
63	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
64	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
65	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
66	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
67
68	RT_C_DECLS_END
69
70
71	/**
72	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
73	*
74	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
75	* @param enmKind The page kind.
76	*/
77	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
78	{
79	switch (enmKind)
80	{
81	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
82	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
83	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
84	return true;
85	default:
86	return false;
87	}
88	}
89
90
91	/**
92	* Flushes a chain of pages sharing the same access monitor.
93	*
94	* @returns VBox status code suitable for scheduling.
95	* @param pPool The pool.
96	* @param pPage A page in the chain.
97	*/
98	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
99	{
100	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
101
102	/*
103	* Find the list head.
104	*/
105	uint16_t idx = pPage->idx;
106	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
107	{
108	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
109	{
110	idx = pPage->iMonitoredPrev;
111	Assert(idx != pPage->idx);
112	pPage = &pPool->aPages[idx];
113	}
114	}
115
116	/*
117	* Iterate the list flushing each shadow page.
118	*/
119	int rc = VINF_SUCCESS;
120	for (;;)
121	{
122	idx = pPage->iMonitoredNext;
123	Assert(idx != pPage->idx);
124	if (pPage->idx >= PGMPOOL_IDX_FIRST)
125	{
126	int rc2 = pgmPoolFlushPage(pPool, pPage);
127	AssertRC(rc2);
128	}
129	/* next */
130	if (idx == NIL_PGMPOOL_IDX)
131	break;
132	pPage = &pPool->aPages[idx];
133	}
134	return rc;
135	}
136
137
138	/**
139	* Wrapper for getting the current context pointer to the entry being modified.
140	*
141	* @returns VBox status code suitable for scheduling.
142	* @param pVM VM Handle.
143	* @param pvDst Destination address
144	* @param pvSrc Source guest virtual address.
145	* @param GCPhysSrc The source guest physical address.
146	* @param cb Size of data to read
147	*/
148	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
149	{
150	#if defined(IN_RING3)
151	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
152	return VINF_SUCCESS;
153	#else
154	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
155	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
156	#endif
157	}
158
159	/**
160	* Process shadow entries before they are changed by the guest.
161	*
162	* For PT entries we will clear them. For PD entries, we'll simply check
163	* for mapping conflicts and set the SyncCR3 FF if found.
164	*
165	* @param pVCpu VMCPU handle
166	* @param pPool The pool.
167	* @param pPage The head page.
168	* @param GCPhysFault The guest physical fault address.
169	* @param uAddress In R0 and GC this is the guest context fault address (flat).
170	* In R3 this is the host context 'fault' address.
171	* @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
172	*/
173	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite)
174	{
175	AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%#x (idx=%#x)\n", pPage->iMonitoredPrev, pPage->idx));
176	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
177	PVM pVM = pPool->CTX_SUFF(pVM);
178
179	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))pvAddress, GCPhysFault, cbWrite));
180
181	for (;;)
182	{
183	union
184	{
185	void *pv;
186	PX86PT pPT;
187	PX86PTPAE pPTPae;
188	PX86PD pPD;
189	PX86PDPAE pPDPae;
190	PX86PDPT pPDPT;
191	PX86PML4 pPML4;
192	} uShw;
193
194	LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
195
196	uShw.pv = NULL;
197	switch (pPage->enmKind)
198	{
199	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
200	{
201	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
202	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
203	const unsigned iShw = off / sizeof(X86PTE);
204	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
205	if (uShw.pPT->a[iShw].n.u1Present)
206	{
207	X86PTE GstPte;
208
209	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
210	AssertRC(rc);
211	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
212	pgmPoolTracDerefGCPhysHint(pPool, pPage,
213	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
214	GstPte.u & X86_PTE_PG_MASK,
215	iShw);
216	ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
217	}
218	break;
219	}
220
221	/* page/2 sized */
222	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
223	{
224	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
225	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
226	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
227	{
228	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
229	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
230	if (uShw.pPTPae->a[iShw].n.u1Present)
231	{
232	X86PTE GstPte;
233	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
234	AssertRC(rc);
235
236	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
237	pgmPoolTracDerefGCPhysHint(pPool, pPage,
238	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
239	GstPte.u & X86_PTE_PG_MASK,
240	iShw);
241	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
242	}
243	}
244	break;
245	}
246
247	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
248	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
249	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
250	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
251	{
252	unsigned iGst = off / sizeof(X86PDE);
253	unsigned iShwPdpt = iGst / 256;
254	unsigned iShw = (iGst % 256) * 2;
255	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
256
257	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
258	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
259	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
260	{
261	for (unsigned i = 0; i < 2; i++)
262	{
263	# ifndef IN_RING0
264	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
265	{
266	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
267	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
268	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
269	break;
270	}
271	else
272	# endif /* !IN_RING0 */
273	if (uShw.pPDPae->a[iShw+i].n.u1Present)
274	{
275	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
276	pgmPoolFree(pVM,
277	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
278	pPage->idx,
279	iShw + i);
280	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
281	}
282
283	/* paranoia / a bit assumptive. */
284	if ( (off & 3)
285	&& (off & 3) + cbWrite > 4)
286	{
287	const unsigned iShw2 = iShw + 2 + i;
288	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
289	{
290	# ifndef IN_RING0
291	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
292	{
293	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
294	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
295	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
296	break;
297	}
298	else
299	# endif /* !IN_RING0 */
300	if (uShw.pPDPae->a[iShw2].n.u1Present)
301	{
302	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
303	pgmPoolFree(pVM,
304	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
305	pPage->idx,
306	iShw2);
307	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
308	}
309	}
310	}
311	}
312	}
313	break;
314	}
315
316	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
317	{
318	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
319	const unsigned iShw = off / sizeof(X86PTEPAE);
320	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
321	if (uShw.pPTPae->a[iShw].n.u1Present)
322	{
323	X86PTEPAE GstPte;
324	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
325	AssertRC(rc);
326
327	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
328	pgmPoolTracDerefGCPhysHint(pPool, pPage,
329	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
330	GstPte.u & X86_PTE_PAE_PG_MASK,
331	iShw);
332	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
333	}
334
335	/* paranoia / a bit assumptive. */
336	if ( (off & 7)
337	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
338	{
339	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
340	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
341
342	if (uShw.pPTPae->a[iShw2].n.u1Present)
343	{
344	X86PTEPAE GstPte;
345	# ifdef IN_RING3
346	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
347	# else
348	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
349	# endif
350	AssertRC(rc);
351	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
352	pgmPoolTracDerefGCPhysHint(pPool, pPage,
353	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
354	GstPte.u & X86_PTE_PAE_PG_MASK,
355	iShw2);
356	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
357	}
358	}
359	break;
360	}
361
362	case PGMPOOLKIND_32BIT_PD:
363	{
364	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
365	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
366
367	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
368	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
369	# ifndef IN_RING0
370	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
371	{
372	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
373	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
374	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
375	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
376	break;
377	}
378	# endif /* !IN_RING0 */
379	# ifndef IN_RING0
380	else
381	# endif /* !IN_RING0 */
382	{
383	if (uShw.pPD->a[iShw].n.u1Present)
384	{
385	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
386	pgmPoolFree(pVM,
387	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
388	pPage->idx,
389	iShw);
390	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
391	}
392	}
393	/* paranoia / a bit assumptive. */
394	if ( (off & 3)
395	&& (off & 3) + cbWrite > sizeof(X86PTE))
396	{
397	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
398	if ( iShw2 != iShw
399	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
400	{
401	# ifndef IN_RING0
402	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
403	{
404	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
405	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
406	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
407	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
408	break;
409	}
410	# endif /* !IN_RING0 */
411	# ifndef IN_RING0
412	else
413	# endif /* !IN_RING0 */
414	{
415	if (uShw.pPD->a[iShw2].n.u1Present)
416	{
417	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
418	pgmPoolFree(pVM,
419	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
420	pPage->idx,
421	iShw2);
422	ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
423	}
424	}
425	}
426	}
427	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
428	if ( uShw.pPD->a[iShw].n.u1Present
429	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
430	{
431	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
432	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
433	ASMProbeReadByte(pvAddress);
434	# endif
435	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
436	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
437	}
438	#endif
439	break;
440	}
441
442	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
443	{
444	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
445	const unsigned iShw = off / sizeof(X86PDEPAE);
446	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
447	#ifndef IN_RING0
448	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
449	{
450	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
451	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
452	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
453	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
454	break;
455	}
456	#endif /* !IN_RING0 */
457	/*
458	* Causes trouble when the guest uses a PDE to refer to the whole page table level
459	* structure. (Invalidate here; faults later on when it tries to change the page
460	* table entries -> recheck; probably only applies to the RC case.)
461	*/
462	# ifndef IN_RING0
463	else
464	# endif /* !IN_RING0 */
465	{
466	if (uShw.pPDPae->a[iShw].n.u1Present)
467	{
468	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
469	pgmPoolFree(pVM,
470	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
471	pPage->idx,
472	iShw);
473	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
474	}
475	}
476	/* paranoia / a bit assumptive. */
477	if ( (off & 7)
478	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
479	{
480	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
481	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
482
483	#ifndef IN_RING0
484	if ( iShw2 != iShw
485	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
486	{
487	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
488	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
489	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
490	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
491	break;
492	}
493	#endif /* !IN_RING0 */
494	# ifndef IN_RING0
495	else
496	# endif /* !IN_RING0 */
497	if (uShw.pPDPae->a[iShw2].n.u1Present)
498	{
499	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
500	pgmPoolFree(pVM,
501	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
502	pPage->idx,
503	iShw2);
504	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
505	}
506	}
507	break;
508	}
509
510	case PGMPOOLKIND_PAE_PDPT:
511	{
512	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
513	/*
514	* Hopefully this doesn't happen very often:
515	* - touching unused parts of the page
516	* - messing with the bits of pd pointers without changing the physical address
517	*/
518	/* PDPT roots are not page aligned; 32 byte only! */
519	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
520
521	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
522	const unsigned iShw = offPdpt / sizeof(X86PDPE);
523	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
524	{
525	# ifndef IN_RING0
526	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
527	{
528	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
529	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
530	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
531	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
532	break;
533	}
534	# endif /* !IN_RING0 */
535	# ifndef IN_RING0
536	else
537	# endif /* !IN_RING0 */
538	if (uShw.pPDPT->a[iShw].n.u1Present)
539	{
540	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
541	pgmPoolFree(pVM,
542	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
543	pPage->idx,
544	iShw);
545	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
546	}
547
548	/* paranoia / a bit assumptive. */
549	if ( (offPdpt & 7)
550	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
551	{
552	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
553	if ( iShw2 != iShw
554	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
555	{
556	# ifndef IN_RING0
557	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
558	{
559	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
560	STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
561	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
562	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
563	break;
564	}
565	# endif /* !IN_RING0 */
566	# ifndef IN_RING0
567	else
568	# endif /* !IN_RING0 */
569	if (uShw.pPDPT->a[iShw2].n.u1Present)
570	{
571	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
572	pgmPoolFree(pVM,
573	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
574	pPage->idx,
575	iShw2);
576	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
577	}
578	}
579	}
580	}
581	break;
582	}
583
584	#ifndef IN_RC
585	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
586	{
587	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
588	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
589	const unsigned iShw = off / sizeof(X86PDEPAE);
590	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
591	if (uShw.pPDPae->a[iShw].n.u1Present)
592	{
593	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
594	pgmPoolFree(pVM,
595	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
596	pPage->idx,
597	iShw);
598	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
599	}
600	/* paranoia / a bit assumptive. */
601	if ( (off & 7)
602	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
603	{
604	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
605	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
606
607	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
608	if (uShw.pPDPae->a[iShw2].n.u1Present)
609	{
610	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
611	pgmPoolFree(pVM,
612	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
613	pPage->idx,
614	iShw2);
615	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
616	}
617	}
618	break;
619	}
620
621	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
622	{
623	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
624	/*
625	* Hopefully this doesn't happen very often:
626	* - messing with the bits of pd pointers without changing the physical address
627	*/
628	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
629	const unsigned iShw = off / sizeof(X86PDPE);
630	if (uShw.pPDPT->a[iShw].n.u1Present)
631	{
632	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
633	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
634	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
635	}
636	/* paranoia / a bit assumptive. */
637	if ( (off & 7)
638	&& (off & 7) + cbWrite > sizeof(X86PDPE))
639	{
640	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
641	if (uShw.pPDPT->a[iShw2].n.u1Present)
642	{
643	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
644	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
645	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
646	}
647	}
648	break;
649	}
650
651	case PGMPOOLKIND_64BIT_PML4:
652	{
653	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
654	/*
655	* Hopefully this doesn't happen very often:
656	* - messing with the bits of pd pointers without changing the physical address
657	*/
658	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
659	const unsigned iShw = off / sizeof(X86PDPE);
660	if (uShw.pPML4->a[iShw].n.u1Present)
661	{
662	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
663	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
664	ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
665	}
666	/* paranoia / a bit assumptive. */
667	if ( (off & 7)
668	&& (off & 7) + cbWrite > sizeof(X86PDPE))
669	{
670	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
671	if (uShw.pPML4->a[iShw2].n.u1Present)
672	{
673	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
674	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
675	ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
676	}
677	}
678	break;
679	}
680	#endif /* IN_RING0 */
681
682	default:
683	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
684	}
685	PGM_DYNMAP_UNUSED_HINT_VM(pVM, uShw.pv);
686
687	/* next */
688	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
689	return;
690	pPage = &pPool->aPages[pPage->iMonitoredNext];
691	}
692	}
693
694	# ifndef IN_RING3
695	/**
696	* Checks if a access could be a fork operation in progress.
697	*
698	* Meaning, that the guest is setting up the parent process for Copy-On-Write.
699	*
700	* @returns true if it's likly that we're forking, otherwise false.
701	* @param pPool The pool.
702	* @param pDis The disassembled instruction.
703	* @param offFault The access offset.
704	*/
705	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
706	{
707	/*
708	* i386 linux is using btr to clear X86_PTE_RW.
709	* The functions involved are (2.6.16 source inspection):
710	* clear_bit
711	* ptep_set_wrprotect
712	* copy_one_pte
713	* copy_pte_range
714	* copy_pmd_range
715	* copy_pud_range
716	* copy_page_range
717	* dup_mmap
718	* dup_mm
719	* copy_mm
720	* copy_process
721	* do_fork
722	*/
723	if ( pDis->pCurInstr->opcode == OP_BTR
724	&& !(offFault & 4)
725	/** @todo Validate that the bit index is X86_PTE_RW. */
726	)
727	{
728	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
729	return true;
730	}
731	return false;
732	}
733
734
735	/**
736	* Determine whether the page is likely to have been reused.
737	*
738	* @returns true if we consider the page as being reused for a different purpose.
739	* @returns false if we consider it to still be a paging page.
740	* @param pVM VM Handle.
741	* @param pVCpu VMCPU Handle.
742	* @param pRegFrame Trap register frame.
743	* @param pDis The disassembly info for the faulting instruction.
744	* @param pvFault The fault address.
745	*
746	* @remark The REP prefix check is left to the caller because of STOSD/W.
747	*/
748	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
749	{
750	#ifndef IN_RC
751	/** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
752	if ( HWACCMHasPendingIrq(pVM)
753	&& (pRegFrame->rsp - pvFault) < 32)
754	{
755	/* Fault caused by stack writes while trying to inject an interrupt event. */
756	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
757	return true;
758	}
759	#else
760	NOREF(pVM); NOREF(pvFault);
761	#endif
762
763	LogFlow(("Reused instr %RGv %d at %RGv param1.flags=%x param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.flags, pDis->param1.base.reg_gen));
764
765	/* Non-supervisor mode write means it's used for something else. */
766	if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
767	return true;
768
769	switch (pDis->pCurInstr->opcode)
770	{
771	/* call implies the actual push of the return address faulted */
772	case OP_CALL:
773	Log4(("pgmPoolMonitorIsReused: CALL\n"));
774	return true;
775	case OP_PUSH:
776	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
777	return true;
778	case OP_PUSHF:
779	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
780	return true;
781	case OP_PUSHA:
782	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
783	return true;
784	case OP_FXSAVE:
785	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
786	return true;
787	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
788	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
789	return true;
790	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
791	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
792	return true;
793	case OP_MOVSWD:
794	case OP_STOSWD:
795	if ( pDis->prefix == (PREFIX_REP\|PREFIX_REX)
796	&& pRegFrame->rcx >= 0x40
797	)
798	{
799	Assert(pDis->mode == CPUMODE_64BIT);
800
801	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
802	return true;
803	}
804	return false;
805	}
806	if ( ( (pDis->param1.flags & USE_REG_GEN32)
807	\|\| (pDis->param1.flags & USE_REG_GEN64))
808	&& (pDis->param1.base.reg_gen == USE_REG_ESP))
809	{
810	Log4(("pgmPoolMonitorIsReused: ESP\n"));
811	return true;
812	}
813
814	return false;
815	}
816
817	/**
818	* Flushes the page being accessed.
819	*
820	* @returns VBox status code suitable for scheduling.
821	* @param pVM The VM handle.
822	* @param pVCpu The VMCPU handle.
823	* @param pPool The pool.
824	* @param pPage The pool page (head).
825	* @param pDis The disassembly of the write instruction.
826	* @param pRegFrame The trap register frame.
827	* @param GCPhysFault The fault address as guest physical address.
828	* @param pvFault The fault address.
829	*/
830	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
831	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
832	{
833	/*
834	* First, do the flushing.
835	*/
836	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
837
838	/*
839	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). Must do this in raw mode (!); XP boot will fail otherwise
840	*/
841	uint32_t cbWritten;
842	int rc2 = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten, EMCODETYPE_ALL);
843	if (RT_SUCCESS(rc2))
844	pRegFrame->rip += pDis->opsize;
845	else if (rc2 == VERR_EM_INTERPRETER)
846	{
847	#ifdef IN_RC
848	if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
849	{
850	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
851	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
852	rc = VINF_SUCCESS;
853	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
854	}
855	else
856	#endif
857	{
858	rc = VINF_EM_RAW_EMULATE_INSTR;
859	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
860	}
861	}
862	else
863	rc = rc2;
864
865	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
866	return rc;
867	}
868
869	/**
870	* Handles the STOSD write accesses.
871	*
872	* @returns VBox status code suitable for scheduling.
873	* @param pVM The VM handle.
874	* @param pPool The pool.
875	* @param pPage The pool page (head).
876	* @param pDis The disassembly of the write instruction.
877	* @param pRegFrame The trap register frame.
878	* @param GCPhysFault The fault address as guest physical address.
879	* @param pvFault The fault address.
880	*/
881	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
882	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
883	{
884	unsigned uIncrement = pDis->param1.size;
885
886	Assert(pDis->mode == CPUMODE_32BIT \|\| pDis->mode == CPUMODE_64BIT);
887	Assert(pRegFrame->rcx <= 0x20);
888
889	#ifdef VBOX_STRICT
890	if (pDis->opmode == CPUMODE_32BIT)
891	Assert(uIncrement == 4);
892	else
893	Assert(uIncrement == 8);
894	#endif
895
896	Log3(("pgmPoolAccessHandlerSTOSD\n"));
897
898	/*
899	* Increment the modification counter and insert it into the list
900	* of modified pages the first time.
901	*/
902	if (!pPage->cModifications++)
903	pgmPoolMonitorModifiedInsert(pPool, pPage);
904
905	/*
906	* Execute REP STOSD.
907	*
908	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
909	* write situation, meaning that it's safe to write here.
910	*/
911	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
912	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
913	while (pRegFrame->rcx)
914	{
915	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
916	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
917	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
918	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
919	#else
920	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
921	#endif
922	#ifdef IN_RC
923	(uint32_t )(uintptr_t)pu32 = pRegFrame->eax;
924	#else
925	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
926	#endif
927	pu32 += uIncrement;
928	GCPhysFault += uIncrement;
929	pRegFrame->rdi += uIncrement;
930	pRegFrame->rcx--;
931	}
932	pRegFrame->rip += pDis->opsize;
933
934	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
935	return VINF_SUCCESS;
936	}
937
938
939	/**
940	* Handles the simple write accesses.
941	*
942	* @returns VBox status code suitable for scheduling.
943	* @param pVM The VM handle.
944	* @param pVCpu The VMCPU handle.
945	* @param pPool The pool.
946	* @param pPage The pool page (head).
947	* @param pDis The disassembly of the write instruction.
948	* @param pRegFrame The trap register frame.
949	* @param GCPhysFault The fault address as guest physical address.
950	* @param pvFault The fault address.
951	* @param pfReused Reused state (out)
952	*/
953	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
954	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
955	{
956	Log3(("pgmPoolAccessHandlerSimple\n"));
957	/*
958	* Increment the modification counter and insert it into the list
959	* of modified pages the first time.
960	*/
961	if (!pPage->cModifications++)
962	pgmPoolMonitorModifiedInsert(pPool, pPage);
963
964	/*
965	* Clear all the pages. ASSUMES that pvFault is readable.
966	*/
967	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
968	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
969	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
970	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
971	#else
972	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
973	#endif
974
975	/*
976	* Interpret the instruction.
977	*/
978	uint32_t cb;
979	int rc = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb, EMCODETYPE_ALL);
980	if (RT_SUCCESS(rc))
981	pRegFrame->rip += pDis->opsize;
982	else if (rc == VERR_EM_INTERPRETER)
983	{
984	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
985	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
986	rc = VINF_EM_RAW_EMULATE_INSTR;
987	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
988	}
989
990	#if 0 /* experimental code */
991	if (rc == VINF_SUCCESS)
992	{
993	switch (pPage->enmKind)
994	{
995	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
996	{
997	X86PTEPAE GstPte;
998	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
999	AssertRC(rc);
1000
1001	/* Check the new value written by the guest. If present and with a bogus physical address, then
1002	* it's fairly safe to assume the guest is reusing the PT.
1003	*/
1004	if (GstPte.n.u1Present)
1005	{
1006	RTHCPHYS HCPhys = -1;
1007	int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1008	if (rc != VINF_SUCCESS)
1009	{
1010	*pfReused = true;
1011	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1012	}
1013	}
1014	break;
1015	}
1016	}
1017	}
1018	#endif
1019
1020	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1021	return rc;
1022	}
1023
1024	/**
1025	* \#PF Handler callback for PT write accesses.
1026	*
1027	* @returns VBox status code (appropriate for GC return).
1028	* @param pVM VM Handle.
1029	* @param uErrorCode CPU Error code.
1030	* @param pRegFrame Trap register frame.
1031	* NULL on DMA and other non CPU access.
1032	* @param pvFault The fault address (cr2).
1033	* @param GCPhysFault The GC physical address corresponding to pvFault.
1034	* @param pvUser User argument.
1035	*/
1036	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1037	{
1038	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1039	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1040	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1041	PVMCPU pVCpu = VMMGetCpu(pVM);
1042	unsigned cMaxModifications;
1043	bool fForcedFlush = false;
1044
1045	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1046
1047	pgmLock(pVM);
1048	if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1049	{
1050	/* Pool page changed while we were waiting for the lock; ignore. */
1051	Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1052	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1053	pgmUnlock(pVM);
1054	return VINF_SUCCESS;
1055	}
1056	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1057	if (pPage->fDirty)
1058	{
1059	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH));
1060	pgmUnlock(pVM);
1061	return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1062	}
1063	#endif
1064
1065	#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1066	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1067	{
1068	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1069	void *pvGst;
1070	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1071	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1072	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1073	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1074	}
1075	#endif
1076
1077	/*
1078	* Disassemble the faulting instruction.
1079	*/
1080	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1081	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1082	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1083	{
1084	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1085	pgmUnlock(pVM);
1086	return rc;
1087	}
1088
1089	Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1090
1091	/*
1092	* We should ALWAYS have the list head as user parameter. This
1093	* is because we use that page to record the changes.
1094	*/
1095	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1096
1097	#ifdef IN_RING0
1098	/* Maximum nr of modifications depends on the page type. */
1099	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1100	cMaxModifications = 4;
1101	else
1102	cMaxModifications = 24;
1103	#else
1104	cMaxModifications = 48;
1105	#endif
1106
1107	/*
1108	* Incremental page table updates should weigh more than random ones.
1109	* (Only applies when started from offset 0)
1110	*/
1111	pVCpu->pgm.s.cPoolAccessHandler++;
1112	if ( pPage->pvLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1113	&& pPage->pvLastAccessHandlerRip < pRegFrame->rip + 0x40
1114	&& pvFault == (pPage->pvLastAccessHandlerFault + pDis->param1.size)
1115	&& pVCpu->pgm.s.cPoolAccessHandler == (pPage->cLastAccessHandlerCount + 1))
1116	{
1117	Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1118	Assert(pPage->cModifications < 32000);
1119	pPage->cModifications = pPage->cModifications * 2;
1120	pPage->pvLastAccessHandlerFault = pvFault;
1121	pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1122	if (pPage->cModifications >= cMaxModifications)
1123	{
1124	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1125	fForcedFlush = true;
1126	}
1127	}
1128
1129	if (pPage->cModifications >= cMaxModifications)
1130	Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1131
1132	/*
1133	* Check if it's worth dealing with.
1134	*/
1135	bool fReused = false;
1136	bool fNotReusedNotForking = false;
1137	if ( ( pPage->cModifications < cMaxModifications /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1138	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1139	)
1140	&& !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1141	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1142	{
1143	/*
1144	* Simple instructions, no REP prefix.
1145	*/
1146	if (!(pDis->prefix & (PREFIX_REP \| PREFIX_REPNE)))
1147	{
1148	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1149	if (fReused)
1150	goto flushPage;
1151
1152	/* A mov instruction to change the first page table entry will be remembered so we can detect
1153	* full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1154	*/
1155	if ( rc == VINF_SUCCESS
1156	&& !pPage->cLocked /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
1157	&& pDis->pCurInstr->opcode == OP_MOV
1158	&& (pvFault & PAGE_OFFSET_MASK) == 0)
1159	{
1160	pPage->pvLastAccessHandlerFault = pvFault;
1161	pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1162	pPage->pvLastAccessHandlerRip = pRegFrame->rip;
1163	/* Make sure we don't kick out a page too quickly. */
1164	if (pPage->cModifications > 8)
1165	pPage->cModifications = 2;
1166	}
1167	else
1168	if (pPage->pvLastAccessHandlerFault == pvFault)
1169	{
1170	/* ignore the 2nd write to this page table entry. */
1171	pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1172	}
1173	else
1174	{
1175	pPage->pvLastAccessHandlerFault = 0;
1176	pPage->pvLastAccessHandlerRip = 0;
1177	}
1178
1179	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1180	pgmUnlock(pVM);
1181	return rc;
1182	}
1183
1184	/*
1185	* Windows is frequently doing small memset() operations (netio test 4k+).
1186	* We have to deal with these or we'll kill the cache and performance.
1187	*/
1188	if ( pDis->pCurInstr->opcode == OP_STOSWD
1189	&& !pRegFrame->eflags.Bits.u1DF
1190	&& pDis->opmode == pDis->mode
1191	&& pDis->addrmode == pDis->mode)
1192	{
1193	bool fValidStosd = false;
1194
1195	if ( pDis->mode == CPUMODE_32BIT
1196	&& pDis->prefix == PREFIX_REP
1197	&& pRegFrame->ecx <= 0x20
1198	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1199	&& !((uintptr_t)pvFault & 3)
1200	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1201	)
1202	{
1203	fValidStosd = true;
1204	pRegFrame->rcx &= 0xffffffff; /* paranoia */
1205	}
1206	else
1207	if ( pDis->mode == CPUMODE_64BIT
1208	&& pDis->prefix == (PREFIX_REP \| PREFIX_REX)
1209	&& pRegFrame->rcx <= 0x20
1210	&& pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1211	&& !((uintptr_t)pvFault & 7)
1212	&& (pRegFrame->rax == 0 \|\| pRegFrame->rax == 0x80) /* the two values observed. */
1213	)
1214	{
1215	fValidStosd = true;
1216	}
1217
1218	if (fValidStosd)
1219	{
1220	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1221	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1222	pgmUnlock(pVM);
1223	return rc;
1224	}
1225	}
1226
1227	/* REP prefix, don't bother. */
1228	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1229	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1230	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1231	fNotReusedNotForking = true;
1232	}
1233
1234	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1235	/* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1236	* leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1237	*/
1238	if ( pPage->cModifications >= cMaxModifications
1239	&& !fForcedFlush
1240	&& pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1241	&& ( fNotReusedNotForking
1242	\|\| ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1243	&& !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1244	)
1245	)
1246	{
1247	Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
1248	Assert(pPage->fDirty == false);
1249
1250	/* Flush any monitored duplicates as we will disable write protection. */
1251	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1252	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1253	{
1254	PPGMPOOLPAGE pPageHead = pPage;
1255
1256	/* Find the monitor head. */
1257	while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1258	pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1259
1260	while (pPageHead)
1261	{
1262	unsigned idxNext = pPageHead->iMonitoredNext;
1263
1264	if (pPageHead != pPage)
1265	{
1266	STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1267	Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1268	int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1269	AssertRC(rc2);
1270	}
1271
1272	if (idxNext == NIL_PGMPOOL_IDX)
1273	break;
1274
1275	pPageHead = &pPool->aPages[idxNext];
1276	}
1277	}
1278
1279	/* The flushing above might fail for locked pages, so double check. */
1280	if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1281	&& pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1282	{
1283	pgmPoolAddDirtyPage(pVM, pPool, pPage);
1284
1285	/* Temporarily allow write access to the page table again. */
1286	rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys, pPage->GCPhys);
1287	if (rc == VINF_SUCCESS)
1288	{
1289	rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
1290	AssertMsg(rc == VINF_SUCCESS
1291	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1292	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1293	\|\| rc == VERR_PAGE_NOT_PRESENT,
1294	("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1295
1296	pPage->pvDirtyFault = pvFault;
1297
1298	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1299	pgmUnlock(pVM);
1300	return rc;
1301	}
1302	}
1303	}
1304	#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1305
1306	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1307	flushPage:
1308	/*
1309	* Not worth it, so flush it.
1310	*
1311	* If we considered it to be reused, don't go back to ring-3
1312	* to emulate failed instructions since we usually cannot
1313	* interpret then. This may be a bit risky, in which case
1314	* the reuse detection must be fixed.
1315	*/
1316	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1317	if ( rc == VINF_EM_RAW_EMULATE_INSTR
1318	&& fReused)
1319	{
1320	/* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1321	if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1322	rc = VINF_SUCCESS; /* safe to restart the instruction. */
1323	}
1324	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1325	pgmUnlock(pVM);
1326	return rc;
1327	}
1328
1329	# endif /* !IN_RING3 */
1330
1331	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1332
1333	# ifdef VBOX_STRICT
1334	/**
1335	* Check references to guest physical memory in a PAE / PAE page table.
1336	*
1337	* @param pPool The pool.
1338	* @param pPage The page.
1339	* @param pShwPT The shadow page table (mapping of the page).
1340	* @param pGstPT The guest page table.
1341	*/
1342	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
1343	{
1344	unsigned cErrors = 0;
1345	int LastRc = -1; /* initialized to shut up gcc */
1346	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1347	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1348	PVM pVM = pPool->CTX_SUFF(pVM);
1349
1350	#ifdef VBOX_STRICT
1351	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1352	AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1353	#endif
1354	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1355	{
1356	if (pShwPT->a[i].n.u1Present)
1357	{
1358	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1359	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1360	if ( rc != VINF_SUCCESS
1361	\|\| (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys)
1362	{
1363	Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1364	LastPTE = i;
1365	LastRc = rc;
1366	LastHCPhys = HCPhys;
1367	cErrors++;
1368
1369	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1370	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1371	AssertRC(rc);
1372
1373	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1374	{
1375	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1376
1377	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1378	{
1379	PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1380
1381	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1382	{
1383	if ( pShwPT2->a[j].n.u1Present
1384	&& pShwPT2->a[j].n.u1Write
1385	&& ((pShwPT2->a[j].u & X86_PTE_PAE_PG_MASK) == HCPhysPT))
1386	{
1387	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, pShwPT->a[j].u, pShwPT2->a[j].u));
1388	}
1389	}
1390
1391	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1392	}
1393	}
1394	}
1395	}
1396	}
1397	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, pShwPT->a[LastPTE].u, LastHCPhys));
1398	}
1399	# endif /* VBOX_STRICT */
1400
1401	/**
1402	* Clear references to guest physical memory in a PAE / PAE page table.
1403	*
1404	* @returns nr of changed PTEs
1405	* @param pPool The pool.
1406	* @param pPage The page.
1407	* @param pShwPT The shadow page table (mapping of the page).
1408	* @param pGstPT The guest page table.
1409	* @param pOldGstPT The old cached guest page table.
1410	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1411	* @param pfFlush Flush reused page table (out)
1412	*/
1413	DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT,
1414	PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1415	{
1416	unsigned cChanged = 0;
1417
1418	#ifdef VBOX_STRICT
1419	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1420	AssertMsg(!pShwPT->a[i].n.u1Present, ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1421	#endif
1422	*pfFlush = false;
1423
1424	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1425	{
1426	/* Check the new value written by the guest. If present and with a bogus physical address, then
1427	* it's fairly safe to assume the guest is reusing the PT.
1428	*/
1429	if ( fAllowRemoval
1430	&& pGstPT->a[i].n.u1Present)
1431	{
1432	if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1433	{
1434	*pfFlush = true;
1435	return ++cChanged;
1436	}
1437	}
1438	if (pShwPT->a[i].n.u1Present)
1439	{
1440	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1441	if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1442	{
1443	#ifdef VBOX_STRICT
1444	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1445	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1446	AssertMsg(rc == VINF_SUCCESS && (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1447	#endif
1448	uint64_t uHostAttr = pShwPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1449	bool fHostRW = !!(pShwPT->a[i].u & X86_PTE_RW);
1450	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1451	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1452
1453	if ( uHostAttr == uGuestAttr
1454	&& fHostRW <= fGuestRW)
1455	continue;
1456	}
1457	cChanged++;
1458	/* Something was changed, so flush it. */
1459	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1460	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1461	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
1462	ASMAtomicWriteSize(&pShwPT->a[i].u, 0);
1463	}
1464	}
1465	return cChanged;
1466	}
1467
1468
1469	/**
1470	* Flush a dirty page
1471	*
1472	* @param pVM VM Handle.
1473	* @param pPool The pool.
1474	* @param idxSlot Dirty array slot index
1475	* @param fAllowRemoval Allow a reused page table to be removed
1476	*/
1477	static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1478	{
1479	PPGMPOOLPAGE pPage;
1480	unsigned idxPage;
1481
1482	Assert(idxSlot < RT_ELEMENTS(pPool->aIdxDirtyPages));
1483	if (pPool->aIdxDirtyPages[idxSlot] == NIL_PGMPOOL_IDX)
1484	return;
1485
1486	idxPage = pPool->aIdxDirtyPages[idxSlot];
1487	AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1488	pPage = &pPool->aPages[idxPage];
1489	Assert(pPage->idx == idxPage);
1490	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1491
1492	AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1493	Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1494
1495	/* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1496	int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys);
1497	Assert(rc == VINF_SUCCESS);
1498	pPage->fDirty = false;
1499
1500	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
1501	PVMCPU pVCpu = VMMGetCpu(pVM);
1502	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
1503	#endif
1504
1505	#ifdef VBOX_STRICT
1506	uint64_t fFlags = 0;
1507	RTHCPHYS HCPhys;
1508	rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys);
1509	AssertMsg( ( rc == VINF_SUCCESS
1510	&& (!(fFlags & X86_PTE_RW) \|\| HCPhys != pPage->Core.Key))
1511	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1512	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1513	\|\| rc == VERR_PAGE_NOT_PRESENT,
1514	("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags));
1515	#endif
1516
1517	/* Flush those PTEs that have changed. */
1518	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1519	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1520	void *pvGst;
1521	rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1522	bool fFlush;
1523	unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst,
1524	(PCX86PTPAE)&pPool->aDirtyPages[idxSlot][0], fAllowRemoval, &fFlush);
1525	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1526	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1527	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1528	/* Note: we might want to consider keeping the dirty page active in case there were many changes. */
1529
1530	/* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1531	Assert(pPage->cModifications);
1532	if (cChanges < 4)
1533	pPage->cModifications = 1; /* must use > 0 here */
1534	else
1535	pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1536
1537	STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1538	if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages))
1539	pPool->idxFreeDirtyPage = idxSlot;
1540
1541	pPool->cDirtyPages--;
1542	pPool->aIdxDirtyPages[idxSlot] = NIL_PGMPOOL_IDX;
1543	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1544	if (fFlush)
1545	{
1546	Assert(fAllowRemoval);
1547	Log(("Flush reused page table!\n"));
1548	pgmPoolFlushPage(pPool, pPage);
1549	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1550	}
1551	else
1552	Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1553
1554	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_R0) \|\| defined(IN_RC)
1555	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
1556	#endif
1557	}
1558
1559	# ifndef IN_RING3
1560	/**
1561	* Add a new dirty page
1562	*
1563	* @param pVM VM Handle.
1564	* @param pPool The pool.
1565	* @param pPage The page.
1566	*/
1567	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1568	{
1569	unsigned idxFree;
1570
1571	Assert(PGMIsLocked(pVM));
1572	AssertCompile(RT_ELEMENTS(pPool->aIdxDirtyPages) == 8 \|\| RT_ELEMENTS(pPool->aIdxDirtyPages) == 16);
1573	Assert(!pPage->fDirty);
1574
1575	idxFree = pPool->idxFreeDirtyPage;
1576	Assert(idxFree < RT_ELEMENTS(pPool->aIdxDirtyPages));
1577	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1578
1579	if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aIdxDirtyPages))
1580	{
1581	STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1582	pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1583	}
1584	Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages));
1585	AssertMsg(pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1586
1587	Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1588
1589	/*
1590	* Make a copy of the guest page table as we require valid GCPhys addresses
1591	* when removing references to physical pages.
1592	* (The HCPhys linear lookup is extremely expensive!)
1593	*/
1594	void *pvGst;
1595	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1596	memcpy(&pPool->aDirtyPages[idxFree][0], pvGst, PAGE_SIZE);
1597	#ifdef VBOX_STRICT
1598	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1599	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1600	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1601	#endif
1602	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1603
1604	STAM_COUNTER_INC(&pPool->StatDirtyPage);
1605	pPage->fDirty = true;
1606	pPage->idxDirty = idxFree;
1607	pPool->aIdxDirtyPages[idxFree] = pPage->idx;
1608	pPool->cDirtyPages++;
1609
1610	pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1611	if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages)
1612	&& pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1613	{
1614	unsigned i;
1615	for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1616	{
1617	idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1618	if (pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX)
1619	{
1620	pPool->idxFreeDirtyPage = idxFree;
1621	break;
1622	}
1623	}
1624	Assert(i != RT_ELEMENTS(pPool->aIdxDirtyPages));
1625	}
1626
1627	Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages) \|\| pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX);
1628	return;
1629	}
1630	# endif /* !IN_RING3 */
1631
1632	/**
1633	* Check if the specified page is dirty (not write monitored)
1634	*
1635	* @return dirty or not
1636	* @param pVM VM Handle.
1637	* @param GCPhys Guest physical address
1638	*/
1639	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1640	{
1641	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1642	Assert(PGMIsLocked(pVM));
1643	if (!pPool->cDirtyPages)
1644	return false;
1645
1646	GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1647
1648	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1649	{
1650	if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1651	{
1652	PPGMPOOLPAGE pPage;
1653	unsigned idxPage = pPool->aIdxDirtyPages[i];
1654
1655	pPage = &pPool->aPages[idxPage];
1656	if (pPage->GCPhys == GCPhys)
1657	return true;
1658	}
1659	}
1660	return false;
1661	}
1662
1663	/**
1664	* Reset all dirty pages by reinstating page monitoring.
1665	*
1666	* @param pVM VM Handle.
1667	*/
1668	void pgmPoolResetDirtyPages(PVM pVM)
1669	{
1670	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1671	Assert(PGMIsLocked(pVM));
1672	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1673
1674	if (!pPool->cDirtyPages)
1675	return;
1676
1677	Log(("pgmPoolResetDirtyPages\n"));
1678	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1679	pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1680
1681	pPool->idxFreeDirtyPage = 0;
1682	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1683	&& pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1684	{
1685	unsigned i;
1686	for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1687	{
1688	if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1689	{
1690	pPool->idxFreeDirtyPage = i;
1691	break;
1692	}
1693	}
1694	AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1695	}
1696
1697	Assert(pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX \|\| pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages));
1698	return;
1699	}
1700
1701	/**
1702	* Reset all dirty pages by reinstating page monitoring.
1703	*
1704	* @param pVM VM Handle.
1705	* @param GCPhysPT Physical address of the page table
1706	*/
1707	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT)
1708	{
1709	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1710	Assert(PGMIsLocked(pVM));
1711	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1712	unsigned idxDirtyPage = RT_ELEMENTS(pPool->aIdxDirtyPages);
1713
1714	if (!pPool->cDirtyPages)
1715	return;
1716
1717	GCPhysPT = GCPhysPT & ~(RTGCPHYS)(PAGE_SIZE - 1);
1718
1719	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1720	{
1721	if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1722	{
1723	unsigned idxPage = pPool->aIdxDirtyPages[i];
1724
1725	PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1726	if (pPage->GCPhys == GCPhysPT)
1727	{
1728	idxDirtyPage = i;
1729	break;
1730	}
1731	}
1732	}
1733
1734	if (idxDirtyPage != RT_ELEMENTS(pPool->aIdxDirtyPages))
1735	{
1736	pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1737	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1738	&& pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1739	{
1740	unsigned i;
1741	for (i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1742	{
1743	if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1744	{
1745	pPool->idxFreeDirtyPage = i;
1746	break;
1747	}
1748	}
1749	AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1750	}
1751	}
1752	}
1753
1754	# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1755
1756	/**
1757	* Inserts a page into the GCPhys hash table.
1758	*
1759	* @param pPool The pool.
1760	* @param pPage The page.
1761	*/
1762	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1763	{
1764	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1765	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1766	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1767	pPage->iNext = pPool->aiHash[iHash];
1768	pPool->aiHash[iHash] = pPage->idx;
1769	}
1770
1771
1772	/**
1773	* Removes a page from the GCPhys hash table.
1774	*
1775	* @param pPool The pool.
1776	* @param pPage The page.
1777	*/
1778	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1779	{
1780	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1781	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1782	if (pPool->aiHash[iHash] == pPage->idx)
1783	pPool->aiHash[iHash] = pPage->iNext;
1784	else
1785	{
1786	uint16_t iPrev = pPool->aiHash[iHash];
1787	for (;;)
1788	{
1789	const int16_t i = pPool->aPages[iPrev].iNext;
1790	if (i == pPage->idx)
1791	{
1792	pPool->aPages[iPrev].iNext = pPage->iNext;
1793	break;
1794	}
1795	if (i == NIL_PGMPOOL_IDX)
1796	{
1797	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1798	break;
1799	}
1800	iPrev = i;
1801	}
1802	}
1803	pPage->iNext = NIL_PGMPOOL_IDX;
1804	}
1805
1806
1807	/**
1808	* Frees up one cache page.
1809	*
1810	* @returns VBox status code.
1811	* @retval VINF_SUCCESS on success.
1812	* @param pPool The pool.
1813	* @param iUser The user index.
1814	*/
1815	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1816	{
1817	#ifndef IN_RC
1818	const PVM pVM = pPool->CTX_SUFF(pVM);
1819	#endif
1820	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1821	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1822
1823	/*
1824	* Select one page from the tail of the age list.
1825	*/
1826	PPGMPOOLPAGE pPage;
1827	for (unsigned iLoop = 0; ; iLoop++)
1828	{
1829	uint16_t iToFree = pPool->iAgeTail;
1830	if (iToFree == iUser)
1831	iToFree = pPool->aPages[iToFree].iAgePrev;
1832	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1833	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1834	{
1835	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1836	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1837	{
1838	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1839	continue;
1840	iToFree = i;
1841	break;
1842	}
1843	}
1844	*/
1845	Assert(iToFree != iUser);
1846	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1847	pPage = &pPool->aPages[iToFree];
1848
1849	/*
1850	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1851	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1852	*/
1853	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1854	break;
1855	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1856	pgmPoolCacheUsed(pPool, pPage);
1857	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1858	}
1859
1860	/*
1861	* Found a usable page, flush it and return.
1862	*/
1863	int rc = pgmPoolFlushPage(pPool, pPage);
1864	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
1865	/* todo: find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
1866	if (rc == VINF_SUCCESS)
1867	PGM_INVL_ALL_VCPU_TLBS(pVM);
1868	return rc;
1869	}
1870
1871
1872	/**
1873	* Checks if a kind mismatch is really a page being reused
1874	* or if it's just normal remappings.
1875	*
1876	* @returns true if reused and the cached page (enmKind1) should be flushed
1877	* @returns false if not reused.
1878	* @param enmKind1 The kind of the cached page.
1879	* @param enmKind2 The kind of the requested page.
1880	*/
1881	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1882	{
1883	switch (enmKind1)
1884	{
1885	/*
1886	* Never reuse them. There is no remapping in non-paging mode.
1887	*/
1888	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1889	case PGMPOOLKIND_32BIT_PD_PHYS:
1890	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1891	case PGMPOOLKIND_PAE_PD_PHYS:
1892	case PGMPOOLKIND_PAE_PDPT_PHYS:
1893	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1894	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1895	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1896	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1897	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1898	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1899	return false;
1900
1901	/*
1902	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1903	*/
1904	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1905	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1906	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1907	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1908	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1909	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1910	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1911	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1912	case PGMPOOLKIND_32BIT_PD:
1913	case PGMPOOLKIND_PAE_PDPT:
1914	switch (enmKind2)
1915	{
1916	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1917	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1918	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1919	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1920	case PGMPOOLKIND_64BIT_PML4:
1921	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1922	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1923	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1924	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1925	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1926	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1927	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1928	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1929	return true;
1930	default:
1931	return false;
1932	}
1933
1934	/*
1935	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1936	*/
1937	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1938	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1939	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1940	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1941	case PGMPOOLKIND_64BIT_PML4:
1942	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1943	switch (enmKind2)
1944	{
1945	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1946	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1947	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1948	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1949	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1950	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1951	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1952	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1953	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1954	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1955	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1956	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1957	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1958	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1959	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1960	return true;
1961	default:
1962	return false;
1963	}
1964
1965	/*
1966	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1967	*/
1968	case PGMPOOLKIND_ROOT_NESTED:
1969	return false;
1970
1971	default:
1972	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1973	}
1974	}
1975
1976
1977	/**
1978	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1979	*
1980	* @returns VBox status code.
1981	* @retval VINF_PGM_CACHED_PAGE on success.
1982	* @retval VERR_FILE_NOT_FOUND if not found.
1983	* @param pPool The pool.
1984	* @param GCPhys The GC physical address of the page we're gonna shadow.
1985	* @param enmKind The kind of mapping.
1986	* @param enmAccess Access type for the mapping (only relevant for big pages)
1987	* @param iUser The shadow page pool index of the user table.
1988	* @param iUserTable The index into the user table (shadowed).
1989	* @param ppPage Where to store the pointer to the page.
1990	*/
1991	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1992	{
1993	#ifndef IN_RC
1994	const PVM pVM = pPool->CTX_SUFF(pVM);
1995	#endif
1996	/*
1997	* Look up the GCPhys in the hash.
1998	*/
1999	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2000	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2001	if (i != NIL_PGMPOOL_IDX)
2002	{
2003	do
2004	{
2005	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2006	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2007	if (pPage->GCPhys == GCPhys)
2008	{
2009	if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2010	&& (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
2011	{
2012	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2013	* doesn't flush it in case there are no more free use records.
2014	*/
2015	pgmPoolCacheUsed(pPool, pPage);
2016
2017	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2018	if (RT_SUCCESS(rc))
2019	{
2020	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2021	*ppPage = pPage;
2022	if (pPage->cModifications)
2023	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2024	STAM_COUNTER_INC(&pPool->StatCacheHits);
2025	return VINF_PGM_CACHED_PAGE;
2026	}
2027	return rc;
2028	}
2029
2030	if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2031	{
2032	/*
2033	* The kind is different. In some cases we should now flush the page
2034	* as it has been reused, but in most cases this is normal remapping
2035	* of PDs as PT or big pages using the GCPhys field in a slightly
2036	* different way than the other kinds.
2037	*/
2038	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2039	{
2040	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2041	pgmPoolFlushPage(pPool, pPage);
2042	break;
2043	}
2044	}
2045	}
2046
2047	/* next */
2048	i = pPage->iNext;
2049	} while (i != NIL_PGMPOOL_IDX);
2050	}
2051
2052	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2053	STAM_COUNTER_INC(&pPool->StatCacheMisses);
2054	return VERR_FILE_NOT_FOUND;
2055	}
2056
2057
2058	/**
2059	* Inserts a page into the cache.
2060	*
2061	* @param pPool The pool.
2062	* @param pPage The cached page.
2063	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2064	*/
2065	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2066	{
2067	/*
2068	* Insert into the GCPhys hash if the page is fit for that.
2069	*/
2070	Assert(!pPage->fCached);
2071	if (fCanBeCached)
2072	{
2073	pPage->fCached = true;
2074	pgmPoolHashInsert(pPool, pPage);
2075	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2076	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2077	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2078	}
2079	else
2080	{
2081	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2082	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2083	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2084	}
2085
2086	/*
2087	* Insert at the head of the age list.
2088	*/
2089	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2090	pPage->iAgeNext = pPool->iAgeHead;
2091	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2092	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2093	else
2094	pPool->iAgeTail = pPage->idx;
2095	pPool->iAgeHead = pPage->idx;
2096	}
2097
2098
2099	/**
2100	* Flushes a cached page.
2101	*
2102	* @param pPool The pool.
2103	* @param pPage The cached page.
2104	*/
2105	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2106	{
2107	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2108
2109	/*
2110	* Remove the page from the hash.
2111	*/
2112	if (pPage->fCached)
2113	{
2114	pPage->fCached = false;
2115	pgmPoolHashRemove(pPool, pPage);
2116	}
2117	else
2118	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2119
2120	/*
2121	* Remove it from the age list.
2122	*/
2123	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2124	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2125	else
2126	pPool->iAgeTail = pPage->iAgePrev;
2127	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2128	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2129	else
2130	pPool->iAgeHead = pPage->iAgeNext;
2131	pPage->iAgeNext = NIL_PGMPOOL_IDX;
2132	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2133	}
2134
2135
2136	/**
2137	* Looks for pages sharing the monitor.
2138	*
2139	* @returns Pointer to the head page.
2140	* @returns NULL if not found.
2141	* @param pPool The Pool
2142	* @param pNewPage The page which is going to be monitored.
2143	*/
2144	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2145	{
2146	/*
2147	* Look up the GCPhys in the hash.
2148	*/
2149	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2150	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2151	if (i == NIL_PGMPOOL_IDX)
2152	return NULL;
2153	do
2154	{
2155	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2156	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2157	&& pPage != pNewPage)
2158	{
2159	switch (pPage->enmKind)
2160	{
2161	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2162	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2163	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2164	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2165	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2166	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2167	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2168	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2169	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2170	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2171	case PGMPOOLKIND_64BIT_PML4:
2172	case PGMPOOLKIND_32BIT_PD:
2173	case PGMPOOLKIND_PAE_PDPT:
2174	{
2175	/* find the head */
2176	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2177	{
2178	Assert(pPage->iMonitoredPrev != pPage->idx);
2179	pPage = &pPool->aPages[pPage->iMonitoredPrev];
2180	}
2181	return pPage;
2182	}
2183
2184	/* ignore, no monitoring. */
2185	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2186	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2187	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2188	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2189	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2190	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2191	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2192	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2193	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2194	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2195	case PGMPOOLKIND_ROOT_NESTED:
2196	case PGMPOOLKIND_PAE_PD_PHYS:
2197	case PGMPOOLKIND_PAE_PDPT_PHYS:
2198	case PGMPOOLKIND_32BIT_PD_PHYS:
2199	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2200	break;
2201	default:
2202	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2203	}
2204	}
2205
2206	/* next */
2207	i = pPage->iNext;
2208	} while (i != NIL_PGMPOOL_IDX);
2209	return NULL;
2210	}
2211
2212
2213	/**
2214	* Enabled write monitoring of a guest page.
2215	*
2216	* @returns VBox status code.
2217	* @retval VINF_SUCCESS on success.
2218	* @param pPool The pool.
2219	* @param pPage The cached page.
2220	*/
2221	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2222	{
2223	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
2224
2225	/*
2226	* Filter out the relevant kinds.
2227	*/
2228	switch (pPage->enmKind)
2229	{
2230	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2231	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2232	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2233	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2234	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2235	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2236	case PGMPOOLKIND_64BIT_PML4:
2237	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2238	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2239	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2240	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2241	case PGMPOOLKIND_32BIT_PD:
2242	case PGMPOOLKIND_PAE_PDPT:
2243	break;
2244
2245	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2246	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2247	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2248	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2249	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2250	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2251	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2252	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2253	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2254	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2255	case PGMPOOLKIND_ROOT_NESTED:
2256	/* Nothing to monitor here. */
2257	return VINF_SUCCESS;
2258
2259	case PGMPOOLKIND_32BIT_PD_PHYS:
2260	case PGMPOOLKIND_PAE_PDPT_PHYS:
2261	case PGMPOOLKIND_PAE_PD_PHYS:
2262	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2263	/* Nothing to monitor here. */
2264	return VINF_SUCCESS;
2265	default:
2266	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2267	}
2268
2269	/*
2270	* Install handler.
2271	*/
2272	int rc;
2273	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2274	if (pPageHead)
2275	{
2276	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2277	Assert(pPageHead->iMonitoredPrev != pPage->idx);
2278
2279	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2280	if (pPageHead->fDirty)
2281	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirty, false /* do not remove */);
2282	#endif
2283
2284	pPage->iMonitoredPrev = pPageHead->idx;
2285	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2286	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2287	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2288	pPageHead->iMonitoredNext = pPage->idx;
2289	rc = VINF_SUCCESS;
2290	}
2291	else
2292	{
2293	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2294	PVM pVM = pPool->CTX_SUFF(pVM);
2295	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2296	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2297	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
2298	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2299	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2300	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2301	pPool->pszAccessHandler);
2302	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2303	* the heap size should suffice. */
2304	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2305	PVMCPU pVCpu = VMMGetCpu(pVM);
2306	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
2307	}
2308	pPage->fMonitored = true;
2309	return rc;
2310	}
2311
2312
2313	/**
2314	* Disables write monitoring of a guest page.
2315	*
2316	* @returns VBox status code.
2317	* @retval VINF_SUCCESS on success.
2318	* @param pPool The pool.
2319	* @param pPage The cached page.
2320	*/
2321	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2322	{
2323	/*
2324	* Filter out the relevant kinds.
2325	*/
2326	switch (pPage->enmKind)
2327	{
2328	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2329	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2330	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2331	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2332	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2333	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2334	case PGMPOOLKIND_64BIT_PML4:
2335	case PGMPOOLKIND_32BIT_PD:
2336	case PGMPOOLKIND_PAE_PDPT:
2337	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2338	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2339	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2340	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2341	break;
2342
2343	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2344	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2345	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2346	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2347	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2348	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2349	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2350	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2351	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2352	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2353	case PGMPOOLKIND_ROOT_NESTED:
2354	case PGMPOOLKIND_PAE_PD_PHYS:
2355	case PGMPOOLKIND_PAE_PDPT_PHYS:
2356	case PGMPOOLKIND_32BIT_PD_PHYS:
2357	/* Nothing to monitor here. */
2358	Assert(!pPage->fMonitored);
2359	return VINF_SUCCESS;
2360
2361	default:
2362	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2363	}
2364	Assert(pPage->fMonitored);
2365
2366	/*
2367	* Remove the page from the monitored list or uninstall it if last.
2368	*/
2369	const PVM pVM = pPool->CTX_SUFF(pVM);
2370	int rc;
2371	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2372	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2373	{
2374	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2375	{
2376	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2377	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2378	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
2379	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2380	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2381	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2382	pPool->pszAccessHandler);
2383	AssertFatalRCSuccess(rc);
2384	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2385	}
2386	else
2387	{
2388	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2389	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2390	{
2391	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2392	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2393	}
2394	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2395	rc = VINF_SUCCESS;
2396	}
2397	}
2398	else
2399	{
2400	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
2401	AssertFatalRC(rc);
2402	PVMCPU pVCpu = VMMGetCpu(pVM);
2403	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2404	("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2405	}
2406	pPage->fMonitored = false;
2407
2408	/*
2409	* Remove it from the list of modified pages (if in it).
2410	*/
2411	pgmPoolMonitorModifiedRemove(pPool, pPage);
2412
2413	return rc;
2414	}
2415
2416
2417	/**
2418	* Inserts the page into the list of modified pages.
2419	*
2420	* @param pPool The pool.
2421	* @param pPage The page.
2422	*/
2423	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2424	{
2425	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2426	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2427	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2428	&& pPool->iModifiedHead != pPage->idx,
2429	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2430	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2431	pPool->iModifiedHead, pPool->cModifiedPages));
2432
2433	pPage->iModifiedNext = pPool->iModifiedHead;
2434	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2435	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2436	pPool->iModifiedHead = pPage->idx;
2437	pPool->cModifiedPages++;
2438	#ifdef VBOX_WITH_STATISTICS
2439	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2440	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2441	#endif
2442	}
2443
2444
2445	/**
2446	* Removes the page from the list of modified pages and resets the
2447	* moficiation counter.
2448	*
2449	* @param pPool The pool.
2450	* @param pPage The page which is believed to be in the list of modified pages.
2451	*/
2452	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2453	{
2454	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2455	if (pPool->iModifiedHead == pPage->idx)
2456	{
2457	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2458	pPool->iModifiedHead = pPage->iModifiedNext;
2459	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2460	{
2461	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2462	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2463	}
2464	pPool->cModifiedPages--;
2465	}
2466	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2467	{
2468	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2469	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2470	{
2471	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2472	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2473	}
2474	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2475	pPool->cModifiedPages--;
2476	}
2477	else
2478	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2479	pPage->cModifications = 0;
2480	}
2481
2482
2483	/**
2484	* Zaps the list of modified pages, resetting their modification counters in the process.
2485	*
2486	* @param pVM The VM handle.
2487	*/
2488	static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2489	{
2490	pgmLock(pVM);
2491	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2492	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2493
2494	unsigned cPages = 0; NOREF(cPages);
2495
2496	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2497	pgmPoolResetDirtyPages(pVM);
2498	#endif
2499
2500	uint16_t idx = pPool->iModifiedHead;
2501	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2502	while (idx != NIL_PGMPOOL_IDX)
2503	{
2504	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2505	idx = pPage->iModifiedNext;
2506	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2507	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2508	pPage->cModifications = 0;
2509	Assert(++cPages);
2510	}
2511	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2512	pPool->cModifiedPages = 0;
2513	pgmUnlock(pVM);
2514	}
2515
2516
2517	/**
2518	* Handle SyncCR3 pool tasks
2519	*
2520	* @returns VBox status code.
2521	* @retval VINF_SUCCESS if successfully added.
2522	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2523	* @param pVCpu The VMCPU handle.
2524	* @remark Should only be used when monitoring is available, thus placed in
2525	* the PGMPOOL_WITH_MONITORING #ifdef.
2526	*/
2527	int pgmPoolSyncCR3(PVMCPU pVCpu)
2528	{
2529	PVM pVM = pVCpu->CTX_SUFF(pVM);
2530	LogFlow(("pgmPoolSyncCR3 fSyncFlags=%x\n", pVCpu->pgm.s.fSyncFlags));
2531
2532	/*
2533	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2534	* Occasionally we will have to clear all the shadow page tables because we wanted
2535	* to monitor a page which was mapped by too many shadowed page tables. This operation
2536	* sometimes refered to as a 'lightweight flush'.
2537	*/
2538	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2539	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2540	pgmR3PoolClearAll(pVM, false /fFlushRemTlb/);
2541	# else /* !IN_RING3 */
2542	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2543	{
2544	Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2545	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2546
2547	/* Make sure all other VCPUs return to ring 3. */
2548	if (pVM->cCpus > 1)
2549	{
2550	VM_FF_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
2551	PGM_INVL_ALL_VCPU_TLBS(pVM);
2552	}
2553	return VINF_PGM_SYNC_CR3;
2554	}
2555	# endif /* !IN_RING3 */
2556	else
2557	{
2558	pgmPoolMonitorModifiedClearAll(pVM);
2559
2560	/* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
2561	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2562	{
2563	Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
2564	return pgmPoolSyncCR3(pVCpu);
2565	}
2566	}
2567	return VINF_SUCCESS;
2568	}
2569
2570
2571	/**
2572	* Frees up at least one user entry.
2573	*
2574	* @returns VBox status code.
2575	* @retval VINF_SUCCESS if successfully added.
2576	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2577	* @param pPool The pool.
2578	* @param iUser The user index.
2579	*/
2580	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2581	{
2582	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2583	/*
2584	* Just free cached pages in a braindead fashion.
2585	*/
2586	/** @todo walk the age list backwards and free the first with usage. */
2587	int rc = VINF_SUCCESS;
2588	do
2589	{
2590	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2591	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2592	rc = rc2;
2593	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2594	return rc;
2595	}
2596
2597
2598	/**
2599	* Inserts a page into the cache.
2600	*
2601	* This will create user node for the page, insert it into the GCPhys
2602	* hash, and insert it into the age list.
2603	*
2604	* @returns VBox status code.
2605	* @retval VINF_SUCCESS if successfully added.
2606	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2607	* @param pPool The pool.
2608	* @param pPage The cached page.
2609	* @param GCPhys The GC physical address of the page we're gonna shadow.
2610	* @param iUser The user index.
2611	* @param iUserTable The user table index.
2612	*/
2613	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2614	{
2615	int rc = VINF_SUCCESS;
2616	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2617
2618	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2619
2620	#ifdef VBOX_STRICT
2621	/*
2622	* Check that the entry doesn't already exists.
2623	*/
2624	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2625	{
2626	uint16_t i = pPage->iUserHead;
2627	do
2628	{
2629	Assert(i < pPool->cMaxUsers);
2630	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2631	i = paUsers[i].iNext;
2632	} while (i != NIL_PGMPOOL_USER_INDEX);
2633	}
2634	#endif
2635
2636	/*
2637	* Find free a user node.
2638	*/
2639	uint16_t i = pPool->iUserFreeHead;
2640	if (i == NIL_PGMPOOL_USER_INDEX)
2641	{
2642	rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2643	if (RT_FAILURE(rc))
2644	return rc;
2645	i = pPool->iUserFreeHead;
2646	}
2647
2648	/*
2649	* Unlink the user node from the free list,
2650	* initialize and insert it into the user list.
2651	*/
2652	pPool->iUserFreeHead = paUsers[i].iNext;
2653	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2654	paUsers[i].iUser = iUser;
2655	paUsers[i].iUserTable = iUserTable;
2656	pPage->iUserHead = i;
2657
2658	/*
2659	* Insert into cache and enable monitoring of the guest page if enabled.
2660	*
2661	* Until we implement caching of all levels, including the CR3 one, we'll
2662	* have to make sure we don't try monitor & cache any recursive reuse of
2663	* a monitored CR3 page. Because all windows versions are doing this we'll
2664	* have to be able to do combined access monitoring, CR3 + PT and
2665	* PD + PT (guest PAE).
2666	*
2667	* Update:
2668	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2669	*/
2670	const bool fCanBeMonitored = true;
2671	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2672	if (fCanBeMonitored)
2673	{
2674	rc = pgmPoolMonitorInsert(pPool, pPage);
2675	AssertRC(rc);
2676	}
2677	return rc;
2678	}
2679
2680
2681	/**
2682	* Adds a user reference to a page.
2683	*
2684	* This will move the page to the head of the
2685	*
2686	* @returns VBox status code.
2687	* @retval VINF_SUCCESS if successfully added.
2688	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2689	* @param pPool The pool.
2690	* @param pPage The cached page.
2691	* @param iUser The user index.
2692	* @param iUserTable The user table.
2693	*/
2694	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2695	{
2696	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2697
2698	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2699
2700	# ifdef VBOX_STRICT
2701	/*
2702	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2703	*/
2704	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2705	{
2706	uint16_t i = pPage->iUserHead;
2707	do
2708	{
2709	Assert(i < pPool->cMaxUsers);
2710	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2711	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2712	i = paUsers[i].iNext;
2713	} while (i != NIL_PGMPOOL_USER_INDEX);
2714	}
2715	# endif
2716
2717	/*
2718	* Allocate a user node.
2719	*/
2720	uint16_t i = pPool->iUserFreeHead;
2721	if (i == NIL_PGMPOOL_USER_INDEX)
2722	{
2723	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2724	if (RT_FAILURE(rc))
2725	return rc;
2726	i = pPool->iUserFreeHead;
2727	}
2728	pPool->iUserFreeHead = paUsers[i].iNext;
2729
2730	/*
2731	* Initialize the user node and insert it.
2732	*/
2733	paUsers[i].iNext = pPage->iUserHead;
2734	paUsers[i].iUser = iUser;
2735	paUsers[i].iUserTable = iUserTable;
2736	pPage->iUserHead = i;
2737
2738	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2739	if (pPage->fDirty)
2740	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirty, false /* do not remove */);
2741	# endif
2742
2743	/*
2744	* Tell the cache to update its replacement stats for this page.
2745	*/
2746	pgmPoolCacheUsed(pPool, pPage);
2747	return VINF_SUCCESS;
2748	}
2749
2750
2751	/**
2752	* Frees a user record associated with a page.
2753	*
2754	* This does not clear the entry in the user table, it simply replaces the
2755	* user record to the chain of free records.
2756	*
2757	* @param pPool The pool.
2758	* @param HCPhys The HC physical address of the shadow page.
2759	* @param iUser The shadow page pool index of the user table.
2760	* @param iUserTable The index into the user table (shadowed).
2761	*/
2762	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2763	{
2764	/*
2765	* Unlink and free the specified user entry.
2766	*/
2767	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2768
2769	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2770	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2771	uint16_t i = pPage->iUserHead;
2772	if ( i != NIL_PGMPOOL_USER_INDEX
2773	&& paUsers[i].iUser == iUser
2774	&& paUsers[i].iUserTable == iUserTable)
2775	{
2776	pPage->iUserHead = paUsers[i].iNext;
2777
2778	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2779	paUsers[i].iNext = pPool->iUserFreeHead;
2780	pPool->iUserFreeHead = i;
2781	return;
2782	}
2783
2784	/* General: Linear search. */
2785	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2786	while (i != NIL_PGMPOOL_USER_INDEX)
2787	{
2788	if ( paUsers[i].iUser == iUser
2789	&& paUsers[i].iUserTable == iUserTable)
2790	{
2791	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2792	paUsers[iPrev].iNext = paUsers[i].iNext;
2793	else
2794	pPage->iUserHead = paUsers[i].iNext;
2795
2796	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2797	paUsers[i].iNext = pPool->iUserFreeHead;
2798	pPool->iUserFreeHead = i;
2799	return;
2800	}
2801	iPrev = i;
2802	i = paUsers[i].iNext;
2803	}
2804
2805	/* Fatal: didn't find it */
2806	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2807	iUser, iUserTable, pPage->GCPhys));
2808	}
2809
2810
2811	/**
2812	* Gets the entry size of a shadow table.
2813	*
2814	* @param enmKind The kind of page.
2815	*
2816	* @returns The size of the entry in bytes. That is, 4 or 8.
2817	* @returns If the kind is not for a table, an assertion is raised and 0 is
2818	* returned.
2819	*/
2820	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2821	{
2822	switch (enmKind)
2823	{
2824	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2825	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2826	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2827	case PGMPOOLKIND_32BIT_PD:
2828	case PGMPOOLKIND_32BIT_PD_PHYS:
2829	return 4;
2830
2831	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2832	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2833	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2834	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2835	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2836	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2837	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2838	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2839	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2840	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2841	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2842	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2843	case PGMPOOLKIND_64BIT_PML4:
2844	case PGMPOOLKIND_PAE_PDPT:
2845	case PGMPOOLKIND_ROOT_NESTED:
2846	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2847	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2848	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2849	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2850	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2851	case PGMPOOLKIND_PAE_PD_PHYS:
2852	case PGMPOOLKIND_PAE_PDPT_PHYS:
2853	return 8;
2854
2855	default:
2856	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2857	}
2858	}
2859
2860
2861	/**
2862	* Gets the entry size of a guest table.
2863	*
2864	* @param enmKind The kind of page.
2865	*
2866	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2867	* @returns If the kind is not for a table, an assertion is raised and 0 is
2868	* returned.
2869	*/
2870	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2871	{
2872	switch (enmKind)
2873	{
2874	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2875	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2876	case PGMPOOLKIND_32BIT_PD:
2877	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2878	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2879	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2880	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2881	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2882	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2883	return 4;
2884
2885	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2886	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2887	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2888	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2889	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2890	case PGMPOOLKIND_64BIT_PML4:
2891	case PGMPOOLKIND_PAE_PDPT:
2892	return 8;
2893
2894	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2895	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2896	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2897	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2898	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2899	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2900	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2901	case PGMPOOLKIND_ROOT_NESTED:
2902	case PGMPOOLKIND_PAE_PD_PHYS:
2903	case PGMPOOLKIND_PAE_PDPT_PHYS:
2904	case PGMPOOLKIND_32BIT_PD_PHYS:
2905	/** @todo can we return 0? (nobody is calling this...) */
2906	AssertFailed();
2907	return 0;
2908
2909	default:
2910	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2911	}
2912	}
2913
2914
2915	/**
2916	* Scans one shadow page table for mappings of a physical page.
2917	*
2918	* @returns true/false indicating removal of all relevant PTEs
2919	* @param pVM The VM handle.
2920	* @param pPhysPage The guest page in question.
2921	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
2922	* @param iShw The shadow page table.
2923	* @param iPte Page table entry or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown
2924	* @param cRefs The number of references made in that PT.
2925	*/
2926	static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t iPte, uint16_t cRefs)
2927	{
2928	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d iPte=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, iPte, cRefs));
2929	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2930	bool fRet = false;
2931
2932	/*
2933	* Assert sanity.
2934	*/
2935	Assert(cRefs == 1);
2936	Assert(iPte != NIL_PGMPOOL_PHYSEXT_IDX_PTE);
2937	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2938	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2939
2940	/*
2941	* Then, clear the actual mappings to the page in the shadow PT.
2942	*/
2943	switch (pPage->enmKind)
2944	{
2945	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2946	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2947	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2948	{
2949	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2950	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2951	uint32_t u32AndMask = 0;
2952	uint32_t u32OrMask = 0;
2953
2954	if (!fFlushPTEs)
2955	{
2956	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
2957	{
2958	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
2959	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
2960	u32OrMask = X86_PTE_RW;
2961	u32AndMask = UINT32_MAX;
2962	fRet = true;
2963	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
2964	break;
2965
2966	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
2967	u32OrMask = 0;
2968	u32AndMask = ~X86_PTE_RW;
2969	fRet = true;
2970	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
2971	break;
2972	default:
2973	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
2974	break;
2975	}
2976	}
2977	else
2978	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
2979
2980	/* Update the counter if we're removing references. */
2981	if (!u32AndMask)
2982	{
2983	Assert(pPage->cPresent >= cRefs);
2984	Assert(pPool->cPresent >= cRefs);
2985	pPage->cPresent -= cRefs;
2986	pPool->cPresent -= cRefs;
2987	}
2988
2989	if ((pPT->a[iPte].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2990	{
2991	X86PTE Pte;
2992
2993	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", iPte, pPT->a[iPte], cRefs));
2994	Pte.u = (pPT->a[iPte].u & u32AndMask) \| u32OrMask;
2995	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
2996	Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
2997
2998	ASMAtomicWriteSize(&pPT->a[iPte].u, Pte.u);
2999	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3000	return fRet;
3001	}
3002	#ifdef LOG_ENABLED
3003	Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3004	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3005	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3006	{
3007	Log(("i=%d cRefs=%d\n", i, cRefs--));
3008	}
3009	#endif
3010	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
3011	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3012	break;
3013	}
3014
3015	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3016	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3017	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3018	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3019	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3020	case PGMPOOLKIND_EPT_PT_FOR_PHYS: /* physical mask the same as PAE; RW bit as well; be careful! */
3021	{
3022	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3023	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3024	uint64_t u64OrMask = 0;
3025	uint64_t u64AndMask = 0;
3026
3027	if (!fFlushPTEs)
3028	{
3029	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3030	{
3031	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3032	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3033	u64OrMask = X86_PTE_RW;
3034	u64AndMask = UINT64_MAX;
3035	fRet = true;
3036	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3037	break;
3038
3039	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3040	u64OrMask = 0;
3041	u64AndMask = ~((uint64_t)X86_PTE_RW);
3042	fRet = true;
3043	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3044	break;
3045
3046	default:
3047	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3048	break;
3049	}
3050	}
3051	else
3052	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3053
3054	/* Update the counter if we're removing references. */
3055	if (!u64AndMask)
3056	{
3057	Assert(pPage->cPresent >= cRefs);
3058	Assert(pPool->cPresent >= cRefs);
3059	pPage->cPresent -= cRefs;
3060	pPool->cPresent -= cRefs;
3061	}
3062
3063	if ((pPT->a[iPte].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
3064	{
3065	X86PTEPAE Pte;
3066
3067	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", iPte, pPT->a[iPte], cRefs));
3068	Pte.u = (pPT->a[iPte].u & u64AndMask) \| u64OrMask;
3069	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3070	Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3071
3072	ASMAtomicWriteSize(&pPT->a[iPte].u, Pte.u);
3073	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3074	return fRet;
3075	}
3076	#ifdef LOG_ENABLED
3077	Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3078	Log(("Found %RX64 expected %RX64\n", pPT->a[iPte].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P), u64));
3079	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3080	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
3081	{
3082	Log(("i=%d cRefs=%d\n", i, cRefs--));
3083	}
3084	#endif
3085	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind));
3086	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3087	break;
3088	}
3089
3090	#ifdef PGM_WITH_LARGE_PAGES
3091	/* Large page case only. */
3092	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3093	{
3094	Assert(pVM->pgm.s.fNestedPaging);
3095
3096	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3097	PEPTPD pPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3098
3099	if ((pPD->a[iPte].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3100	{
3101	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64 cRefs=%#x\n", iPte, pPD->a[iPte], cRefs));
3102	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3103	pPD->a[iPte].u = 0;
3104	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3105
3106	/* Update the counter as we're removing references. */
3107	Assert(pPage->cPresent);
3108	Assert(pPool->cPresent);
3109	pPage->cPresent--;
3110	pPool->cPresent--;
3111
3112	return fRet;
3113	}
3114	# ifdef LOG_ENABLED
3115	Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3116	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3117	if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3118	{
3119	Log(("i=%d cRefs=%d\n", i, cRefs--));
3120	}
3121	# endif
3122	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3123	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3124	break;
3125	}
3126
3127	/* AMD-V nested paging - @todo merge with EPT as we only check the parts that are identical. */
3128	case PGMPOOLKIND_PAE_PD_PHYS:
3129	{
3130	Assert(pVM->pgm.s.fNestedPaging);
3131
3132	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3133	PX86PD pPD = (PX86PD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3134
3135	if ((pPD->a[iPte].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3136	{
3137	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64 cRefs=%#x\n", iPte, pPD->a[iPte], cRefs));
3138	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3139	pPD->a[iPte].u = 0;
3140	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3141
3142	/* Update the counter as we're removing references. */
3143	Assert(pPage->cPresent);
3144	Assert(pPool->cPresent);
3145	pPage->cPresent--;
3146	pPool->cPresent--;
3147	return fRet;
3148	}
3149	# ifdef LOG_ENABLED
3150	Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3151	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3152	if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3153	{
3154	Log(("i=%d cRefs=%d\n", i, cRefs--));
3155	}
3156	# endif
3157	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3158	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3159	break;
3160	}
3161	#endif /* PGM_WITH_LARGE_PAGES */
3162
3163	default:
3164	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3165	}
3166	return fRet;
3167	}
3168
3169
3170	/**
3171	* Scans one shadow page table for mappings of a physical page.
3172	*
3173	* @param pVM The VM handle.
3174	* @param pPhysPage The guest page in question.
3175	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3176	* @param iShw The shadow page table.
3177	* @param cRefs The number of references made in that PT.
3178	*/
3179	static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
3180	{
3181	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3182
3183	/* We should only come here with when there's only one reference to this physical page. */
3184	Assert(PGMPOOL_TD_GET_CREFS(PGM_PAGE_GET_TRACKING(pPhysPage)) == 1);
3185	Assert(cRefs == 1);
3186
3187	Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
3188	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3189	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, PGM_PAGE_GET_PTE_INDEX(pPhysPage), cRefs);
3190	if (!fKeptPTEs)
3191	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3192	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3193	}
3194
3195
3196	/**
3197	* Flushes a list of shadow page tables mapping the same physical page.
3198	*
3199	* @param pVM The VM handle.
3200	* @param pPhysPage The guest page in question.
3201	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3202	* @param iPhysExt The physical cross reference extent list to flush.
3203	*/
3204	static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3205	{
3206	Assert(PGMIsLockOwner(pVM));
3207	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3208	bool fKeepList = false;
3209
3210	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3211	Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3212
3213	const uint16_t iPhysExtStart = iPhysExt;
3214	PPGMPOOLPHYSEXT pPhysExt;
3215	do
3216	{
3217	Assert(iPhysExt < pPool->cMaxPhysExts);
3218	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3219	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3220	{
3221	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3222	{
3223	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], pPhysExt->apte[i], 1);
3224	if (!fKeptPTEs)
3225	{
3226	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3227	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3228	}
3229	else
3230	fKeepList = true;
3231	}
3232	}
3233	/* next */
3234	iPhysExt = pPhysExt->iNext;
3235	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3236
3237	if (!fKeepList)
3238	{
3239	/* insert the list into the free list and clear the ram range entry. */
3240	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3241	pPool->iPhysExtFreeHead = iPhysExtStart;
3242	/* Invalidate the tracking data. */
3243	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3244	}
3245
3246	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3247	}
3248
3249
3250	/**
3251	* Flushes all shadow page table mappings of the given guest page.
3252	*
3253	* This is typically called when the host page backing the guest one has been
3254	* replaced or when the page protection was changed due to an access handler.
3255	*
3256	* @returns VBox status code.
3257	* @retval VINF_SUCCESS if all references has been successfully cleared.
3258	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3259	* pool cleaning. FF and sync flags are set.
3260	*
3261	* @param pVM The VM handle.
3262	* @param GCPhysPage GC physical address of the page in question
3263	* @param pPhysPage The guest page in question.
3264	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3265	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3266	* flushed, it is NOT touched if this isn't necessary.
3267	* The caller MUST initialized this to @a false.
3268	*/
3269	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3270	{
3271	PVMCPU pVCpu = VMMGetCpu(pVM);
3272	pgmLock(pVM);
3273	int rc = VINF_SUCCESS;
3274
3275	#ifdef PGM_WITH_LARGE_PAGES
3276	/* Is this page part of a large page? */
3277	if (PGM_PAGE_GET_PDE_TYPE(pPhysPage) == PGM_PAGE_PDE_TYPE_PDE)
3278	{
3279	PPGMPAGE pPhysBase;
3280	RTGCPHYS GCPhysBase = GCPhysPage & X86_PDE2M_PAE_PG_MASK;
3281
3282	GCPhysPage &= X86_PDE_PAE_PG_MASK;
3283
3284	/* Fetch the large page base. */
3285	if (GCPhysBase != GCPhysPage)
3286	{
3287	pPhysBase = pgmPhysGetPage(&pVM->pgm.s, GCPhysBase);
3288	AssertFatal(pPhysBase);
3289	}
3290	else
3291	pPhysBase = pPhysPage;
3292
3293	Log(("pgmPoolTrackUpdateGCPhys: update large page PDE for %RGp (%RGp)\n", GCPhysBase, GCPhysPage));
3294
3295	if (PGM_PAGE_GET_PDE_TYPE(pPhysBase) == PGM_PAGE_PDE_TYPE_PDE)
3296	{
3297	/* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
3298	PGM_PAGE_SET_PDE_TYPE(pPhysBase, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3299
3300	/* Update the base as that only that one has a reference and there's only one PDE to clear. */
3301	rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysBase, pPhysBase, fFlushPTEs, pfFlushTLBs);
3302
3303	*pfFlushTLBs = true;
3304	pgmUnlock(pVM);
3305	return rc;
3306	}
3307	}
3308	#else
3309	NOREF(GCPhysPage);
3310	#endif /* PGM_WITH_LARGE_PAGES */
3311
3312	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3313	if (u16)
3314	{
3315	/*
3316	* The zero page is currently screwing up the tracking and we'll
3317	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3318	* is defined, zero pages won't normally be mapped. Some kind of solution
3319	* will be needed for this problem of course, but it will have to wait...
3320	*/
3321	if ( PGM_PAGE_IS_ZERO(pPhysPage)
3322	\|\| PGM_PAGE_IS_BALLOONED(pPhysPage))
3323	rc = VINF_PGM_GCPHYS_ALIASED;
3324	else
3325	{
3326	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC) /** @todo we can drop this now. */
3327	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3328	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3329	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
3330	# endif
3331
3332	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3333	pgmPoolTrackFlushGCPhysPT(pVM,
3334	pPhysPage,
3335	fFlushPTEs,
3336	PGMPOOL_TD_GET_IDX(u16),
3337	PGMPOOL_TD_GET_CREFS(u16));
3338	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3339	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3340	else
3341	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3342	*pfFlushTLBs = true;
3343
3344	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_R0) \|\| defined(IN_RC)
3345	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
3346	# endif
3347	}
3348	}
3349
3350	if (rc == VINF_PGM_GCPHYS_ALIASED)
3351	{
3352	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3353	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3354	rc = VINF_PGM_SYNC_CR3;
3355	}
3356	pgmUnlock(pVM);
3357	return rc;
3358	}
3359
3360
3361	/**
3362	* Scans all shadow page tables for mappings of a physical page.
3363	*
3364	* This may be slow, but it's most likely more efficient than cleaning
3365	* out the entire page pool / cache.
3366	*
3367	* @returns VBox status code.
3368	* @retval VINF_SUCCESS if all references has been successfully cleared.
3369	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3370	* a page pool cleaning.
3371	*
3372	* @param pVM The VM handle.
3373	* @param pPhysPage The guest page in question.
3374	*/
3375	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3376	{
3377	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3378	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3379	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3380	pPool->cUsedPages, pPool->cPresent, pPhysPage));
3381
3382	/*
3383	* There is a limit to what makes sense.
3384	*/
3385	if ( pPool->cPresent > 1024
3386	&& pVM->cCpus == 1)
3387	{
3388	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3389	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3390	return VINF_PGM_GCPHYS_ALIASED;
3391	}
3392
3393	/*
3394	* Iterate all the pages until we've encountered all that in use.
3395	* This is simple but not quite optimal solution.
3396	*/
3397	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3398	const uint32_t u32 = u64;
3399	unsigned cLeft = pPool->cUsedPages;
3400	unsigned iPage = pPool->cCurPages;
3401	while (--iPage >= PGMPOOL_IDX_FIRST)
3402	{
3403	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3404	if ( pPage->GCPhys != NIL_RTGCPHYS
3405	&& pPage->cPresent)
3406	{
3407	switch (pPage->enmKind)
3408	{
3409	/*
3410	* We only care about shadow page tables.
3411	*/
3412	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3413	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3414	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3415	{
3416	unsigned cPresent = pPage->cPresent;
3417	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3418	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3419	if (pPT->a[i].n.u1Present)
3420	{
3421	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3422	{
3423	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3424	pPT->a[i].u = 0;
3425
3426	/* Update the counter as we're removing references. */
3427	Assert(pPage->cPresent);
3428	Assert(pPool->cPresent);
3429	pPage->cPresent--;
3430	pPool->cPresent--;
3431	}
3432	if (!--cPresent)
3433	break;
3434	}
3435	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3436	break;
3437	}
3438
3439	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3440	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3441	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3442	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3443	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3444	{
3445	unsigned cPresent = pPage->cPresent;
3446	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3447	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3448	if (pPT->a[i].n.u1Present)
3449	{
3450	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
3451	{
3452	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3453	pPT->a[i].u = 0;
3454
3455	/* Update the counter as we're removing references. */
3456	Assert(pPage->cPresent);
3457	Assert(pPool->cPresent);
3458	pPage->cPresent--;
3459	pPool->cPresent--;
3460	}
3461	if (!--cPresent)
3462	break;
3463	}
3464	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3465	break;
3466	}
3467	#ifndef IN_RC
3468	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3469	{
3470	unsigned cPresent = pPage->cPresent;
3471	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3472	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3473	if (pPT->a[i].n.u1Present)
3474	{
3475	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
3476	{
3477	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3478	pPT->a[i].u = 0;
3479
3480	/* Update the counter as we're removing references. */
3481	Assert(pPage->cPresent);
3482	Assert(pPool->cPresent);
3483	pPage->cPresent--;
3484	pPool->cPresent--;
3485	}
3486	if (!--cPresent)
3487	break;
3488	}
3489	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3490	break;
3491	}
3492	#endif
3493	}
3494	if (!--cLeft)
3495	break;
3496	}
3497	}
3498
3499	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3500	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3501
3502	/*
3503	* There is a limit to what makes sense. The above search is very expensive, so force a pgm pool flush.
3504	*/
3505	if (pPool->cPresent > 1024)
3506	{
3507	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3508	return VINF_PGM_GCPHYS_ALIASED;
3509	}
3510
3511	return VINF_SUCCESS;
3512	}
3513
3514
3515	/**
3516	* Clears the user entry in a user table.
3517	*
3518	* This is used to remove all references to a page when flushing it.
3519	*/
3520	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3521	{
3522	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3523	Assert(pUser->iUser < pPool->cCurPages);
3524	uint32_t iUserTable = pUser->iUserTable;
3525
3526	/*
3527	* Map the user page.
3528	*/
3529	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3530	union
3531	{
3532	uint64_t *pau64;
3533	uint32_t *pau32;
3534	} u;
3535	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3536
3537	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3538
3539	/* Safety precaution in case we change the paging for other modes too in the future. */
3540	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
3541
3542	#ifdef VBOX_STRICT
3543	/*
3544	* Some sanity checks.
3545	*/
3546	switch (pUserPage->enmKind)
3547	{
3548	case PGMPOOLKIND_32BIT_PD:
3549	case PGMPOOLKIND_32BIT_PD_PHYS:
3550	Assert(iUserTable < X86_PG_ENTRIES);
3551	break;
3552	case PGMPOOLKIND_PAE_PDPT:
3553	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3554	case PGMPOOLKIND_PAE_PDPT_PHYS:
3555	Assert(iUserTable < 4);
3556	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3557	break;
3558	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3559	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3560	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3561	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3562	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3563	case PGMPOOLKIND_PAE_PD_PHYS:
3564	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3565	break;
3566	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3567	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3568	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3569	break;
3570	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3571	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3572	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3573	break;
3574	case PGMPOOLKIND_64BIT_PML4:
3575	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3576	/* GCPhys >> PAGE_SHIFT is the index here */
3577	break;
3578	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3579	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3580	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3581	break;
3582
3583	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3584	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3585	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3586	break;
3587
3588	case PGMPOOLKIND_ROOT_NESTED:
3589	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3590	break;
3591
3592	default:
3593	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3594	break;
3595	}
3596	#endif /* VBOX_STRICT */
3597
3598	/*
3599	* Clear the entry in the user page.
3600	*/
3601	switch (pUserPage->enmKind)
3602	{
3603	/* 32-bit entries */
3604	case PGMPOOLKIND_32BIT_PD:
3605	case PGMPOOLKIND_32BIT_PD_PHYS:
3606	ASMAtomicWriteSize(&u.pau32[iUserTable], 0);
3607	break;
3608
3609	/* 64-bit entries */
3610	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3611	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3612	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3613	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3614	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3615	#if defined(IN_RC)
3616	/*
3617	* In 32 bits PAE mode we must invalidate the TLB when changing a
3618	* PDPT entry; the CPU fetches them only during cr3 load, so any
3619	* non-present PDPT will continue to cause page faults.
3620	*/
3621	ASMReloadCR3();
3622	/* no break */
3623	#endif
3624	case PGMPOOLKIND_PAE_PD_PHYS:
3625	case PGMPOOLKIND_PAE_PDPT_PHYS:
3626	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3627	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3628	case PGMPOOLKIND_64BIT_PML4:
3629	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3630	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3631	case PGMPOOLKIND_PAE_PDPT:
3632	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3633	case PGMPOOLKIND_ROOT_NESTED:
3634	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3635	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3636	ASMAtomicWriteSize(&u.pau64[iUserTable], 0);
3637	break;
3638
3639	default:
3640	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3641	}
3642	PGM_DYNMAP_UNUSED_HINT_VM(pPool->CTX_SUFF(pVM), u.pau64);
3643	}
3644
3645
3646	/**
3647	* Clears all users of a page.
3648	*/
3649	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3650	{
3651	/*
3652	* Free all the user records.
3653	*/
3654	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3655
3656	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3657	uint16_t i = pPage->iUserHead;
3658	while (i != NIL_PGMPOOL_USER_INDEX)
3659	{
3660	/* Clear enter in user table. */
3661	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3662
3663	/* Free it. */
3664	const uint16_t iNext = paUsers[i].iNext;
3665	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3666	paUsers[i].iNext = pPool->iUserFreeHead;
3667	pPool->iUserFreeHead = i;
3668
3669	/* Next. */
3670	i = iNext;
3671	}
3672	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3673	}
3674
3675
3676	/**
3677	* Allocates a new physical cross reference extent.
3678	*
3679	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3680	* @param pVM The VM handle.
3681	* @param piPhysExt Where to store the phys ext index.
3682	*/
3683	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3684	{
3685	Assert(PGMIsLockOwner(pVM));
3686	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3687	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3688	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3689	{
3690	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3691	return NULL;
3692	}
3693	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3694	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3695	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3696	*piPhysExt = iPhysExt;
3697	return pPhysExt;
3698	}
3699
3700
3701	/**
3702	* Frees a physical cross reference extent.
3703	*
3704	* @param pVM The VM handle.
3705	* @param iPhysExt The extent to free.
3706	*/
3707	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3708	{
3709	Assert(PGMIsLockOwner(pVM));
3710	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3711	Assert(iPhysExt < pPool->cMaxPhysExts);
3712	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3713	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3714	{
3715	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3716	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3717	}
3718	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3719	pPool->iPhysExtFreeHead = iPhysExt;
3720	}
3721
3722
3723	/**
3724	* Frees a physical cross reference extent.
3725	*
3726	* @param pVM The VM handle.
3727	* @param iPhysExt The extent to free.
3728	*/
3729	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3730	{
3731	Assert(PGMIsLockOwner(pVM));
3732	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3733
3734	const uint16_t iPhysExtStart = iPhysExt;
3735	PPGMPOOLPHYSEXT pPhysExt;
3736	do
3737	{
3738	Assert(iPhysExt < pPool->cMaxPhysExts);
3739	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3740	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3741	{
3742	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3743	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3744	}
3745
3746	/* next */
3747	iPhysExt = pPhysExt->iNext;
3748	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3749
3750	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3751	pPool->iPhysExtFreeHead = iPhysExtStart;
3752	}
3753
3754
3755	/**
3756	* Insert a reference into a list of physical cross reference extents.
3757	*
3758	* @returns The new tracking data for PGMPAGE.
3759	*
3760	* @param pVM The VM handle.
3761	* @param iPhysExt The physical extent index of the list head.
3762	* @param iShwPT The shadow page table index.
3763	* @param iPte Page table entry
3764	*
3765	*/
3766	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT, uint16_t iPte)
3767	{
3768	Assert(PGMIsLockOwner(pVM));
3769	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3770	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3771
3772	/* special common case. */
3773	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3774	{
3775	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3776	paPhysExts[iPhysExt].apte[2] = iPte;
3777	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3778	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d pte %d}\n", iPhysExt, iShwPT, iPte));
3779	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3780	}
3781
3782	/* general treatment. */
3783	const uint16_t iPhysExtStart = iPhysExt;
3784	unsigned cMax = 15;
3785	for (;;)
3786	{
3787	Assert(iPhysExt < pPool->cMaxPhysExts);
3788	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3789	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3790	{
3791	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3792	paPhysExts[iPhysExt].apte[i] = iPte;
3793	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3794	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d pte %d} i=%d cMax=%d\n", iPhysExt, iShwPT, iPte, i, cMax));
3795	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3796	}
3797	if (!--cMax)
3798	{
3799	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackOverflows);
3800	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3801	LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3802	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3803	}
3804	}
3805
3806	/* add another extent to the list. */
3807	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3808	if (!pNew)
3809	{
3810	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackNoExtentsLeft);
3811	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3812	LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3813	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3814	}
3815	pNew->iNext = iPhysExtStart;
3816	pNew->aidx[0] = iShwPT;
3817	pNew->apte[0] = iPte;
3818	LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d pte %d}->%d\n", iPhysExt, iShwPT, iPte, iPhysExtStart));
3819	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3820	}
3821
3822
3823	/**
3824	* Add a reference to guest physical page where extents are in use.
3825	*
3826	* @returns The new tracking data for PGMPAGE.
3827	*
3828	* @param pVM The VM handle.
3829	* @param pPhysPage Pointer to the aPages entry in the ram range.
3830	* @param u16 The ram range flags (top 16-bits).
3831	* @param iShwPT The shadow page table index.
3832	* @param iPte Page table entry
3833	*/
3834	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte)
3835	{
3836	pgmLock(pVM);
3837	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3838	{
3839	/*
3840	* Convert to extent list.
3841	*/
3842	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3843	uint16_t iPhysExt;
3844	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3845	if (pPhysExt)
3846	{
3847	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3848	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliased);
3849	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3850	pPhysExt->apte[0] = PGM_PAGE_GET_PTE_INDEX(pPhysPage);
3851	pPhysExt->aidx[1] = iShwPT;
3852	pPhysExt->apte[1] = iPte;
3853	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3854	}
3855	else
3856	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3857	}
3858	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3859	{
3860	/*
3861	* Insert into the extent list.
3862	*/
3863	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT, iPte);
3864	}
3865	else
3866	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedLots);
3867	pgmUnlock(pVM);
3868	return u16;
3869	}
3870
3871	/**
3872	* Clear references to guest physical memory.
3873	*
3874	* @param pPool The pool.
3875	* @param pPage The page.
3876	* @param pPhysPage Pointer to the aPages entry in the ram range.
3877	* @param iPte Shadow PTE index
3878	*/
3879	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage, uint16_t iPte)
3880	{
3881	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3882	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3883
3884	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3885	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3886	{
3887	PVM pVM = pPool->CTX_SUFF(pVM);
3888	pgmLock(pVM);
3889
3890	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3891	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3892	do
3893	{
3894	Assert(iPhysExt < pPool->cMaxPhysExts);
3895
3896	/*
3897	* Look for the shadow page and check if it's all freed.
3898	*/
3899	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3900	{
3901	if ( paPhysExts[iPhysExt].aidx[i] == pPage->idx
3902	&& paPhysExts[iPhysExt].apte[i] == iPte)
3903	{
3904	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3905	paPhysExts[iPhysExt].apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3906
3907	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3908	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3909	{
3910	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3911	pgmUnlock(pVM);
3912	return;
3913	}
3914
3915	/* we can free the node. */
3916	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3917	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3918	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3919	{
3920	/* lonely node */
3921	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3922	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3923	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3924	}
3925	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3926	{
3927	/* head */
3928	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3929	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3930	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3931	}
3932	else
3933	{
3934	/* in list */
3935	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d in list\n", pPhysPage, pPage->idx));
3936	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3937	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3938	}
3939	iPhysExt = iPhysExtNext;
3940	pgmUnlock(pVM);
3941	return;
3942	}
3943	}
3944
3945	/* next */
3946	iPhysExtPrev = iPhysExt;
3947	iPhysExt = paPhysExts[iPhysExt].iNext;
3948	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3949
3950	pgmUnlock(pVM);
3951	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3952	}
3953	else /* nothing to do */
3954	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3955	}
3956
3957	/**
3958	* Clear references to guest physical memory.
3959	*
3960	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3961	* is assumed to be correct, so the linear search can be skipped and we can assert
3962	* at an earlier point.
3963	*
3964	* @param pPool The pool.
3965	* @param pPage The page.
3966	* @param HCPhys The host physical address corresponding to the guest page.
3967	* @param GCPhys The guest physical address corresponding to HCPhys.
3968	* @param iPte Shadow PTE index
3969	*/
3970	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys, uint16_t iPte)
3971	{
3972	/*
3973	* Walk range list.
3974	*/
3975	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3976	while (pRam)
3977	{
3978	RTGCPHYS off = GCPhys - pRam->GCPhys;
3979	if (off < pRam->cb)
3980	{
3981	/* does it match? */
3982	const unsigned iPage = off >> PAGE_SHIFT;
3983	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3984	#ifdef LOG_ENABLED
3985	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3986	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3987	#endif
3988	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3989	{
3990	Assert(pPage->cPresent);
3991	Assert(pPool->cPresent);
3992	pPage->cPresent--;
3993	pPool->cPresent--;
3994	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
3995	return;
3996	}
3997	break;
3998	}
3999	pRam = pRam->CTX_SUFF(pNext);
4000	}
4001	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4002	}
4003
4004
4005	/**
4006	* Clear references to guest physical memory.
4007	*
4008	* @param pPool The pool.
4009	* @param pPage The page.
4010	* @param HCPhys The host physical address corresponding to the guest page.
4011	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4012	* @param iPte Shadow pte index
4013	*/
4014	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte)
4015	{
4016	RTHCPHYS HCPhysExpected = 0xDEADBEEFDEADBEEFULL;
4017
4018	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4019
4020	/*
4021	* Walk range list.
4022	*/
4023	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4024	while (pRam)
4025	{
4026	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
4027	if (off < pRam->cb)
4028	{
4029	/* does it match? */
4030	const unsigned iPage = off >> PAGE_SHIFT;
4031	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4032	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4033	{
4034	Assert(pPage->cPresent);
4035	Assert(pPool->cPresent);
4036	pPage->cPresent--;
4037	pPool->cPresent--;
4038	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4039	return;
4040	}
4041	HCPhysExpected = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
4042	break;
4043	}
4044	pRam = pRam->CTX_SUFF(pNext);
4045	}
4046
4047	/*
4048	* Damn, the hint didn't work. We'll have to do an expensive linear search.
4049	*/
4050	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4051	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4052	while (pRam)
4053	{
4054	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4055	while (iPage-- > 0)
4056	{
4057	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4058	{
4059	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4060	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4061	Assert(pPage->cPresent);
4062	Assert(pPool->cPresent);
4063	pPage->cPresent--;
4064	pPool->cPresent--;
4065	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4066	return;
4067	}
4068	}
4069	pRam = pRam->CTX_SUFF(pNext);
4070	}
4071
4072	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp (Expected HCPhys with hint = %RHp)\n", HCPhys, GCPhysHint, HCPhysExpected));
4073	}
4074
4075
4076	/**
4077	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
4078	*
4079	* @param pPool The pool.
4080	* @param pPage The page.
4081	* @param pShwPT The shadow page table (mapping of the page).
4082	* @param pGstPT The guest page table.
4083	*/
4084	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4085	{
4086	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4087	if (pShwPT->a[i].n.u1Present)
4088	{
4089	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4090	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4091	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK, i);
4092	if (!pPage->cPresent)
4093	break;
4094	}
4095	}
4096
4097
4098	/**
4099	* Clear references to guest physical memory in a PAE / 32-bit page table.
4100	*
4101	* @param pPool The pool.
4102	* @param pPage The page.
4103	* @param pShwPT The shadow page table (mapping of the page).
4104	* @param pGstPT The guest page table (just a half one).
4105	*/
4106	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
4107	{
4108	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4109	if (pShwPT->a[i].n.u1Present)
4110	{
4111	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4112	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4113	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK, i);
4114	if (!pPage->cPresent)
4115	break;
4116	}
4117	}
4118
4119
4120	/**
4121	* Clear references to guest physical memory in a PAE / PAE page table.
4122	*
4123	* @param pPool The pool.
4124	* @param pPage The page.
4125	* @param pShwPT The shadow page table (mapping of the page).
4126	* @param pGstPT The guest page table.
4127	*/
4128	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
4129	{
4130	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4131	if (pShwPT->a[i].n.u1Present)
4132	{
4133	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4134	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4135	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
4136	if (!pPage->cPresent)
4137	break;
4138	}
4139	}
4140
4141
4142	/**
4143	* Clear references to guest physical memory in a 32-bit / 4MB page table.
4144	*
4145	* @param pPool The pool.
4146	* @param pPage The page.
4147	* @param pShwPT The shadow page table (mapping of the page).
4148	*/
4149	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4150	{
4151	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4152	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4153	if (pShwPT->a[i].n.u1Present)
4154	{
4155	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4156	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4157	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys, i);
4158	if (!pPage->cPresent)
4159	break;
4160	}
4161	}
4162
4163
4164	/**
4165	* Clear references to guest physical memory in a PAE / 2/4MB page table.
4166	*
4167	* @param pPool The pool.
4168	* @param pPage The page.
4169	* @param pShwPT The shadow page table (mapping of the page).
4170	*/
4171	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
4172	{
4173	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4174	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4175	if (pShwPT->a[i].n.u1Present)
4176	{
4177	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4178	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
4179	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys, i);
4180	if (!pPage->cPresent)
4181	break;
4182	}
4183	}
4184
4185
4186	/**
4187	* Clear references to shadowed pages in an EPT page table.
4188	*
4189	* @param pPool The pool.
4190	* @param pPage The page.
4191	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4192	*/
4193	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4194	{
4195	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4196	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4197	if (pShwPT->a[i].n.u1Present)
4198	{
4199	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4200	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4201	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys, i);
4202	if (!pPage->cPresent)
4203	break;
4204	}
4205	}
4206
4207
4208
4209	/**
4210	* Clear references to shadowed pages in a 32 bits page directory.
4211	*
4212	* @param pPool The pool.
4213	* @param pPage The page.
4214	* @param pShwPD The shadow page directory (mapping of the page).
4215	*/
4216	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4217	{
4218	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4219	{
4220	if ( pShwPD->a[i].n.u1Present
4221	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4222	)
4223	{
4224	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4225	if (pSubPage)
4226	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4227	else
4228	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4229	}
4230	}
4231	}
4232
4233	/**
4234	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4235	*
4236	* @param pPool The pool.
4237	* @param pPage The page.
4238	* @param pShwPD The shadow page directory (mapping of the page).
4239	*/
4240	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4241	{
4242	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4243	{
4244	if ( pShwPD->a[i].n.u1Present
4245	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4246	)
4247	{
4248	#ifdef PGM_WITH_LARGE_PAGES
4249	if (pShwPD->a[i].b.u1Size)
4250	{
4251	Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
4252	i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4253	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys /* == base of 2 MB page */, i);
4254	}
4255	else
4256	#endif
4257	{
4258	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4259	if (pSubPage)
4260	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4261	else
4262	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4263	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4264	}
4265	}
4266	}
4267	}
4268
4269	/**
4270	* Clear references to shadowed pages in a PAE page directory pointer table.
4271	*
4272	* @param pPool The pool.
4273	* @param pPage The page.
4274	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4275	*/
4276	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4277	{
4278	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4279	{
4280	if ( pShwPDPT->a[i].n.u1Present
4281	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4282	)
4283	{
4284	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4285	if (pSubPage)
4286	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4287	else
4288	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4289	}
4290	}
4291	}
4292
4293
4294	/**
4295	* Clear references to shadowed pages in a 64-bit page directory pointer table.
4296	*
4297	* @param pPool The pool.
4298	* @param pPage The page.
4299	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4300	*/
4301	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4302	{
4303	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4304	{
4305	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
4306	if (pShwPDPT->a[i].n.u1Present)
4307	{
4308	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4309	if (pSubPage)
4310	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4311	else
4312	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4313	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4314	}
4315	}
4316	}
4317
4318
4319	/**
4320	* Clear references to shadowed pages in a 64-bit level 4 page table.
4321	*
4322	* @param pPool The pool.
4323	* @param pPage The page.
4324	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4325	*/
4326	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4327	{
4328	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4329	{
4330	if (pShwPML4->a[i].n.u1Present)
4331	{
4332	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4333	if (pSubPage)
4334	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4335	else
4336	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4337	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4338	}
4339	}
4340	}
4341
4342
4343	/**
4344	* Clear references to shadowed pages in an EPT page directory.
4345	*
4346	* @param pPool The pool.
4347	* @param pPage The page.
4348	* @param pShwPD The shadow page directory (mapping of the page).
4349	*/
4350	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4351	{
4352	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4353	{
4354	if (pShwPD->a[i].n.u1Present)
4355	{
4356	#ifdef PGM_WITH_LARGE_PAGES
4357	if (pShwPD->a[i].b.u1Size)
4358	{
4359	Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
4360	i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4361	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys /* == base of 2 MB page */, i);
4362	}
4363	else
4364	#endif
4365	{
4366	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4367	if (pSubPage)
4368	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4369	else
4370	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4371	}
4372	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4373	}
4374	}
4375	}
4376
4377
4378	/**
4379	* Clear references to shadowed pages in an EPT page directory pointer table.
4380	*
4381	* @param pPool The pool.
4382	* @param pPage The page.
4383	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4384	*/
4385	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4386	{
4387	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4388	{
4389	if (pShwPDPT->a[i].n.u1Present)
4390	{
4391	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4392	if (pSubPage)
4393	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4394	else
4395	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4396	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4397	}
4398	}
4399	}
4400
4401
4402	/**
4403	* Clears all references made by this page.
4404	*
4405	* This includes other shadow pages and GC physical addresses.
4406	*
4407	* @param pPool The pool.
4408	* @param pPage The page.
4409	*/
4410	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4411	{
4412	/*
4413	* Map the shadow page and take action according to the page kind.
4414	*/
4415	PVM pVM = pPool->CTX_SUFF(pVM);
4416	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4417	switch (pPage->enmKind)
4418	{
4419	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4420	{
4421	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4422	void *pvGst;
4423	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4424	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4425	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4426	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4427	break;
4428	}
4429
4430	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4431	{
4432	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4433	void *pvGst;
4434	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4435	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
4436	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4437	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4438	break;
4439	}
4440
4441	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4442	{
4443	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4444	void *pvGst;
4445	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4446	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
4447	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4448	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4449	break;
4450	}
4451
4452	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4453	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4454	{
4455	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4456	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4457	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4458	break;
4459	}
4460
4461	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4462	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4463	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4464	{
4465	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4466	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
4467	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4468	break;
4469	}
4470
4471	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4472	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4473	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4474	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4475	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4476	case PGMPOOLKIND_PAE_PD_PHYS:
4477	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4478	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4479	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4480	break;
4481
4482	case PGMPOOLKIND_32BIT_PD_PHYS:
4483	case PGMPOOLKIND_32BIT_PD:
4484	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4485	break;
4486
4487	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4488	case PGMPOOLKIND_PAE_PDPT:
4489	case PGMPOOLKIND_PAE_PDPT_PHYS:
4490	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4491	break;
4492
4493	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4494	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4495	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4496	break;
4497
4498	case PGMPOOLKIND_64BIT_PML4:
4499	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4500	break;
4501
4502	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4503	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4504	break;
4505
4506	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4507	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4508	break;
4509
4510	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4511	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4512	break;
4513
4514	default:
4515	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4516	}
4517
4518	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4519	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4520	ASMMemZeroPage(pvShw);
4521	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4522	pPage->fZeroed = true;
4523	Assert(!pPage->cPresent);
4524	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
4525	}
4526
4527	/**
4528	* Flushes a pool page.
4529	*
4530	* This moves the page to the free list after removing all user references to it.
4531	*
4532	* @returns VBox status code.
4533	* @retval VINF_SUCCESS on success.
4534	* @param pPool The pool.
4535	* @param HCPhys The HC physical address of the shadow page.
4536	* @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
4537	*/
4538	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush)
4539	{
4540	PVM pVM = pPool->CTX_SUFF(pVM);
4541	bool fFlushRequired = false;
4542
4543	int rc = VINF_SUCCESS;
4544	STAM_PROFILE_START(&pPool->StatFlushPage, f);
4545	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4546	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4547
4548	/*
4549	* Quietly reject any attempts at flushing any of the special root pages.
4550	*/
4551	if (pPage->idx < PGMPOOL_IDX_FIRST)
4552	{
4553	AssertFailed(); /* can no longer happen */
4554	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4555	return VINF_SUCCESS;
4556	}
4557
4558	pgmLock(pVM);
4559
4560	/*
4561	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4562	*/
4563	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4564	{
4565	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4566	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4567	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4568	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4569	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4570	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4571	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4572	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4573	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4574	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4575	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4576	pgmUnlock(pVM);
4577	return VINF_SUCCESS;
4578	}
4579
4580	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4581	/* Start a subset so we won't run out of mapping space. */
4582	PVMCPU pVCpu = VMMGetCpu(pVM);
4583	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
4584	#endif
4585
4586	/*
4587	* Mark the page as being in need of an ASMMemZeroPage().
4588	*/
4589	pPage->fZeroed = false;
4590
4591	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4592	if (pPage->fDirty)
4593	pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirty, false /* do not remove */);
4594	#endif
4595
4596	/* If there are any users of this table, then we must issue a tlb flush on all VCPUs. */
4597	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
4598	fFlushRequired = true;
4599
4600	/*
4601	* Clear the page.
4602	*/
4603	pgmPoolTrackClearPageUsers(pPool, pPage);
4604	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4605	pgmPoolTrackDeref(pPool, pPage);
4606	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4607
4608	/*
4609	* Flush it from the cache.
4610	*/
4611	pgmPoolCacheFlushPage(pPool, pPage);
4612
4613	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_R0) \|\| defined(IN_RC)
4614	/* Heavy stuff done. */
4615	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
4616	#endif
4617
4618	/*
4619	* Deregistering the monitoring.
4620	*/
4621	if (pPage->fMonitored)
4622	rc = pgmPoolMonitorFlush(pPool, pPage);
4623
4624	/*
4625	* Free the page.
4626	*/
4627	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4628	pPage->iNext = pPool->iFreeHead;
4629	pPool->iFreeHead = pPage->idx;
4630	pPage->enmKind = PGMPOOLKIND_FREE;
4631	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4632	pPage->GCPhys = NIL_RTGCPHYS;
4633	pPage->fReusedFlushPending = false;
4634
4635	pPool->cUsedPages--;
4636
4637	/* Flush the TLBs of all VCPUs if required. */
4638	if ( fFlushRequired
4639	&& fFlush)
4640	{
4641	PGM_INVL_ALL_VCPU_TLBS(pVM);
4642	}
4643
4644	pgmUnlock(pVM);
4645	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4646	return rc;
4647	}
4648
4649
4650	/**
4651	* Frees a usage of a pool page.
4652	*
4653	* The caller is responsible to updating the user table so that it no longer
4654	* references the shadow page.
4655	*
4656	* @param pPool The pool.
4657	* @param HCPhys The HC physical address of the shadow page.
4658	* @param iUser The shadow page pool index of the user table.
4659	* @param iUserTable The index into the user table (shadowed).
4660	*/
4661	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4662	{
4663	PVM pVM = pPool->CTX_SUFF(pVM);
4664
4665	STAM_PROFILE_START(&pPool->StatFree, a);
4666	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4667	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4668	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4669	pgmLock(pVM);
4670	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4671	if (!pPage->fCached)
4672	pgmPoolFlushPage(pPool, pPage);
4673	pgmUnlock(pVM);
4674	STAM_PROFILE_STOP(&pPool->StatFree, a);
4675	}
4676
4677
4678	/**
4679	* Makes one or more free page free.
4680	*
4681	* @returns VBox status code.
4682	* @retval VINF_SUCCESS on success.
4683	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4684	*
4685	* @param pPool The pool.
4686	* @param enmKind Page table kind
4687	* @param iUser The user of the page.
4688	*/
4689	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4690	{
4691	PVM pVM = pPool->CTX_SUFF(pVM);
4692
4693	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4694
4695	/*
4696	* If the pool isn't full grown yet, expand it.
4697	*/
4698	if ( pPool->cCurPages < pPool->cMaxPages
4699	#if defined(IN_RC)
4700	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4701	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4702	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4703	#endif
4704	)
4705	{
4706	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4707	#ifdef IN_RING3
4708	int rc = PGMR3PoolGrow(pVM);
4709	#else
4710	int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4711	#endif
4712	if (RT_FAILURE(rc))
4713	return rc;
4714	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4715	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4716	return VINF_SUCCESS;
4717	}
4718
4719	/*
4720	* Free one cached page.
4721	*/
4722	return pgmPoolCacheFreeOne(pPool, iUser);
4723	}
4724
4725	/**
4726	* Allocates a page from the pool.
4727	*
4728	* This page may actually be a cached page and not in need of any processing
4729	* on the callers part.
4730	*
4731	* @returns VBox status code.
4732	* @retval VINF_SUCCESS if a NEW page was allocated.
4733	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4734	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4735	* @param pVM The VM handle.
4736	* @param GCPhys The GC physical address of the page we're gonna shadow.
4737	* For 4MB and 2MB PD entries, it's the first address the
4738	* shadow PT is covering.
4739	* @param enmKind The kind of mapping.
4740	* @param enmAccess Access type for the mapping (only relevant for big pages)
4741	* @param iUser The shadow page pool index of the user table.
4742	* @param iUserTable The index into the user table (shadowed).
4743	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4744	* @param fLockPage Lock the page
4745	*/
4746	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage)
4747	{
4748	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4749	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4750	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4751	*ppPage = NULL;
4752	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4753	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4754	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4755
4756	pgmLock(pVM);
4757
4758	if (pPool->fCacheEnabled)
4759	{
4760	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4761	if (RT_SUCCESS(rc2))
4762	{
4763	if (fLockPage)
4764	pgmPoolLockPage(pPool, *ppPage);
4765	pgmUnlock(pVM);
4766	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4767	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4768	return rc2;
4769	}
4770	}
4771
4772	/*
4773	* Allocate a new one.
4774	*/
4775	int rc = VINF_SUCCESS;
4776	uint16_t iNew = pPool->iFreeHead;
4777	if (iNew == NIL_PGMPOOL_IDX)
4778	{
4779	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4780	if (RT_FAILURE(rc))
4781	{
4782	pgmUnlock(pVM);
4783	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4784	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4785	return rc;
4786	}
4787	iNew = pPool->iFreeHead;
4788	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4789	}
4790
4791	/* unlink the free head */
4792	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4793	pPool->iFreeHead = pPage->iNext;
4794	pPage->iNext = NIL_PGMPOOL_IDX;
4795
4796	/*
4797	* Initialize it.
4798	*/
4799	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4800	pPage->enmKind = enmKind;
4801	pPage->enmAccess = enmAccess;
4802	pPage->GCPhys = GCPhys;
4803	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4804	pPage->fMonitored = false;
4805	pPage->fCached = false;
4806	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4807	pPage->fDirty = false;
4808	#endif
4809	pPage->fReusedFlushPending = false;
4810	pPage->cModifications = 0;
4811	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4812	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4813	pPage->cLocked = 0;
4814	pPage->cPresent = 0;
4815	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
4816	pPage->pvLastAccessHandlerFault = 0;
4817	pPage->cLastAccessHandlerCount = 0;
4818	pPage->pvLastAccessHandlerRip = 0;
4819
4820	/*
4821	* Insert into the tracking and cache. If this fails, free the page.
4822	*/
4823	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4824	if (RT_FAILURE(rc3))
4825	{
4826	pPool->cUsedPages--;
4827	pPage->enmKind = PGMPOOLKIND_FREE;
4828	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4829	pPage->GCPhys = NIL_RTGCPHYS;
4830	pPage->iNext = pPool->iFreeHead;
4831	pPool->iFreeHead = pPage->idx;
4832	pgmUnlock(pVM);
4833	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4834	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4835	return rc3;
4836	}
4837
4838	/*
4839	* Commit the allocation, clear the page and return.
4840	*/
4841	#ifdef VBOX_WITH_STATISTICS
4842	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4843	pPool->cUsedPagesHigh = pPool->cUsedPages;
4844	#endif
4845
4846	if (!pPage->fZeroed)
4847	{
4848	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4849	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4850	ASMMemZeroPage(pv);
4851	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4852	}
4853
4854	*ppPage = pPage;
4855	if (fLockPage)
4856	pgmPoolLockPage(pPool, pPage);
4857	pgmUnlock(pVM);
4858	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4859	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4860	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4861	return rc;
4862	}
4863
4864
4865	/**
4866	* Frees a usage of a pool page.
4867	*
4868	* @param pVM The VM handle.
4869	* @param HCPhys The HC physical address of the shadow page.
4870	* @param iUser The shadow page pool index of the user table.
4871	* @param iUserTable The index into the user table (shadowed).
4872	*/
4873	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4874	{
4875	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4876	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4877	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4878	}
4879
4880	/**
4881	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4882	*
4883	* @returns Pointer to the shadow page structure.
4884	* @param pPool The pool.
4885	* @param HCPhys The HC physical address of the shadow page.
4886	*/
4887	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4888	{
4889	PVM pVM = pPool->CTX_SUFF(pVM);
4890
4891	Assert(PGMIsLockOwner(pVM));
4892
4893	/*
4894	* Look up the page.
4895	*/
4896	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4897
4898	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4899	return pPage;
4900	}
4901
4902	#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
4903	/**
4904	* Flush the specified page if present
4905	*
4906	* @param pVM The VM handle.
4907	* @param GCPhys Guest physical address of the page to flush
4908	*/
4909	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
4910	{
4911	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4912
4913	VM_ASSERT_EMT(pVM);
4914
4915	/*
4916	* Look up the GCPhys in the hash.
4917	*/
4918	GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
4919	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
4920	if (i == NIL_PGMPOOL_IDX)
4921	return;
4922
4923	do
4924	{
4925	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4926	if (pPage->GCPhys - GCPhys < PAGE_SIZE)
4927	{
4928	switch (pPage->enmKind)
4929	{
4930	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4931	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4932	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4933	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4934	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4935	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4936	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4937	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4938	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4939	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4940	case PGMPOOLKIND_64BIT_PML4:
4941	case PGMPOOLKIND_32BIT_PD:
4942	case PGMPOOLKIND_PAE_PDPT:
4943	{
4944	Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
4945	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4946	if (pPage->fDirty)
4947	STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
4948	else
4949	#endif
4950	STAM_COUNTER_INC(&pPool->StatForceFlushPage);
4951	Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
4952	pgmPoolMonitorChainFlush(pPool, pPage);
4953	return;
4954	}
4955
4956	/* ignore, no monitoring. */
4957	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4958	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4959	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4960	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4961	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4962	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4963	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4964	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4965	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4966	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4967	case PGMPOOLKIND_ROOT_NESTED:
4968	case PGMPOOLKIND_PAE_PD_PHYS:
4969	case PGMPOOLKIND_PAE_PDPT_PHYS:
4970	case PGMPOOLKIND_32BIT_PD_PHYS:
4971	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4972	break;
4973
4974	default:
4975	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
4976	}
4977	}
4978
4979	/* next */
4980	i = pPage->iNext;
4981	} while (i != NIL_PGMPOOL_IDX);
4982	return;
4983	}
4984	#endif /* IN_RING3 */
4985
4986	#ifdef IN_RING3
4987
4988
4989	/**
4990	* Reset CPU on hot plugging.
4991	*
4992	* @param pVM The VM handle.
4993	* @param pVCpu The virtual CPU.
4994	*/
4995	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
4996	{
4997	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4998
4999	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5000	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5001	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5002	}
5003
5004
5005	/**
5006	* Flushes the entire cache.
5007	*
5008	* It will assert a global CR3 flush (FF) and assumes the caller is aware of
5009	* this and execute this CR3 flush.
5010	*
5011	* @param pPool The pool.
5012	*/
5013	void pgmR3PoolReset(PVM pVM)
5014	{
5015	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5016
5017	Assert(PGMIsLockOwner(pVM));
5018	STAM_PROFILE_START(&pPool->StatR3Reset, a);
5019	LogFlow(("pgmR3PoolReset:\n"));
5020
5021	/*
5022	* If there are no pages in the pool, there is nothing to do.
5023	*/
5024	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5025	{
5026	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5027	return;
5028	}
5029
5030	/*
5031	* Exit the shadow mode since we're going to clear everything,
5032	* including the root page.
5033	*/
5034	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5035	{
5036	PVMCPU pVCpu = &pVM->aCpus[i];
5037	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
5038	}
5039
5040	/*
5041	* Nuke the free list and reinsert all pages into it.
5042	*/
5043	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5044	{
5045	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5046
5047	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
5048	if (pPage->fMonitored)
5049	pgmPoolMonitorFlush(pPool, pPage);
5050	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5051	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5052	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5053	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5054	pPage->cModifications = 0;
5055	pPage->GCPhys = NIL_RTGCPHYS;
5056	pPage->enmKind = PGMPOOLKIND_FREE;
5057	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5058	Assert(pPage->idx == i);
5059	pPage->iNext = i + 1;
5060	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5061	pPage->fSeenNonGlobal = false;
5062	pPage->fMonitored = false;
5063	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5064	pPage->fDirty = false;
5065	#endif
5066	pPage->fCached = false;
5067	pPage->fReusedFlushPending = false;
5068	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5069	pPage->iAgeNext = NIL_PGMPOOL_IDX;
5070	pPage->iAgePrev = NIL_PGMPOOL_IDX;
5071	pPage->cLocked = 0;
5072	}
5073	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5074	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5075	pPool->cUsedPages = 0;
5076
5077	/*
5078	* Zap and reinitialize the user records.
5079	*/
5080	pPool->cPresent = 0;
5081	pPool->iUserFreeHead = 0;
5082	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5083	const unsigned cMaxUsers = pPool->cMaxUsers;
5084	for (unsigned i = 0; i < cMaxUsers; i++)
5085	{
5086	paUsers[i].iNext = i + 1;
5087	paUsers[i].iUser = NIL_PGMPOOL_IDX;
5088	paUsers[i].iUserTable = 0xfffffffe;
5089	}
5090	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5091
5092	/*
5093	* Clear all the GCPhys links and rebuild the phys ext free list.
5094	*/
5095	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
5096	pRam;
5097	pRam = pRam->CTX_SUFF(pNext))
5098	{
5099	unsigned iPage = pRam->cb >> PAGE_SHIFT;
5100	while (iPage-- > 0)
5101	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
5102	}
5103
5104	pPool->iPhysExtFreeHead = 0;
5105	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5106	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5107	for (unsigned i = 0; i < cMaxPhysExts; i++)
5108	{
5109	paPhysExts[i].iNext = i + 1;
5110	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5111	paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5112	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5113	paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5114	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5115	paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5116	}
5117	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5118
5119	/*
5120	* Just zap the modified list.
5121	*/
5122	pPool->cModifiedPages = 0;
5123	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5124
5125	/*
5126	* Clear the GCPhys hash and the age list.
5127	*/
5128	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5129	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5130	pPool->iAgeHead = NIL_PGMPOOL_IDX;
5131	pPool->iAgeTail = NIL_PGMPOOL_IDX;
5132
5133	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5134	/* Clear all dirty pages. */
5135	pPool->idxFreeDirtyPage = 0;
5136	pPool->cDirtyPages = 0;
5137	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
5138	pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
5139	#endif
5140
5141	/*
5142	* Reinsert active pages into the hash and ensure monitoring chains are correct.
5143	*/
5144	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
5145	{
5146	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5147	pPage->iNext = NIL_PGMPOOL_IDX;
5148	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5149	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5150	pPage->cModifications = 0;
5151	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
5152	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5153	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5154	if (pPage->fMonitored)
5155	{
5156	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
5157	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
5158	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
5159	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
5160	pPool->pszAccessHandler);
5161	AssertFatalRCSuccess(rc);
5162	pgmPoolHashInsert(pPool, pPage);
5163	}
5164	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
5165	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
5166	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
5167	}
5168
5169	for (VMCPUID i = 0; i < pVM->cCpus; i++)
5170	{
5171	/*
5172	* Re-enter the shadowing mode and assert Sync CR3 FF.
5173	*/
5174	PVMCPU pVCpu = &pVM->aCpus[i];
5175	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5176	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5177	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5178	}
5179
5180	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5181	}
5182	#endif /* IN_RING3 */
5183
5184	#ifdef LOG_ENABLED
5185	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5186	{
5187	switch(enmKind)
5188	{
5189	case PGMPOOLKIND_INVALID:
5190	return "PGMPOOLKIND_INVALID";
5191	case PGMPOOLKIND_FREE:
5192	return "PGMPOOLKIND_FREE";
5193	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5194	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5195	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5196	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5197	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5198	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5199	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5200	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5201	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5202	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5203	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5204	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5205	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5206	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5207	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5208	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5209	case PGMPOOLKIND_32BIT_PD:
5210	return "PGMPOOLKIND_32BIT_PD";
5211	case PGMPOOLKIND_32BIT_PD_PHYS:
5212	return "PGMPOOLKIND_32BIT_PD_PHYS";
5213	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5214	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5215	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5216	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5217	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5218	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5219	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5220	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5221	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5222	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5223	case PGMPOOLKIND_PAE_PD_PHYS:
5224	return "PGMPOOLKIND_PAE_PD_PHYS";
5225	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5226	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5227	case PGMPOOLKIND_PAE_PDPT:
5228	return "PGMPOOLKIND_PAE_PDPT";
5229	case PGMPOOLKIND_PAE_PDPT_PHYS:
5230	return "PGMPOOLKIND_PAE_PDPT_PHYS";
5231	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5232	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5233	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5234	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5235	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5236	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5237	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5238	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5239	case PGMPOOLKIND_64BIT_PML4:
5240	return "PGMPOOLKIND_64BIT_PML4";
5241	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5242	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5243	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5244	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5245	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5246	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5247	case PGMPOOLKIND_ROOT_NESTED:
5248	return "PGMPOOLKIND_ROOT_NESTED";
5249	}
5250	return "Unknown kind!";
5251	}
5252	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 31463

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