VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 31596

Last change on this file since 31596 was 31593, checked in by vboxsync, 14 years ago

PGM,IOM: MMIO optimization - hacking in progress. (still disabled)
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1/* $Id: PGMAllPool.cpp 31593 2010-08-12 00:52:52Z vboxsync $ */
2/** @file
3 * PGM Shadow Page Pool.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM_POOL
23#include <VBox/pgm.h>
24#include <VBox/mm.h>
25#include <VBox/em.h>
26#include <VBox/cpum.h>
27#ifdef IN_RC
28# include <VBox/patm.h>
29#endif
30#include "../PGMInternal.h"
31#include <VBox/vm.h>
32#include "../PGMInline.h"
33#include <VBox/disopcode.h>
34#include <VBox/hwacc_vmx.h>
35
36#include <VBox/log.h>
37#include <VBox/err.h>
38#include <iprt/asm.h>
39#include <iprt/asm-amd64-x86.h>
40#include <iprt/string.h>
41
42
43/*******************************************************************************
44* Defined Constants And Macros *
45*******************************************************************************/
46/**
47 * Checks if a PAE PTE entry is actually present and not just invalid because
48 * of the MMIO optimization.
49 * @todo Move this to PGMInternal.h if necessary.
50 */
51#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
52# define PGM_POOL_IS_PAE_PTE_PRESENT(Pte) \
53 ( ((Pte).u & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P)
54#else
55# define PGM_POOL_IS_PAE_PTE_PRESENT(Pte) \
56 ( (Pte).n.u1Present )
57#endif
58
59/**
60 * Checks if a EPT PTE entry is actually present and not just invalid
61 * because of the MMIO optimization.
62 * @todo Move this to PGMInternal.h if necessary.
63 */
64#define PGM_POOL_IS_EPT_PTE_PRESENT(Pte) \
65 ( (Pte).n.u1Present )
66
67
68/*******************************************************************************
69* Internal Functions *
70*******************************************************************************/
71RT_C_DECLS_BEGIN
72static void pgmPoolFlushAllInt(PPGMPOOL pPool);
73DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
74DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
75static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
76static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
77static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
78#ifndef IN_RING3
79DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
80#endif
81#ifdef LOG_ENABLED
82static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
83#endif
84#if defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)
85static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT);
86#endif
87
88int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
89PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
90void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
91void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
92
93RT_C_DECLS_END
94
95
96/**
97 * Checks if the specified page pool kind is for a 4MB or 2MB guest page.
98 *
99 * @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
100 * @param enmKind The page kind.
101 */
102DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
103{
104 switch (enmKind)
105 {
106 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
107 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
108 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
109 return true;
110 default:
111 return false;
112 }
113}
114
115
116/**
117 * Flushes a chain of pages sharing the same access monitor.
118 *
119 * @returns VBox status code suitable for scheduling.
120 * @param pPool The pool.
121 * @param pPage A page in the chain.
122 */
123int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
124{
125 LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
126
127 /*
128 * Find the list head.
129 */
130 uint16_t idx = pPage->idx;
131 if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
132 {
133 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
134 {
135 idx = pPage->iMonitoredPrev;
136 Assert(idx != pPage->idx);
137 pPage = &pPool->aPages[idx];
138 }
139 }
140
141 /*
142 * Iterate the list flushing each shadow page.
143 */
144 int rc = VINF_SUCCESS;
145 for (;;)
146 {
147 idx = pPage->iMonitoredNext;
148 Assert(idx != pPage->idx);
149 if (pPage->idx >= PGMPOOL_IDX_FIRST)
150 {
151 int rc2 = pgmPoolFlushPage(pPool, pPage);
152 AssertRC(rc2);
153 }
154 /* next */
155 if (idx == NIL_PGMPOOL_IDX)
156 break;
157 pPage = &pPool->aPages[idx];
158 }
159 return rc;
160}
161
162
163/**
164 * Wrapper for getting the current context pointer to the entry being modified.
165 *
166 * @returns VBox status code suitable for scheduling.
167 * @param pVM VM Handle.
168 * @param pvDst Destination address
169 * @param pvSrc Source guest virtual address.
170 * @param GCPhysSrc The source guest physical address.
171 * @param cb Size of data to read
172 */
173DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
174{
175#if defined(IN_RING3)
176 memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
177 return VINF_SUCCESS;
178#else
179 /* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
180 return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
181#endif
182}
183
184/**
185 * Process shadow entries before they are changed by the guest.
186 *
187 * For PT entries we will clear them. For PD entries, we'll simply check
188 * for mapping conflicts and set the SyncCR3 FF if found.
189 *
190 * @param pVCpu VMCPU handle
191 * @param pPool The pool.
192 * @param pPage The head page.
193 * @param GCPhysFault The guest physical fault address.
194 * @param uAddress In R0 and GC this is the guest context fault address (flat).
195 * In R3 this is the host context 'fault' address.
196 * @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
197 */
198void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite)
199{
200 AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%#x (idx=%#x)\n", pPage->iMonitoredPrev, pPage->idx));
201 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
202 PVM pVM = pPool->CTX_SUFF(pVM);
203
204 LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))pvAddress, GCPhysFault, cbWrite));
205
206 for (;;)
207 {
208 union
209 {
210 void *pv;
211 PX86PT pPT;
212 PX86PTPAE pPTPae;
213 PX86PD pPD;
214 PX86PDPAE pPDPae;
215 PX86PDPT pPDPT;
216 PX86PML4 pPML4;
217 } uShw;
218
219 LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
220
221 uShw.pv = NULL;
222 switch (pPage->enmKind)
223 {
224 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
225 {
226 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
227 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
228 const unsigned iShw = off / sizeof(X86PTE);
229 LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
230 if (uShw.pPT->a[iShw].n.u1Present)
231 {
232 X86PTE GstPte;
233
234 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
235 AssertRC(rc);
236 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
237 pgmPoolTracDerefGCPhysHint(pPool, pPage,
238 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
239 GstPte.u & X86_PTE_PG_MASK,
240 iShw);
241 ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
242 }
243 break;
244 }
245
246 /* page/2 sized */
247 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
248 {
249 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
250 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
251 if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
252 {
253 const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
254 LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
255 if (PGM_POOL_IS_PAE_PTE_PRESENT(uShw.pPTPae->a[iShw]))
256 {
257 X86PTE GstPte;
258 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
259 AssertRC(rc);
260
261 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
262 pgmPoolTracDerefGCPhysHint(pPool, pPage,
263 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
264 GstPte.u & X86_PTE_PG_MASK,
265 iShw);
266 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
267 }
268 }
269 break;
270 }
271
272 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
273 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
274 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
275 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
276 {
277 unsigned iGst = off / sizeof(X86PDE);
278 unsigned iShwPdpt = iGst / 256;
279 unsigned iShw = (iGst % 256) * 2;
280 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
281
282 LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
283 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
284 if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
285 {
286 for (unsigned i = 0; i < 2; i++)
287 {
288# ifndef IN_RING0
289 if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
290 {
291 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
292 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
293 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
294 break;
295 }
296 else
297# endif /* !IN_RING0 */
298 if (uShw.pPDPae->a[iShw+i].n.u1Present)
299 {
300 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
301 pgmPoolFree(pVM,
302 uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
303 pPage->idx,
304 iShw + i);
305 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
306 }
307
308 /* paranoia / a bit assumptive. */
309 if ( (off & 3)
310 && (off & 3) + cbWrite > 4)
311 {
312 const unsigned iShw2 = iShw + 2 + i;
313 if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
314 {
315# ifndef IN_RING0
316 if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
317 {
318 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
319 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
320 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
321 break;
322 }
323 else
324# endif /* !IN_RING0 */
325 if (uShw.pPDPae->a[iShw2].n.u1Present)
326 {
327 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
328 pgmPoolFree(pVM,
329 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
330 pPage->idx,
331 iShw2);
332 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
333 }
334 }
335 }
336 }
337 }
338 break;
339 }
340
341 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
342 {
343 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
344 const unsigned iShw = off / sizeof(X86PTEPAE);
345 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
346 if (PGM_POOL_IS_PAE_PTE_PRESENT(uShw.pPTPae->a[iShw]))
347 {
348 X86PTEPAE GstPte;
349 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
350 AssertRC(rc);
351
352 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
353 pgmPoolTracDerefGCPhysHint(pPool, pPage,
354 uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
355 GstPte.u & X86_PTE_PAE_PG_MASK,
356 iShw);
357 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
358 }
359
360 /* paranoia / a bit assumptive. */
361 if ( (off & 7)
362 && (off & 7) + cbWrite > sizeof(X86PTEPAE))
363 {
364 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
365 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
366
367 if (PGM_POOL_IS_PAE_PTE_PRESENT(uShw.pPTPae->a[iShw2]))
368 {
369 X86PTEPAE GstPte;
370# ifdef IN_RING3
371 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
372# else
373 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
374# endif
375 AssertRC(rc);
376 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
377 pgmPoolTracDerefGCPhysHint(pPool, pPage,
378 uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
379 GstPte.u & X86_PTE_PAE_PG_MASK,
380 iShw2);
381 ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
382 }
383 }
384 break;
385 }
386
387 case PGMPOOLKIND_32BIT_PD:
388 {
389 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
390 const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
391
392 LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
393 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
394# ifndef IN_RING0
395 if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
396 {
397 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
398 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
399 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
400 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
401 break;
402 }
403# endif /* !IN_RING0 */
404# ifndef IN_RING0
405 else
406# endif /* !IN_RING0 */
407 {
408 if (uShw.pPD->a[iShw].n.u1Present)
409 {
410 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
411 pgmPoolFree(pVM,
412 uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
413 pPage->idx,
414 iShw);
415 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
416 }
417 }
418 /* paranoia / a bit assumptive. */
419 if ( (off & 3)
420 && (off & 3) + cbWrite > sizeof(X86PTE))
421 {
422 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
423 if ( iShw2 != iShw
424 && iShw2 < RT_ELEMENTS(uShw.pPD->a))
425 {
426# ifndef IN_RING0
427 if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
428 {
429 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
430 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
431 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
432 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
433 break;
434 }
435# endif /* !IN_RING0 */
436# ifndef IN_RING0
437 else
438# endif /* !IN_RING0 */
439 {
440 if (uShw.pPD->a[iShw2].n.u1Present)
441 {
442 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
443 pgmPoolFree(pVM,
444 uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
445 pPage->idx,
446 iShw2);
447 ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
448 }
449 }
450 }
451 }
452#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
453 if ( uShw.pPD->a[iShw].n.u1Present
454 && !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
455 {
456 LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
457# ifdef IN_RC /* TLB load - we're pushing things a bit... */
458 ASMProbeReadByte(pvAddress);
459# endif
460 pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
461 ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
462 }
463#endif
464 break;
465 }
466
467 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
468 {
469 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
470 const unsigned iShw = off / sizeof(X86PDEPAE);
471 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
472#ifndef IN_RING0
473 if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
474 {
475 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
476 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
477 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
478 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
479 break;
480 }
481#endif /* !IN_RING0 */
482 /*
483 * Causes trouble when the guest uses a PDE to refer to the whole page table level
484 * structure. (Invalidate here; faults later on when it tries to change the page
485 * table entries -> recheck; probably only applies to the RC case.)
486 */
487# ifndef IN_RING0
488 else
489# endif /* !IN_RING0 */
490 {
491 if (uShw.pPDPae->a[iShw].n.u1Present)
492 {
493 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
494 pgmPoolFree(pVM,
495 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
496 pPage->idx,
497 iShw);
498 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
499 }
500 }
501 /* paranoia / a bit assumptive. */
502 if ( (off & 7)
503 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
504 {
505 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
506 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
507
508#ifndef IN_RING0
509 if ( iShw2 != iShw
510 && uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
511 {
512 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
513 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
514 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
515 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
516 break;
517 }
518#endif /* !IN_RING0 */
519# ifndef IN_RING0
520 else
521# endif /* !IN_RING0 */
522 if (uShw.pPDPae->a[iShw2].n.u1Present)
523 {
524 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
525 pgmPoolFree(pVM,
526 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
527 pPage->idx,
528 iShw2);
529 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
530 }
531 }
532 break;
533 }
534
535 case PGMPOOLKIND_PAE_PDPT:
536 {
537 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
538 /*
539 * Hopefully this doesn't happen very often:
540 * - touching unused parts of the page
541 * - messing with the bits of pd pointers without changing the physical address
542 */
543 /* PDPT roots are not page aligned; 32 byte only! */
544 const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
545
546 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
547 const unsigned iShw = offPdpt / sizeof(X86PDPE);
548 if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
549 {
550# ifndef IN_RING0
551 if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
552 {
553 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
554 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
555 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
556 LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
557 break;
558 }
559# endif /* !IN_RING0 */
560# ifndef IN_RING0
561 else
562# endif /* !IN_RING0 */
563 if (uShw.pPDPT->a[iShw].n.u1Present)
564 {
565 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
566 pgmPoolFree(pVM,
567 uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
568 pPage->idx,
569 iShw);
570 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
571 }
572
573 /* paranoia / a bit assumptive. */
574 if ( (offPdpt & 7)
575 && (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
576 {
577 const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
578 if ( iShw2 != iShw
579 && iShw2 < X86_PG_PAE_PDPE_ENTRIES)
580 {
581# ifndef IN_RING0
582 if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
583 {
584 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
585 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
586 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
587 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
588 break;
589 }
590# endif /* !IN_RING0 */
591# ifndef IN_RING0
592 else
593# endif /* !IN_RING0 */
594 if (uShw.pPDPT->a[iShw2].n.u1Present)
595 {
596 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
597 pgmPoolFree(pVM,
598 uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
599 pPage->idx,
600 iShw2);
601 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
602 }
603 }
604 }
605 }
606 break;
607 }
608
609#ifndef IN_RC
610 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
611 {
612 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
613 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
614 const unsigned iShw = off / sizeof(X86PDEPAE);
615 Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
616 if (uShw.pPDPae->a[iShw].n.u1Present)
617 {
618 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
619 pgmPoolFree(pVM,
620 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
621 pPage->idx,
622 iShw);
623 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
624 }
625 /* paranoia / a bit assumptive. */
626 if ( (off & 7)
627 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
628 {
629 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
630 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
631
632 Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
633 if (uShw.pPDPae->a[iShw2].n.u1Present)
634 {
635 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
636 pgmPoolFree(pVM,
637 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
638 pPage->idx,
639 iShw2);
640 ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
641 }
642 }
643 break;
644 }
645
646 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
647 {
648 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
649 /*
650 * Hopefully this doesn't happen very often:
651 * - messing with the bits of pd pointers without changing the physical address
652 */
653 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
654 const unsigned iShw = off / sizeof(X86PDPE);
655 if (uShw.pPDPT->a[iShw].n.u1Present)
656 {
657 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
658 pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
659 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
660 }
661 /* paranoia / a bit assumptive. */
662 if ( (off & 7)
663 && (off & 7) + cbWrite > sizeof(X86PDPE))
664 {
665 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
666 if (uShw.pPDPT->a[iShw2].n.u1Present)
667 {
668 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
669 pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
670 ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
671 }
672 }
673 break;
674 }
675
676 case PGMPOOLKIND_64BIT_PML4:
677 {
678 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
679 /*
680 * Hopefully this doesn't happen very often:
681 * - messing with the bits of pd pointers without changing the physical address
682 */
683 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
684 const unsigned iShw = off / sizeof(X86PDPE);
685 if (uShw.pPML4->a[iShw].n.u1Present)
686 {
687 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
688 pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
689 ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
690 }
691 /* paranoia / a bit assumptive. */
692 if ( (off & 7)
693 && (off & 7) + cbWrite > sizeof(X86PDPE))
694 {
695 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
696 if (uShw.pPML4->a[iShw2].n.u1Present)
697 {
698 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
699 pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
700 ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
701 }
702 }
703 break;
704 }
705#endif /* IN_RING0 */
706
707 default:
708 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
709 }
710 PGM_DYNMAP_UNUSED_HINT_VM(pVM, uShw.pv);
711
712 /* next */
713 if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
714 return;
715 pPage = &pPool->aPages[pPage->iMonitoredNext];
716 }
717}
718
719# ifndef IN_RING3
720/**
721 * Checks if a access could be a fork operation in progress.
722 *
723 * Meaning, that the guest is setting up the parent process for Copy-On-Write.
724 *
725 * @returns true if it's likly that we're forking, otherwise false.
726 * @param pPool The pool.
727 * @param pDis The disassembled instruction.
728 * @param offFault The access offset.
729 */
730DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
731{
732 /*
733 * i386 linux is using btr to clear X86_PTE_RW.
734 * The functions involved are (2.6.16 source inspection):
735 * clear_bit
736 * ptep_set_wrprotect
737 * copy_one_pte
738 * copy_pte_range
739 * copy_pmd_range
740 * copy_pud_range
741 * copy_page_range
742 * dup_mmap
743 * dup_mm
744 * copy_mm
745 * copy_process
746 * do_fork
747 */
748 if ( pDis->pCurInstr->opcode == OP_BTR
749 && !(offFault & 4)
750 /** @todo Validate that the bit index is X86_PTE_RW. */
751 )
752 {
753 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
754 return true;
755 }
756 return false;
757}
758
759
760/**
761 * Determine whether the page is likely to have been reused.
762 *
763 * @returns true if we consider the page as being reused for a different purpose.
764 * @returns false if we consider it to still be a paging page.
765 * @param pVM VM Handle.
766 * @param pVCpu VMCPU Handle.
767 * @param pRegFrame Trap register frame.
768 * @param pDis The disassembly info for the faulting instruction.
769 * @param pvFault The fault address.
770 *
771 * @remark The REP prefix check is left to the caller because of STOSD/W.
772 */
773DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
774{
775#ifndef IN_RC
776 /** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
777 if ( HWACCMHasPendingIrq(pVM)
778 && (pRegFrame->rsp - pvFault) < 32)
779 {
780 /* Fault caused by stack writes while trying to inject an interrupt event. */
781 Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
782 return true;
783 }
784#else
785 NOREF(pVM); NOREF(pvFault);
786#endif
787
788 LogFlow(("Reused instr %RGv %d at %RGv param1.flags=%x param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.flags, pDis->param1.base.reg_gen));
789
790 /* Non-supervisor mode write means it's used for something else. */
791 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
792 return true;
793
794 switch (pDis->pCurInstr->opcode)
795 {
796 /* call implies the actual push of the return address faulted */
797 case OP_CALL:
798 Log4(("pgmPoolMonitorIsReused: CALL\n"));
799 return true;
800 case OP_PUSH:
801 Log4(("pgmPoolMonitorIsReused: PUSH\n"));
802 return true;
803 case OP_PUSHF:
804 Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
805 return true;
806 case OP_PUSHA:
807 Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
808 return true;
809 case OP_FXSAVE:
810 Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
811 return true;
812 case OP_MOVNTI: /* solaris - block_zero_no_xmm */
813 Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
814 return true;
815 case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
816 Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
817 return true;
818 case OP_MOVSWD:
819 case OP_STOSWD:
820 if ( pDis->prefix == (PREFIX_REP|PREFIX_REX)
821 && pRegFrame->rcx >= 0x40
822 )
823 {
824 Assert(pDis->mode == CPUMODE_64BIT);
825
826 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
827 return true;
828 }
829 return false;
830 }
831 if ( ( (pDis->param1.flags & USE_REG_GEN32)
832 || (pDis->param1.flags & USE_REG_GEN64))
833 && (pDis->param1.base.reg_gen == USE_REG_ESP))
834 {
835 Log4(("pgmPoolMonitorIsReused: ESP\n"));
836 return true;
837 }
838
839 return false;
840}
841
842/**
843 * Flushes the page being accessed.
844 *
845 * @returns VBox status code suitable for scheduling.
846 * @param pVM The VM handle.
847 * @param pVCpu The VMCPU handle.
848 * @param pPool The pool.
849 * @param pPage The pool page (head).
850 * @param pDis The disassembly of the write instruction.
851 * @param pRegFrame The trap register frame.
852 * @param GCPhysFault The fault address as guest physical address.
853 * @param pvFault The fault address.
854 */
855static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
856 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
857{
858 /*
859 * First, do the flushing.
860 */
861 int rc = pgmPoolMonitorChainFlush(pPool, pPage);
862
863 /*
864 * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection). Must do this in raw mode (!); XP boot will fail otherwise
865 */
866 uint32_t cbWritten;
867 int rc2 = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cbWritten, EMCODETYPE_ALL);
868 if (RT_SUCCESS(rc2))
869 pRegFrame->rip += pDis->opsize;
870 else if (rc2 == VERR_EM_INTERPRETER)
871 {
872#ifdef IN_RC
873 if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
874 {
875 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
876 pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
877 rc = VINF_SUCCESS;
878 STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
879 }
880 else
881#endif
882 {
883 rc = VINF_EM_RAW_EMULATE_INSTR;
884 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
885 }
886 }
887 else
888 rc = rc2;
889
890 LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
891 return rc;
892}
893
894/**
895 * Handles the STOSD write accesses.
896 *
897 * @returns VBox status code suitable for scheduling.
898 * @param pVM The VM handle.
899 * @param pPool The pool.
900 * @param pPage The pool page (head).
901 * @param pDis The disassembly of the write instruction.
902 * @param pRegFrame The trap register frame.
903 * @param GCPhysFault The fault address as guest physical address.
904 * @param pvFault The fault address.
905 */
906DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
907 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
908{
909 unsigned uIncrement = pDis->param1.size;
910
911 Assert(pDis->mode == CPUMODE_32BIT || pDis->mode == CPUMODE_64BIT);
912 Assert(pRegFrame->rcx <= 0x20);
913
914#ifdef VBOX_STRICT
915 if (pDis->opmode == CPUMODE_32BIT)
916 Assert(uIncrement == 4);
917 else
918 Assert(uIncrement == 8);
919#endif
920
921 Log3(("pgmPoolAccessHandlerSTOSD\n"));
922
923 /*
924 * Increment the modification counter and insert it into the list
925 * of modified pages the first time.
926 */
927 if (!pPage->cModifications++)
928 pgmPoolMonitorModifiedInsert(pPool, pPage);
929
930 /*
931 * Execute REP STOSD.
932 *
933 * This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
934 * write situation, meaning that it's safe to write here.
935 */
936 PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
937 RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
938 while (pRegFrame->rcx)
939 {
940#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
941 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
942 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
943 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
944#else
945 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
946#endif
947#ifdef IN_RC
948 *(uint32_t *)(uintptr_t)pu32 = pRegFrame->eax;
949#else
950 PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
951#endif
952 pu32 += uIncrement;
953 GCPhysFault += uIncrement;
954 pRegFrame->rdi += uIncrement;
955 pRegFrame->rcx--;
956 }
957 pRegFrame->rip += pDis->opsize;
958
959 LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
960 return VINF_SUCCESS;
961}
962
963
964/**
965 * Handles the simple write accesses.
966 *
967 * @returns VBox status code suitable for scheduling.
968 * @param pVM The VM handle.
969 * @param pVCpu The VMCPU handle.
970 * @param pPool The pool.
971 * @param pPage The pool page (head).
972 * @param pDis The disassembly of the write instruction.
973 * @param pRegFrame The trap register frame.
974 * @param GCPhysFault The fault address as guest physical address.
975 * @param pvFault The fault address.
976 * @param pfReused Reused state (out)
977 */
978DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
979 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
980{
981 Log3(("pgmPoolAccessHandlerSimple\n"));
982 /*
983 * Increment the modification counter and insert it into the list
984 * of modified pages the first time.
985 */
986 if (!pPage->cModifications++)
987 pgmPoolMonitorModifiedInsert(pPool, pPage);
988
989 /*
990 * Clear all the pages. ASSUMES that pvFault is readable.
991 */
992#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
993 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
994 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
995 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
996#else
997 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
998#endif
999
1000 /*
1001 * Interpret the instruction.
1002 */
1003 uint32_t cb;
1004 int rc = EMInterpretInstructionCPUEx(pVM, pVCpu, pDis, pRegFrame, pvFault, &cb, EMCODETYPE_ALL);
1005 if (RT_SUCCESS(rc))
1006 pRegFrame->rip += pDis->opsize;
1007 else if (rc == VERR_EM_INTERPRETER)
1008 {
1009 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1010 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
1011 rc = VINF_EM_RAW_EMULATE_INSTR;
1012 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1013 }
1014
1015#if 0 /* experimental code */
1016 if (rc == VINF_SUCCESS)
1017 {
1018 switch (pPage->enmKind)
1019 {
1020 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1021 {
1022 X86PTEPAE GstPte;
1023 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1024 AssertRC(rc);
1025
1026 /* Check the new value written by the guest. If present and with a bogus physical address, then
1027 * it's fairly safe to assume the guest is reusing the PT.
1028 */
1029 if (PGM_POOL_IS_PAE_PTE_PRESENT(GstPte))
1030 {
1031 RTHCPHYS HCPhys = -1;
1032 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1033 if (rc != VINF_SUCCESS)
1034 {
1035 *pfReused = true;
1036 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1037 }
1038 }
1039 break;
1040 }
1041 }
1042 }
1043#endif
1044
1045 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1046 return rc;
1047}
1048
1049/**
1050 * \#PF Handler callback for PT write accesses.
1051 *
1052 * @returns VBox status code (appropriate for GC return).
1053 * @param pVM VM Handle.
1054 * @param uErrorCode CPU Error code.
1055 * @param pRegFrame Trap register frame.
1056 * NULL on DMA and other non CPU access.
1057 * @param pvFault The fault address (cr2).
1058 * @param GCPhysFault The GC physical address corresponding to pvFault.
1059 * @param pvUser User argument.
1060 */
1061DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1062{
1063 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1064 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1065 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1066 PVMCPU pVCpu = VMMGetCpu(pVM);
1067 unsigned cMaxModifications;
1068 bool fForcedFlush = false;
1069
1070 LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1071
1072 pgmLock(pVM);
1073 if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1074 {
1075 /* Pool page changed while we were waiting for the lock; ignore. */
1076 Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1077 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1078 pgmUnlock(pVM);
1079 return VINF_SUCCESS;
1080 }
1081#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1082 if (pPage->fDirty)
1083 {
1084 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH));
1085 pgmUnlock(pVM);
1086 return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1087 }
1088#endif
1089
1090#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1091 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1092 {
1093 void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1094 void *pvGst;
1095 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1096 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1097 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1098 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1099 }
1100#endif
1101
1102 /*
1103 * Disassemble the faulting instruction.
1104 */
1105 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1106 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1107 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1108 {
1109 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1110 pgmUnlock(pVM);
1111 return rc;
1112 }
1113
1114 Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1115
1116 /*
1117 * We should ALWAYS have the list head as user parameter. This
1118 * is because we use that page to record the changes.
1119 */
1120 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1121
1122#ifdef IN_RING0
1123 /* Maximum nr of modifications depends on the page type. */
1124 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1125 cMaxModifications = 4;
1126 else
1127 cMaxModifications = 24;
1128#else
1129 cMaxModifications = 48;
1130#endif
1131
1132 /*
1133 * Incremental page table updates should weigh more than random ones.
1134 * (Only applies when started from offset 0)
1135 */
1136 pVCpu->pgm.s.cPoolAccessHandler++;
1137 if ( pPage->pvLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1138 && pPage->pvLastAccessHandlerRip < pRegFrame->rip + 0x40
1139 && pvFault == (pPage->pvLastAccessHandlerFault + pDis->param1.size)
1140 && pVCpu->pgm.s.cPoolAccessHandler == (pPage->cLastAccessHandlerCount + 1))
1141 {
1142 Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1143 Assert(pPage->cModifications < 32000);
1144 pPage->cModifications = pPage->cModifications * 2;
1145 pPage->pvLastAccessHandlerFault = pvFault;
1146 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1147 if (pPage->cModifications >= cMaxModifications)
1148 {
1149 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1150 fForcedFlush = true;
1151 }
1152 }
1153
1154 if (pPage->cModifications >= cMaxModifications)
1155 Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1156
1157 /*
1158 * Check if it's worth dealing with.
1159 */
1160 bool fReused = false;
1161 bool fNotReusedNotForking = false;
1162 if ( ( pPage->cModifications < cMaxModifications /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
1163 || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1164 )
1165 && !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1166 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1167 {
1168 /*
1169 * Simple instructions, no REP prefix.
1170 */
1171 if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE)))
1172 {
1173 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1174 if (fReused)
1175 goto flushPage;
1176
1177 /* A mov instruction to change the first page table entry will be remembered so we can detect
1178 * full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1179 */
1180 if ( rc == VINF_SUCCESS
1181 && !pPage->cLocked /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
1182 && pDis->pCurInstr->opcode == OP_MOV
1183 && (pvFault & PAGE_OFFSET_MASK) == 0)
1184 {
1185 pPage->pvLastAccessHandlerFault = pvFault;
1186 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1187 pPage->pvLastAccessHandlerRip = pRegFrame->rip;
1188 /* Make sure we don't kick out a page too quickly. */
1189 if (pPage->cModifications > 8)
1190 pPage->cModifications = 2;
1191 }
1192 else
1193 if (pPage->pvLastAccessHandlerFault == pvFault)
1194 {
1195 /* ignore the 2nd write to this page table entry. */
1196 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1197 }
1198 else
1199 {
1200 pPage->pvLastAccessHandlerFault = 0;
1201 pPage->pvLastAccessHandlerRip = 0;
1202 }
1203
1204 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1205 pgmUnlock(pVM);
1206 return rc;
1207 }
1208
1209 /*
1210 * Windows is frequently doing small memset() operations (netio test 4k+).
1211 * We have to deal with these or we'll kill the cache and performance.
1212 */
1213 if ( pDis->pCurInstr->opcode == OP_STOSWD
1214 && !pRegFrame->eflags.Bits.u1DF
1215 && pDis->opmode == pDis->mode
1216 && pDis->addrmode == pDis->mode)
1217 {
1218 bool fValidStosd = false;
1219
1220 if ( pDis->mode == CPUMODE_32BIT
1221 && pDis->prefix == PREFIX_REP
1222 && pRegFrame->ecx <= 0x20
1223 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1224 && !((uintptr_t)pvFault & 3)
1225 && (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */
1226 )
1227 {
1228 fValidStosd = true;
1229 pRegFrame->rcx &= 0xffffffff; /* paranoia */
1230 }
1231 else
1232 if ( pDis->mode == CPUMODE_64BIT
1233 && pDis->prefix == (PREFIX_REP | PREFIX_REX)
1234 && pRegFrame->rcx <= 0x20
1235 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1236 && !((uintptr_t)pvFault & 7)
1237 && (pRegFrame->rax == 0 || pRegFrame->rax == 0x80) /* the two values observed. */
1238 )
1239 {
1240 fValidStosd = true;
1241 }
1242
1243 if (fValidStosd)
1244 {
1245 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1246 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1247 pgmUnlock(pVM);
1248 return rc;
1249 }
1250 }
1251
1252 /* REP prefix, don't bother. */
1253 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1254 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1255 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1256 fNotReusedNotForking = true;
1257 }
1258
1259#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1260 /* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1261 * leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1262 */
1263 if ( pPage->cModifications >= cMaxModifications
1264 && !fForcedFlush
1265 && pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1266 && ( fNotReusedNotForking
1267 || ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1268 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1269 )
1270 )
1271 {
1272 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
1273 Assert(pPage->fDirty == false);
1274
1275 /* Flush any monitored duplicates as we will disable write protection. */
1276 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1277 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1278 {
1279 PPGMPOOLPAGE pPageHead = pPage;
1280
1281 /* Find the monitor head. */
1282 while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1283 pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1284
1285 while (pPageHead)
1286 {
1287 unsigned idxNext = pPageHead->iMonitoredNext;
1288
1289 if (pPageHead != pPage)
1290 {
1291 STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1292 Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1293 int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1294 AssertRC(rc2);
1295 }
1296
1297 if (idxNext == NIL_PGMPOOL_IDX)
1298 break;
1299
1300 pPageHead = &pPool->aPages[idxNext];
1301 }
1302 }
1303
1304 /* The flushing above might fail for locked pages, so double check. */
1305 if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1306 && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1307 {
1308 pgmPoolAddDirtyPage(pVM, pPool, pPage);
1309
1310 /* Temporarily allow write access to the page table again. */
1311 rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys, pPage->GCPhys);
1312 if (rc == VINF_SUCCESS)
1313 {
1314 rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
1315 AssertMsg(rc == VINF_SUCCESS
1316 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1317 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1318 || rc == VERR_PAGE_NOT_PRESENT,
1319 ("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1320
1321 pPage->pvDirtyFault = pvFault;
1322
1323 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1324 pgmUnlock(pVM);
1325 return rc;
1326 }
1327 }
1328 }
1329#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1330
1331 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1332flushPage:
1333 /*
1334 * Not worth it, so flush it.
1335 *
1336 * If we considered it to be reused, don't go back to ring-3
1337 * to emulate failed instructions since we usually cannot
1338 * interpret then. This may be a bit risky, in which case
1339 * the reuse detection must be fixed.
1340 */
1341 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1342 if ( rc == VINF_EM_RAW_EMULATE_INSTR
1343 && fReused)
1344 {
1345 /* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1346 if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1347 rc = VINF_SUCCESS; /* safe to restart the instruction. */
1348 }
1349 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1350 pgmUnlock(pVM);
1351 return rc;
1352}
1353
1354# endif /* !IN_RING3 */
1355
1356# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1357
1358# ifdef VBOX_STRICT
1359/**
1360 * Check references to guest physical memory in a PAE / PAE page table.
1361 *
1362 * @param pPool The pool.
1363 * @param pPage The page.
1364 * @param pShwPT The shadow page table (mapping of the page).
1365 * @param pGstPT The guest page table.
1366 */
1367static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
1368{
1369 unsigned cErrors = 0;
1370 int LastRc = -1; /* initialized to shut up gcc */
1371 unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1372 RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1373 PVM pVM = pPool->CTX_SUFF(pVM);
1374
1375#ifdef VBOX_STRICT
1376 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1377 AssertMsg(!PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1378#endif
1379 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1380 {
1381 if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
1382 {
1383 RTHCPHYS HCPhys = NIL_RTHCPHYS;
1384 int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1385 if ( rc != VINF_SUCCESS
1386 || (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) != HCPhys)
1387 {
1388 Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1389 LastPTE = i;
1390 LastRc = rc;
1391 LastHCPhys = HCPhys;
1392 cErrors++;
1393
1394 RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1395 rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1396 AssertRC(rc);
1397
1398 for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1399 {
1400 PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1401
1402 if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1403 {
1404 PX86PTPAE pShwPT2 = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1405
1406 for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1407 {
1408 if ( PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT2->a[j])
1409 && pShwPT2->a[j].n.u1Write
1410 && (pShwPT2->a[j].u & X86_PTE_PAE_PG_MASK) == HCPhysPT)
1411 {
1412 Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, pShwPT->a[j].u, pShwPT2->a[j].u));
1413 }
1414 }
1415
1416 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1417 }
1418 }
1419 }
1420 }
1421 }
1422 AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, pShwPT->a[LastPTE].u, LastHCPhys));
1423}
1424# endif /* VBOX_STRICT */
1425
1426/**
1427 * Clear references to guest physical memory in a PAE / PAE page table.
1428 *
1429 * @returns nr of changed PTEs
1430 * @param pPool The pool.
1431 * @param pPage The page.
1432 * @param pShwPT The shadow page table (mapping of the page).
1433 * @param pGstPT The guest page table.
1434 * @param pOldGstPT The old cached guest page table.
1435 * @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1436 * @param pfFlush Flush reused page table (out)
1437 */
1438DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT,
1439 PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1440{
1441 unsigned cChanged = 0;
1442
1443#ifdef VBOX_STRICT
1444 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1445 AssertMsg(!PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, pShwPT->a[i].u, pPage->iFirstPresent));
1446#endif
1447 *pfFlush = false;
1448
1449 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1450 {
1451 /* Check the new value written by the guest. If present and with a bogus physical address, then
1452 * it's fairly safe to assume the guest is reusing the PT.
1453 */
1454 if ( fAllowRemoval
1455 && pGstPT->a[i].n.u1Present)
1456 {
1457 if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1458 {
1459 *pfFlush = true;
1460 return ++cChanged;
1461 }
1462 }
1463 if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
1464 {
1465 /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1466 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1467 {
1468#ifdef VBOX_STRICT
1469 RTHCPHYS HCPhys = NIL_RTGCPHYS;
1470 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1471 AssertMsg(rc == VINF_SUCCESS && (pShwPT->a[i].u & X86_PTE_PAE_PG_MASK) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, pShwPT->a[i].u, HCPhys));
1472#endif
1473 uint64_t uHostAttr = pShwPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1474 bool fHostRW = !!(pShwPT->a[i].u & X86_PTE_RW);
1475 uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1476 bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1477
1478 if ( uHostAttr == uGuestAttr
1479 && fHostRW <= fGuestRW)
1480 continue;
1481 }
1482 cChanged++;
1483 /* Something was changed, so flush it. */
1484 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1485 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1486 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
1487 ASMAtomicWriteSize(&pShwPT->a[i].u, 0);
1488 }
1489 }
1490 return cChanged;
1491}
1492
1493
1494/**
1495 * Flush a dirty page
1496 *
1497 * @param pVM VM Handle.
1498 * @param pPool The pool.
1499 * @param idxSlot Dirty array slot index
1500 * @param fAllowRemoval Allow a reused page table to be removed
1501 */
1502static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1503{
1504 PPGMPOOLPAGE pPage;
1505 unsigned idxPage;
1506
1507 Assert(idxSlot < RT_ELEMENTS(pPool->aIdxDirtyPages));
1508 if (pPool->aIdxDirtyPages[idxSlot] == NIL_PGMPOOL_IDX)
1509 return;
1510
1511 idxPage = pPool->aIdxDirtyPages[idxSlot];
1512 AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1513 pPage = &pPool->aPages[idxPage];
1514 Assert(pPage->idx == idxPage);
1515 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1516
1517 AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1518 Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1519
1520 /* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1521 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys);
1522 Assert(rc == VINF_SUCCESS);
1523 pPage->fDirty = false;
1524
1525#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
1526 PVMCPU pVCpu = VMMGetCpu(pVM);
1527 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
1528#endif
1529
1530#ifdef VBOX_STRICT
1531 uint64_t fFlags = 0;
1532 RTHCPHYS HCPhys;
1533 rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys);
1534 AssertMsg( ( rc == VINF_SUCCESS
1535 && (!(fFlags & X86_PTE_RW) || HCPhys != pPage->Core.Key))
1536 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1537 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1538 || rc == VERR_PAGE_NOT_PRESENT,
1539 ("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags));
1540#endif
1541
1542 /* Flush those PTEs that have changed. */
1543 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1544 void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1545 void *pvGst;
1546 rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1547 bool fFlush;
1548 unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst,
1549 (PCX86PTPAE)&pPool->aDirtyPages[idxSlot][0], fAllowRemoval, &fFlush);
1550 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1551 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1552 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1553 /* Note: we might want to consider keeping the dirty page active in case there were many changes. */
1554
1555 /* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1556 Assert(pPage->cModifications);
1557 if (cChanges < 4)
1558 pPage->cModifications = 1; /* must use > 0 here */
1559 else
1560 pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1561
1562 STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1563 if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages))
1564 pPool->idxFreeDirtyPage = idxSlot;
1565
1566 pPool->cDirtyPages--;
1567 pPool->aIdxDirtyPages[idxSlot] = NIL_PGMPOOL_IDX;
1568 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1569 if (fFlush)
1570 {
1571 Assert(fAllowRemoval);
1572 Log(("Flush reused page table!\n"));
1573 pgmPoolFlushPage(pPool, pPage);
1574 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1575 }
1576 else
1577 Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1578
1579#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_R0) || defined(IN_RC)
1580 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
1581#endif
1582}
1583
1584# ifndef IN_RING3
1585/**
1586 * Add a new dirty page
1587 *
1588 * @param pVM VM Handle.
1589 * @param pPool The pool.
1590 * @param pPage The page.
1591 */
1592void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1593{
1594 unsigned idxFree;
1595
1596 Assert(PGMIsLocked(pVM));
1597 AssertCompile(RT_ELEMENTS(pPool->aIdxDirtyPages) == 8 || RT_ELEMENTS(pPool->aIdxDirtyPages) == 16);
1598 Assert(!pPage->fDirty);
1599
1600 idxFree = pPool->idxFreeDirtyPage;
1601 Assert(idxFree < RT_ELEMENTS(pPool->aIdxDirtyPages));
1602 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1603
1604 if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aIdxDirtyPages))
1605 {
1606 STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1607 pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1608 }
1609 Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages));
1610 AssertMsg(pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1611
1612 Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1613
1614 /*
1615 * Make a copy of the guest page table as we require valid GCPhys addresses
1616 * when removing references to physical pages.
1617 * (The HCPhys linear lookup is *extremely* expensive!)
1618 */
1619 void *pvGst;
1620 int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1621 memcpy(&pPool->aDirtyPages[idxFree][0], pvGst, PAGE_SIZE);
1622#ifdef VBOX_STRICT
1623 void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1624 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
1625 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1626#endif
1627 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1628
1629 STAM_COUNTER_INC(&pPool->StatDirtyPage);
1630 pPage->fDirty = true;
1631 pPage->idxDirty = idxFree;
1632 pPool->aIdxDirtyPages[idxFree] = pPage->idx;
1633 pPool->cDirtyPages++;
1634
1635 pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1636 if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aIdxDirtyPages)
1637 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1638 {
1639 unsigned i;
1640 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1641 {
1642 idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aIdxDirtyPages) - 1);
1643 if (pPool->aIdxDirtyPages[idxFree] == NIL_PGMPOOL_IDX)
1644 {
1645 pPool->idxFreeDirtyPage = idxFree;
1646 break;
1647 }
1648 }
1649 Assert(i != RT_ELEMENTS(pPool->aIdxDirtyPages));
1650 }
1651
1652 Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages) || pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX);
1653 return;
1654}
1655# endif /* !IN_RING3 */
1656
1657/**
1658 * Check if the specified page is dirty (not write monitored)
1659 *
1660 * @return dirty or not
1661 * @param pVM VM Handle.
1662 * @param GCPhys Guest physical address
1663 */
1664bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1665{
1666 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1667 Assert(PGMIsLocked(pVM));
1668 if (!pPool->cDirtyPages)
1669 return false;
1670
1671 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1672
1673 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1674 {
1675 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1676 {
1677 PPGMPOOLPAGE pPage;
1678 unsigned idxPage = pPool->aIdxDirtyPages[i];
1679
1680 pPage = &pPool->aPages[idxPage];
1681 if (pPage->GCPhys == GCPhys)
1682 return true;
1683 }
1684 }
1685 return false;
1686}
1687
1688/**
1689 * Reset all dirty pages by reinstating page monitoring.
1690 *
1691 * @param pVM VM Handle.
1692 */
1693void pgmPoolResetDirtyPages(PVM pVM)
1694{
1695 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1696 Assert(PGMIsLocked(pVM));
1697 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1698
1699 if (!pPool->cDirtyPages)
1700 return;
1701
1702 Log(("pgmPoolResetDirtyPages\n"));
1703 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1704 pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1705
1706 pPool->idxFreeDirtyPage = 0;
1707 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1708 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1709 {
1710 unsigned i;
1711 for (i = 1; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1712 {
1713 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1714 {
1715 pPool->idxFreeDirtyPage = i;
1716 break;
1717 }
1718 }
1719 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1720 }
1721
1722 Assert(pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX || pPool->cDirtyPages == RT_ELEMENTS(pPool->aIdxDirtyPages));
1723 return;
1724}
1725
1726/**
1727 * Reset all dirty pages by reinstating page monitoring.
1728 *
1729 * @param pVM VM Handle.
1730 * @param GCPhysPT Physical address of the page table
1731 */
1732void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT)
1733{
1734 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1735 Assert(PGMIsLocked(pVM));
1736 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aIdxDirtyPages));
1737 unsigned idxDirtyPage = RT_ELEMENTS(pPool->aIdxDirtyPages);
1738
1739 if (!pPool->cDirtyPages)
1740 return;
1741
1742 GCPhysPT = GCPhysPT & ~(RTGCPHYS)(PAGE_SIZE - 1);
1743
1744 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1745 {
1746 if (pPool->aIdxDirtyPages[i] != NIL_PGMPOOL_IDX)
1747 {
1748 unsigned idxPage = pPool->aIdxDirtyPages[i];
1749
1750 PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1751 if (pPage->GCPhys == GCPhysPT)
1752 {
1753 idxDirtyPage = i;
1754 break;
1755 }
1756 }
1757 }
1758
1759 if (idxDirtyPage != RT_ELEMENTS(pPool->aIdxDirtyPages))
1760 {
1761 pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1762 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aIdxDirtyPages)
1763 && pPool->aIdxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1764 {
1765 unsigned i;
1766 for (i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
1767 {
1768 if (pPool->aIdxDirtyPages[i] == NIL_PGMPOOL_IDX)
1769 {
1770 pPool->idxFreeDirtyPage = i;
1771 break;
1772 }
1773 }
1774 AssertMsg(i != RT_ELEMENTS(pPool->aIdxDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1775 }
1776 }
1777}
1778
1779# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1780
1781/**
1782 * Inserts a page into the GCPhys hash table.
1783 *
1784 * @param pPool The pool.
1785 * @param pPage The page.
1786 */
1787DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1788{
1789 Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1790 Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1791 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1792 pPage->iNext = pPool->aiHash[iHash];
1793 pPool->aiHash[iHash] = pPage->idx;
1794}
1795
1796
1797/**
1798 * Removes a page from the GCPhys hash table.
1799 *
1800 * @param pPool The pool.
1801 * @param pPage The page.
1802 */
1803DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1804{
1805 Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1806 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1807 if (pPool->aiHash[iHash] == pPage->idx)
1808 pPool->aiHash[iHash] = pPage->iNext;
1809 else
1810 {
1811 uint16_t iPrev = pPool->aiHash[iHash];
1812 for (;;)
1813 {
1814 const int16_t i = pPool->aPages[iPrev].iNext;
1815 if (i == pPage->idx)
1816 {
1817 pPool->aPages[iPrev].iNext = pPage->iNext;
1818 break;
1819 }
1820 if (i == NIL_PGMPOOL_IDX)
1821 {
1822 AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1823 break;
1824 }
1825 iPrev = i;
1826 }
1827 }
1828 pPage->iNext = NIL_PGMPOOL_IDX;
1829}
1830
1831
1832/**
1833 * Frees up one cache page.
1834 *
1835 * @returns VBox status code.
1836 * @retval VINF_SUCCESS on success.
1837 * @param pPool The pool.
1838 * @param iUser The user index.
1839 */
1840static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1841{
1842#ifndef IN_RC
1843 const PVM pVM = pPool->CTX_SUFF(pVM);
1844#endif
1845 Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1846 STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1847
1848 /*
1849 * Select one page from the tail of the age list.
1850 */
1851 PPGMPOOLPAGE pPage;
1852 for (unsigned iLoop = 0; ; iLoop++)
1853 {
1854 uint16_t iToFree = pPool->iAgeTail;
1855 if (iToFree == iUser)
1856 iToFree = pPool->aPages[iToFree].iAgePrev;
1857/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1858 if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1859 {
1860 uint16_t i = pPool->aPages[iToFree].iAgePrev;
1861 for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1862 {
1863 if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1864 continue;
1865 iToFree = i;
1866 break;
1867 }
1868 }
1869*/
1870 Assert(iToFree != iUser);
1871 AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1872 pPage = &pPool->aPages[iToFree];
1873
1874 /*
1875 * Reject any attempts at flushing the currently active shadow CR3 mapping.
1876 * Call pgmPoolCacheUsed to move the page to the head of the age list.
1877 */
1878 if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1879 break;
1880 LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1881 pgmPoolCacheUsed(pPool, pPage);
1882 AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1883 }
1884
1885 /*
1886 * Found a usable page, flush it and return.
1887 */
1888 int rc = pgmPoolFlushPage(pPool, pPage);
1889 /* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
1890 /* todo: find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
1891 if (rc == VINF_SUCCESS)
1892 PGM_INVL_ALL_VCPU_TLBS(pVM);
1893 return rc;
1894}
1895
1896
1897/**
1898 * Checks if a kind mismatch is really a page being reused
1899 * or if it's just normal remappings.
1900 *
1901 * @returns true if reused and the cached page (enmKind1) should be flushed
1902 * @returns false if not reused.
1903 * @param enmKind1 The kind of the cached page.
1904 * @param enmKind2 The kind of the requested page.
1905 */
1906static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1907{
1908 switch (enmKind1)
1909 {
1910 /*
1911 * Never reuse them. There is no remapping in non-paging mode.
1912 */
1913 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1914 case PGMPOOLKIND_32BIT_PD_PHYS:
1915 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1916 case PGMPOOLKIND_PAE_PD_PHYS:
1917 case PGMPOOLKIND_PAE_PDPT_PHYS:
1918 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1919 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1920 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1921 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1922 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1923 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1924 return false;
1925
1926 /*
1927 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1928 */
1929 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1930 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1931 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1932 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1933 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1934 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1935 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1936 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1937 case PGMPOOLKIND_32BIT_PD:
1938 case PGMPOOLKIND_PAE_PDPT:
1939 switch (enmKind2)
1940 {
1941 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1942 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1943 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1944 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1945 case PGMPOOLKIND_64BIT_PML4:
1946 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1947 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1948 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1949 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1950 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1951 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1952 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1953 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1954 return true;
1955 default:
1956 return false;
1957 }
1958
1959 /*
1960 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1961 */
1962 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1963 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1964 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1965 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1966 case PGMPOOLKIND_64BIT_PML4:
1967 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1968 switch (enmKind2)
1969 {
1970 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1971 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1972 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1973 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1974 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1975 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1976 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1977 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1978 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1979 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1980 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1981 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1982 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1983 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1984 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1985 return true;
1986 default:
1987 return false;
1988 }
1989
1990 /*
1991 * These cannot be flushed, and it's common to reuse the PDs as PTs.
1992 */
1993 case PGMPOOLKIND_ROOT_NESTED:
1994 return false;
1995
1996 default:
1997 AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1998 }
1999}
2000
2001
2002/**
2003 * Attempts to satisfy a pgmPoolAlloc request from the cache.
2004 *
2005 * @returns VBox status code.
2006 * @retval VINF_PGM_CACHED_PAGE on success.
2007 * @retval VERR_FILE_NOT_FOUND if not found.
2008 * @param pPool The pool.
2009 * @param GCPhys The GC physical address of the page we're gonna shadow.
2010 * @param enmKind The kind of mapping.
2011 * @param enmAccess Access type for the mapping (only relevant for big pages)
2012 * @param iUser The shadow page pool index of the user table.
2013 * @param iUserTable The index into the user table (shadowed).
2014 * @param ppPage Where to store the pointer to the page.
2015 */
2016static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2017{
2018#ifndef IN_RC
2019 const PVM pVM = pPool->CTX_SUFF(pVM);
2020#endif
2021 /*
2022 * Look up the GCPhys in the hash.
2023 */
2024 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2025 Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2026 if (i != NIL_PGMPOOL_IDX)
2027 {
2028 do
2029 {
2030 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2031 Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2032 if (pPage->GCPhys == GCPhys)
2033 {
2034 if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2035 && (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
2036 {
2037 /* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2038 * doesn't flush it in case there are no more free use records.
2039 */
2040 pgmPoolCacheUsed(pPool, pPage);
2041
2042 int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2043 if (RT_SUCCESS(rc))
2044 {
2045 Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2046 *ppPage = pPage;
2047 if (pPage->cModifications)
2048 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2049 STAM_COUNTER_INC(&pPool->StatCacheHits);
2050 return VINF_PGM_CACHED_PAGE;
2051 }
2052 return rc;
2053 }
2054
2055 if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2056 {
2057 /*
2058 * The kind is different. In some cases we should now flush the page
2059 * as it has been reused, but in most cases this is normal remapping
2060 * of PDs as PT or big pages using the GCPhys field in a slightly
2061 * different way than the other kinds.
2062 */
2063 if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2064 {
2065 STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2066 pgmPoolFlushPage(pPool, pPage);
2067 break;
2068 }
2069 }
2070 }
2071
2072 /* next */
2073 i = pPage->iNext;
2074 } while (i != NIL_PGMPOOL_IDX);
2075 }
2076
2077 Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2078 STAM_COUNTER_INC(&pPool->StatCacheMisses);
2079 return VERR_FILE_NOT_FOUND;
2080}
2081
2082
2083/**
2084 * Inserts a page into the cache.
2085 *
2086 * @param pPool The pool.
2087 * @param pPage The cached page.
2088 * @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2089 */
2090static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2091{
2092 /*
2093 * Insert into the GCPhys hash if the page is fit for that.
2094 */
2095 Assert(!pPage->fCached);
2096 if (fCanBeCached)
2097 {
2098 pPage->fCached = true;
2099 pgmPoolHashInsert(pPool, pPage);
2100 Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2101 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2102 STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2103 }
2104 else
2105 {
2106 Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2107 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2108 STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2109 }
2110
2111 /*
2112 * Insert at the head of the age list.
2113 */
2114 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2115 pPage->iAgeNext = pPool->iAgeHead;
2116 if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2117 pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2118 else
2119 pPool->iAgeTail = pPage->idx;
2120 pPool->iAgeHead = pPage->idx;
2121}
2122
2123
2124/**
2125 * Flushes a cached page.
2126 *
2127 * @param pPool The pool.
2128 * @param pPage The cached page.
2129 */
2130static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2131{
2132 Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2133
2134 /*
2135 * Remove the page from the hash.
2136 */
2137 if (pPage->fCached)
2138 {
2139 pPage->fCached = false;
2140 pgmPoolHashRemove(pPool, pPage);
2141 }
2142 else
2143 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2144
2145 /*
2146 * Remove it from the age list.
2147 */
2148 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2149 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2150 else
2151 pPool->iAgeTail = pPage->iAgePrev;
2152 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2153 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2154 else
2155 pPool->iAgeHead = pPage->iAgeNext;
2156 pPage->iAgeNext = NIL_PGMPOOL_IDX;
2157 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2158}
2159
2160
2161/**
2162 * Looks for pages sharing the monitor.
2163 *
2164 * @returns Pointer to the head page.
2165 * @returns NULL if not found.
2166 * @param pPool The Pool
2167 * @param pNewPage The page which is going to be monitored.
2168 */
2169static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2170{
2171 /*
2172 * Look up the GCPhys in the hash.
2173 */
2174 RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2175 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2176 if (i == NIL_PGMPOOL_IDX)
2177 return NULL;
2178 do
2179 {
2180 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2181 if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2182 && pPage != pNewPage)
2183 {
2184 switch (pPage->enmKind)
2185 {
2186 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2187 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2188 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2189 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2190 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2191 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2192 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2193 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2194 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2195 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2196 case PGMPOOLKIND_64BIT_PML4:
2197 case PGMPOOLKIND_32BIT_PD:
2198 case PGMPOOLKIND_PAE_PDPT:
2199 {
2200 /* find the head */
2201 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2202 {
2203 Assert(pPage->iMonitoredPrev != pPage->idx);
2204 pPage = &pPool->aPages[pPage->iMonitoredPrev];
2205 }
2206 return pPage;
2207 }
2208
2209 /* ignore, no monitoring. */
2210 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2211 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2212 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2213 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2214 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2215 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2216 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2217 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2218 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2219 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2220 case PGMPOOLKIND_ROOT_NESTED:
2221 case PGMPOOLKIND_PAE_PD_PHYS:
2222 case PGMPOOLKIND_PAE_PDPT_PHYS:
2223 case PGMPOOLKIND_32BIT_PD_PHYS:
2224 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2225 break;
2226 default:
2227 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2228 }
2229 }
2230
2231 /* next */
2232 i = pPage->iNext;
2233 } while (i != NIL_PGMPOOL_IDX);
2234 return NULL;
2235}
2236
2237
2238/**
2239 * Enabled write monitoring of a guest page.
2240 *
2241 * @returns VBox status code.
2242 * @retval VINF_SUCCESS on success.
2243 * @param pPool The pool.
2244 * @param pPage The cached page.
2245 */
2246static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2247{
2248 LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
2249
2250 /*
2251 * Filter out the relevant kinds.
2252 */
2253 switch (pPage->enmKind)
2254 {
2255 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2256 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2257 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2258 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2259 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2260 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2261 case PGMPOOLKIND_64BIT_PML4:
2262 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2263 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2264 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2265 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2266 case PGMPOOLKIND_32BIT_PD:
2267 case PGMPOOLKIND_PAE_PDPT:
2268 break;
2269
2270 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2271 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2272 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2273 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2274 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2275 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2276 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2277 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2278 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2279 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2280 case PGMPOOLKIND_ROOT_NESTED:
2281 /* Nothing to monitor here. */
2282 return VINF_SUCCESS;
2283
2284 case PGMPOOLKIND_32BIT_PD_PHYS:
2285 case PGMPOOLKIND_PAE_PDPT_PHYS:
2286 case PGMPOOLKIND_PAE_PD_PHYS:
2287 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2288 /* Nothing to monitor here. */
2289 return VINF_SUCCESS;
2290 default:
2291 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2292 }
2293
2294 /*
2295 * Install handler.
2296 */
2297 int rc;
2298 PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2299 if (pPageHead)
2300 {
2301 Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2302 Assert(pPageHead->iMonitoredPrev != pPage->idx);
2303
2304#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2305 if (pPageHead->fDirty)
2306 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirty, false /* do not remove */);
2307#endif
2308
2309 pPage->iMonitoredPrev = pPageHead->idx;
2310 pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2311 if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2312 pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2313 pPageHead->iMonitoredNext = pPage->idx;
2314 rc = VINF_SUCCESS;
2315 }
2316 else
2317 {
2318 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2319 PVM pVM = pPool->CTX_SUFF(pVM);
2320 const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
2321 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2322 GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
2323 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2324 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2325 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2326 pPool->pszAccessHandler);
2327 /** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2328 * the heap size should suffice. */
2329 AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2330 PVMCPU pVCpu = VMMGetCpu(pVM);
2331 AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
2332 }
2333 pPage->fMonitored = true;
2334 return rc;
2335}
2336
2337
2338/**
2339 * Disables write monitoring of a guest page.
2340 *
2341 * @returns VBox status code.
2342 * @retval VINF_SUCCESS on success.
2343 * @param pPool The pool.
2344 * @param pPage The cached page.
2345 */
2346static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2347{
2348 /*
2349 * Filter out the relevant kinds.
2350 */
2351 switch (pPage->enmKind)
2352 {
2353 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2354 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2355 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2356 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2357 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2358 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2359 case PGMPOOLKIND_64BIT_PML4:
2360 case PGMPOOLKIND_32BIT_PD:
2361 case PGMPOOLKIND_PAE_PDPT:
2362 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2363 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2364 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2365 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2366 break;
2367
2368 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2369 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2370 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2371 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2372 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2373 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2374 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2375 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2376 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2377 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2378 case PGMPOOLKIND_ROOT_NESTED:
2379 case PGMPOOLKIND_PAE_PD_PHYS:
2380 case PGMPOOLKIND_PAE_PDPT_PHYS:
2381 case PGMPOOLKIND_32BIT_PD_PHYS:
2382 /* Nothing to monitor here. */
2383 Assert(!pPage->fMonitored);
2384 return VINF_SUCCESS;
2385
2386 default:
2387 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2388 }
2389 Assert(pPage->fMonitored);
2390
2391 /*
2392 * Remove the page from the monitored list or uninstall it if last.
2393 */
2394 const PVM pVM = pPool->CTX_SUFF(pVM);
2395 int rc;
2396 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2397 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2398 {
2399 if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2400 {
2401 PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2402 pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2403 rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
2404 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2405 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2406 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2407 pPool->pszAccessHandler);
2408 AssertFatalRCSuccess(rc);
2409 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2410 }
2411 else
2412 {
2413 pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2414 if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2415 {
2416 pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2417 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2418 }
2419 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2420 rc = VINF_SUCCESS;
2421 }
2422 }
2423 else
2424 {
2425 rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
2426 AssertFatalRC(rc);
2427 PVMCPU pVCpu = VMMGetCpu(pVM);
2428 AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2429 ("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2430 }
2431 pPage->fMonitored = false;
2432
2433 /*
2434 * Remove it from the list of modified pages (if in it).
2435 */
2436 pgmPoolMonitorModifiedRemove(pPool, pPage);
2437
2438 return rc;
2439}
2440
2441
2442/**
2443 * Inserts the page into the list of modified pages.
2444 *
2445 * @param pPool The pool.
2446 * @param pPage The page.
2447 */
2448void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2449{
2450 Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2451 AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2452 && pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2453 && pPool->iModifiedHead != pPage->idx,
2454 ("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2455 pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2456 pPool->iModifiedHead, pPool->cModifiedPages));
2457
2458 pPage->iModifiedNext = pPool->iModifiedHead;
2459 if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2460 pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2461 pPool->iModifiedHead = pPage->idx;
2462 pPool->cModifiedPages++;
2463#ifdef VBOX_WITH_STATISTICS
2464 if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2465 pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2466#endif
2467}
2468
2469
2470/**
2471 * Removes the page from the list of modified pages and resets the
2472 * moficiation counter.
2473 *
2474 * @param pPool The pool.
2475 * @param pPage The page which is believed to be in the list of modified pages.
2476 */
2477static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2478{
2479 Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2480 if (pPool->iModifiedHead == pPage->idx)
2481 {
2482 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2483 pPool->iModifiedHead = pPage->iModifiedNext;
2484 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2485 {
2486 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2487 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2488 }
2489 pPool->cModifiedPages--;
2490 }
2491 else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2492 {
2493 pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2494 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2495 {
2496 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2497 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2498 }
2499 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2500 pPool->cModifiedPages--;
2501 }
2502 else
2503 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2504 pPage->cModifications = 0;
2505}
2506
2507
2508/**
2509 * Zaps the list of modified pages, resetting their modification counters in the process.
2510 *
2511 * @param pVM The VM handle.
2512 */
2513static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2514{
2515 pgmLock(pVM);
2516 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2517 LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2518
2519 unsigned cPages = 0; NOREF(cPages);
2520
2521#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2522 pgmPoolResetDirtyPages(pVM);
2523#endif
2524
2525 uint16_t idx = pPool->iModifiedHead;
2526 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2527 while (idx != NIL_PGMPOOL_IDX)
2528 {
2529 PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2530 idx = pPage->iModifiedNext;
2531 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2532 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2533 pPage->cModifications = 0;
2534 Assert(++cPages);
2535 }
2536 AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2537 pPool->cModifiedPages = 0;
2538 pgmUnlock(pVM);
2539}
2540
2541
2542/**
2543 * Handle SyncCR3 pool tasks
2544 *
2545 * @returns VBox status code.
2546 * @retval VINF_SUCCESS if successfully added.
2547 * @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2548 * @param pVCpu The VMCPU handle.
2549 * @remark Should only be used when monitoring is available, thus placed in
2550 * the PGMPOOL_WITH_MONITORING #ifdef.
2551 */
2552int pgmPoolSyncCR3(PVMCPU pVCpu)
2553{
2554 PVM pVM = pVCpu->CTX_SUFF(pVM);
2555 LogFlow(("pgmPoolSyncCR3 fSyncFlags=%x\n", pVCpu->pgm.s.fSyncFlags));
2556
2557 /*
2558 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2559 * Occasionally we will have to clear all the shadow page tables because we wanted
2560 * to monitor a page which was mapped by too many shadowed page tables. This operation
2561 * sometimes refered to as a 'lightweight flush'.
2562 */
2563# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2564 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2565 pgmR3PoolClearAll(pVM, false /*fFlushRemTlb*/);
2566# else /* !IN_RING3 */
2567 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2568 {
2569 Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2570 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2571
2572 /* Make sure all other VCPUs return to ring 3. */
2573 if (pVM->cCpus > 1)
2574 {
2575 VM_FF_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
2576 PGM_INVL_ALL_VCPU_TLBS(pVM);
2577 }
2578 return VINF_PGM_SYNC_CR3;
2579 }
2580# endif /* !IN_RING3 */
2581 else
2582 {
2583 pgmPoolMonitorModifiedClearAll(pVM);
2584
2585 /* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
2586 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2587 {
2588 Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
2589 return pgmPoolSyncCR3(pVCpu);
2590 }
2591 }
2592 return VINF_SUCCESS;
2593}
2594
2595
2596/**
2597 * Frees up at least one user entry.
2598 *
2599 * @returns VBox status code.
2600 * @retval VINF_SUCCESS if successfully added.
2601 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2602 * @param pPool The pool.
2603 * @param iUser The user index.
2604 */
2605static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2606{
2607 STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2608 /*
2609 * Just free cached pages in a braindead fashion.
2610 */
2611 /** @todo walk the age list backwards and free the first with usage. */
2612 int rc = VINF_SUCCESS;
2613 do
2614 {
2615 int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2616 if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2617 rc = rc2;
2618 } while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2619 return rc;
2620}
2621
2622
2623/**
2624 * Inserts a page into the cache.
2625 *
2626 * This will create user node for the page, insert it into the GCPhys
2627 * hash, and insert it into the age list.
2628 *
2629 * @returns VBox status code.
2630 * @retval VINF_SUCCESS if successfully added.
2631 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2632 * @param pPool The pool.
2633 * @param pPage The cached page.
2634 * @param GCPhys The GC physical address of the page we're gonna shadow.
2635 * @param iUser The user index.
2636 * @param iUserTable The user table index.
2637 */
2638DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2639{
2640 int rc = VINF_SUCCESS;
2641 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2642
2643 LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2644
2645#ifdef VBOX_STRICT
2646 /*
2647 * Check that the entry doesn't already exists.
2648 */
2649 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2650 {
2651 uint16_t i = pPage->iUserHead;
2652 do
2653 {
2654 Assert(i < pPool->cMaxUsers);
2655 AssertMsg(paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2656 i = paUsers[i].iNext;
2657 } while (i != NIL_PGMPOOL_USER_INDEX);
2658 }
2659#endif
2660
2661 /*
2662 * Find free a user node.
2663 */
2664 uint16_t i = pPool->iUserFreeHead;
2665 if (i == NIL_PGMPOOL_USER_INDEX)
2666 {
2667 rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2668 if (RT_FAILURE(rc))
2669 return rc;
2670 i = pPool->iUserFreeHead;
2671 }
2672
2673 /*
2674 * Unlink the user node from the free list,
2675 * initialize and insert it into the user list.
2676 */
2677 pPool->iUserFreeHead = paUsers[i].iNext;
2678 paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2679 paUsers[i].iUser = iUser;
2680 paUsers[i].iUserTable = iUserTable;
2681 pPage->iUserHead = i;
2682
2683 /*
2684 * Insert into cache and enable monitoring of the guest page if enabled.
2685 *
2686 * Until we implement caching of all levels, including the CR3 one, we'll
2687 * have to make sure we don't try monitor & cache any recursive reuse of
2688 * a monitored CR3 page. Because all windows versions are doing this we'll
2689 * have to be able to do combined access monitoring, CR3 + PT and
2690 * PD + PT (guest PAE).
2691 *
2692 * Update:
2693 * We're now cooperating with the CR3 monitor if an uncachable page is found.
2694 */
2695 const bool fCanBeMonitored = true;
2696 pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2697 if (fCanBeMonitored)
2698 {
2699 rc = pgmPoolMonitorInsert(pPool, pPage);
2700 AssertRC(rc);
2701 }
2702 return rc;
2703}
2704
2705
2706/**
2707 * Adds a user reference to a page.
2708 *
2709 * This will move the page to the head of the
2710 *
2711 * @returns VBox status code.
2712 * @retval VINF_SUCCESS if successfully added.
2713 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2714 * @param pPool The pool.
2715 * @param pPage The cached page.
2716 * @param iUser The user index.
2717 * @param iUserTable The user table.
2718 */
2719static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2720{
2721 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2722
2723 Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2724
2725# ifdef VBOX_STRICT
2726 /*
2727 * Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2728 */
2729 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2730 {
2731 uint16_t i = pPage->iUserHead;
2732 do
2733 {
2734 Assert(i < pPool->cMaxUsers);
2735 AssertMsg(iUser != PGMPOOL_IDX_PD || iUser != PGMPOOL_IDX_PDPT || iUser != PGMPOOL_IDX_NESTED_ROOT || iUser != PGMPOOL_IDX_AMD64_CR3 ||
2736 paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2737 i = paUsers[i].iNext;
2738 } while (i != NIL_PGMPOOL_USER_INDEX);
2739 }
2740# endif
2741
2742 /*
2743 * Allocate a user node.
2744 */
2745 uint16_t i = pPool->iUserFreeHead;
2746 if (i == NIL_PGMPOOL_USER_INDEX)
2747 {
2748 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2749 if (RT_FAILURE(rc))
2750 return rc;
2751 i = pPool->iUserFreeHead;
2752 }
2753 pPool->iUserFreeHead = paUsers[i].iNext;
2754
2755 /*
2756 * Initialize the user node and insert it.
2757 */
2758 paUsers[i].iNext = pPage->iUserHead;
2759 paUsers[i].iUser = iUser;
2760 paUsers[i].iUserTable = iUserTable;
2761 pPage->iUserHead = i;
2762
2763# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2764 if (pPage->fDirty)
2765 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirty, false /* do not remove */);
2766# endif
2767
2768 /*
2769 * Tell the cache to update its replacement stats for this page.
2770 */
2771 pgmPoolCacheUsed(pPool, pPage);
2772 return VINF_SUCCESS;
2773}
2774
2775
2776/**
2777 * Frees a user record associated with a page.
2778 *
2779 * This does not clear the entry in the user table, it simply replaces the
2780 * user record to the chain of free records.
2781 *
2782 * @param pPool The pool.
2783 * @param HCPhys The HC physical address of the shadow page.
2784 * @param iUser The shadow page pool index of the user table.
2785 * @param iUserTable The index into the user table (shadowed).
2786 */
2787static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2788{
2789 /*
2790 * Unlink and free the specified user entry.
2791 */
2792 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2793
2794 Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2795 /* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2796 uint16_t i = pPage->iUserHead;
2797 if ( i != NIL_PGMPOOL_USER_INDEX
2798 && paUsers[i].iUser == iUser
2799 && paUsers[i].iUserTable == iUserTable)
2800 {
2801 pPage->iUserHead = paUsers[i].iNext;
2802
2803 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2804 paUsers[i].iNext = pPool->iUserFreeHead;
2805 pPool->iUserFreeHead = i;
2806 return;
2807 }
2808
2809 /* General: Linear search. */
2810 uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2811 while (i != NIL_PGMPOOL_USER_INDEX)
2812 {
2813 if ( paUsers[i].iUser == iUser
2814 && paUsers[i].iUserTable == iUserTable)
2815 {
2816 if (iPrev != NIL_PGMPOOL_USER_INDEX)
2817 paUsers[iPrev].iNext = paUsers[i].iNext;
2818 else
2819 pPage->iUserHead = paUsers[i].iNext;
2820
2821 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2822 paUsers[i].iNext = pPool->iUserFreeHead;
2823 pPool->iUserFreeHead = i;
2824 return;
2825 }
2826 iPrev = i;
2827 i = paUsers[i].iNext;
2828 }
2829
2830 /* Fatal: didn't find it */
2831 AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2832 iUser, iUserTable, pPage->GCPhys));
2833}
2834
2835
2836/**
2837 * Gets the entry size of a shadow table.
2838 *
2839 * @param enmKind The kind of page.
2840 *
2841 * @returns The size of the entry in bytes. That is, 4 or 8.
2842 * @returns If the kind is not for a table, an assertion is raised and 0 is
2843 * returned.
2844 */
2845DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2846{
2847 switch (enmKind)
2848 {
2849 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2850 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2851 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2852 case PGMPOOLKIND_32BIT_PD:
2853 case PGMPOOLKIND_32BIT_PD_PHYS:
2854 return 4;
2855
2856 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2857 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2858 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2859 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2860 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2861 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2862 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2863 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2864 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2865 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2866 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2867 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2868 case PGMPOOLKIND_64BIT_PML4:
2869 case PGMPOOLKIND_PAE_PDPT:
2870 case PGMPOOLKIND_ROOT_NESTED:
2871 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2872 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2873 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2874 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2875 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2876 case PGMPOOLKIND_PAE_PD_PHYS:
2877 case PGMPOOLKIND_PAE_PDPT_PHYS:
2878 return 8;
2879
2880 default:
2881 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2882 }
2883}
2884
2885
2886/**
2887 * Gets the entry size of a guest table.
2888 *
2889 * @param enmKind The kind of page.
2890 *
2891 * @returns The size of the entry in bytes. That is, 0, 4 or 8.
2892 * @returns If the kind is not for a table, an assertion is raised and 0 is
2893 * returned.
2894 */
2895DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2896{
2897 switch (enmKind)
2898 {
2899 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2900 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2901 case PGMPOOLKIND_32BIT_PD:
2902 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2903 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2904 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2905 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2906 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2907 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2908 return 4;
2909
2910 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2911 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2912 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2913 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2914 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2915 case PGMPOOLKIND_64BIT_PML4:
2916 case PGMPOOLKIND_PAE_PDPT:
2917 return 8;
2918
2919 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2920 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2921 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2922 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2923 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2924 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2925 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2926 case PGMPOOLKIND_ROOT_NESTED:
2927 case PGMPOOLKIND_PAE_PD_PHYS:
2928 case PGMPOOLKIND_PAE_PDPT_PHYS:
2929 case PGMPOOLKIND_32BIT_PD_PHYS:
2930 /** @todo can we return 0? (nobody is calling this...) */
2931 AssertFailed();
2932 return 0;
2933
2934 default:
2935 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2936 }
2937}
2938
2939
2940/**
2941 * Scans one shadow page table for mappings of a physical page.
2942 *
2943 * @returns true/false indicating removal of all relevant PTEs
2944 * @param pVM The VM handle.
2945 * @param pPhysPage The guest page in question.
2946 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
2947 * @param iShw The shadow page table.
2948 * @param iPte Page table entry or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown
2949 * @param cRefs The number of references made in that PT.
2950 */
2951static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t iPte, uint16_t cRefs)
2952{
2953 LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d iPte=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, iPte, cRefs));
2954 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2955 bool fRet = false;
2956
2957 /*
2958 * Assert sanity.
2959 */
2960 Assert(cRefs == 1);
2961 Assert(iPte != NIL_PGMPOOL_PHYSEXT_IDX_PTE);
2962 AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2963 PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2964
2965 /*
2966 * Then, clear the actual mappings to the page in the shadow PT.
2967 */
2968 switch (pPage->enmKind)
2969 {
2970 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2971 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2972 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2973 {
2974 const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
2975 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2976 uint32_t u32AndMask = 0;
2977 uint32_t u32OrMask = 0;
2978
2979 if (!fFlushPTEs)
2980 {
2981 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
2982 {
2983 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
2984 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
2985 u32OrMask = X86_PTE_RW;
2986 u32AndMask = UINT32_MAX;
2987 fRet = true;
2988 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
2989 break;
2990
2991 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
2992 u32OrMask = 0;
2993 u32AndMask = ~X86_PTE_RW;
2994 fRet = true;
2995 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
2996 break;
2997 default:
2998 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
2999 break;
3000 }
3001 }
3002 else
3003 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3004
3005 /* Update the counter if we're removing references. */
3006 if (!u32AndMask)
3007 {
3008 Assert(pPage->cPresent >= cRefs);
3009 Assert(pPool->cPresent >= cRefs);
3010 pPage->cPresent -= cRefs;
3011 pPool->cPresent -= cRefs;
3012 }
3013
3014 if ((pPT->a[iPte].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3015 {
3016 X86PTE Pte;
3017
3018 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", iPte, pPT->a[iPte], cRefs));
3019 Pte.u = (pPT->a[iPte].u & u32AndMask) | u32OrMask;
3020 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3021 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3022
3023 ASMAtomicWriteSize(&pPT->a[iPte].u, Pte.u);
3024 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3025 return fRet;
3026 }
3027#ifdef LOG_ENABLED
3028 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3029 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3030 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3031 {
3032 Log(("i=%d cRefs=%d\n", i, cRefs--));
3033 }
3034#endif
3035 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
3036 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3037 break;
3038 }
3039
3040 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3041 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3042 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3043 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3044 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3045 case PGMPOOLKIND_EPT_PT_FOR_PHYS: /* physical mask the same as PAE; RW bit as well; be careful! */
3046 {
3047 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3048 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3049 uint64_t u64OrMask = 0;
3050 uint64_t u64AndMask = 0;
3051
3052 if (!fFlushPTEs)
3053 {
3054 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3055 {
3056 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
3057 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
3058 u64OrMask = X86_PTE_RW;
3059 u64AndMask = UINT64_MAX;
3060 fRet = true;
3061 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3062 break;
3063
3064 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
3065 u64OrMask = 0;
3066 u64AndMask = ~((uint64_t)X86_PTE_RW);
3067 fRet = true;
3068 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3069 break;
3070
3071 default:
3072 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3073 break;
3074 }
3075 }
3076 else
3077 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3078
3079 /* Update the counter if we're removing references. */
3080 if (!u64AndMask)
3081 {
3082 Assert(pPage->cPresent >= cRefs);
3083 Assert(pPool->cPresent >= cRefs);
3084 pPage->cPresent -= cRefs;
3085 pPool->cPresent -= cRefs;
3086 }
3087
3088 if ((pPT->a[iPte].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3089 {
3090 X86PTEPAE Pte;
3091
3092 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", iPte, pPT->a[iPte], cRefs));
3093 Pte.u = (pPT->a[iPte].u & u64AndMask) | u64OrMask;
3094 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3095 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3096
3097 ASMAtomicWriteSize(&pPT->a[iPte].u, Pte.u);
3098 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3099 return fRet;
3100 }
3101#ifdef LOG_ENABLED
3102 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3103 Log(("Found %RX64 expected %RX64\n", pPT->a[iPte].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P), u64));
3104 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3105 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3106 {
3107 Log(("i=%d cRefs=%d\n", i, cRefs--));
3108 }
3109#endif
3110 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind));
3111 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3112 break;
3113 }
3114
3115#ifdef PGM_WITH_LARGE_PAGES
3116 /* Large page case only. */
3117 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3118 {
3119 Assert(pVM->pgm.s.fNestedPaging);
3120
3121 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PDE4M_P | X86_PDE4M_PS;
3122 PEPTPD pPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3123
3124 if ((pPD->a[iPte].u & (EPT_PDE2M_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3125 {
3126 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64 cRefs=%#x\n", iPte, pPD->a[iPte], cRefs));
3127 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3128 pPD->a[iPte].u = 0;
3129 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3130
3131 /* Update the counter as we're removing references. */
3132 Assert(pPage->cPresent);
3133 Assert(pPool->cPresent);
3134 pPage->cPresent--;
3135 pPool->cPresent--;
3136
3137 return fRet;
3138 }
3139# ifdef LOG_ENABLED
3140 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3141 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3142 if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3143 {
3144 Log(("i=%d cRefs=%d\n", i, cRefs--));
3145 }
3146# endif
3147 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3148 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3149 break;
3150 }
3151
3152 /* AMD-V nested paging - @todo merge with EPT as we only check the parts that are identical. */
3153 case PGMPOOLKIND_PAE_PD_PHYS:
3154 {
3155 Assert(pVM->pgm.s.fNestedPaging);
3156
3157 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PDE4M_P | X86_PDE4M_PS;
3158 PX86PD pPD = (PX86PD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3159
3160 if ((pPD->a[iPte].u & (X86_PDE2M_PAE_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3161 {
3162 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64 cRefs=%#x\n", iPte, pPD->a[iPte], cRefs));
3163 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3164 pPD->a[iPte].u = 0;
3165 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3166
3167 /* Update the counter as we're removing references. */
3168 Assert(pPage->cPresent);
3169 Assert(pPool->cPresent);
3170 pPage->cPresent--;
3171 pPool->cPresent--;
3172 return fRet;
3173 }
3174# ifdef LOG_ENABLED
3175 Log(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3176 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3177 if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3178 {
3179 Log(("i=%d cRefs=%d\n", i, cRefs--));
3180 }
3181# endif
3182 AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
3183 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3184 break;
3185 }
3186#endif /* PGM_WITH_LARGE_PAGES */
3187
3188 default:
3189 AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3190 }
3191 return fRet;
3192}
3193
3194
3195/**
3196 * Scans one shadow page table for mappings of a physical page.
3197 *
3198 * @param pVM The VM handle.
3199 * @param pPhysPage The guest page in question.
3200 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3201 * @param iShw The shadow page table.
3202 * @param cRefs The number of references made in that PT.
3203 */
3204static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t cRefs)
3205{
3206 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3207
3208 /* We should only come here with when there's only one reference to this physical page. */
3209 Assert(PGMPOOL_TD_GET_CREFS(PGM_PAGE_GET_TRACKING(pPhysPage)) == 1);
3210 Assert(cRefs == 1);
3211
3212 Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d cRefs=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, cRefs));
3213 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3214 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, PGM_PAGE_GET_PTE_INDEX(pPhysPage), cRefs);
3215 if (!fKeptPTEs)
3216 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3217 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3218}
3219
3220
3221/**
3222 * Flushes a list of shadow page tables mapping the same physical page.
3223 *
3224 * @param pVM The VM handle.
3225 * @param pPhysPage The guest page in question.
3226 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3227 * @param iPhysExt The physical cross reference extent list to flush.
3228 */
3229static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3230{
3231 Assert(PGMIsLockOwner(pVM));
3232 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3233 bool fKeepList = false;
3234
3235 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3236 Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3237
3238 const uint16_t iPhysExtStart = iPhysExt;
3239 PPGMPOOLPHYSEXT pPhysExt;
3240 do
3241 {
3242 Assert(iPhysExt < pPool->cMaxPhysExts);
3243 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3244 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3245 {
3246 if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3247 {
3248 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], pPhysExt->apte[i], 1);
3249 if (!fKeptPTEs)
3250 {
3251 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3252 pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3253 }
3254 else
3255 fKeepList = true;
3256 }
3257 }
3258 /* next */
3259 iPhysExt = pPhysExt->iNext;
3260 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3261
3262 if (!fKeepList)
3263 {
3264 /* insert the list into the free list and clear the ram range entry. */
3265 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3266 pPool->iPhysExtFreeHead = iPhysExtStart;
3267 /* Invalidate the tracking data. */
3268 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3269 }
3270
3271 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3272}
3273
3274
3275/**
3276 * Flushes all shadow page table mappings of the given guest page.
3277 *
3278 * This is typically called when the host page backing the guest one has been
3279 * replaced or when the page protection was changed due to an access handler.
3280 *
3281 * @returns VBox status code.
3282 * @retval VINF_SUCCESS if all references has been successfully cleared.
3283 * @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3284 * pool cleaning. FF and sync flags are set.
3285 *
3286 * @param pVM The VM handle.
3287 * @param GCPhysPage GC physical address of the page in question
3288 * @param pPhysPage The guest page in question.
3289 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3290 * @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3291 * flushed, it is NOT touched if this isn't necessary.
3292 * The caller MUST initialized this to @a false.
3293 */
3294int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3295{
3296 PVMCPU pVCpu = VMMGetCpu(pVM);
3297 pgmLock(pVM);
3298 int rc = VINF_SUCCESS;
3299
3300#ifdef PGM_WITH_LARGE_PAGES
3301 /* Is this page part of a large page? */
3302 if (PGM_PAGE_GET_PDE_TYPE(pPhysPage) == PGM_PAGE_PDE_TYPE_PDE)
3303 {
3304 PPGMPAGE pPhysBase;
3305 RTGCPHYS GCPhysBase = GCPhysPage & X86_PDE2M_PAE_PG_MASK;
3306
3307 GCPhysPage &= X86_PDE_PAE_PG_MASK;
3308
3309 /* Fetch the large page base. */
3310 if (GCPhysBase != GCPhysPage)
3311 {
3312 pPhysBase = pgmPhysGetPage(&pVM->pgm.s, GCPhysBase);
3313 AssertFatal(pPhysBase);
3314 }
3315 else
3316 pPhysBase = pPhysPage;
3317
3318 Log(("pgmPoolTrackUpdateGCPhys: update large page PDE for %RGp (%RGp)\n", GCPhysBase, GCPhysPage));
3319
3320 if (PGM_PAGE_GET_PDE_TYPE(pPhysBase) == PGM_PAGE_PDE_TYPE_PDE)
3321 {
3322 /* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
3323 PGM_PAGE_SET_PDE_TYPE(pPhysBase, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3324
3325 /* Update the base as that *only* that one has a reference and there's only one PDE to clear. */
3326 rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysBase, pPhysBase, fFlushPTEs, pfFlushTLBs);
3327
3328 *pfFlushTLBs = true;
3329 pgmUnlock(pVM);
3330 return rc;
3331 }
3332 }
3333#else
3334 NOREF(GCPhysPage);
3335#endif /* PGM_WITH_LARGE_PAGES */
3336
3337 const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3338 if (u16)
3339 {
3340 /*
3341 * The zero page is currently screwing up the tracking and we'll
3342 * have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3343 * is defined, zero pages won't normally be mapped. Some kind of solution
3344 * will be needed for this problem of course, but it will have to wait...
3345 */
3346 if ( PGM_PAGE_IS_ZERO(pPhysPage)
3347 || PGM_PAGE_IS_BALLOONED(pPhysPage))
3348 rc = VINF_PGM_GCPHYS_ALIASED;
3349 else
3350 {
3351# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC) /** @todo we can drop this now. */
3352 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3353 pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3354 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
3355# endif
3356
3357 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3358 pgmPoolTrackFlushGCPhysPT(pVM,
3359 pPhysPage,
3360 fFlushPTEs,
3361 PGMPOOL_TD_GET_IDX(u16),
3362 PGMPOOL_TD_GET_CREFS(u16));
3363 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3364 pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3365 else
3366 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3367 *pfFlushTLBs = true;
3368
3369# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_R0) || defined(IN_RC)
3370 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
3371# endif
3372 }
3373 }
3374
3375 if (rc == VINF_PGM_GCPHYS_ALIASED)
3376 {
3377 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3378 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3379 rc = VINF_PGM_SYNC_CR3;
3380 }
3381 pgmUnlock(pVM);
3382 return rc;
3383}
3384
3385
3386/**
3387 * Scans all shadow page tables for mappings of a physical page.
3388 *
3389 * This may be slow, but it's most likely more efficient than cleaning
3390 * out the entire page pool / cache.
3391 *
3392 * @returns VBox status code.
3393 * @retval VINF_SUCCESS if all references has been successfully cleared.
3394 * @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3395 * a page pool cleaning.
3396 *
3397 * @param pVM The VM handle.
3398 * @param pPhysPage The guest page in question.
3399 */
3400int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3401{
3402 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3403 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3404 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3405 pPool->cUsedPages, pPool->cPresent, pPhysPage));
3406
3407 /*
3408 * There is a limit to what makes sense.
3409 */
3410 if ( pPool->cPresent > 1024
3411 && pVM->cCpus == 1)
3412 {
3413 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3414 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3415 return VINF_PGM_GCPHYS_ALIASED;
3416 }
3417
3418 /*
3419 * Iterate all the pages until we've encountered all that in use.
3420 * This is simple but not quite optimal solution.
3421 */
3422 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3423 const uint32_t u32 = u64;
3424 unsigned cLeft = pPool->cUsedPages;
3425 unsigned iPage = pPool->cCurPages;
3426 while (--iPage >= PGMPOOL_IDX_FIRST)
3427 {
3428 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3429 if ( pPage->GCPhys != NIL_RTGCPHYS
3430 && pPage->cPresent)
3431 {
3432 switch (pPage->enmKind)
3433 {
3434 /*
3435 * We only care about shadow page tables.
3436 */
3437 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3438 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3439 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3440 {
3441 unsigned cPresent = pPage->cPresent;
3442 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3443 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3444 if (pPT->a[i].n.u1Present)
3445 {
3446 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3447 {
3448 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3449 pPT->a[i].u = 0;
3450
3451 /* Update the counter as we're removing references. */
3452 Assert(pPage->cPresent);
3453 Assert(pPool->cPresent);
3454 pPage->cPresent--;
3455 pPool->cPresent--;
3456 }
3457 if (!--cPresent)
3458 break;
3459 }
3460 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3461 break;
3462 }
3463
3464 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3465 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3466 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3467 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3468 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3469 {
3470 unsigned cPresent = pPage->cPresent;
3471 PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3472 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3473 if (PGM_POOL_IS_PAE_PTE_PRESENT(pPT->a[i]))
3474 {
3475 if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3476 {
3477 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3478 pPT->a[i].u = 0;
3479
3480 /* Update the counter as we're removing references. */
3481 Assert(pPage->cPresent);
3482 Assert(pPool->cPresent);
3483 pPage->cPresent--;
3484 pPool->cPresent--;
3485 }
3486 if (!--cPresent)
3487 break;
3488 }
3489 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3490 break;
3491 }
3492#ifndef IN_RC
3493 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3494 {
3495 unsigned cPresent = pPage->cPresent;
3496 PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3497 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3498 if (PGM_POOL_IS_EPT_PTE_PRESENT(pPT->a[i]))
3499 {
3500 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3501 {
3502 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3503 pPT->a[i].u = 0;
3504
3505 /* Update the counter as we're removing references. */
3506 Assert(pPage->cPresent);
3507 Assert(pPool->cPresent);
3508 pPage->cPresent--;
3509 pPool->cPresent--;
3510 }
3511 if (!--cPresent)
3512 break;
3513 }
3514 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3515 break;
3516 }
3517#endif
3518 }
3519 if (!--cLeft)
3520 break;
3521 }
3522 }
3523
3524 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3525 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3526
3527 /*
3528 * There is a limit to what makes sense. The above search is very expensive, so force a pgm pool flush.
3529 */
3530 if (pPool->cPresent > 1024)
3531 {
3532 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3533 return VINF_PGM_GCPHYS_ALIASED;
3534 }
3535
3536 return VINF_SUCCESS;
3537}
3538
3539
3540/**
3541 * Clears the user entry in a user table.
3542 *
3543 * This is used to remove all references to a page when flushing it.
3544 */
3545static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3546{
3547 Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3548 Assert(pUser->iUser < pPool->cCurPages);
3549 uint32_t iUserTable = pUser->iUserTable;
3550
3551 /*
3552 * Map the user page.
3553 */
3554 PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3555 union
3556 {
3557 uint64_t *pau64;
3558 uint32_t *pau32;
3559 } u;
3560 u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3561
3562 LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3563
3564 /* Safety precaution in case we change the paging for other modes too in the future. */
3565 Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
3566
3567#ifdef VBOX_STRICT
3568 /*
3569 * Some sanity checks.
3570 */
3571 switch (pUserPage->enmKind)
3572 {
3573 case PGMPOOLKIND_32BIT_PD:
3574 case PGMPOOLKIND_32BIT_PD_PHYS:
3575 Assert(iUserTable < X86_PG_ENTRIES);
3576 break;
3577 case PGMPOOLKIND_PAE_PDPT:
3578 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3579 case PGMPOOLKIND_PAE_PDPT_PHYS:
3580 Assert(iUserTable < 4);
3581 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3582 break;
3583 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3584 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3585 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3586 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3587 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3588 case PGMPOOLKIND_PAE_PD_PHYS:
3589 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3590 break;
3591 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3592 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3593 Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3594 break;
3595 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3596 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3597 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3598 break;
3599 case PGMPOOLKIND_64BIT_PML4:
3600 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3601 /* GCPhys >> PAGE_SHIFT is the index here */
3602 break;
3603 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3604 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3605 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3606 break;
3607
3608 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3609 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3610 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3611 break;
3612
3613 case PGMPOOLKIND_ROOT_NESTED:
3614 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3615 break;
3616
3617 default:
3618 AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3619 break;
3620 }
3621#endif /* VBOX_STRICT */
3622
3623 /*
3624 * Clear the entry in the user page.
3625 */
3626 switch (pUserPage->enmKind)
3627 {
3628 /* 32-bit entries */
3629 case PGMPOOLKIND_32BIT_PD:
3630 case PGMPOOLKIND_32BIT_PD_PHYS:
3631 ASMAtomicWriteSize(&u.pau32[iUserTable], 0);
3632 break;
3633
3634 /* 64-bit entries */
3635 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3636 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3637 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3638 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3639 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3640#if defined(IN_RC)
3641 /*
3642 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
3643 * PDPT entry; the CPU fetches them only during cr3 load, so any
3644 * non-present PDPT will continue to cause page faults.
3645 */
3646 ASMReloadCR3();
3647 /* no break */
3648#endif
3649 case PGMPOOLKIND_PAE_PD_PHYS:
3650 case PGMPOOLKIND_PAE_PDPT_PHYS:
3651 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3652 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3653 case PGMPOOLKIND_64BIT_PML4:
3654 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3655 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3656 case PGMPOOLKIND_PAE_PDPT:
3657 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3658 case PGMPOOLKIND_ROOT_NESTED:
3659 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3660 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3661 ASMAtomicWriteSize(&u.pau64[iUserTable], 0);
3662 break;
3663
3664 default:
3665 AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3666 }
3667 PGM_DYNMAP_UNUSED_HINT_VM(pPool->CTX_SUFF(pVM), u.pau64);
3668}
3669
3670
3671/**
3672 * Clears all users of a page.
3673 */
3674static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3675{
3676 /*
3677 * Free all the user records.
3678 */
3679 LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3680
3681 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3682 uint16_t i = pPage->iUserHead;
3683 while (i != NIL_PGMPOOL_USER_INDEX)
3684 {
3685 /* Clear enter in user table. */
3686 pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3687
3688 /* Free it. */
3689 const uint16_t iNext = paUsers[i].iNext;
3690 paUsers[i].iUser = NIL_PGMPOOL_IDX;
3691 paUsers[i].iNext = pPool->iUserFreeHead;
3692 pPool->iUserFreeHead = i;
3693
3694 /* Next. */
3695 i = iNext;
3696 }
3697 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3698}
3699
3700
3701/**
3702 * Allocates a new physical cross reference extent.
3703 *
3704 * @returns Pointer to the allocated extent on success. NULL if we're out of them.
3705 * @param pVM The VM handle.
3706 * @param piPhysExt Where to store the phys ext index.
3707 */
3708PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3709{
3710 Assert(PGMIsLockOwner(pVM));
3711 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3712 uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3713 if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3714 {
3715 STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3716 return NULL;
3717 }
3718 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3719 pPool->iPhysExtFreeHead = pPhysExt->iNext;
3720 pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3721 *piPhysExt = iPhysExt;
3722 return pPhysExt;
3723}
3724
3725
3726/**
3727 * Frees a physical cross reference extent.
3728 *
3729 * @param pVM The VM handle.
3730 * @param iPhysExt The extent to free.
3731 */
3732void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3733{
3734 Assert(PGMIsLockOwner(pVM));
3735 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3736 Assert(iPhysExt < pPool->cMaxPhysExts);
3737 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3738 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3739 {
3740 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3741 pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3742 }
3743 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3744 pPool->iPhysExtFreeHead = iPhysExt;
3745}
3746
3747
3748/**
3749 * Frees a physical cross reference extent.
3750 *
3751 * @param pVM The VM handle.
3752 * @param iPhysExt The extent to free.
3753 */
3754void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3755{
3756 Assert(PGMIsLockOwner(pVM));
3757 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3758
3759 const uint16_t iPhysExtStart = iPhysExt;
3760 PPGMPOOLPHYSEXT pPhysExt;
3761 do
3762 {
3763 Assert(iPhysExt < pPool->cMaxPhysExts);
3764 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3765 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3766 {
3767 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3768 pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3769 }
3770
3771 /* next */
3772 iPhysExt = pPhysExt->iNext;
3773 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3774
3775 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3776 pPool->iPhysExtFreeHead = iPhysExtStart;
3777}
3778
3779
3780/**
3781 * Insert a reference into a list of physical cross reference extents.
3782 *
3783 * @returns The new tracking data for PGMPAGE.
3784 *
3785 * @param pVM The VM handle.
3786 * @param iPhysExt The physical extent index of the list head.
3787 * @param iShwPT The shadow page table index.
3788 * @param iPte Page table entry
3789 *
3790 */
3791static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT, uint16_t iPte)
3792{
3793 Assert(PGMIsLockOwner(pVM));
3794 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3795 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3796
3797 /* special common case. */
3798 if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3799 {
3800 paPhysExts[iPhysExt].aidx[2] = iShwPT;
3801 paPhysExts[iPhysExt].apte[2] = iPte;
3802 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3803 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d pte %d}\n", iPhysExt, iShwPT, iPte));
3804 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3805 }
3806
3807 /* general treatment. */
3808 const uint16_t iPhysExtStart = iPhysExt;
3809 unsigned cMax = 15;
3810 for (;;)
3811 {
3812 Assert(iPhysExt < pPool->cMaxPhysExts);
3813 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3814 if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3815 {
3816 paPhysExts[iPhysExt].aidx[i] = iShwPT;
3817 paPhysExts[iPhysExt].apte[i] = iPte;
3818 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3819 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d pte %d} i=%d cMax=%d\n", iPhysExt, iShwPT, iPte, i, cMax));
3820 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3821 }
3822 if (!--cMax)
3823 {
3824 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackOverflows);
3825 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3826 LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3827 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3828 }
3829 }
3830
3831 /* add another extent to the list. */
3832 PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3833 if (!pNew)
3834 {
3835 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackNoExtentsLeft);
3836 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3837 LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3838 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3839 }
3840 pNew->iNext = iPhysExtStart;
3841 pNew->aidx[0] = iShwPT;
3842 pNew->apte[0] = iPte;
3843 LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d pte %d}->%d\n", iPhysExt, iShwPT, iPte, iPhysExtStart));
3844 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3845}
3846
3847
3848/**
3849 * Add a reference to guest physical page where extents are in use.
3850 *
3851 * @returns The new tracking data for PGMPAGE.
3852 *
3853 * @param pVM The VM handle.
3854 * @param pPhysPage Pointer to the aPages entry in the ram range.
3855 * @param u16 The ram range flags (top 16-bits).
3856 * @param iShwPT The shadow page table index.
3857 * @param iPte Page table entry
3858 */
3859uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte)
3860{
3861 pgmLock(pVM);
3862 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3863 {
3864 /*
3865 * Convert to extent list.
3866 */
3867 Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3868 uint16_t iPhysExt;
3869 PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3870 if (pPhysExt)
3871 {
3872 LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3873 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliased);
3874 pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3875 pPhysExt->apte[0] = PGM_PAGE_GET_PTE_INDEX(pPhysPage);
3876 pPhysExt->aidx[1] = iShwPT;
3877 pPhysExt->apte[1] = iPte;
3878 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3879 }
3880 else
3881 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3882 }
3883 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3884 {
3885 /*
3886 * Insert into the extent list.
3887 */
3888 u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT, iPte);
3889 }
3890 else
3891 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedLots);
3892 pgmUnlock(pVM);
3893 return u16;
3894}
3895
3896/**
3897 * Clear references to guest physical memory.
3898 *
3899 * @param pPool The pool.
3900 * @param pPage The page.
3901 * @param pPhysPage Pointer to the aPages entry in the ram range.
3902 * @param iPte Shadow PTE index
3903 */
3904void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage, uint16_t iPte)
3905{
3906 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3907 AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3908
3909 uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3910 if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3911 {
3912 PVM pVM = pPool->CTX_SUFF(pVM);
3913 pgmLock(pVM);
3914
3915 uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3916 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3917 do
3918 {
3919 Assert(iPhysExt < pPool->cMaxPhysExts);
3920
3921 /*
3922 * Look for the shadow page and check if it's all freed.
3923 */
3924 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3925 {
3926 if ( paPhysExts[iPhysExt].aidx[i] == pPage->idx
3927 && paPhysExts[iPhysExt].apte[i] == iPte)
3928 {
3929 paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3930 paPhysExts[iPhysExt].apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3931
3932 for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3933 if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3934 {
3935 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3936 pgmUnlock(pVM);
3937 return;
3938 }
3939
3940 /* we can free the node. */
3941 const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3942 if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3943 && iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3944 {
3945 /* lonely node */
3946 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3947 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3948 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3949 }
3950 else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3951 {
3952 /* head */
3953 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3954 PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3955 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3956 }
3957 else
3958 {
3959 /* in list */
3960 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d in list\n", pPhysPage, pPage->idx));
3961 paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3962 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3963 }
3964 iPhysExt = iPhysExtNext;
3965 pgmUnlock(pVM);
3966 return;
3967 }
3968 }
3969
3970 /* next */
3971 iPhysExtPrev = iPhysExt;
3972 iPhysExt = paPhysExts[iPhysExt].iNext;
3973 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3974
3975 pgmUnlock(pVM);
3976 AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3977 }
3978 else /* nothing to do */
3979 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3980}
3981
3982/**
3983 * Clear references to guest physical memory.
3984 *
3985 * This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3986 * is assumed to be correct, so the linear search can be skipped and we can assert
3987 * at an earlier point.
3988 *
3989 * @param pPool The pool.
3990 * @param pPage The page.
3991 * @param HCPhys The host physical address corresponding to the guest page.
3992 * @param GCPhys The guest physical address corresponding to HCPhys.
3993 * @param iPte Shadow PTE index
3994 */
3995static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys, uint16_t iPte)
3996{
3997 /*
3998 * Walk range list.
3999 */
4000 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4001 while (pRam)
4002 {
4003 RTGCPHYS off = GCPhys - pRam->GCPhys;
4004 if (off < pRam->cb)
4005 {
4006 /* does it match? */
4007 const unsigned iPage = off >> PAGE_SHIFT;
4008 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4009#ifdef LOG_ENABLED
4010 RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
4011 Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
4012#endif
4013 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4014 {
4015 Assert(pPage->cPresent);
4016 Assert(pPool->cPresent);
4017 pPage->cPresent--;
4018 pPool->cPresent--;
4019 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4020 return;
4021 }
4022 break;
4023 }
4024 pRam = pRam->CTX_SUFF(pNext);
4025 }
4026 AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4027}
4028
4029
4030/**
4031 * Clear references to guest physical memory.
4032 *
4033 * @param pPool The pool.
4034 * @param pPage The page.
4035 * @param HCPhys The host physical address corresponding to the guest page.
4036 * @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4037 * @param iPte Shadow pte index
4038 */
4039void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte)
4040{
4041 RTHCPHYS HCPhysExpected = 0xDEADBEEFDEADBEEFULL;
4042
4043 Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4044
4045 /*
4046 * Walk range list.
4047 */
4048 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4049 while (pRam)
4050 {
4051 RTGCPHYS off = GCPhysHint - pRam->GCPhys;
4052 if (off < pRam->cb)
4053 {
4054 /* does it match? */
4055 const unsigned iPage = off >> PAGE_SHIFT;
4056 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4057 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4058 {
4059 Assert(pPage->cPresent);
4060 Assert(pPool->cPresent);
4061 pPage->cPresent--;
4062 pPool->cPresent--;
4063 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4064 return;
4065 }
4066 HCPhysExpected = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
4067 break;
4068 }
4069 pRam = pRam->CTX_SUFF(pNext);
4070 }
4071
4072 /*
4073 * Damn, the hint didn't work. We'll have to do an expensive linear search.
4074 */
4075 STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4076 pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4077 while (pRam)
4078 {
4079 unsigned iPage = pRam->cb >> PAGE_SHIFT;
4080 while (iPage-- > 0)
4081 {
4082 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4083 {
4084 Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4085 HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4086 Assert(pPage->cPresent);
4087 Assert(pPool->cPresent);
4088 pPage->cPresent--;
4089 pPool->cPresent--;
4090 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4091 return;
4092 }
4093 }
4094 pRam = pRam->CTX_SUFF(pNext);
4095 }
4096
4097 AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp (Expected HCPhys with hint = %RHp)\n", HCPhys, GCPhysHint, HCPhysExpected));
4098}
4099
4100
4101/**
4102 * Clear references to guest physical memory in a 32-bit / 32-bit page table.
4103 *
4104 * @param pPool The pool.
4105 * @param pPage The page.
4106 * @param pShwPT The shadow page table (mapping of the page).
4107 * @param pGstPT The guest page table.
4108 */
4109DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4110{
4111 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4112 if (pShwPT->a[i].n.u1Present)
4113 {
4114 Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4115 i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4116 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK, i);
4117 if (!pPage->cPresent)
4118 break;
4119 }
4120}
4121
4122
4123/**
4124 * Clear references to guest physical memory in a PAE / 32-bit page table.
4125 *
4126 * @param pPool The pool.
4127 * @param pPage The page.
4128 * @param pShwPT The shadow page table (mapping of the page).
4129 * @param pGstPT The guest page table (just a half one).
4130 */
4131DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
4132{
4133 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4134 if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
4135 {
4136 Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4137 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4138 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK, i);
4139 if (!pPage->cPresent)
4140 break;
4141 }
4142}
4143
4144
4145/**
4146 * Clear references to guest physical memory in a PAE / PAE page table.
4147 *
4148 * @param pPool The pool.
4149 * @param pPage The page.
4150 * @param pShwPT The shadow page table (mapping of the page).
4151 * @param pGstPT The guest page table.
4152 */
4153DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
4154{
4155 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4156 if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
4157 {
4158 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4159 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4160 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
4161 if (!pPage->cPresent)
4162 break;
4163 }
4164}
4165
4166
4167/**
4168 * Clear references to guest physical memory in a 32-bit / 4MB page table.
4169 *
4170 * @param pPool The pool.
4171 * @param pPage The page.
4172 * @param pShwPT The shadow page table (mapping of the page).
4173 */
4174DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4175{
4176 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4177 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4178 if (pShwPT->a[i].n.u1Present)
4179 {
4180 Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4181 i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4182 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys, i);
4183 if (!pPage->cPresent)
4184 break;
4185 }
4186}
4187
4188
4189/**
4190 * Clear references to guest physical memory in a PAE / 2/4MB page table.
4191 *
4192 * @param pPool The pool.
4193 * @param pPage The page.
4194 * @param pShwPT The shadow page table (mapping of the page).
4195 */
4196DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
4197{
4198 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4199 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4200 if (PGM_POOL_IS_PAE_PTE_PRESENT(pShwPT->a[i]))
4201 {
4202 Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4203 i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
4204 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys, i);
4205 if (!pPage->cPresent)
4206 break;
4207 }
4208}
4209
4210
4211/**
4212 * Clear references to shadowed pages in an EPT page table.
4213 *
4214 * @param pPool The pool.
4215 * @param pPage The page.
4216 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4217 */
4218DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4219{
4220 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4221 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4222 if (PGM_POOL_IS_EPT_PTE_PRESENT(pShwPT->a[i]))
4223 {
4224 Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4225 i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4226 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys, i);
4227 if (!pPage->cPresent)
4228 break;
4229 }
4230}
4231
4232
4233
4234/**
4235 * Clear references to shadowed pages in a 32 bits page directory.
4236 *
4237 * @param pPool The pool.
4238 * @param pPage The page.
4239 * @param pShwPD The shadow page directory (mapping of the page).
4240 */
4241DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4242{
4243 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4244 {
4245 if ( pShwPD->a[i].n.u1Present
4246 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4247 )
4248 {
4249 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4250 if (pSubPage)
4251 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4252 else
4253 AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4254 }
4255 }
4256}
4257
4258/**
4259 * Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4260 *
4261 * @param pPool The pool.
4262 * @param pPage The page.
4263 * @param pShwPD The shadow page directory (mapping of the page).
4264 */
4265DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4266{
4267 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4268 {
4269 if ( pShwPD->a[i].n.u1Present
4270 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4271 )
4272 {
4273#ifdef PGM_WITH_LARGE_PAGES
4274 if (pShwPD->a[i].b.u1Size)
4275 {
4276 Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
4277 i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4278 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys /* == base of 2 MB page */, i);
4279 }
4280 else
4281#endif
4282 {
4283 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4284 if (pSubPage)
4285 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4286 else
4287 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4288 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4289 }
4290 }
4291 }
4292}
4293
4294/**
4295 * Clear references to shadowed pages in a PAE page directory pointer table.
4296 *
4297 * @param pPool The pool.
4298 * @param pPage The page.
4299 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4300 */
4301DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4302{
4303 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4304 {
4305 if ( pShwPDPT->a[i].n.u1Present
4306 && !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4307 )
4308 {
4309 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4310 if (pSubPage)
4311 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4312 else
4313 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4314 }
4315 }
4316}
4317
4318
4319/**
4320 * Clear references to shadowed pages in a 64-bit page directory pointer table.
4321 *
4322 * @param pPool The pool.
4323 * @param pPage The page.
4324 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4325 */
4326DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4327{
4328 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4329 {
4330 Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
4331 if (pShwPDPT->a[i].n.u1Present)
4332 {
4333 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4334 if (pSubPage)
4335 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4336 else
4337 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4338 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4339 }
4340 }
4341}
4342
4343
4344/**
4345 * Clear references to shadowed pages in a 64-bit level 4 page table.
4346 *
4347 * @param pPool The pool.
4348 * @param pPage The page.
4349 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4350 */
4351DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4352{
4353 for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4354 {
4355 if (pShwPML4->a[i].n.u1Present)
4356 {
4357 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4358 if (pSubPage)
4359 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4360 else
4361 AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4362 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4363 }
4364 }
4365}
4366
4367
4368/**
4369 * Clear references to shadowed pages in an EPT page directory.
4370 *
4371 * @param pPool The pool.
4372 * @param pPage The page.
4373 * @param pShwPD The shadow page directory (mapping of the page).
4374 */
4375DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4376{
4377 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4378 {
4379 if (pShwPD->a[i].n.u1Present)
4380 {
4381#ifdef PGM_WITH_LARGE_PAGES
4382 if (pShwPD->a[i].b.u1Size)
4383 {
4384 Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
4385 i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4386 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys /* == base of 2 MB page */, i);
4387 }
4388 else
4389#endif
4390 {
4391 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4392 if (pSubPage)
4393 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4394 else
4395 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4396 }
4397 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4398 }
4399 }
4400}
4401
4402
4403/**
4404 * Clear references to shadowed pages in an EPT page directory pointer table.
4405 *
4406 * @param pPool The pool.
4407 * @param pPage The page.
4408 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4409 */
4410DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4411{
4412 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4413 {
4414 if (pShwPDPT->a[i].n.u1Present)
4415 {
4416 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4417 if (pSubPage)
4418 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4419 else
4420 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4421 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4422 }
4423 }
4424}
4425
4426
4427/**
4428 * Clears all references made by this page.
4429 *
4430 * This includes other shadow pages and GC physical addresses.
4431 *
4432 * @param pPool The pool.
4433 * @param pPage The page.
4434 */
4435static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4436{
4437 /*
4438 * Map the shadow page and take action according to the page kind.
4439 */
4440 PVM pVM = pPool->CTX_SUFF(pVM);
4441 void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4442 switch (pPage->enmKind)
4443 {
4444 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4445 {
4446 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4447 void *pvGst;
4448 int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4449 pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4450 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4451 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4452 break;
4453 }
4454
4455 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4456 {
4457 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4458 void *pvGst;
4459 int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4460 pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
4461 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4462 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4463 break;
4464 }
4465
4466 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4467 {
4468 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4469 void *pvGst;
4470 int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4471 pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
4472 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4473 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4474 break;
4475 }
4476
4477 case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4478 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4479 {
4480 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4481 pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4482 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4483 break;
4484 }
4485
4486 case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4487 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4488 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4489 {
4490 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4491 pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
4492 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4493 break;
4494 }
4495
4496 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4497 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4498 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4499 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4500 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4501 case PGMPOOLKIND_PAE_PD_PHYS:
4502 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4503 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4504 pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4505 break;
4506
4507 case PGMPOOLKIND_32BIT_PD_PHYS:
4508 case PGMPOOLKIND_32BIT_PD:
4509 pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4510 break;
4511
4512 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4513 case PGMPOOLKIND_PAE_PDPT:
4514 case PGMPOOLKIND_PAE_PDPT_PHYS:
4515 pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4516 break;
4517
4518 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4519 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4520 pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4521 break;
4522
4523 case PGMPOOLKIND_64BIT_PML4:
4524 pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4525 break;
4526
4527 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4528 pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4529 break;
4530
4531 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4532 pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4533 break;
4534
4535 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4536 pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4537 break;
4538
4539 default:
4540 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4541 }
4542
4543 /* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4544 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4545 ASMMemZeroPage(pvShw);
4546 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4547 pPage->fZeroed = true;
4548 Assert(!pPage->cPresent);
4549 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
4550}
4551
4552/**
4553 * Flushes a pool page.
4554 *
4555 * This moves the page to the free list after removing all user references to it.
4556 *
4557 * @returns VBox status code.
4558 * @retval VINF_SUCCESS on success.
4559 * @param pPool The pool.
4560 * @param HCPhys The HC physical address of the shadow page.
4561 * @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
4562 */
4563int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush)
4564{
4565 PVM pVM = pPool->CTX_SUFF(pVM);
4566 bool fFlushRequired = false;
4567
4568 int rc = VINF_SUCCESS;
4569 STAM_PROFILE_START(&pPool->StatFlushPage, f);
4570 LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4571 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4572
4573 /*
4574 * Quietly reject any attempts at flushing any of the special root pages.
4575 */
4576 if (pPage->idx < PGMPOOL_IDX_FIRST)
4577 {
4578 AssertFailed(); /* can no longer happen */
4579 Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4580 return VINF_SUCCESS;
4581 }
4582
4583 pgmLock(pVM);
4584
4585 /*
4586 * Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4587 */
4588 if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4589 {
4590 AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4591 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4592 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4593 || pPage->enmKind == PGMPOOLKIND_32BIT_PD
4594 || pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4595 || pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4596 || pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4597 || pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4598 || pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4599 ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4600 Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4601 pgmUnlock(pVM);
4602 return VINF_SUCCESS;
4603 }
4604
4605#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4606 /* Start a subset so we won't run out of mapping space. */
4607 PVMCPU pVCpu = VMMGetCpu(pVM);
4608 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
4609#endif
4610
4611 /*
4612 * Mark the page as being in need of an ASMMemZeroPage().
4613 */
4614 pPage->fZeroed = false;
4615
4616#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4617 if (pPage->fDirty)
4618 pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirty, false /* do not remove */);
4619#endif
4620
4621 /* If there are any users of this table, then we *must* issue a tlb flush on all VCPUs. */
4622 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
4623 fFlushRequired = true;
4624
4625 /*
4626 * Clear the page.
4627 */
4628 pgmPoolTrackClearPageUsers(pPool, pPage);
4629 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4630 pgmPoolTrackDeref(pPool, pPage);
4631 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4632
4633 /*
4634 * Flush it from the cache.
4635 */
4636 pgmPoolCacheFlushPage(pPool, pPage);
4637
4638#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_R0) || defined(IN_RC)
4639 /* Heavy stuff done. */
4640 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
4641#endif
4642
4643 /*
4644 * Deregistering the monitoring.
4645 */
4646 if (pPage->fMonitored)
4647 rc = pgmPoolMonitorFlush(pPool, pPage);
4648
4649 /*
4650 * Free the page.
4651 */
4652 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4653 pPage->iNext = pPool->iFreeHead;
4654 pPool->iFreeHead = pPage->idx;
4655 pPage->enmKind = PGMPOOLKIND_FREE;
4656 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4657 pPage->GCPhys = NIL_RTGCPHYS;
4658 pPage->fReusedFlushPending = false;
4659
4660 pPool->cUsedPages--;
4661
4662 /* Flush the TLBs of all VCPUs if required. */
4663 if ( fFlushRequired
4664 && fFlush)
4665 {
4666 PGM_INVL_ALL_VCPU_TLBS(pVM);
4667 }
4668
4669 pgmUnlock(pVM);
4670 STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4671 return rc;
4672}
4673
4674
4675/**
4676 * Frees a usage of a pool page.
4677 *
4678 * The caller is responsible to updating the user table so that it no longer
4679 * references the shadow page.
4680 *
4681 * @param pPool The pool.
4682 * @param HCPhys The HC physical address of the shadow page.
4683 * @param iUser The shadow page pool index of the user table.
4684 * @param iUserTable The index into the user table (shadowed).
4685 */
4686void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4687{
4688 PVM pVM = pPool->CTX_SUFF(pVM);
4689
4690 STAM_PROFILE_START(&pPool->StatFree, a);
4691 LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
4692 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4693 Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4694 pgmLock(pVM);
4695 pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4696 if (!pPage->fCached)
4697 pgmPoolFlushPage(pPool, pPage);
4698 pgmUnlock(pVM);
4699 STAM_PROFILE_STOP(&pPool->StatFree, a);
4700}
4701
4702
4703/**
4704 * Makes one or more free page free.
4705 *
4706 * @returns VBox status code.
4707 * @retval VINF_SUCCESS on success.
4708 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4709 *
4710 * @param pPool The pool.
4711 * @param enmKind Page table kind
4712 * @param iUser The user of the page.
4713 */
4714static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4715{
4716 PVM pVM = pPool->CTX_SUFF(pVM);
4717
4718 LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
4719
4720 /*
4721 * If the pool isn't full grown yet, expand it.
4722 */
4723 if ( pPool->cCurPages < pPool->cMaxPages
4724#if defined(IN_RC)
4725 /* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4726 && enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4727 && (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD || enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4728#endif
4729 )
4730 {
4731 STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4732#ifdef IN_RING3
4733 int rc = PGMR3PoolGrow(pVM);
4734#else
4735 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4736#endif
4737 if (RT_FAILURE(rc))
4738 return rc;
4739 STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4740 if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4741 return VINF_SUCCESS;
4742 }
4743
4744 /*
4745 * Free one cached page.
4746 */
4747 return pgmPoolCacheFreeOne(pPool, iUser);
4748}
4749
4750/**
4751 * Allocates a page from the pool.
4752 *
4753 * This page may actually be a cached page and not in need of any processing
4754 * on the callers part.
4755 *
4756 * @returns VBox status code.
4757 * @retval VINF_SUCCESS if a NEW page was allocated.
4758 * @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4759 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4760 * @param pVM The VM handle.
4761 * @param GCPhys The GC physical address of the page we're gonna shadow.
4762 * For 4MB and 2MB PD entries, it's the first address the
4763 * shadow PT is covering.
4764 * @param enmKind The kind of mapping.
4765 * @param enmAccess Access type for the mapping (only relevant for big pages)
4766 * @param iUser The shadow page pool index of the user table.
4767 * @param iUserTable The index into the user table (shadowed).
4768 * @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4769 * @param fLockPage Lock the page
4770 */
4771int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage, bool fLockPage)
4772{
4773 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4774 STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4775 LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4776 *ppPage = NULL;
4777 /** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4778 * (TRPMR3SyncIDT) because of FF priority. Try fix that?
4779 * Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4780
4781 pgmLock(pVM);
4782
4783 if (pPool->fCacheEnabled)
4784 {
4785 int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4786 if (RT_SUCCESS(rc2))
4787 {
4788 if (fLockPage)
4789 pgmPoolLockPage(pPool, *ppPage);
4790 pgmUnlock(pVM);
4791 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4792 LogFlow(("pgmPoolAlloc: cached returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, *ppPage, (*ppPage)->Core.Key, (*ppPage)->idx));
4793 return rc2;
4794 }
4795 }
4796
4797 /*
4798 * Allocate a new one.
4799 */
4800 int rc = VINF_SUCCESS;
4801 uint16_t iNew = pPool->iFreeHead;
4802 if (iNew == NIL_PGMPOOL_IDX)
4803 {
4804 rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4805 if (RT_FAILURE(rc))
4806 {
4807 pgmUnlock(pVM);
4808 Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4809 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4810 return rc;
4811 }
4812 iNew = pPool->iFreeHead;
4813 AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4814 }
4815
4816 /* unlink the free head */
4817 PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4818 pPool->iFreeHead = pPage->iNext;
4819 pPage->iNext = NIL_PGMPOOL_IDX;
4820
4821 /*
4822 * Initialize it.
4823 */
4824 pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4825 pPage->enmKind = enmKind;
4826 pPage->enmAccess = enmAccess;
4827 pPage->GCPhys = GCPhys;
4828 pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4829 pPage->fMonitored = false;
4830 pPage->fCached = false;
4831#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4832 pPage->fDirty = false;
4833#endif
4834 pPage->fReusedFlushPending = false;
4835 pPage->cModifications = 0;
4836 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4837 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4838 pPage->cLocked = 0;
4839 pPage->cPresent = 0;
4840 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
4841 pPage->pvLastAccessHandlerFault = 0;
4842 pPage->cLastAccessHandlerCount = 0;
4843 pPage->pvLastAccessHandlerRip = 0;
4844
4845 /*
4846 * Insert into the tracking and cache. If this fails, free the page.
4847 */
4848 int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4849 if (RT_FAILURE(rc3))
4850 {
4851 pPool->cUsedPages--;
4852 pPage->enmKind = PGMPOOLKIND_FREE;
4853 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4854 pPage->GCPhys = NIL_RTGCPHYS;
4855 pPage->iNext = pPool->iFreeHead;
4856 pPool->iFreeHead = pPage->idx;
4857 pgmUnlock(pVM);
4858 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4859 Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4860 return rc3;
4861 }
4862
4863 /*
4864 * Commit the allocation, clear the page and return.
4865 */
4866#ifdef VBOX_WITH_STATISTICS
4867 if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4868 pPool->cUsedPagesHigh = pPool->cUsedPages;
4869#endif
4870
4871 if (!pPage->fZeroed)
4872 {
4873 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4874 void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4875 ASMMemZeroPage(pv);
4876 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4877 }
4878
4879 *ppPage = pPage;
4880 if (fLockPage)
4881 pgmPoolLockPage(pPool, pPage);
4882 pgmUnlock(pVM);
4883 LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4884 rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4885 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4886 return rc;
4887}
4888
4889
4890/**
4891 * Frees a usage of a pool page.
4892 *
4893 * @param pVM The VM handle.
4894 * @param HCPhys The HC physical address of the shadow page.
4895 * @param iUser The shadow page pool index of the user table.
4896 * @param iUserTable The index into the user table (shadowed).
4897 */
4898void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4899{
4900 LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4901 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4902 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4903}
4904
4905/**
4906 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4907 *
4908 * @returns Pointer to the shadow page structure.
4909 * @param pPool The pool.
4910 * @param HCPhys The HC physical address of the shadow page.
4911 */
4912PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4913{
4914 PVM pVM = pPool->CTX_SUFF(pVM);
4915
4916 Assert(PGMIsLockOwner(pVM));
4917
4918 /*
4919 * Look up the page.
4920 */
4921 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4922
4923 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4924 return pPage;
4925}
4926
4927#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
4928/**
4929 * Flush the specified page if present
4930 *
4931 * @param pVM The VM handle.
4932 * @param GCPhys Guest physical address of the page to flush
4933 */
4934void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
4935{
4936 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4937
4938 VM_ASSERT_EMT(pVM);
4939
4940 /*
4941 * Look up the GCPhys in the hash.
4942 */
4943 GCPhys = GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
4944 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
4945 if (i == NIL_PGMPOOL_IDX)
4946 return;
4947
4948 do
4949 {
4950 PPGMPOOLPAGE pPage = &pPool->aPages[i];
4951 if (pPage->GCPhys - GCPhys < PAGE_SIZE)
4952 {
4953 switch (pPage->enmKind)
4954 {
4955 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4956 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4957 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4958 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4959 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4960 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4961 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4962 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4963 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4964 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4965 case PGMPOOLKIND_64BIT_PML4:
4966 case PGMPOOLKIND_32BIT_PD:
4967 case PGMPOOLKIND_PAE_PDPT:
4968 {
4969 Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
4970#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4971 if (pPage->fDirty)
4972 STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
4973 else
4974#endif
4975 STAM_COUNTER_INC(&pPool->StatForceFlushPage);
4976 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
4977 pgmPoolMonitorChainFlush(pPool, pPage);
4978 return;
4979 }
4980
4981 /* ignore, no monitoring. */
4982 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4983 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4984 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4985 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4986 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4987 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4988 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4989 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4990 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4991 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4992 case PGMPOOLKIND_ROOT_NESTED:
4993 case PGMPOOLKIND_PAE_PD_PHYS:
4994 case PGMPOOLKIND_PAE_PDPT_PHYS:
4995 case PGMPOOLKIND_32BIT_PD_PHYS:
4996 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4997 break;
4998
4999 default:
5000 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
5001 }
5002 }
5003
5004 /* next */
5005 i = pPage->iNext;
5006 } while (i != NIL_PGMPOOL_IDX);
5007 return;
5008}
5009#endif /* IN_RING3 */
5010
5011#ifdef IN_RING3
5012
5013
5014/**
5015 * Reset CPU on hot plugging.
5016 *
5017 * @param pVM The VM handle.
5018 * @param pVCpu The virtual CPU.
5019 */
5020void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
5021{
5022 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
5023
5024 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5025 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5026 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5027}
5028
5029
5030/**
5031 * Flushes the entire cache.
5032 *
5033 * It will assert a global CR3 flush (FF) and assumes the caller is aware of
5034 * this and execute this CR3 flush.
5035 *
5036 * @param pPool The pool.
5037 */
5038void pgmR3PoolReset(PVM pVM)
5039{
5040 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5041
5042 Assert(PGMIsLockOwner(pVM));
5043 STAM_PROFILE_START(&pPool->StatR3Reset, a);
5044 LogFlow(("pgmR3PoolReset:\n"));
5045
5046 /*
5047 * If there are no pages in the pool, there is nothing to do.
5048 */
5049 if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5050 {
5051 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5052 return;
5053 }
5054
5055 /*
5056 * Exit the shadow mode since we're going to clear everything,
5057 * including the root page.
5058 */
5059 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5060 {
5061 PVMCPU pVCpu = &pVM->aCpus[i];
5062 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
5063 }
5064
5065 /*
5066 * Nuke the free list and reinsert all pages into it.
5067 */
5068 for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5069 {
5070 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5071
5072 Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
5073 if (pPage->fMonitored)
5074 pgmPoolMonitorFlush(pPool, pPage);
5075 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5076 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5077 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5078 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5079 pPage->cModifications = 0;
5080 pPage->GCPhys = NIL_RTGCPHYS;
5081 pPage->enmKind = PGMPOOLKIND_FREE;
5082 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5083 Assert(pPage->idx == i);
5084 pPage->iNext = i + 1;
5085 pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5086 pPage->fSeenNonGlobal = false;
5087 pPage->fMonitored = false;
5088#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5089 pPage->fDirty = false;
5090#endif
5091 pPage->fCached = false;
5092 pPage->fReusedFlushPending = false;
5093 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5094 pPage->iAgeNext = NIL_PGMPOOL_IDX;
5095 pPage->iAgePrev = NIL_PGMPOOL_IDX;
5096 pPage->cLocked = 0;
5097 }
5098 pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5099 pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5100 pPool->cUsedPages = 0;
5101
5102 /*
5103 * Zap and reinitialize the user records.
5104 */
5105 pPool->cPresent = 0;
5106 pPool->iUserFreeHead = 0;
5107 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5108 const unsigned cMaxUsers = pPool->cMaxUsers;
5109 for (unsigned i = 0; i < cMaxUsers; i++)
5110 {
5111 paUsers[i].iNext = i + 1;
5112 paUsers[i].iUser = NIL_PGMPOOL_IDX;
5113 paUsers[i].iUserTable = 0xfffffffe;
5114 }
5115 paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5116
5117 /*
5118 * Clear all the GCPhys links and rebuild the phys ext free list.
5119 */
5120 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
5121 pRam;
5122 pRam = pRam->CTX_SUFF(pNext))
5123 {
5124 unsigned iPage = pRam->cb >> PAGE_SHIFT;
5125 while (iPage-- > 0)
5126 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
5127 }
5128
5129 pPool->iPhysExtFreeHead = 0;
5130 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5131 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5132 for (unsigned i = 0; i < cMaxPhysExts; i++)
5133 {
5134 paPhysExts[i].iNext = i + 1;
5135 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5136 paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5137 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5138 paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5139 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5140 paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5141 }
5142 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5143
5144 /*
5145 * Just zap the modified list.
5146 */
5147 pPool->cModifiedPages = 0;
5148 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5149
5150 /*
5151 * Clear the GCPhys hash and the age list.
5152 */
5153 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5154 pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5155 pPool->iAgeHead = NIL_PGMPOOL_IDX;
5156 pPool->iAgeTail = NIL_PGMPOOL_IDX;
5157
5158#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5159 /* Clear all dirty pages. */
5160 pPool->idxFreeDirtyPage = 0;
5161 pPool->cDirtyPages = 0;
5162 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aIdxDirtyPages); i++)
5163 pPool->aIdxDirtyPages[i] = NIL_PGMPOOL_IDX;
5164#endif
5165
5166 /*
5167 * Reinsert active pages into the hash and ensure monitoring chains are correct.
5168 */
5169 for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
5170 {
5171 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5172 pPage->iNext = NIL_PGMPOOL_IDX;
5173 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5174 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5175 pPage->cModifications = 0;
5176 /* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
5177 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5178 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5179 if (pPage->fMonitored)
5180 {
5181 int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
5182 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
5183 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
5184 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
5185 pPool->pszAccessHandler);
5186 AssertFatalRCSuccess(rc);
5187 pgmPoolHashInsert(pPool, pPage);
5188 }
5189 Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
5190 Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
5191 Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
5192 }
5193
5194 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5195 {
5196 /*
5197 * Re-enter the shadowing mode and assert Sync CR3 FF.
5198 */
5199 PVMCPU pVCpu = &pVM->aCpus[i];
5200 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5201 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5202 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5203 }
5204
5205 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5206}
5207#endif /* IN_RING3 */
5208
5209#ifdef LOG_ENABLED
5210static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5211{
5212 switch(enmKind)
5213 {
5214 case PGMPOOLKIND_INVALID:
5215 return "PGMPOOLKIND_INVALID";
5216 case PGMPOOLKIND_FREE:
5217 return "PGMPOOLKIND_FREE";
5218 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5219 return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5220 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5221 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5222 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5223 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5224 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5225 return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5226 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5227 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5228 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5229 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5230 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5231 return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5232 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5233 return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5234 case PGMPOOLKIND_32BIT_PD:
5235 return "PGMPOOLKIND_32BIT_PD";
5236 case PGMPOOLKIND_32BIT_PD_PHYS:
5237 return "PGMPOOLKIND_32BIT_PD_PHYS";
5238 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5239 return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5240 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5241 return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5242 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5243 return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5244 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5245 return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5246 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5247 return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5248 case PGMPOOLKIND_PAE_PD_PHYS:
5249 return "PGMPOOLKIND_PAE_PD_PHYS";
5250 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5251 return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5252 case PGMPOOLKIND_PAE_PDPT:
5253 return "PGMPOOLKIND_PAE_PDPT";
5254 case PGMPOOLKIND_PAE_PDPT_PHYS:
5255 return "PGMPOOLKIND_PAE_PDPT_PHYS";
5256 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5257 return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5258 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5259 return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5260 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5261 return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5262 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5263 return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5264 case PGMPOOLKIND_64BIT_PML4:
5265 return "PGMPOOLKIND_64BIT_PML4";
5266 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5267 return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5268 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5269 return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5270 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5271 return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5272 case PGMPOOLKIND_ROOT_NESTED:
5273 return "PGMPOOLKIND_ROOT_NESTED";
5274 }
5275 return "Unknown kind!";
5276}
5277#endif /* LOG_ENABLED*/
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