VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 32362

Last change on this file since 32362 was 32362, checked in by vboxsync, 15 years ago

Some cleanup
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File size: 201.6 KB
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1/* $Id: PGMAllPool.cpp 32362 2010-09-09 15:55:20Z vboxsync $ */
2/** @file
3 * PGM Shadow Page Pool.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM_POOL
23#include <VBox/pgm.h>
24#include <VBox/mm.h>
25#include <VBox/em.h>
26#include <VBox/cpum.h>
27#ifdef IN_RC
28# include <VBox/patm.h>
29#endif
30#include "../PGMInternal.h"
31#include <VBox/vm.h>
32#include "../PGMInline.h"
33#include <VBox/disopcode.h>
34#include <VBox/hwacc_vmx.h>
35
36#include <VBox/log.h>
37#include <VBox/err.h>
38#include <iprt/asm.h>
39#include <iprt/asm-amd64-x86.h>
40#include <iprt/string.h>
41
42
43/*******************************************************************************
44* Internal Functions *
45*******************************************************************************/
46RT_C_DECLS_BEGIN
47static void pgmPoolFlushAllInt(PPGMPOOL pPool);
48DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
49DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
50static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
51static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
52static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
53#ifndef IN_RING3
54DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
55#endif
56#ifdef LOG_ENABLED
57static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
58#endif
59#if defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)
60static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT);
61#endif
62
63int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
64PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
65void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
66void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
67
68RT_C_DECLS_END
69
70
71/**
72 * Checks if the specified page pool kind is for a 4MB or 2MB guest page.
73 *
74 * @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
75 * @param enmKind The page kind.
76 */
77DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
78{
79 switch (enmKind)
80 {
81 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
82 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
83 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
84 return true;
85 default:
86 return false;
87 }
88}
89
90
91/**
92 * Flushes a chain of pages sharing the same access monitor.
93 *
94 * @returns VBox status code suitable for scheduling.
95 * @param pPool The pool.
96 * @param pPage A page in the chain.
97 * @todo VBOXSTRICTRC
98 */
99int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
100{
101 LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
102
103 /*
104 * Find the list head.
105 */
106 uint16_t idx = pPage->idx;
107 if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
108 {
109 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
110 {
111 idx = pPage->iMonitoredPrev;
112 Assert(idx != pPage->idx);
113 pPage = &pPool->aPages[idx];
114 }
115 }
116
117 /*
118 * Iterate the list flushing each shadow page.
119 */
120 int rc = VINF_SUCCESS;
121 for (;;)
122 {
123 idx = pPage->iMonitoredNext;
124 Assert(idx != pPage->idx);
125 if (pPage->idx >= PGMPOOL_IDX_FIRST)
126 {
127 int rc2 = pgmPoolFlushPage(pPool, pPage);
128 AssertRC(rc2);
129 }
130 /* next */
131 if (idx == NIL_PGMPOOL_IDX)
132 break;
133 pPage = &pPool->aPages[idx];
134 }
135 return rc;
136}
137
138
139/**
140 * Wrapper for getting the current context pointer to the entry being modified.
141 *
142 * @returns VBox status code suitable for scheduling.
143 * @param pVM VM Handle.
144 * @param pvDst Destination address
145 * @param pvSrc Source guest virtual address.
146 * @param GCPhysSrc The source guest physical address.
147 * @param cb Size of data to read
148 */
149DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
150{
151#if defined(IN_RING3)
152 memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
153 return VINF_SUCCESS;
154#else
155 /* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
156 return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
157#endif
158}
159
160/**
161 * Process shadow entries before they are changed by the guest.
162 *
163 * For PT entries we will clear them. For PD entries, we'll simply check
164 * for mapping conflicts and set the SyncCR3 FF if found.
165 *
166 * @param pVCpu VMCPU handle
167 * @param pPool The pool.
168 * @param pPage The head page.
169 * @param GCPhysFault The guest physical fault address.
170 * @param uAddress In R0 and GC this is the guest context fault address (flat).
171 * In R3 this is the host context 'fault' address.
172 * @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
173 */
174void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite)
175{
176 AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%u (idx=%u)\n", pPage->iMonitoredPrev, pPage->idx));
177 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
178 PVM pVM = pPool->CTX_SUFF(pVM);
179
180 LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n", (RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))pvAddress, GCPhysFault, cbWrite));
181
182 for (;;)
183 {
184 union
185 {
186 void *pv;
187 PX86PT pPT;
188 PPGMSHWPTPAE pPTPae;
189 PX86PD pPD;
190 PX86PDPAE pPDPae;
191 PX86PDPT pPDPT;
192 PX86PML4 pPML4;
193 } uShw;
194
195 LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s\n", pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
196
197 uShw.pv = NULL;
198 switch (pPage->enmKind)
199 {
200 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
201 {
202 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
203 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
204 const unsigned iShw = off / sizeof(X86PTE);
205 LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
206 if (uShw.pPT->a[iShw].n.u1Present)
207 {
208 X86PTE GstPte;
209
210 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
211 AssertRC(rc);
212 Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
213 pgmPoolTracDerefGCPhysHint(pPool, pPage,
214 uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
215 GstPte.u & X86_PTE_PG_MASK,
216 iShw);
217 ASMAtomicWriteU32(&uShw.pPT->a[iShw].u, 0);
218 }
219 break;
220 }
221
222 /* page/2 sized */
223 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
224 {
225 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
226 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
227 if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
228 {
229 const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
230 LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
231 if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
232 {
233 X86PTE GstPte;
234 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
235 AssertRC(rc);
236
237 Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
238 pgmPoolTracDerefGCPhysHint(pPool, pPage,
239 PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
240 GstPte.u & X86_PTE_PG_MASK,
241 iShw);
242 PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
243 }
244 }
245 break;
246 }
247
248 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
249 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
250 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
251 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
252 {
253 unsigned iGst = off / sizeof(X86PDE);
254 unsigned iShwPdpt = iGst / 256;
255 unsigned iShw = (iGst % 256) * 2;
256 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
257
258 LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
259 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
260 if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
261 {
262 for (unsigned i = 0; i < 2; i++)
263 {
264# ifndef IN_RING0
265 if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
266 {
267 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
268 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
269 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
270 break;
271 }
272 else
273# endif /* !IN_RING0 */
274 if (uShw.pPDPae->a[iShw+i].n.u1Present)
275 {
276 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
277 pgmPoolFree(pVM,
278 uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
279 pPage->idx,
280 iShw + i);
281 ASMAtomicWriteU64(&uShw.pPDPae->a[iShw+i].u, 0);
282 }
283
284 /* paranoia / a bit assumptive. */
285 if ( (off & 3)
286 && (off & 3) + cbWrite > 4)
287 {
288 const unsigned iShw2 = iShw + 2 + i;
289 if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
290 {
291# ifndef IN_RING0
292 if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING | X86_PDE_P)) == (PGM_PDFLAGS_MAPPING | X86_PDE_P))
293 {
294 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
295 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
296 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
297 break;
298 }
299 else
300# endif /* !IN_RING0 */
301 if (uShw.pPDPae->a[iShw2].n.u1Present)
302 {
303 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
304 pgmPoolFree(pVM,
305 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
306 pPage->idx,
307 iShw2);
308 ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
309 }
310 }
311 }
312 }
313 }
314 break;
315 }
316
317 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
318 {
319 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
320 const unsigned iShw = off / sizeof(X86PTEPAE);
321 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
322 if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
323 {
324 X86PTEPAE GstPte;
325 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
326 AssertRC(rc);
327
328 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK));
329 pgmPoolTracDerefGCPhysHint(pPool, pPage,
330 PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
331 GstPte.u & X86_PTE_PAE_PG_MASK,
332 iShw);
333 PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
334 }
335
336 /* paranoia / a bit assumptive. */
337 if ( (off & 7)
338 && (off & 7) + cbWrite > sizeof(X86PTEPAE))
339 {
340 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
341 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
342
343 if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw2]))
344 {
345 X86PTEPAE GstPte;
346# ifdef IN_RING3
347 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
348# else
349 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
350# endif
351 AssertRC(rc);
352 Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK));
353 pgmPoolTracDerefGCPhysHint(pPool, pPage,
354 PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]),
355 GstPte.u & X86_PTE_PAE_PG_MASK,
356 iShw2);
357 PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw2], 0);
358 }
359 }
360 break;
361 }
362
363 case PGMPOOLKIND_32BIT_PD:
364 {
365 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
366 const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
367
368 LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
369 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
370# ifndef IN_RING0
371 if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
372 {
373 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
374 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
375 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
376 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
377 break;
378 }
379# endif /* !IN_RING0 */
380# ifndef IN_RING0
381 else
382# endif /* !IN_RING0 */
383 {
384 if (uShw.pPD->a[iShw].n.u1Present)
385 {
386 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
387 pgmPoolFree(pVM,
388 uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
389 pPage->idx,
390 iShw);
391 ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
392 }
393 }
394 /* paranoia / a bit assumptive. */
395 if ( (off & 3)
396 && (off & 3) + cbWrite > sizeof(X86PTE))
397 {
398 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
399 if ( iShw2 != iShw
400 && iShw2 < RT_ELEMENTS(uShw.pPD->a))
401 {
402# ifndef IN_RING0
403 if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
404 {
405 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
406 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
407 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
408 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
409 break;
410 }
411# endif /* !IN_RING0 */
412# ifndef IN_RING0
413 else
414# endif /* !IN_RING0 */
415 {
416 if (uShw.pPD->a[iShw2].n.u1Present)
417 {
418 LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
419 pgmPoolFree(pVM,
420 uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
421 pPage->idx,
422 iShw2);
423 ASMAtomicWriteU32(&uShw.pPD->a[iShw2].u, 0);
424 }
425 }
426 }
427 }
428#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
429 if ( uShw.pPD->a[iShw].n.u1Present
430 && !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
431 {
432 LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
433# ifdef IN_RC /* TLB load - we're pushing things a bit... */
434 ASMProbeReadByte(pvAddress);
435# endif
436 pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
437 ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
438 }
439#endif
440 break;
441 }
442
443 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
444 {
445 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
446 const unsigned iShw = off / sizeof(X86PDEPAE);
447 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
448#ifndef IN_RING0
449 if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
450 {
451 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
452 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
453 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
454 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
455 break;
456 }
457#endif /* !IN_RING0 */
458 /*
459 * Causes trouble when the guest uses a PDE to refer to the whole page table level
460 * structure. (Invalidate here; faults later on when it tries to change the page
461 * table entries -> recheck; probably only applies to the RC case.)
462 */
463# ifndef IN_RING0
464 else
465# endif /* !IN_RING0 */
466 {
467 if (uShw.pPDPae->a[iShw].n.u1Present)
468 {
469 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
470 pgmPoolFree(pVM,
471 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
472 pPage->idx,
473 iShw);
474 ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
475 }
476 }
477 /* paranoia / a bit assumptive. */
478 if ( (off & 7)
479 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
480 {
481 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
482 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
483
484#ifndef IN_RING0
485 if ( iShw2 != iShw
486 && uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
487 {
488 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
489 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
490 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
491 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
492 break;
493 }
494#endif /* !IN_RING0 */
495# ifndef IN_RING0
496 else
497# endif /* !IN_RING0 */
498 if (uShw.pPDPae->a[iShw2].n.u1Present)
499 {
500 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
501 pgmPoolFree(pVM,
502 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
503 pPage->idx,
504 iShw2);
505 ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
506 }
507 }
508 break;
509 }
510
511 case PGMPOOLKIND_PAE_PDPT:
512 {
513 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
514 /*
515 * Hopefully this doesn't happen very often:
516 * - touching unused parts of the page
517 * - messing with the bits of pd pointers without changing the physical address
518 */
519 /* PDPT roots are not page aligned; 32 byte only! */
520 const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
521
522 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
523 const unsigned iShw = offPdpt / sizeof(X86PDPE);
524 if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
525 {
526# ifndef IN_RING0
527 if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
528 {
529 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
530 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
531 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
532 LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
533 break;
534 }
535# endif /* !IN_RING0 */
536# ifndef IN_RING0
537 else
538# endif /* !IN_RING0 */
539 if (uShw.pPDPT->a[iShw].n.u1Present)
540 {
541 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
542 pgmPoolFree(pVM,
543 uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
544 pPage->idx,
545 iShw);
546 ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
547 }
548
549 /* paranoia / a bit assumptive. */
550 if ( (offPdpt & 7)
551 && (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
552 {
553 const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
554 if ( iShw2 != iShw
555 && iShw2 < X86_PG_PAE_PDPE_ENTRIES)
556 {
557# ifndef IN_RING0
558 if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
559 {
560 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
561 STAM_COUNTER_INC(&(pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZGuestCR3WriteConflict));
562 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
563 LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
564 break;
565 }
566# endif /* !IN_RING0 */
567# ifndef IN_RING0
568 else
569# endif /* !IN_RING0 */
570 if (uShw.pPDPT->a[iShw2].n.u1Present)
571 {
572 LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
573 pgmPoolFree(pVM,
574 uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
575 pPage->idx,
576 iShw2);
577 ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
578 }
579 }
580 }
581 }
582 break;
583 }
584
585#ifndef IN_RC
586 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
587 {
588 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
589 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
590 const unsigned iShw = off / sizeof(X86PDEPAE);
591 Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
592 if (uShw.pPDPae->a[iShw].n.u1Present)
593 {
594 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
595 pgmPoolFree(pVM,
596 uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
597 pPage->idx,
598 iShw);
599 ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
600 }
601 /* paranoia / a bit assumptive. */
602 if ( (off & 7)
603 && (off & 7) + cbWrite > sizeof(X86PDEPAE))
604 {
605 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
606 AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
607
608 Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
609 if (uShw.pPDPae->a[iShw2].n.u1Present)
610 {
611 LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
612 pgmPoolFree(pVM,
613 uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
614 pPage->idx,
615 iShw2);
616 ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
617 }
618 }
619 break;
620 }
621
622 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
623 {
624 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
625 /*
626 * Hopefully this doesn't happen very often:
627 * - messing with the bits of pd pointers without changing the physical address
628 */
629 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
630 const unsigned iShw = off / sizeof(X86PDPE);
631 if (uShw.pPDPT->a[iShw].n.u1Present)
632 {
633 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
634 pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
635 ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
636 }
637 /* paranoia / a bit assumptive. */
638 if ( (off & 7)
639 && (off & 7) + cbWrite > sizeof(X86PDPE))
640 {
641 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
642 if (uShw.pPDPT->a[iShw2].n.u1Present)
643 {
644 LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
645 pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
646 ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
647 }
648 }
649 break;
650 }
651
652 case PGMPOOLKIND_64BIT_PML4:
653 {
654 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
655 /*
656 * Hopefully this doesn't happen very often:
657 * - messing with the bits of pd pointers without changing the physical address
658 */
659 uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
660 const unsigned iShw = off / sizeof(X86PDPE);
661 if (uShw.pPML4->a[iShw].n.u1Present)
662 {
663 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
664 pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
665 ASMAtomicWriteU64(&uShw.pPML4->a[iShw].u, 0);
666 }
667 /* paranoia / a bit assumptive. */
668 if ( (off & 7)
669 && (off & 7) + cbWrite > sizeof(X86PDPE))
670 {
671 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
672 if (uShw.pPML4->a[iShw2].n.u1Present)
673 {
674 LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
675 pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
676 ASMAtomicWriteU64(&uShw.pPML4->a[iShw2].u, 0);
677 }
678 }
679 break;
680 }
681#endif /* IN_RING0 */
682
683 default:
684 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
685 }
686 PGM_DYNMAP_UNUSED_HINT_VM(pVM, uShw.pv);
687
688 /* next */
689 if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
690 return;
691 pPage = &pPool->aPages[pPage->iMonitoredNext];
692 }
693}
694
695# ifndef IN_RING3
696/**
697 * Checks if a access could be a fork operation in progress.
698 *
699 * Meaning, that the guest is setting up the parent process for Copy-On-Write.
700 *
701 * @returns true if it's likly that we're forking, otherwise false.
702 * @param pPool The pool.
703 * @param pDis The disassembled instruction.
704 * @param offFault The access offset.
705 */
706DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
707{
708 /*
709 * i386 linux is using btr to clear X86_PTE_RW.
710 * The functions involved are (2.6.16 source inspection):
711 * clear_bit
712 * ptep_set_wrprotect
713 * copy_one_pte
714 * copy_pte_range
715 * copy_pmd_range
716 * copy_pud_range
717 * copy_page_range
718 * dup_mmap
719 * dup_mm
720 * copy_mm
721 * copy_process
722 * do_fork
723 */
724 if ( pDis->pCurInstr->opcode == OP_BTR
725 && !(offFault & 4)
726 /** @todo Validate that the bit index is X86_PTE_RW. */
727 )
728 {
729 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
730 return true;
731 }
732 return false;
733}
734
735
736/**
737 * Determine whether the page is likely to have been reused.
738 *
739 * @returns true if we consider the page as being reused for a different purpose.
740 * @returns false if we consider it to still be a paging page.
741 * @param pVM VM Handle.
742 * @param pVCpu VMCPU Handle.
743 * @param pRegFrame Trap register frame.
744 * @param pDis The disassembly info for the faulting instruction.
745 * @param pvFault The fault address.
746 *
747 * @remark The REP prefix check is left to the caller because of STOSD/W.
748 */
749DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault)
750{
751#ifndef IN_RC
752 /** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
753 if ( HWACCMHasPendingIrq(pVM)
754 && (pRegFrame->rsp - pvFault) < 32)
755 {
756 /* Fault caused by stack writes while trying to inject an interrupt event. */
757 Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
758 return true;
759 }
760#else
761 NOREF(pVM); NOREF(pvFault);
762#endif
763
764 LogFlow(("Reused instr %RGv %d at %RGv param1.flags=%x param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->opcode, pvFault, pDis->param1.flags, pDis->param1.base.reg_gen));
765
766 /* Non-supervisor mode write means it's used for something else. */
767 if (CPUMGetGuestCPL(pVCpu, pRegFrame) != 0)
768 return true;
769
770 switch (pDis->pCurInstr->opcode)
771 {
772 /* call implies the actual push of the return address faulted */
773 case OP_CALL:
774 Log4(("pgmPoolMonitorIsReused: CALL\n"));
775 return true;
776 case OP_PUSH:
777 Log4(("pgmPoolMonitorIsReused: PUSH\n"));
778 return true;
779 case OP_PUSHF:
780 Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
781 return true;
782 case OP_PUSHA:
783 Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
784 return true;
785 case OP_FXSAVE:
786 Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
787 return true;
788 case OP_MOVNTI: /* solaris - block_zero_no_xmm */
789 Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
790 return true;
791 case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
792 Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
793 return true;
794 case OP_MOVSWD:
795 case OP_STOSWD:
796 if ( pDis->prefix == (PREFIX_REP|PREFIX_REX)
797 && pRegFrame->rcx >= 0x40
798 )
799 {
800 Assert(pDis->mode == CPUMODE_64BIT);
801
802 Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
803 return true;
804 }
805 return false;
806 }
807 if ( ( (pDis->param1.flags & USE_REG_GEN32)
808 || (pDis->param1.flags & USE_REG_GEN64))
809 && (pDis->param1.base.reg_gen == USE_REG_ESP))
810 {
811 Log4(("pgmPoolMonitorIsReused: ESP\n"));
812 return true;
813 }
814
815 return false;
816}
817
818/**
819 * Flushes the page being accessed.
820 *
821 * @returns VBox status code suitable for scheduling.
822 * @param pVM The VM handle.
823 * @param pVCpu The VMCPU handle.
824 * @param pPool The pool.
825 * @param pPage The pool page (head).
826 * @param pDis The disassembly of the write instruction.
827 * @param pRegFrame The trap register frame.
828 * @param GCPhysFault The fault address as guest physical address.
829 * @param pvFault The fault address.
830 * @todo VBOXSTRICTRC
831 */
832static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
833 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
834{
835 /*
836 * First, do the flushing.
837 */
838 int rc = pgmPoolMonitorChainFlush(pPool, pPage);
839
840 /*
841 * Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
842 * Must do this in raw mode (!); XP boot will fail otherwise.
843 */
844 uint32_t cbWritten;
845 VBOXSTRICTRC rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL, &cbWritten);
846 if (RT_SUCCESS(rc2))
847 {
848 pRegFrame->rip += pDis->opsize;
849 AssertMsg(rc2 == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc2))); /* ASSUMES no complicated stuff here. */
850 }
851 else if (rc2 == VERR_EM_INTERPRETER)
852 {
853#ifdef IN_RC
854 if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
855 {
856 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
857 pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
858 rc = VINF_SUCCESS;
859 STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
860 }
861 else
862#endif
863 {
864 rc = VINF_EM_RAW_EMULATE_INSTR;
865 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
866 }
867 }
868 else
869 rc = VBOXSTRICTRC_VAL(rc2);
870
871 LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
872 return rc;
873}
874
875/**
876 * Handles the STOSD write accesses.
877 *
878 * @returns VBox status code suitable for scheduling.
879 * @param pVM The VM handle.
880 * @param pPool The pool.
881 * @param pPage The pool page (head).
882 * @param pDis The disassembly of the write instruction.
883 * @param pRegFrame The trap register frame.
884 * @param GCPhysFault The fault address as guest physical address.
885 * @param pvFault The fault address.
886 */
887DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
888 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
889{
890 unsigned uIncrement = pDis->param1.size;
891
892 Assert(pDis->mode == CPUMODE_32BIT || pDis->mode == CPUMODE_64BIT);
893 Assert(pRegFrame->rcx <= 0x20);
894
895#ifdef VBOX_STRICT
896 if (pDis->opmode == CPUMODE_32BIT)
897 Assert(uIncrement == 4);
898 else
899 Assert(uIncrement == 8);
900#endif
901
902 Log3(("pgmPoolAccessHandlerSTOSD\n"));
903
904 /*
905 * Increment the modification counter and insert it into the list
906 * of modified pages the first time.
907 */
908 if (!pPage->cModifications++)
909 pgmPoolMonitorModifiedInsert(pPool, pPage);
910
911 /*
912 * Execute REP STOSD.
913 *
914 * This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
915 * write situation, meaning that it's safe to write here.
916 */
917 PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
918 RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
919 while (pRegFrame->rcx)
920 {
921#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
922 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
923 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
924 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
925#else
926 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, uIncrement);
927#endif
928#ifdef IN_RC
929 *(uint32_t *)(uintptr_t)pu32 = pRegFrame->eax;
930#else
931 PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
932#endif
933 pu32 += uIncrement;
934 GCPhysFault += uIncrement;
935 pRegFrame->rdi += uIncrement;
936 pRegFrame->rcx--;
937 }
938 pRegFrame->rip += pDis->opsize;
939
940 LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
941 return VINF_SUCCESS;
942}
943
944
945/**
946 * Handles the simple write accesses.
947 *
948 * @returns VBox status code suitable for scheduling.
949 * @param pVM The VM handle.
950 * @param pVCpu The VMCPU handle.
951 * @param pPool The pool.
952 * @param pPage The pool page (head).
953 * @param pDis The disassembly of the write instruction.
954 * @param pRegFrame The trap register frame.
955 * @param GCPhysFault The fault address as guest physical address.
956 * @param pvFault The fault address.
957 * @param pfReused Reused state (out)
958 */
959DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
960 PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
961{
962 Log3(("pgmPoolAccessHandlerSimple\n"));
963 /*
964 * Increment the modification counter and insert it into the list
965 * of modified pages the first time.
966 */
967 if (!pPage->cModifications++)
968 pgmPoolMonitorModifiedInsert(pPool, pPage);
969
970 /*
971 * Clear all the pages. ASSUMES that pvFault is readable.
972 */
973#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
974 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
975 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
976 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
977#else
978 pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, DISGetParamSize(pDis, &pDis->param1));
979#endif
980
981 /*
982 * Interpret the instruction.
983 */
984 uint32_t cb;
985 VBOXSTRICTRC rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL, &cb);
986 if (RT_SUCCESS(rc))
987 {
988 pRegFrame->rip += pDis->opsize;
989 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); /* ASSUMES no complicated stuff here. */
990 }
991 else if (rc == VERR_EM_INTERPRETER)
992 {
993 LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
994 pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode));
995 rc = VINF_EM_RAW_EMULATE_INSTR;
996 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
997 }
998
999#if 0 /* experimental code */
1000 if (rc == VINF_SUCCESS)
1001 {
1002 switch (pPage->enmKind)
1003 {
1004 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1005 {
1006 X86PTEPAE GstPte;
1007 int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
1008 AssertRC(rc);
1009
1010 /* Check the new value written by the guest. If present and with a bogus physical address, then
1011 * it's fairly safe to assume the guest is reusing the PT.
1012 */
1013 if (GstPte.n.u1Present)
1014 {
1015 RTHCPHYS HCPhys = -1;
1016 int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
1017 if (rc != VINF_SUCCESS)
1018 {
1019 *pfReused = true;
1020 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1021 }
1022 }
1023 break;
1024 }
1025 }
1026 }
1027#endif
1028
1029 LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", VBOXSTRICTRC_VAL(rc), cb));
1030 return VBOXSTRICTRC_VAL(rc);
1031}
1032
1033/**
1034 * \#PF Handler callback for PT write accesses.
1035 *
1036 * @returns VBox status code (appropriate for GC return).
1037 * @param pVM VM Handle.
1038 * @param uErrorCode CPU Error code.
1039 * @param pRegFrame Trap register frame.
1040 * NULL on DMA and other non CPU access.
1041 * @param pvFault The fault address (cr2).
1042 * @param GCPhysFault The GC physical address corresponding to pvFault.
1043 * @param pvUser User argument.
1044 */
1045DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1046{
1047 STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1048 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1049 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1050 PVMCPU pVCpu = VMMGetCpu(pVM);
1051 unsigned cMaxModifications;
1052 bool fForcedFlush = false;
1053
1054 LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1055
1056 pgmLock(pVM);
1057 if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1058 {
1059 /* Pool page changed while we were waiting for the lock; ignore. */
1060 Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1061 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1062 pgmUnlock(pVM);
1063 return VINF_SUCCESS;
1064 }
1065#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1066 if (pPage->fDirty)
1067 {
1068 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH));
1069 pgmUnlock(pVM);
1070 return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
1071 }
1072#endif
1073
1074#if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
1075 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1076 {
1077 void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1078 void *pvGst;
1079 int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1080 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1081 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1082 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1083 }
1084#endif
1085
1086 /*
1087 * Disassemble the faulting instruction.
1088 */
1089 PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1090 int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, pDis, NULL);
1091 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1092 {
1093 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1094 pgmUnlock(pVM);
1095 return rc;
1096 }
1097
1098 Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1099
1100 /*
1101 * We should ALWAYS have the list head as user parameter. This
1102 * is because we use that page to record the changes.
1103 */
1104 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1105
1106#ifdef IN_RING0
1107 /* Maximum nr of modifications depends on the page type. */
1108 if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1109 cMaxModifications = 4;
1110 else
1111 cMaxModifications = 24;
1112#else
1113 cMaxModifications = 48;
1114#endif
1115
1116 /*
1117 * Incremental page table updates should weigh more than random ones.
1118 * (Only applies when started from offset 0)
1119 */
1120 pVCpu->pgm.s.cPoolAccessHandler++;
1121 if ( pPage->pvLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1122 && pPage->pvLastAccessHandlerRip < pRegFrame->rip + 0x40
1123 && pvFault == (pPage->pvLastAccessHandlerFault + pDis->param1.size)
1124 && pVCpu->pgm.s.cPoolAccessHandler == (pPage->cLastAccessHandlerCount + 1))
1125 {
1126 Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1127 Assert(pPage->cModifications < 32000);
1128 pPage->cModifications = pPage->cModifications * 2;
1129 pPage->pvLastAccessHandlerFault = pvFault;
1130 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1131 if (pPage->cModifications >= cMaxModifications)
1132 {
1133 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushReinit));
1134 fForcedFlush = true;
1135 }
1136 }
1137
1138 if (pPage->cModifications >= cMaxModifications)
1139 Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(&pVM->pgm.s, pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1140
1141 /*
1142 * Check if it's worth dealing with.
1143 */
1144 bool fReused = false;
1145 bool fNotReusedNotForking = false;
1146 if ( ( pPage->cModifications < cMaxModifications /** @todo #define */ /** @todo need to check that it's not mapping EIP. */ /** @todo adjust this! */
1147 || pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1148 )
1149 && !(fReused = pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault))
1150 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1151 {
1152 /*
1153 * Simple instructions, no REP prefix.
1154 */
1155 if (!(pDis->prefix & (PREFIX_REP | PREFIX_REPNE)))
1156 {
1157 rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1158 if (fReused)
1159 goto flushPage;
1160
1161 /* A mov instruction to change the first page table entry will be remembered so we can detect
1162 * full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1163 */
1164 if ( rc == VINF_SUCCESS
1165 && !pPage->cLocked /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
1166 && pDis->pCurInstr->opcode == OP_MOV
1167 && (pvFault & PAGE_OFFSET_MASK) == 0)
1168 {
1169 pPage->pvLastAccessHandlerFault = pvFault;
1170 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1171 pPage->pvLastAccessHandlerRip = pRegFrame->rip;
1172 /* Make sure we don't kick out a page too quickly. */
1173 if (pPage->cModifications > 8)
1174 pPage->cModifications = 2;
1175 }
1176 else
1177 if (pPage->pvLastAccessHandlerFault == pvFault)
1178 {
1179 /* ignore the 2nd write to this page table entry. */
1180 pPage->cLastAccessHandlerCount = pVCpu->pgm.s.cPoolAccessHandler;
1181 }
1182 else
1183 {
1184 pPage->pvLastAccessHandlerFault = 0;
1185 pPage->pvLastAccessHandlerRip = 0;
1186 }
1187
1188 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1189 pgmUnlock(pVM);
1190 return rc;
1191 }
1192
1193 /*
1194 * Windows is frequently doing small memset() operations (netio test 4k+).
1195 * We have to deal with these or we'll kill the cache and performance.
1196 */
1197 if ( pDis->pCurInstr->opcode == OP_STOSWD
1198 && !pRegFrame->eflags.Bits.u1DF
1199 && pDis->opmode == pDis->mode
1200 && pDis->addrmode == pDis->mode)
1201 {
1202 bool fValidStosd = false;
1203
1204 if ( pDis->mode == CPUMODE_32BIT
1205 && pDis->prefix == PREFIX_REP
1206 && pRegFrame->ecx <= 0x20
1207 && pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1208 && !((uintptr_t)pvFault & 3)
1209 && (pRegFrame->eax == 0 || pRegFrame->eax == 0x80) /* the two values observed. */
1210 )
1211 {
1212 fValidStosd = true;
1213 pRegFrame->rcx &= 0xffffffff; /* paranoia */
1214 }
1215 else
1216 if ( pDis->mode == CPUMODE_64BIT
1217 && pDis->prefix == (PREFIX_REP | PREFIX_REX)
1218 && pRegFrame->rcx <= 0x20
1219 && pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1220 && !((uintptr_t)pvFault & 7)
1221 && (pRegFrame->rax == 0 || pRegFrame->rax == 0x80) /* the two values observed. */
1222 )
1223 {
1224 fValidStosd = true;
1225 }
1226
1227 if (fValidStosd)
1228 {
1229 rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1230 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1231 pgmUnlock(pVM);
1232 return rc;
1233 }
1234 }
1235
1236 /* REP prefix, don't bother. */
1237 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1238 Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1239 pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->opcode, pDis->prefix));
1240 fNotReusedNotForking = true;
1241 }
1242
1243#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1244 /* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1245 * leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1246 */
1247 if ( pPage->cModifications >= cMaxModifications
1248 && !fForcedFlush
1249 && pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1250 && ( fNotReusedNotForking
1251 || ( !pgmPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault)
1252 && !pgmPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1253 )
1254 )
1255 {
1256 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
1257 Assert(pPage->fDirty == false);
1258
1259 /* Flush any monitored duplicates as we will disable write protection. */
1260 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1261 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1262 {
1263 PPGMPOOLPAGE pPageHead = pPage;
1264
1265 /* Find the monitor head. */
1266 while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1267 pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1268
1269 while (pPageHead)
1270 {
1271 unsigned idxNext = pPageHead->iMonitoredNext;
1272
1273 if (pPageHead != pPage)
1274 {
1275 STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1276 Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1277 int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1278 AssertRC(rc2);
1279 }
1280
1281 if (idxNext == NIL_PGMPOOL_IDX)
1282 break;
1283
1284 pPageHead = &pPool->aPages[idxNext];
1285 }
1286 }
1287
1288 /* The flushing above might fail for locked pages, so double check. */
1289 if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1290 && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1291 {
1292 pgmPoolAddDirtyPage(pVM, pPool, pPage);
1293
1294 /* Temporarily allow write access to the page table again. */
1295 rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys, pPage->GCPhys);
1296 if (rc == VINF_SUCCESS)
1297 {
1298 rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
1299 AssertMsg(rc == VINF_SUCCESS
1300 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1301 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1302 || rc == VERR_PAGE_NOT_PRESENT,
1303 ("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1304
1305 pPage->pvDirtyFault = pvFault;
1306
1307 STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1308 pgmUnlock(pVM);
1309 return rc;
1310 }
1311 }
1312 }
1313#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1314
1315 STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FlushModOverflow));
1316flushPage:
1317 /*
1318 * Not worth it, so flush it.
1319 *
1320 * If we considered it to be reused, don't go back to ring-3
1321 * to emulate failed instructions since we usually cannot
1322 * interpret then. This may be a bit risky, in which case
1323 * the reuse detection must be fixed.
1324 */
1325 rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1326 if ( rc == VINF_EM_RAW_EMULATE_INSTR
1327 && fReused)
1328 {
1329 /* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1330 if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1331 rc = VINF_SUCCESS; /* safe to restart the instruction. */
1332 }
1333 STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1334 pgmUnlock(pVM);
1335 return rc;
1336}
1337
1338# endif /* !IN_RING3 */
1339
1340# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1341
1342# ifdef VBOX_STRICT
1343/**
1344 * Check references to guest physical memory in a PAE / PAE page table.
1345 *
1346 * @param pPool The pool.
1347 * @param pPage The page.
1348 * @param pShwPT The shadow page table (mapping of the page).
1349 * @param pGstPT The guest page table.
1350 */
1351static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
1352{
1353 unsigned cErrors = 0;
1354 int LastRc = -1; /* initialized to shut up gcc */
1355 unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1356 RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1357 PVM pVM = pPool->CTX_SUFF(pVM);
1358
1359#ifdef VBOX_STRICT
1360 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1361 AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1362#endif
1363 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1364 {
1365 if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1366 {
1367 RTHCPHYS HCPhys = NIL_RTHCPHYS;
1368 int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1369 if ( rc != VINF_SUCCESS
1370 || PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1371 {
1372 Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1373 LastPTE = i;
1374 LastRc = rc;
1375 LastHCPhys = HCPhys;
1376 cErrors++;
1377
1378 RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1379 rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1380 AssertRC(rc);
1381
1382 for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1383 {
1384 PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1385
1386 if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1387 {
1388 PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1389
1390 for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1391 {
1392 if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1393 && PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1394 {
1395 Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1396 }
1397 }
1398
1399 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1400 }
1401 }
1402 }
1403 }
1404 }
1405 AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1406}
1407# endif /* VBOX_STRICT */
1408
1409/**
1410 * Clear references to guest physical memory in a PAE / PAE page table.
1411 *
1412 * @returns nr of changed PTEs
1413 * @param pPool The pool.
1414 * @param pPage The page.
1415 * @param pShwPT The shadow page table (mapping of the page).
1416 * @param pGstPT The guest page table.
1417 * @param pOldGstPT The old cached guest page table.
1418 * @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1419 * @param pfFlush Flush reused page table (out)
1420 */
1421DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT,
1422 PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1423{
1424 unsigned cChanged = 0;
1425
1426#ifdef VBOX_STRICT
1427 for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1428 AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1429#endif
1430 *pfFlush = false;
1431
1432 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1433 {
1434 /* Check the new value written by the guest. If present and with a bogus physical address, then
1435 * it's fairly safe to assume the guest is reusing the PT.
1436 */
1437 if ( fAllowRemoval
1438 && pGstPT->a[i].n.u1Present)
1439 {
1440 if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1441 {
1442 *pfFlush = true;
1443 return ++cChanged;
1444 }
1445 }
1446 if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1447 {
1448 /* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1449 if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1450 {
1451#ifdef VBOX_STRICT
1452 RTHCPHYS HCPhys = NIL_RTGCPHYS;
1453 int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1454 AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1455#endif
1456 uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1457 bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1458 uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P | X86_PTE_US | X86_PTE_A | X86_PTE_D | X86_PTE_G | X86_PTE_PAE_NX);
1459 bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1460
1461 if ( uHostAttr == uGuestAttr
1462 && fHostRW <= fGuestRW)
1463 continue;
1464 }
1465 cChanged++;
1466 /* Something was changed, so flush it. */
1467 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1468 i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1469 pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
1470 PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1471 }
1472 }
1473 return cChanged;
1474}
1475
1476
1477/**
1478 * Flush a dirty page
1479 *
1480 * @param pVM VM Handle.
1481 * @param pPool The pool.
1482 * @param idxSlot Dirty array slot index
1483 * @param fAllowRemoval Allow a reused page table to be removed
1484 */
1485static void pgmPoolFlushDirtyPage(PVM pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1486{
1487 PPGMPOOLPAGE pPage;
1488 unsigned idxPage;
1489
1490 Assert(idxSlot < RT_ELEMENTS(pPool->aDirtyPages));
1491 if (pPool->aDirtyPages[idxSlot].uIdx == NIL_PGMPOOL_IDX)
1492 return;
1493
1494 idxPage = pPool->aDirtyPages[idxSlot].uIdx;
1495 AssertRelease(idxPage != NIL_PGMPOOL_IDX);
1496 pPage = &pPool->aPages[idxPage];
1497 Assert(pPage->idx == idxPage);
1498 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1499
1500 AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1501 Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1502
1503#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
1504 PVMCPU pVCpu = VMMGetCpu(pVM);
1505 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
1506#endif
1507
1508 /* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1509 int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys);
1510 Assert(rc == VINF_SUCCESS);
1511 pPage->fDirty = false;
1512
1513#ifdef VBOX_STRICT
1514 uint64_t fFlags = 0;
1515 RTHCPHYS HCPhys;
1516 rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->pvDirtyFault, &fFlags, &HCPhys);
1517 AssertMsg( ( rc == VINF_SUCCESS
1518 && (!(fFlags & X86_PTE_RW) || HCPhys != pPage->Core.Key))
1519 /* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1520 || rc == VERR_PAGE_TABLE_NOT_PRESENT
1521 || rc == VERR_PAGE_NOT_PRESENT,
1522 ("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->pvDirtyFault, rc, fFlags));
1523#endif
1524
1525 /* Flush those PTEs that have changed. */
1526 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1527 void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1528 void *pvGst;
1529 rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1530 bool fFlush;
1531 unsigned cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst,
1532 (PCX86PTPAE)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1533 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1534 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1535 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1536 /* Note: we might want to consider keeping the dirty page active in case there were many changes. */
1537
1538 /* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1539 Assert(pPage->cModifications);
1540 if (cChanges < 4)
1541 pPage->cModifications = 1; /* must use > 0 here */
1542 else
1543 pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1544
1545 STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1546 if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages))
1547 pPool->idxFreeDirtyPage = idxSlot;
1548
1549 pPool->cDirtyPages--;
1550 pPool->aDirtyPages[idxSlot].uIdx = NIL_PGMPOOL_IDX;
1551 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1552 if (fFlush)
1553 {
1554 Assert(fAllowRemoval);
1555 Log(("Flush reused page table!\n"));
1556 pgmPoolFlushPage(pPool, pPage);
1557 STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1558 }
1559 else
1560 Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1561
1562#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
1563 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
1564#endif
1565}
1566
1567# ifndef IN_RING3
1568/**
1569 * Add a new dirty page
1570 *
1571 * @param pVM VM Handle.
1572 * @param pPool The pool.
1573 * @param pPage The page.
1574 */
1575void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1576{
1577 unsigned idxFree;
1578
1579 Assert(PGMIsLocked(pVM));
1580 AssertCompile(RT_ELEMENTS(pPool->aDirtyPages) == 8 || RT_ELEMENTS(pPool->aDirtyPages) == 16);
1581 Assert(!pPage->fDirty);
1582
1583 idxFree = pPool->idxFreeDirtyPage;
1584 Assert(idxFree < RT_ELEMENTS(pPool->aDirtyPages));
1585 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1586
1587 if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aDirtyPages))
1588 {
1589 STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1590 pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1591 }
1592 Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages));
1593 AssertMsg(pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1594
1595 Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1596
1597 /*
1598 * Make a copy of the guest page table as we require valid GCPhys addresses
1599 * when removing references to physical pages.
1600 * (The HCPhys linear lookup is *extremely* expensive!)
1601 */
1602 void *pvGst;
1603 int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1604 memcpy(&pPool->aDirtyPages[idxFree].aPage[0], pvGst, PAGE_SIZE);
1605#ifdef VBOX_STRICT
1606 void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1607 pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1608 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1609#endif
1610 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1611
1612 STAM_COUNTER_INC(&pPool->StatDirtyPage);
1613 pPage->fDirty = true;
1614 pPage->idxDirty = idxFree;
1615 pPool->aDirtyPages[idxFree].uIdx = pPage->idx;
1616 pPool->cDirtyPages++;
1617
1618 pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1619 if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages)
1620 && pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1621 {
1622 unsigned i;
1623 for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1624 {
1625 idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1626 if (pPool->aDirtyPages[idxFree].uIdx == NIL_PGMPOOL_IDX)
1627 {
1628 pPool->idxFreeDirtyPage = idxFree;
1629 break;
1630 }
1631 }
1632 Assert(i != RT_ELEMENTS(pPool->aDirtyPages));
1633 }
1634
1635 Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages) || pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX);
1636 return;
1637}
1638# endif /* !IN_RING3 */
1639
1640/**
1641 * Check if the specified page is dirty (not write monitored)
1642 *
1643 * @return dirty or not
1644 * @param pVM VM Handle.
1645 * @param GCPhys Guest physical address
1646 */
1647bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys)
1648{
1649 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1650 Assert(PGMIsLocked(pVM));
1651 if (!pPool->cDirtyPages)
1652 return false;
1653
1654 GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1655
1656 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1657 {
1658 if (pPool->aDirtyPages[i].uIdx != NIL_PGMPOOL_IDX)
1659 {
1660 PPGMPOOLPAGE pPage;
1661 unsigned idxPage = pPool->aDirtyPages[i].uIdx;
1662
1663 pPage = &pPool->aPages[idxPage];
1664 if (pPage->GCPhys == GCPhys)
1665 return true;
1666 }
1667 }
1668 return false;
1669}
1670
1671/**
1672 * Reset all dirty pages by reinstating page monitoring.
1673 *
1674 * @param pVM VM Handle.
1675 */
1676void pgmPoolResetDirtyPages(PVM pVM)
1677{
1678 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1679 Assert(PGMIsLocked(pVM));
1680 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1681
1682 if (!pPool->cDirtyPages)
1683 return;
1684
1685 Log(("pgmPoolResetDirtyPages\n"));
1686 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1687 pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1688
1689 pPool->idxFreeDirtyPage = 0;
1690 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1691 && pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1692 {
1693 unsigned i;
1694 for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1695 {
1696 if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
1697 {
1698 pPool->idxFreeDirtyPage = i;
1699 break;
1700 }
1701 }
1702 AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1703 }
1704
1705 Assert(pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx == NIL_PGMPOOL_IDX || pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages));
1706 return;
1707}
1708
1709/**
1710 * Invalidate the PT entry for the specified page
1711 *
1712 * @param pVM VM Handle.
1713 * @param GCPtrPage Guest page to invalidate
1714 */
1715void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage)
1716{
1717 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1718 Assert(PGMIsLocked(pVM));
1719 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1720
1721 if (!pPool->cDirtyPages)
1722 return;
1723
1724 Log(("pgmPoolResetDirtyPage %RGv\n", GCPtrPage));
1725 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1726 {
1727 }
1728}
1729
1730/**
1731 * Reset all dirty pages by reinstating page monitoring.
1732 *
1733 * @param pVM VM Handle.
1734 * @param GCPhysPT Physical address of the page table
1735 */
1736void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT)
1737{
1738 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1739 Assert(PGMIsLocked(pVM));
1740 Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1741 unsigned idxDirtyPage = RT_ELEMENTS(pPool->aDirtyPages);
1742
1743 if (!pPool->cDirtyPages)
1744 return;
1745
1746 GCPhysPT = GCPhysPT & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1747
1748 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1749 {
1750 if (pPool->aDirtyPages[i].uIdx != NIL_PGMPOOL_IDX)
1751 {
1752 unsigned idxPage = pPool->aDirtyPages[i].uIdx;
1753
1754 PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1755 if (pPage->GCPhys == GCPhysPT)
1756 {
1757 idxDirtyPage = i;
1758 break;
1759 }
1760 }
1761 }
1762
1763 if (idxDirtyPage != RT_ELEMENTS(pPool->aDirtyPages))
1764 {
1765 pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1766 if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1767 && pPool->aDirtyPages[pPool->idxFreeDirtyPage].uIdx != NIL_PGMPOOL_IDX)
1768 {
1769 unsigned i;
1770 for (i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1771 {
1772 if (pPool->aDirtyPages[i].uIdx == NIL_PGMPOOL_IDX)
1773 {
1774 pPool->idxFreeDirtyPage = i;
1775 break;
1776 }
1777 }
1778 AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1779 }
1780 }
1781}
1782
1783# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1784
1785/**
1786 * Inserts a page into the GCPhys hash table.
1787 *
1788 * @param pPool The pool.
1789 * @param pPage The page.
1790 */
1791DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1792{
1793 Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1794 Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1795 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1796 pPage->iNext = pPool->aiHash[iHash];
1797 pPool->aiHash[iHash] = pPage->idx;
1798}
1799
1800
1801/**
1802 * Removes a page from the GCPhys hash table.
1803 *
1804 * @param pPool The pool.
1805 * @param pPage The page.
1806 */
1807DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1808{
1809 Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1810 uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1811 if (pPool->aiHash[iHash] == pPage->idx)
1812 pPool->aiHash[iHash] = pPage->iNext;
1813 else
1814 {
1815 uint16_t iPrev = pPool->aiHash[iHash];
1816 for (;;)
1817 {
1818 const int16_t i = pPool->aPages[iPrev].iNext;
1819 if (i == pPage->idx)
1820 {
1821 pPool->aPages[iPrev].iNext = pPage->iNext;
1822 break;
1823 }
1824 if (i == NIL_PGMPOOL_IDX)
1825 {
1826 AssertReleaseMsgFailed(("GCPhys=%RGp idx=%d\n", pPage->GCPhys, pPage->idx));
1827 break;
1828 }
1829 iPrev = i;
1830 }
1831 }
1832 pPage->iNext = NIL_PGMPOOL_IDX;
1833}
1834
1835
1836/**
1837 * Frees up one cache page.
1838 *
1839 * @returns VBox status code.
1840 * @retval VINF_SUCCESS on success.
1841 * @param pPool The pool.
1842 * @param iUser The user index.
1843 */
1844static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1845{
1846#ifndef IN_RC
1847 const PVM pVM = pPool->CTX_SUFF(pVM);
1848#endif
1849 Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1850 STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1851
1852 /*
1853 * Select one page from the tail of the age list.
1854 */
1855 PPGMPOOLPAGE pPage;
1856 for (unsigned iLoop = 0; ; iLoop++)
1857 {
1858 uint16_t iToFree = pPool->iAgeTail;
1859 if (iToFree == iUser)
1860 iToFree = pPool->aPages[iToFree].iAgePrev;
1861/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1862 if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1863 {
1864 uint16_t i = pPool->aPages[iToFree].iAgePrev;
1865 for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1866 {
1867 if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1868 continue;
1869 iToFree = i;
1870 break;
1871 }
1872 }
1873*/
1874 Assert(iToFree != iUser);
1875 AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1876 pPage = &pPool->aPages[iToFree];
1877
1878 /*
1879 * Reject any attempts at flushing the currently active shadow CR3 mapping.
1880 * Call pgmPoolCacheUsed to move the page to the head of the age list.
1881 */
1882 if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1883 break;
1884 LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1885 pgmPoolCacheUsed(pPool, pPage);
1886 AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1887 }
1888
1889 /*
1890 * Found a usable page, flush it and return.
1891 */
1892 int rc = pgmPoolFlushPage(pPool, pPage);
1893 /* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
1894 /* todo: find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
1895 if (rc == VINF_SUCCESS)
1896 PGM_INVL_ALL_VCPU_TLBS(pVM);
1897 return rc;
1898}
1899
1900
1901/**
1902 * Checks if a kind mismatch is really a page being reused
1903 * or if it's just normal remappings.
1904 *
1905 * @returns true if reused and the cached page (enmKind1) should be flushed
1906 * @returns false if not reused.
1907 * @param enmKind1 The kind of the cached page.
1908 * @param enmKind2 The kind of the requested page.
1909 */
1910static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1911{
1912 switch (enmKind1)
1913 {
1914 /*
1915 * Never reuse them. There is no remapping in non-paging mode.
1916 */
1917 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1918 case PGMPOOLKIND_32BIT_PD_PHYS:
1919 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1920 case PGMPOOLKIND_PAE_PD_PHYS:
1921 case PGMPOOLKIND_PAE_PDPT_PHYS:
1922 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1923 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1924 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1925 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1926 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1927 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1928 return false;
1929
1930 /*
1931 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1932 */
1933 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1934 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1935 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1936 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1937 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1938 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1939 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1940 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1941 case PGMPOOLKIND_32BIT_PD:
1942 case PGMPOOLKIND_PAE_PDPT:
1943 switch (enmKind2)
1944 {
1945 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1946 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1947 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1948 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1949 case PGMPOOLKIND_64BIT_PML4:
1950 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1951 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1952 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1953 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1954 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1955 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1956 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1957 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1958 return true;
1959 default:
1960 return false;
1961 }
1962
1963 /*
1964 * It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1965 */
1966 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1967 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1968 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1969 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1970 case PGMPOOLKIND_64BIT_PML4:
1971 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1972 switch (enmKind2)
1973 {
1974 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1975 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1976 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1977 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1978 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1979 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1980 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1981 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1982 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1983 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1984 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1985 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1986 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1987 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1988 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1989 return true;
1990 default:
1991 return false;
1992 }
1993
1994 /*
1995 * These cannot be flushed, and it's common to reuse the PDs as PTs.
1996 */
1997 case PGMPOOLKIND_ROOT_NESTED:
1998 return false;
1999
2000 default:
2001 AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
2002 }
2003}
2004
2005
2006/**
2007 * Attempts to satisfy a pgmPoolAlloc request from the cache.
2008 *
2009 * @returns VBox status code.
2010 * @retval VINF_PGM_CACHED_PAGE on success.
2011 * @retval VERR_FILE_NOT_FOUND if not found.
2012 * @param pPool The pool.
2013 * @param GCPhys The GC physical address of the page we're gonna shadow.
2014 * @param enmKind The kind of mapping.
2015 * @param enmAccess Access type for the mapping (only relevant for big pages)
2016 * @param iUser The shadow page pool index of the user table.
2017 * @param iUserTable The index into the user table (shadowed).
2018 * @param ppPage Where to store the pointer to the page.
2019 */
2020static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2021{
2022#ifndef IN_RC
2023 const PVM pVM = pPool->CTX_SUFF(pVM);
2024#endif
2025 /*
2026 * Look up the GCPhys in the hash.
2027 */
2028 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2029 Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%d iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2030 if (i != NIL_PGMPOOL_IDX)
2031 {
2032 do
2033 {
2034 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2035 Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2036 if (pPage->GCPhys == GCPhys)
2037 {
2038 if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2039 && (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
2040 {
2041 /* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2042 * doesn't flush it in case there are no more free use records.
2043 */
2044 pgmPoolCacheUsed(pPool, pPage);
2045
2046 int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2047 if (RT_SUCCESS(rc))
2048 {
2049 Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2050 *ppPage = pPage;
2051 if (pPage->cModifications)
2052 pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2053 STAM_COUNTER_INC(&pPool->StatCacheHits);
2054 return VINF_PGM_CACHED_PAGE;
2055 }
2056 return rc;
2057 }
2058
2059 if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2060 {
2061 /*
2062 * The kind is different. In some cases we should now flush the page
2063 * as it has been reused, but in most cases this is normal remapping
2064 * of PDs as PT or big pages using the GCPhys field in a slightly
2065 * different way than the other kinds.
2066 */
2067 if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2068 {
2069 STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2070 pgmPoolFlushPage(pPool, pPage);
2071 break;
2072 }
2073 }
2074 }
2075
2076 /* next */
2077 i = pPage->iNext;
2078 } while (i != NIL_PGMPOOL_IDX);
2079 }
2080
2081 Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2082 STAM_COUNTER_INC(&pPool->StatCacheMisses);
2083 return VERR_FILE_NOT_FOUND;
2084}
2085
2086
2087/**
2088 * Inserts a page into the cache.
2089 *
2090 * @param pPool The pool.
2091 * @param pPage The cached page.
2092 * @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2093 */
2094static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2095{
2096 /*
2097 * Insert into the GCPhys hash if the page is fit for that.
2098 */
2099 Assert(!pPage->fCached);
2100 if (fCanBeCached)
2101 {
2102 pPage->fCached = true;
2103 pgmPoolHashInsert(pPool, pPage);
2104 Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2105 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2106 STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2107 }
2108 else
2109 {
2110 Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2111 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2112 STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2113 }
2114
2115 /*
2116 * Insert at the head of the age list.
2117 */
2118 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2119 pPage->iAgeNext = pPool->iAgeHead;
2120 if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2121 pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2122 else
2123 pPool->iAgeTail = pPage->idx;
2124 pPool->iAgeHead = pPage->idx;
2125}
2126
2127
2128/**
2129 * Flushes a cached page.
2130 *
2131 * @param pPool The pool.
2132 * @param pPage The cached page.
2133 */
2134static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2135{
2136 Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2137
2138 /*
2139 * Remove the page from the hash.
2140 */
2141 if (pPage->fCached)
2142 {
2143 pPage->fCached = false;
2144 pgmPoolHashRemove(pPool, pPage);
2145 }
2146 else
2147 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2148
2149 /*
2150 * Remove it from the age list.
2151 */
2152 if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2153 pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2154 else
2155 pPool->iAgeTail = pPage->iAgePrev;
2156 if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2157 pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2158 else
2159 pPool->iAgeHead = pPage->iAgeNext;
2160 pPage->iAgeNext = NIL_PGMPOOL_IDX;
2161 pPage->iAgePrev = NIL_PGMPOOL_IDX;
2162}
2163
2164
2165/**
2166 * Looks for pages sharing the monitor.
2167 *
2168 * @returns Pointer to the head page.
2169 * @returns NULL if not found.
2170 * @param pPool The Pool
2171 * @param pNewPage The page which is going to be monitored.
2172 */
2173static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2174{
2175 /*
2176 * Look up the GCPhys in the hash.
2177 */
2178 RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2179 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2180 if (i == NIL_PGMPOOL_IDX)
2181 return NULL;
2182 do
2183 {
2184 PPGMPOOLPAGE pPage = &pPool->aPages[i];
2185 if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2186 && pPage != pNewPage)
2187 {
2188 switch (pPage->enmKind)
2189 {
2190 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2191 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2192 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2193 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2194 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2195 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2196 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2197 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2198 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2199 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2200 case PGMPOOLKIND_64BIT_PML4:
2201 case PGMPOOLKIND_32BIT_PD:
2202 case PGMPOOLKIND_PAE_PDPT:
2203 {
2204 /* find the head */
2205 while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2206 {
2207 Assert(pPage->iMonitoredPrev != pPage->idx);
2208 pPage = &pPool->aPages[pPage->iMonitoredPrev];
2209 }
2210 return pPage;
2211 }
2212
2213 /* ignore, no monitoring. */
2214 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2215 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2216 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2217 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2218 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2219 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2220 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2221 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2222 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2223 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2224 case PGMPOOLKIND_ROOT_NESTED:
2225 case PGMPOOLKIND_PAE_PD_PHYS:
2226 case PGMPOOLKIND_PAE_PDPT_PHYS:
2227 case PGMPOOLKIND_32BIT_PD_PHYS:
2228 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2229 break;
2230 default:
2231 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2232 }
2233 }
2234
2235 /* next */
2236 i = pPage->iNext;
2237 } while (i != NIL_PGMPOOL_IDX);
2238 return NULL;
2239}
2240
2241
2242/**
2243 * Enabled write monitoring of a guest page.
2244 *
2245 * @returns VBox status code.
2246 * @retval VINF_SUCCESS on success.
2247 * @param pPool The pool.
2248 * @param pPage The cached page.
2249 */
2250static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2251{
2252 LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK));
2253
2254 /*
2255 * Filter out the relevant kinds.
2256 */
2257 switch (pPage->enmKind)
2258 {
2259 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2260 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2261 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2262 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2263 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2264 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2265 case PGMPOOLKIND_64BIT_PML4:
2266 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2267 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2268 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2269 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2270 case PGMPOOLKIND_32BIT_PD:
2271 case PGMPOOLKIND_PAE_PDPT:
2272 break;
2273
2274 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2275 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2276 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2277 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2278 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2279 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2280 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2281 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2282 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2283 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2284 case PGMPOOLKIND_ROOT_NESTED:
2285 /* Nothing to monitor here. */
2286 return VINF_SUCCESS;
2287
2288 case PGMPOOLKIND_32BIT_PD_PHYS:
2289 case PGMPOOLKIND_PAE_PDPT_PHYS:
2290 case PGMPOOLKIND_PAE_PD_PHYS:
2291 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2292 /* Nothing to monitor here. */
2293 return VINF_SUCCESS;
2294 default:
2295 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2296 }
2297
2298 /*
2299 * Install handler.
2300 */
2301 int rc;
2302 PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2303 if (pPageHead)
2304 {
2305 Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2306 Assert(pPageHead->iMonitoredPrev != pPage->idx);
2307
2308#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2309 if (pPageHead->fDirty)
2310 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirty, false /* do not remove */);
2311#endif
2312
2313 pPage->iMonitoredPrev = pPageHead->idx;
2314 pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2315 if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2316 pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2317 pPageHead->iMonitoredNext = pPage->idx;
2318 rc = VINF_SUCCESS;
2319 }
2320 else
2321 {
2322 Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2323 PVM pVM = pPool->CTX_SUFF(pVM);
2324 const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2325 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2326 GCPhysPage, GCPhysPage + PAGE_OFFSET_MASK,
2327 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
2328 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
2329 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
2330 pPool->pszAccessHandler);
2331 /** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2332 * the heap size should suffice. */
2333 AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2334 PVMCPU pVCpu = VMMGetCpu(pVM);
2335 AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
2336 }
2337 pPage->fMonitored = true;
2338 return rc;
2339}
2340
2341
2342/**
2343 * Disables write monitoring of a guest page.
2344 *
2345 * @returns VBox status code.
2346 * @retval VINF_SUCCESS on success.
2347 * @param pPool The pool.
2348 * @param pPage The cached page.
2349 */
2350static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2351{
2352 /*
2353 * Filter out the relevant kinds.
2354 */
2355 switch (pPage->enmKind)
2356 {
2357 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2358 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2359 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2360 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2361 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2362 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2363 case PGMPOOLKIND_64BIT_PML4:
2364 case PGMPOOLKIND_32BIT_PD:
2365 case PGMPOOLKIND_PAE_PDPT:
2366 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2367 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2368 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2369 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2370 break;
2371
2372 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2373 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2374 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2375 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2376 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2377 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2378 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2379 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2380 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2381 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2382 case PGMPOOLKIND_ROOT_NESTED:
2383 case PGMPOOLKIND_PAE_PD_PHYS:
2384 case PGMPOOLKIND_PAE_PDPT_PHYS:
2385 case PGMPOOLKIND_32BIT_PD_PHYS:
2386 /* Nothing to monitor here. */
2387 Assert(!pPage->fMonitored);
2388 return VINF_SUCCESS;
2389
2390 default:
2391 AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2392 }
2393 Assert(pPage->fMonitored);
2394
2395 /*
2396 * Remove the page from the monitored list or uninstall it if last.
2397 */
2398 const PVM pVM = pPool->CTX_SUFF(pVM);
2399 int rc;
2400 if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2401 || pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2402 {
2403 if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2404 {
2405 PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2406 pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2407 rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK,
2408 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
2409 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
2410 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
2411 pPool->pszAccessHandler);
2412 AssertFatalRCSuccess(rc);
2413 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2414 }
2415 else
2416 {
2417 pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2418 if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2419 {
2420 pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2421 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2422 }
2423 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2424 rc = VINF_SUCCESS;
2425 }
2426 }
2427 else
2428 {
2429 rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
2430 AssertFatalRC(rc);
2431 PVMCPU pVCpu = VMMGetCpu(pVM);
2432 AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2433 ("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2434 }
2435 pPage->fMonitored = false;
2436
2437 /*
2438 * Remove it from the list of modified pages (if in it).
2439 */
2440 pgmPoolMonitorModifiedRemove(pPool, pPage);
2441
2442 return rc;
2443}
2444
2445
2446/**
2447 * Inserts the page into the list of modified pages.
2448 *
2449 * @param pPool The pool.
2450 * @param pPage The page.
2451 */
2452void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2453{
2454 Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2455 AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2456 && pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2457 && pPool->iModifiedHead != pPage->idx,
2458 ("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2459 pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2460 pPool->iModifiedHead, pPool->cModifiedPages));
2461
2462 pPage->iModifiedNext = pPool->iModifiedHead;
2463 if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2464 pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2465 pPool->iModifiedHead = pPage->idx;
2466 pPool->cModifiedPages++;
2467#ifdef VBOX_WITH_STATISTICS
2468 if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2469 pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2470#endif
2471}
2472
2473
2474/**
2475 * Removes the page from the list of modified pages and resets the
2476 * moficiation counter.
2477 *
2478 * @param pPool The pool.
2479 * @param pPage The page which is believed to be in the list of modified pages.
2480 */
2481static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2482{
2483 Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2484 if (pPool->iModifiedHead == pPage->idx)
2485 {
2486 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2487 pPool->iModifiedHead = pPage->iModifiedNext;
2488 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2489 {
2490 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2491 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2492 }
2493 pPool->cModifiedPages--;
2494 }
2495 else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2496 {
2497 pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2498 if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2499 {
2500 pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2501 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2502 }
2503 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2504 pPool->cModifiedPages--;
2505 }
2506 else
2507 Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2508 pPage->cModifications = 0;
2509}
2510
2511
2512/**
2513 * Zaps the list of modified pages, resetting their modification counters in the process.
2514 *
2515 * @param pVM The VM handle.
2516 */
2517static void pgmPoolMonitorModifiedClearAll(PVM pVM)
2518{
2519 pgmLock(pVM);
2520 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2521 LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2522
2523 unsigned cPages = 0; NOREF(cPages);
2524
2525#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2526 pgmPoolResetDirtyPages(pVM);
2527#endif
2528
2529 uint16_t idx = pPool->iModifiedHead;
2530 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2531 while (idx != NIL_PGMPOOL_IDX)
2532 {
2533 PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2534 idx = pPage->iModifiedNext;
2535 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2536 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2537 pPage->cModifications = 0;
2538 Assert(++cPages);
2539 }
2540 AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2541 pPool->cModifiedPages = 0;
2542 pgmUnlock(pVM);
2543}
2544
2545
2546/**
2547 * Handle SyncCR3 pool tasks
2548 *
2549 * @returns VBox status code.
2550 * @retval VINF_SUCCESS if successfully added.
2551 * @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2552 * @param pVCpu The VMCPU handle.
2553 * @remark Should only be used when monitoring is available, thus placed in
2554 * the PGMPOOL_WITH_MONITORING #ifdef.
2555 */
2556int pgmPoolSyncCR3(PVMCPU pVCpu)
2557{
2558 PVM pVM = pVCpu->CTX_SUFF(pVM);
2559 LogFlow(("pgmPoolSyncCR3 fSyncFlags=%x\n", pVCpu->pgm.s.fSyncFlags));
2560
2561 /*
2562 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2563 * Occasionally we will have to clear all the shadow page tables because we wanted
2564 * to monitor a page which was mapped by too many shadowed page tables. This operation
2565 * sometimes refered to as a 'lightweight flush'.
2566 */
2567# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2568 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2569 pgmR3PoolClearAll(pVM, false /*fFlushRemTlb*/);
2570# else /* !IN_RING3 */
2571 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2572 {
2573 Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2574 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2575
2576 /* Make sure all other VCPUs return to ring 3. */
2577 if (pVM->cCpus > 1)
2578 {
2579 VM_FF_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
2580 PGM_INVL_ALL_VCPU_TLBS(pVM);
2581 }
2582 return VINF_PGM_SYNC_CR3;
2583 }
2584# endif /* !IN_RING3 */
2585 else
2586 {
2587 pgmPoolMonitorModifiedClearAll(pVM);
2588
2589 /* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
2590 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2591 {
2592 Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
2593 return pgmPoolSyncCR3(pVCpu);
2594 }
2595 }
2596 return VINF_SUCCESS;
2597}
2598
2599
2600/**
2601 * Frees up at least one user entry.
2602 *
2603 * @returns VBox status code.
2604 * @retval VINF_SUCCESS if successfully added.
2605 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2606 * @param pPool The pool.
2607 * @param iUser The user index.
2608 */
2609static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2610{
2611 STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2612 /*
2613 * Just free cached pages in a braindead fashion.
2614 */
2615 /** @todo walk the age list backwards and free the first with usage. */
2616 int rc = VINF_SUCCESS;
2617 do
2618 {
2619 int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2620 if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2621 rc = rc2;
2622 } while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2623 return rc;
2624}
2625
2626
2627/**
2628 * Inserts a page into the cache.
2629 *
2630 * This will create user node for the page, insert it into the GCPhys
2631 * hash, and insert it into the age list.
2632 *
2633 * @returns VBox status code.
2634 * @retval VINF_SUCCESS if successfully added.
2635 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2636 * @param pPool The pool.
2637 * @param pPage The cached page.
2638 * @param GCPhys The GC physical address of the page we're gonna shadow.
2639 * @param iUser The user index.
2640 * @param iUserTable The user table index.
2641 */
2642DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2643{
2644 int rc = VINF_SUCCESS;
2645 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2646
2647 LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser=%d iUserTable=%x\n", GCPhys, iUser, iUserTable));
2648
2649#ifdef VBOX_STRICT
2650 /*
2651 * Check that the entry doesn't already exists.
2652 */
2653 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2654 {
2655 uint16_t i = pPage->iUserHead;
2656 do
2657 {
2658 Assert(i < pPool->cMaxUsers);
2659 AssertMsg(paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2660 i = paUsers[i].iNext;
2661 } while (i != NIL_PGMPOOL_USER_INDEX);
2662 }
2663#endif
2664
2665 /*
2666 * Find free a user node.
2667 */
2668 uint16_t i = pPool->iUserFreeHead;
2669 if (i == NIL_PGMPOOL_USER_INDEX)
2670 {
2671 rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2672 if (RT_FAILURE(rc))
2673 return rc;
2674 i = pPool->iUserFreeHead;
2675 }
2676
2677 /*
2678 * Unlink the user node from the free list,
2679 * initialize and insert it into the user list.
2680 */
2681 pPool->iUserFreeHead = paUsers[i].iNext;
2682 paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2683 paUsers[i].iUser = iUser;
2684 paUsers[i].iUserTable = iUserTable;
2685 pPage->iUserHead = i;
2686
2687 /*
2688 * Insert into cache and enable monitoring of the guest page if enabled.
2689 *
2690 * Until we implement caching of all levels, including the CR3 one, we'll
2691 * have to make sure we don't try monitor & cache any recursive reuse of
2692 * a monitored CR3 page. Because all windows versions are doing this we'll
2693 * have to be able to do combined access monitoring, CR3 + PT and
2694 * PD + PT (guest PAE).
2695 *
2696 * Update:
2697 * We're now cooperating with the CR3 monitor if an uncachable page is found.
2698 */
2699 const bool fCanBeMonitored = true;
2700 pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2701 if (fCanBeMonitored)
2702 {
2703 rc = pgmPoolMonitorInsert(pPool, pPage);
2704 AssertRC(rc);
2705 }
2706 return rc;
2707}
2708
2709
2710/**
2711 * Adds a user reference to a page.
2712 *
2713 * This will move the page to the head of the
2714 *
2715 * @returns VBox status code.
2716 * @retval VINF_SUCCESS if successfully added.
2717 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2718 * @param pPool The pool.
2719 * @param pPage The cached page.
2720 * @param iUser The user index.
2721 * @param iUserTable The user table.
2722 */
2723static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2724{
2725 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2726
2727 Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2728
2729# ifdef VBOX_STRICT
2730 /*
2731 * Check that the entry doesn't already exists. We only allow multiple
2732 * users of top-level paging structures (SHW_POOL_ROOT_IDX).
2733 */
2734 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2735 {
2736 uint16_t i = pPage->iUserHead;
2737 do
2738 {
2739 Assert(i < pPool->cMaxUsers);
2740 AssertMsg(iUser != PGMPOOL_IDX_PD || iUser != PGMPOOL_IDX_PDPT || iUser != PGMPOOL_IDX_NESTED_ROOT || iUser != PGMPOOL_IDX_AMD64_CR3 ||
2741 paUsers[i].iUser != iUser || paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2742 i = paUsers[i].iNext;
2743 } while (i != NIL_PGMPOOL_USER_INDEX);
2744 }
2745# endif
2746
2747 /*
2748 * Allocate a user node.
2749 */
2750 uint16_t i = pPool->iUserFreeHead;
2751 if (i == NIL_PGMPOOL_USER_INDEX)
2752 {
2753 int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2754 if (RT_FAILURE(rc))
2755 return rc;
2756 i = pPool->iUserFreeHead;
2757 }
2758 pPool->iUserFreeHead = paUsers[i].iNext;
2759
2760 /*
2761 * Initialize the user node and insert it.
2762 */
2763 paUsers[i].iNext = pPage->iUserHead;
2764 paUsers[i].iUser = iUser;
2765 paUsers[i].iUserTable = iUserTable;
2766 pPage->iUserHead = i;
2767
2768# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2769 if (pPage->fDirty)
2770 pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirty, false /* do not remove */);
2771# endif
2772
2773 /*
2774 * Tell the cache to update its replacement stats for this page.
2775 */
2776 pgmPoolCacheUsed(pPool, pPage);
2777 return VINF_SUCCESS;
2778}
2779
2780
2781/**
2782 * Frees a user record associated with a page.
2783 *
2784 * This does not clear the entry in the user table, it simply replaces the
2785 * user record to the chain of free records.
2786 *
2787 * @param pPool The pool.
2788 * @param HCPhys The HC physical address of the shadow page.
2789 * @param iUser The shadow page pool index of the user table.
2790 * @param iUserTable The index into the user table (shadowed).
2791 */
2792static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2793{
2794 /*
2795 * Unlink and free the specified user entry.
2796 */
2797 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2798
2799 Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2800 /* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2801 uint16_t i = pPage->iUserHead;
2802 if ( i != NIL_PGMPOOL_USER_INDEX
2803 && paUsers[i].iUser == iUser
2804 && paUsers[i].iUserTable == iUserTable)
2805 {
2806 pPage->iUserHead = paUsers[i].iNext;
2807
2808 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2809 paUsers[i].iNext = pPool->iUserFreeHead;
2810 pPool->iUserFreeHead = i;
2811 return;
2812 }
2813
2814 /* General: Linear search. */
2815 uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2816 while (i != NIL_PGMPOOL_USER_INDEX)
2817 {
2818 if ( paUsers[i].iUser == iUser
2819 && paUsers[i].iUserTable == iUserTable)
2820 {
2821 if (iPrev != NIL_PGMPOOL_USER_INDEX)
2822 paUsers[iPrev].iNext = paUsers[i].iNext;
2823 else
2824 pPage->iUserHead = paUsers[i].iNext;
2825
2826 paUsers[i].iUser = NIL_PGMPOOL_IDX;
2827 paUsers[i].iNext = pPool->iUserFreeHead;
2828 pPool->iUserFreeHead = i;
2829 return;
2830 }
2831 iPrev = i;
2832 i = paUsers[i].iNext;
2833 }
2834
2835 /* Fatal: didn't find it */
2836 AssertFatalMsgFailed(("Didn't find the user entry! iUser=%d iUserTable=%#x GCPhys=%RGp\n",
2837 iUser, iUserTable, pPage->GCPhys));
2838}
2839
2840
2841/**
2842 * Gets the entry size of a shadow table.
2843 *
2844 * @param enmKind The kind of page.
2845 *
2846 * @returns The size of the entry in bytes. That is, 4 or 8.
2847 * @returns If the kind is not for a table, an assertion is raised and 0 is
2848 * returned.
2849 */
2850DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2851{
2852 switch (enmKind)
2853 {
2854 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2855 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2856 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2857 case PGMPOOLKIND_32BIT_PD:
2858 case PGMPOOLKIND_32BIT_PD_PHYS:
2859 return 4;
2860
2861 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2862 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2863 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2864 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2865 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2866 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2867 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2868 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2869 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2870 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2871 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2872 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2873 case PGMPOOLKIND_64BIT_PML4:
2874 case PGMPOOLKIND_PAE_PDPT:
2875 case PGMPOOLKIND_ROOT_NESTED:
2876 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2877 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2878 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2879 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2880 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2881 case PGMPOOLKIND_PAE_PD_PHYS:
2882 case PGMPOOLKIND_PAE_PDPT_PHYS:
2883 return 8;
2884
2885 default:
2886 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2887 }
2888}
2889
2890
2891/**
2892 * Gets the entry size of a guest table.
2893 *
2894 * @param enmKind The kind of page.
2895 *
2896 * @returns The size of the entry in bytes. That is, 0, 4 or 8.
2897 * @returns If the kind is not for a table, an assertion is raised and 0 is
2898 * returned.
2899 */
2900DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2901{
2902 switch (enmKind)
2903 {
2904 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2905 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2906 case PGMPOOLKIND_32BIT_PD:
2907 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2908 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2909 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2910 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2911 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2912 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2913 return 4;
2914
2915 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2916 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2917 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2918 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2919 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2920 case PGMPOOLKIND_64BIT_PML4:
2921 case PGMPOOLKIND_PAE_PDPT:
2922 return 8;
2923
2924 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2925 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2926 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2927 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2928 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2929 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2930 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2931 case PGMPOOLKIND_ROOT_NESTED:
2932 case PGMPOOLKIND_PAE_PD_PHYS:
2933 case PGMPOOLKIND_PAE_PDPT_PHYS:
2934 case PGMPOOLKIND_32BIT_PD_PHYS:
2935 /** @todo can we return 0? (nobody is calling this...) */
2936 AssertFailed();
2937 return 0;
2938
2939 default:
2940 AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2941 }
2942}
2943
2944
2945/**
2946 * Checks one shadow page table entry for a mapping of a physical page.
2947 *
2948 * @returns true / false indicating removal of all relevant PTEs
2949 *
2950 * @param pVM The VM handle.
2951 * @param pPhysPage The guest page in question.
2952 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
2953 * @param iShw The shadow page table.
2954 * @param iPte Page table entry or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown
2955 */
2956static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t iPte)
2957{
2958 LogFlow(("pgmPoolTrackFlushGCPhysPTInt: pPhysPage=%RHp iShw=%d iPte=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, iPte));
2959 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2960 bool fRet = false;
2961
2962 /*
2963 * Assert sanity.
2964 */
2965 Assert(iPte != NIL_PGMPOOL_PHYSEXT_IDX_PTE);
2966 AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2967 PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2968
2969 /*
2970 * Then, clear the actual mappings to the page in the shadow PT.
2971 */
2972 switch (pPage->enmKind)
2973 {
2974 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2975 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2976 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2977 {
2978 const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
2979 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2980 uint32_t u32AndMask = 0;
2981 uint32_t u32OrMask = 0;
2982
2983 if (!fFlushPTEs)
2984 {
2985 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
2986 {
2987 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /** No handler installed. */
2988 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /** Monitoring is temporarily disabled. */
2989 u32OrMask = X86_PTE_RW;
2990 u32AndMask = UINT32_MAX;
2991 fRet = true;
2992 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
2993 break;
2994
2995 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /** Write access is monitored. */
2996 u32OrMask = 0;
2997 u32AndMask = ~X86_PTE_RW;
2998 fRet = true;
2999 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3000 break;
3001 default:
3002 /* (shouldn't be here, will assert below) */
3003 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3004 break;
3005 }
3006 }
3007 else
3008 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3009
3010 /* Update the counter if we're removing references. */
3011 if (!u32AndMask)
3012 {
3013 Assert(pPage->cPresent );
3014 Assert(pPool->cPresent);
3015 pPage->cPresent--;
3016 pPool->cPresent--;
3017 }
3018
3019 if ((pPT->a[iPte].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3020 {
3021 X86PTE Pte;
3022
3023 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32\n", iPte, pPT->a[iPte]));
3024 Pte.u = (pPT->a[iPte].u & u32AndMask) | u32OrMask;
3025 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3026 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3027
3028 ASMAtomicWriteU32(&pPT->a[iPte].u, Pte.u);
3029 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3030 return fRet;
3031 }
3032#ifdef LOG_ENABLED
3033 Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3034 for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3035 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3036 {
3037 Log(("i=%d cFound=%d\n", i, ++cFound));
3038 }
3039#endif
3040 AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
3041 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3042 break;
3043 }
3044
3045 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3046 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3047 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3048 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3049 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3050 case PGMPOOLKIND_EPT_PT_FOR_PHYS: /* physical mask the same as PAE; RW bit as well; be careful! */
3051 {
3052 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P;
3053 PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3054 uint64_t u64OrMask = 0;
3055 uint64_t u64AndMask = 0;
3056
3057 if (!fFlushPTEs)
3058 {
3059 switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3060 {
3061 case PGM_PAGE_HNDL_PHYS_STATE_NONE: /* No handler installed. */
3062 case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /* Monitoring is temporarily disabled. */
3063 u64OrMask = X86_PTE_RW;
3064 u64AndMask = UINT64_MAX;
3065 fRet = true;
3066 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3067 break;
3068
3069 case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /* Write access is monitored. */
3070 u64OrMask = 0;
3071 u64AndMask = ~(uint64_t)X86_PTE_RW;
3072 fRet = true;
3073 STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3074 break;
3075
3076 default:
3077 /* (shouldn't be here, will assert below) */
3078 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3079 break;
3080 }
3081 }
3082 else
3083 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3084
3085 /* Update the counter if we're removing references. */
3086 if (!u64AndMask)
3087 {
3088 Assert(pPage->cPresent);
3089 Assert(pPool->cPresent);
3090 pPage->cPresent--;
3091 pPool->cPresent--;
3092 }
3093
3094 if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3095 {
3096 X86PTEPAE Pte;
3097
3098 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64\n", iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3099 Pte.u = (PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & u64AndMask) | u64OrMask;
3100 if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3101 Pte.n.u1Write = 0; /* need to disallow writes when dirty bit tracking is still active. */
3102
3103 PGMSHWPTEPAE_ATOMIC_SET(pPT->a[iPte], Pte.u);
3104 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3105 return fRet;
3106 }
3107#ifdef LOG_ENABLED
3108 Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3109 Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX), u64));
3110 for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3111 if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3112 Log(("i=%d cFound=%d\n", i, ++cFound));
3113#endif
3114 AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x iPte=%d PT=%RX64\n", pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind, iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3115 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3116 break;
3117 }
3118
3119#ifdef PGM_WITH_LARGE_PAGES
3120 /* Large page case only. */
3121 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3122 {
3123 Assert(pVM->pgm.s.fNestedPaging);
3124
3125 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PDE4M_P | X86_PDE4M_PS;
3126 PEPTPD pPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3127
3128 if ((pPD->a[iPte].u & (EPT_PDE2M_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3129 {
3130 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3131 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3132 pPD->a[iPte].u = 0;
3133 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3134
3135 /* Update the counter as we're removing references. */
3136 Assert(pPage->cPresent);
3137 Assert(pPool->cPresent);
3138 pPage->cPresent--;
3139 pPool->cPresent--;
3140
3141 return fRet;
3142 }
3143# ifdef LOG_ENABLED
3144 Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3145 for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3146 if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3147 Log(("i=%d cFound=%d\n", i, ++cFound));
3148# endif
3149 AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3150 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3151 break;
3152 }
3153
3154 /* AMD-V nested paging */ /** @todo merge with EPT as we only check the parts that are identical. */
3155 case PGMPOOLKIND_PAE_PD_PHYS:
3156 {
3157 Assert(pVM->pgm.s.fNestedPaging);
3158
3159 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PDE4M_P | X86_PDE4M_PS;
3160 PX86PD pPD = (PX86PD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3161
3162 if ((pPD->a[iPte].u & (X86_PDE2M_PAE_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3163 {
3164 Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3165 STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3166 pPD->a[iPte].u = 0;
3167 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3168
3169 /* Update the counter as we're removing references. */
3170 Assert(pPage->cPresent);
3171 Assert(pPool->cPresent);
3172 pPage->cPresent--;
3173 pPool->cPresent--;
3174 return fRet;
3175 }
3176# ifdef LOG_ENABLED
3177 Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3178 for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3179 if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK | X86_PDE4M_P | X86_PDE4M_PS)) == u64)
3180 Log(("i=%d cFound=%d\n", i, ++cFound));
3181# endif
3182 AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3183 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3184 break;
3185 }
3186#endif /* PGM_WITH_LARGE_PAGES */
3187
3188 default:
3189 AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3190 }
3191 return fRet;
3192}
3193
3194
3195/**
3196 * Scans one shadow page table for mappings of a physical page.
3197 *
3198 * @param pVM The VM handle.
3199 * @param pPhysPage The guest page in question.
3200 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3201 * @param iShw The shadow page table.
3202 */
3203static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw)
3204{
3205 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3206
3207 /* We should only come here with when there's only one reference to this physical page. */
3208 Assert(PGMPOOL_TD_GET_CREFS(PGM_PAGE_GET_TRACKING(pPhysPage)) == 1);
3209
3210 Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw));
3211 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3212 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, PGM_PAGE_GET_PTE_INDEX(pPhysPage));
3213 if (!fKeptPTEs)
3214 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3215 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3216}
3217
3218
3219/**
3220 * Flushes a list of shadow page tables mapping the same physical page.
3221 *
3222 * @param pVM The VM handle.
3223 * @param pPhysPage The guest page in question.
3224 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3225 * @param iPhysExt The physical cross reference extent list to flush.
3226 */
3227static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3228{
3229 Assert(PGMIsLockOwner(pVM));
3230 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3231 bool fKeepList = false;
3232
3233 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3234 Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3235
3236 const uint16_t iPhysExtStart = iPhysExt;
3237 PPGMPOOLPHYSEXT pPhysExt;
3238 do
3239 {
3240 Assert(iPhysExt < pPool->cMaxPhysExts);
3241 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3242 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3243 {
3244 if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3245 {
3246 bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], pPhysExt->apte[i]);
3247 if (!fKeptPTEs)
3248 {
3249 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3250 pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3251 }
3252 else
3253 fKeepList = true;
3254 }
3255 }
3256 /* next */
3257 iPhysExt = pPhysExt->iNext;
3258 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3259
3260 if (!fKeepList)
3261 {
3262 /* insert the list into the free list and clear the ram range entry. */
3263 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3264 pPool->iPhysExtFreeHead = iPhysExtStart;
3265 /* Invalidate the tracking data. */
3266 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3267 }
3268
3269 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3270}
3271
3272
3273/**
3274 * Flushes all shadow page table mappings of the given guest page.
3275 *
3276 * This is typically called when the host page backing the guest one has been
3277 * replaced or when the page protection was changed due to a guest access
3278 * caught by the monitoring.
3279 *
3280 * @returns VBox status code.
3281 * @retval VINF_SUCCESS if all references has been successfully cleared.
3282 * @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3283 * pool cleaning. FF and sync flags are set.
3284 *
3285 * @param pVM The VM handle.
3286 * @param GCPhysPage GC physical address of the page in question
3287 * @param pPhysPage The guest page in question.
3288 * @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3289 * @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3290 * flushed, it is NOT touched if this isn't necessary.
3291 * The caller MUST initialized this to @a false.
3292 */
3293int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3294{
3295 PVMCPU pVCpu = VMMGetCpu(pVM);
3296 pgmLock(pVM);
3297 int rc = VINF_SUCCESS;
3298
3299#ifdef PGM_WITH_LARGE_PAGES
3300 /* Is this page part of a large page? */
3301 if (PGM_PAGE_GET_PDE_TYPE(pPhysPage) == PGM_PAGE_PDE_TYPE_PDE)
3302 {
3303 PPGMPAGE pPhysBase;
3304 RTGCPHYS GCPhysBase = GCPhysPage & X86_PDE2M_PAE_PG_MASK;
3305
3306 GCPhysPage &= X86_PDE_PAE_PG_MASK;
3307
3308 /* Fetch the large page base. */
3309 if (GCPhysBase != GCPhysPage)
3310 {
3311 pPhysBase = pgmPhysGetPage(&pVM->pgm.s, GCPhysBase);
3312 AssertFatal(pPhysBase);
3313 }
3314 else
3315 pPhysBase = pPhysPage;
3316
3317 Log(("pgmPoolTrackUpdateGCPhys: update large page PDE for %RGp (%RGp)\n", GCPhysBase, GCPhysPage));
3318
3319 if (PGM_PAGE_GET_PDE_TYPE(pPhysBase) == PGM_PAGE_PDE_TYPE_PDE)
3320 {
3321 /* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
3322 PGM_PAGE_SET_PDE_TYPE(pPhysBase, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3323
3324 /* Update the base as that *only* that one has a reference and there's only one PDE to clear. */
3325 rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysBase, pPhysBase, fFlushPTEs, pfFlushTLBs);
3326
3327 *pfFlushTLBs = true;
3328 pgmUnlock(pVM);
3329 return rc;
3330 }
3331 }
3332#else
3333 NOREF(GCPhysPage);
3334#endif /* PGM_WITH_LARGE_PAGES */
3335
3336 const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3337 if (u16)
3338 {
3339 /*
3340 * The zero page is currently screwing up the tracking and we'll
3341 * have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3342 * is defined, zero pages won't normally be mapped. Some kind of solution
3343 * will be needed for this problem of course, but it will have to wait...
3344 */
3345 if ( PGM_PAGE_IS_ZERO(pPhysPage)
3346 || PGM_PAGE_IS_BALLOONED(pPhysPage))
3347 rc = VINF_PGM_GCPHYS_ALIASED;
3348 else
3349 {
3350# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC) /** @todo we can drop this now. */
3351 /* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3352 pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3353 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
3354# endif
3355
3356 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3357 {
3358 Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3359 pgmPoolTrackFlushGCPhysPT(pVM,
3360 pPhysPage,
3361 fFlushPTEs,
3362 PGMPOOL_TD_GET_IDX(u16));
3363 }
3364 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3365 pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3366 else
3367 rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3368 *pfFlushTLBs = true;
3369
3370# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
3371 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
3372# endif
3373 }
3374 }
3375
3376 if (rc == VINF_PGM_GCPHYS_ALIASED)
3377 {
3378 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_CLEAR_PGM_POOL;
3379 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3380 rc = VINF_PGM_SYNC_CR3;
3381 }
3382 pgmUnlock(pVM);
3383 return rc;
3384}
3385
3386
3387/**
3388 * Scans all shadow page tables for mappings of a physical page.
3389 *
3390 * This may be slow, but it's most likely more efficient than cleaning
3391 * out the entire page pool / cache.
3392 *
3393 * @returns VBox status code.
3394 * @retval VINF_SUCCESS if all references has been successfully cleared.
3395 * @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3396 * a page pool cleaning.
3397 *
3398 * @param pVM The VM handle.
3399 * @param pPhysPage The guest page in question.
3400 */
3401int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
3402{
3403 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3404 STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3405 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3406 pPool->cUsedPages, pPool->cPresent, pPhysPage));
3407
3408 /*
3409 * There is a limit to what makes sense.
3410 */
3411 if ( pPool->cPresent > 1024
3412 && pVM->cCpus == 1)
3413 {
3414 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3415 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3416 return VINF_PGM_GCPHYS_ALIASED;
3417 }
3418
3419 /*
3420 * Iterate all the pages until we've encountered all that in use.
3421 * This is simple but not quite optimal solution.
3422 */
3423 const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) | X86_PTE_P; /** @todo drop X86_PTE_P here as we always test if present separately, anyway. */
3424 const uint32_t u32 = u64; /** @todo move into the 32BIT_PT_xx case */
3425 unsigned cLeft = pPool->cUsedPages;
3426 unsigned iPage = pPool->cCurPages;
3427 while (--iPage >= PGMPOOL_IDX_FIRST)
3428 {
3429 PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3430 if ( pPage->GCPhys != NIL_RTGCPHYS
3431 && pPage->cPresent)
3432 {
3433 switch (pPage->enmKind)
3434 {
3435 /*
3436 * We only care about shadow page tables.
3437 */
3438 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3439 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3440 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3441 {
3442 unsigned cPresent = pPage->cPresent;
3443 PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3444 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3445 if (pPT->a[i].n.u1Present)
3446 {
3447 if ((pPT->a[i].u & (X86_PTE_PG_MASK | X86_PTE_P)) == u32)
3448 {
3449 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3450 pPT->a[i].u = 0;
3451
3452 /* Update the counter as we're removing references. */
3453 Assert(pPage->cPresent);
3454 Assert(pPool->cPresent);
3455 pPage->cPresent--;
3456 pPool->cPresent--;
3457 }
3458 if (!--cPresent)
3459 break;
3460 }
3461 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3462 break;
3463 }
3464
3465 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3466 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3467 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3468 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3469 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3470 {
3471 unsigned cPresent = pPage->cPresent;
3472 PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3473 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3474 if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
3475 {
3476 if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK | X86_PTE_P)) == u64)
3477 {
3478 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3479 PGMSHWPTEPAE_SET(pPT->a[i], 0); /// @todo why not atomic?
3480
3481 /* Update the counter as we're removing references. */
3482 Assert(pPage->cPresent);
3483 Assert(pPool->cPresent);
3484 pPage->cPresent--;
3485 pPool->cPresent--;
3486 }
3487 if (!--cPresent)
3488 break;
3489 }
3490 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3491 break;
3492 }
3493#ifndef IN_RC
3494 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3495 {
3496 unsigned cPresent = pPage->cPresent;
3497 PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3498 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3499 if (pPT->a[i].n.u1Present)
3500 {
3501 if ((pPT->a[i].u & (EPT_PTE_PG_MASK | X86_PTE_P)) == u64)
3502 {
3503 //Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3504 pPT->a[i].u = 0;
3505
3506 /* Update the counter as we're removing references. */
3507 Assert(pPage->cPresent);
3508 Assert(pPool->cPresent);
3509 pPage->cPresent--;
3510 pPool->cPresent--;
3511 }
3512 if (!--cPresent)
3513 break;
3514 }
3515 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3516 break;
3517 }
3518#endif
3519 }
3520 if (!--cLeft)
3521 break;
3522 }
3523 }
3524
3525 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3526 STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3527
3528 /*
3529 * There is a limit to what makes sense. The above search is very expensive, so force a pgm pool flush.
3530 */
3531 if (pPool->cPresent > 1024)
3532 {
3533 LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3534 return VINF_PGM_GCPHYS_ALIASED;
3535 }
3536
3537 return VINF_SUCCESS;
3538}
3539
3540
3541/**
3542 * Clears the user entry in a user table.
3543 *
3544 * This is used to remove all references to a page when flushing it.
3545 */
3546static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3547{
3548 Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3549 Assert(pUser->iUser < pPool->cCurPages);
3550 uint32_t iUserTable = pUser->iUserTable;
3551
3552 /*
3553 * Map the user page.
3554 */
3555 PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3556 union
3557 {
3558 uint64_t *pau64;
3559 uint32_t *pau32;
3560 } u;
3561 u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3562
3563 LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3564
3565 /* Safety precaution in case we change the paging for other modes too in the future. */
3566 Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
3567
3568#ifdef VBOX_STRICT
3569 /*
3570 * Some sanity checks.
3571 */
3572 switch (pUserPage->enmKind)
3573 {
3574 case PGMPOOLKIND_32BIT_PD:
3575 case PGMPOOLKIND_32BIT_PD_PHYS:
3576 Assert(iUserTable < X86_PG_ENTRIES);
3577 break;
3578 case PGMPOOLKIND_PAE_PDPT:
3579 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3580 case PGMPOOLKIND_PAE_PDPT_PHYS:
3581 Assert(iUserTable < 4);
3582 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3583 break;
3584 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3585 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3586 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3587 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3588 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3589 case PGMPOOLKIND_PAE_PD_PHYS:
3590 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3591 break;
3592 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3593 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3594 Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3595 break;
3596 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3597 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3598 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3599 break;
3600 case PGMPOOLKIND_64BIT_PML4:
3601 Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3602 /* GCPhys >> PAGE_SHIFT is the index here */
3603 break;
3604 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3605 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3606 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3607 break;
3608
3609 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3610 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3611 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3612 break;
3613
3614 case PGMPOOLKIND_ROOT_NESTED:
3615 Assert(iUserTable < X86_PG_PAE_ENTRIES);
3616 break;
3617
3618 default:
3619 AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3620 break;
3621 }
3622#endif /* VBOX_STRICT */
3623
3624 /*
3625 * Clear the entry in the user page.
3626 */
3627 switch (pUserPage->enmKind)
3628 {
3629 /* 32-bit entries */
3630 case PGMPOOLKIND_32BIT_PD:
3631 case PGMPOOLKIND_32BIT_PD_PHYS:
3632 ASMAtomicWriteU32(&u.pau32[iUserTable], 0);
3633 break;
3634
3635 /* 64-bit entries */
3636 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3637 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3638 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3639 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3640 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3641#ifdef IN_RC
3642 /*
3643 * In 32 bits PAE mode we *must* invalidate the TLB when changing a
3644 * PDPT entry; the CPU fetches them only during cr3 load, so any
3645 * non-present PDPT will continue to cause page faults.
3646 */
3647 ASMReloadCR3();
3648 /* no break */
3649#endif
3650 case PGMPOOLKIND_PAE_PD_PHYS:
3651 case PGMPOOLKIND_PAE_PDPT_PHYS:
3652 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3653 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3654 case PGMPOOLKIND_64BIT_PML4:
3655 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3656 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3657 case PGMPOOLKIND_PAE_PDPT:
3658 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3659 case PGMPOOLKIND_ROOT_NESTED:
3660 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3661 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3662 ASMAtomicWriteU64(&u.pau64[iUserTable], 0);
3663 break;
3664
3665 default:
3666 AssertFatalMsgFailed(("enmKind=%d iUser=%d iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3667 }
3668 PGM_DYNMAP_UNUSED_HINT_VM(pPool->CTX_SUFF(pVM), u.pau64);
3669}
3670
3671
3672/**
3673 * Clears all users of a page.
3674 */
3675static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3676{
3677 /*
3678 * Free all the user records.
3679 */
3680 LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3681
3682 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3683 uint16_t i = pPage->iUserHead;
3684 while (i != NIL_PGMPOOL_USER_INDEX)
3685 {
3686 /* Clear enter in user table. */
3687 pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3688
3689 /* Free it. */
3690 const uint16_t iNext = paUsers[i].iNext;
3691 paUsers[i].iUser = NIL_PGMPOOL_IDX;
3692 paUsers[i].iNext = pPool->iUserFreeHead;
3693 pPool->iUserFreeHead = i;
3694
3695 /* Next. */
3696 i = iNext;
3697 }
3698 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3699}
3700
3701
3702/**
3703 * Allocates a new physical cross reference extent.
3704 *
3705 * @returns Pointer to the allocated extent on success. NULL if we're out of them.
3706 * @param pVM The VM handle.
3707 * @param piPhysExt Where to store the phys ext index.
3708 */
3709PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3710{
3711 Assert(PGMIsLockOwner(pVM));
3712 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3713 uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3714 if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3715 {
3716 STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3717 return NULL;
3718 }
3719 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3720 pPool->iPhysExtFreeHead = pPhysExt->iNext;
3721 pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3722 *piPhysExt = iPhysExt;
3723 return pPhysExt;
3724}
3725
3726
3727/**
3728 * Frees a physical cross reference extent.
3729 *
3730 * @param pVM The VM handle.
3731 * @param iPhysExt The extent to free.
3732 */
3733void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3734{
3735 Assert(PGMIsLockOwner(pVM));
3736 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3737 Assert(iPhysExt < pPool->cMaxPhysExts);
3738 PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3739 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3740 {
3741 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3742 pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3743 }
3744 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3745 pPool->iPhysExtFreeHead = iPhysExt;
3746}
3747
3748
3749/**
3750 * Frees a physical cross reference extent.
3751 *
3752 * @param pVM The VM handle.
3753 * @param iPhysExt The extent to free.
3754 */
3755void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3756{
3757 Assert(PGMIsLockOwner(pVM));
3758 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3759
3760 const uint16_t iPhysExtStart = iPhysExt;
3761 PPGMPOOLPHYSEXT pPhysExt;
3762 do
3763 {
3764 Assert(iPhysExt < pPool->cMaxPhysExts);
3765 pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3766 for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3767 {
3768 pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3769 pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3770 }
3771
3772 /* next */
3773 iPhysExt = pPhysExt->iNext;
3774 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3775
3776 pPhysExt->iNext = pPool->iPhysExtFreeHead;
3777 pPool->iPhysExtFreeHead = iPhysExtStart;
3778}
3779
3780
3781/**
3782 * Insert a reference into a list of physical cross reference extents.
3783 *
3784 * @returns The new tracking data for PGMPAGE.
3785 *
3786 * @param pVM The VM handle.
3787 * @param iPhysExt The physical extent index of the list head.
3788 * @param iShwPT The shadow page table index.
3789 * @param iPte Page table entry
3790 *
3791 */
3792static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT, uint16_t iPte)
3793{
3794 Assert(PGMIsLockOwner(pVM));
3795 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3796 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3797
3798 /*
3799 * Special common cases.
3800 */
3801 if (paPhysExts[iPhysExt].aidx[1] == NIL_PGMPOOL_IDX)
3802 {
3803 paPhysExts[iPhysExt].aidx[1] = iShwPT;
3804 paPhysExts[iPhysExt].apte[1] = iPte;
3805 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3806 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,%d pte %d,}\n", iPhysExt, iShwPT, iPte));
3807 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3808 }
3809 if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3810 {
3811 paPhysExts[iPhysExt].aidx[2] = iShwPT;
3812 paPhysExts[iPhysExt].apte[2] = iPte;
3813 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3814 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d pte %d}\n", iPhysExt, iShwPT, iPte));
3815 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3816 }
3817 AssertCompile(RT_ELEMENTS(paPhysExts[iPhysExt].aidx) == 3);
3818
3819 /*
3820 * General treatment.
3821 */
3822 const uint16_t iPhysExtStart = iPhysExt;
3823 unsigned cMax = 15;
3824 for (;;)
3825 {
3826 Assert(iPhysExt < pPool->cMaxPhysExts);
3827 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3828 if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3829 {
3830 paPhysExts[iPhysExt].aidx[i] = iShwPT;
3831 paPhysExts[iPhysExt].apte[i] = iPte;
3832 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
3833 LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d pte %d} i=%d cMax=%d\n", iPhysExt, iShwPT, iPte, i, cMax));
3834 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3835 }
3836 if (!--cMax)
3837 {
3838 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackOverflows);
3839 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3840 LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
3841 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3842 }
3843
3844 /* advance */
3845 iPhysExt = paPhysExts[iPhysExt].iNext;
3846 if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3847 break;
3848 }
3849
3850 /*
3851 * Add another extent to the list.
3852 */
3853 PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3854 if (!pNew)
3855 {
3856 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackNoExtentsLeft);
3857 pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3858 LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
3859 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3860 }
3861 pNew->iNext = iPhysExtStart;
3862 pNew->aidx[0] = iShwPT;
3863 pNew->apte[0] = iPte;
3864 LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d pte %d}->%d\n", iPhysExt, iShwPT, iPte, iPhysExtStart));
3865 return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3866}
3867
3868
3869/**
3870 * Add a reference to guest physical page where extents are in use.
3871 *
3872 * @returns The new tracking data for PGMPAGE.
3873 *
3874 * @param pVM The VM handle.
3875 * @param pPhysPage Pointer to the aPages entry in the ram range.
3876 * @param u16 The ram range flags (top 16-bits).
3877 * @param iShwPT The shadow page table index.
3878 * @param iPte Page table entry
3879 */
3880uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte)
3881{
3882 pgmLock(pVM);
3883 if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3884 {
3885 /*
3886 * Convert to extent list.
3887 */
3888 Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3889 uint16_t iPhysExt;
3890 PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3891 if (pPhysExt)
3892 {
3893 LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3894 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliased);
3895 pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3896 pPhysExt->apte[0] = PGM_PAGE_GET_PTE_INDEX(pPhysPage);
3897 pPhysExt->aidx[1] = iShwPT;
3898 pPhysExt->apte[1] = iPte;
3899 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3900 }
3901 else
3902 u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3903 }
3904 else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3905 {
3906 /*
3907 * Insert into the extent list.
3908 */
3909 u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT, iPte);
3910 }
3911 else
3912 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedLots);
3913 pgmUnlock(pVM);
3914 return u16;
3915}
3916
3917
3918/**
3919 * Clear references to guest physical memory.
3920 *
3921 * @param pPool The pool.
3922 * @param pPage The page.
3923 * @param pPhysPage Pointer to the aPages entry in the ram range.
3924 * @param iPte Shadow PTE index
3925 */
3926void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage, uint16_t iPte)
3927{
3928 const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3929 AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3930
3931 uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3932 if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3933 {
3934 PVM pVM = pPool->CTX_SUFF(pVM);
3935 pgmLock(pVM);
3936
3937 uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3938 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3939 do
3940 {
3941 Assert(iPhysExt < pPool->cMaxPhysExts);
3942
3943 /*
3944 * Look for the shadow page and check if it's all freed.
3945 */
3946 for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3947 {
3948 if ( paPhysExts[iPhysExt].aidx[i] == pPage->idx
3949 && paPhysExts[iPhysExt].apte[i] == iPte)
3950 {
3951 paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3952 paPhysExts[iPhysExt].apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3953
3954 for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3955 if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3956 {
3957 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3958 pgmUnlock(pVM);
3959 return;
3960 }
3961
3962 /* we can free the node. */
3963 const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3964 if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3965 && iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3966 {
3967 /* lonely node */
3968 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3969 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3970 PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3971 }
3972 else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3973 {
3974 /* head */
3975 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3976 PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3977 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3978 }
3979 else
3980 {
3981 /* in list */
3982 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d in list\n", pPhysPage, pPage->idx));
3983 paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3984 pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3985 }
3986 iPhysExt = iPhysExtNext;
3987 pgmUnlock(pVM);
3988 return;
3989 }
3990 }
3991
3992 /* next */
3993 iPhysExtPrev = iPhysExt;
3994 iPhysExt = paPhysExts[iPhysExt].iNext;
3995 } while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3996
3997 pgmUnlock(pVM);
3998 AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3999 }
4000 else /* nothing to do */
4001 Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
4002}
4003
4004/**
4005 * Clear references to guest physical memory.
4006 *
4007 * This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
4008 * is assumed to be correct, so the linear search can be skipped and we can assert
4009 * at an earlier point.
4010 *
4011 * @param pPool The pool.
4012 * @param pPage The page.
4013 * @param HCPhys The host physical address corresponding to the guest page.
4014 * @param GCPhys The guest physical address corresponding to HCPhys.
4015 * @param iPte Shadow PTE index
4016 */
4017static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys, uint16_t iPte)
4018{
4019 /*
4020 * Walk range list.
4021 */
4022 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4023 while (pRam)
4024 {
4025 RTGCPHYS off = GCPhys - pRam->GCPhys;
4026 if (off < pRam->cb)
4027 {
4028 /* does it match? */
4029 const unsigned iPage = off >> PAGE_SHIFT;
4030 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4031#ifdef LOG_ENABLED
4032 RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
4033 Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
4034#endif
4035 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4036 {
4037 Assert(pPage->cPresent);
4038 Assert(pPool->cPresent);
4039 pPage->cPresent--;
4040 pPool->cPresent--;
4041 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4042 return;
4043 }
4044 break;
4045 }
4046 pRam = pRam->CTX_SUFF(pNext);
4047 }
4048 AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4049}
4050
4051
4052/**
4053 * Clear references to guest physical memory.
4054 *
4055 * @param pPool The pool.
4056 * @param pPage The page.
4057 * @param HCPhys The host physical address corresponding to the guest page.
4058 * @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4059 * @param iPte Shadow pte index
4060 */
4061void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte)
4062{
4063 RTHCPHYS HCPhysExpected = 0xDEADBEEFDEADBEEFULL;
4064
4065 Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4066
4067 /*
4068 * Walk range list.
4069 */
4070 PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4071 while (pRam)
4072 {
4073 RTGCPHYS off = GCPhysHint - pRam->GCPhys;
4074 if (off < pRam->cb)
4075 {
4076 /* does it match? */
4077 const unsigned iPage = off >> PAGE_SHIFT;
4078 Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
4079 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4080 {
4081 Assert(pPage->cPresent);
4082 Assert(pPool->cPresent);
4083 pPage->cPresent--;
4084 pPool->cPresent--;
4085 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4086 return;
4087 }
4088 HCPhysExpected = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
4089 break;
4090 }
4091 pRam = pRam->CTX_SUFF(pNext);
4092 }
4093
4094 /*
4095 * Damn, the hint didn't work. We'll have to do an expensive linear search.
4096 */
4097 STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4098 pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
4099 while (pRam)
4100 {
4101 unsigned iPage = pRam->cb >> PAGE_SHIFT;
4102 while (iPage-- > 0)
4103 {
4104 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4105 {
4106 Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4107 HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4108 Assert(pPage->cPresent);
4109 Assert(pPool->cPresent);
4110 pPage->cPresent--;
4111 pPool->cPresent--;
4112 pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4113 return;
4114 }
4115 }
4116 pRam = pRam->CTX_SUFF(pNext);
4117 }
4118
4119 AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp (Expected HCPhys with hint = %RHp)\n", HCPhys, GCPhysHint, HCPhysExpected));
4120}
4121
4122
4123/**
4124 * Clear references to guest physical memory in a 32-bit / 32-bit page table.
4125 *
4126 * @param pPool The pool.
4127 * @param pPage The page.
4128 * @param pShwPT The shadow page table (mapping of the page).
4129 * @param pGstPT The guest page table.
4130 */
4131DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4132{
4133 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4134 {
4135 Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
4136 if (pShwPT->a[i].n.u1Present)
4137 {
4138 Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4139 i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4140 pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK, i);
4141 if (!pPage->cPresent)
4142 break;
4143 }
4144 }
4145}
4146
4147
4148/**
4149 * Clear references to guest physical memory in a PAE / 32-bit page table.
4150 *
4151 * @param pPool The pool.
4152 * @param pPage The page.
4153 * @param pShwPT The shadow page table (mapping of the page).
4154 * @param pGstPT The guest page table (just a half one).
4155 */
4156DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
4157{
4158 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4159 {
4160 Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4161 || (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4162 if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4163 {
4164 Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4165 i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PG_MASK));
4166 pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PG_MASK, i);
4167 if (!pPage->cPresent)
4168 break;
4169 }
4170 }
4171}
4172
4173
4174/**
4175 * Clear references to guest physical memory in a PAE / PAE page table.
4176 *
4177 * @param pPool The pool.
4178 * @param pPage The page.
4179 * @param pShwPT The shadow page table (mapping of the page).
4180 * @param pGstPT The guest page table.
4181 */
4182DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
4183{
4184 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4185 {
4186 Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4187 || (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4188 if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4189 {
4190 Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4191 i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4192 pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
4193 if (!pPage->cPresent)
4194 break;
4195 }
4196 }
4197}
4198
4199
4200/**
4201 * Clear references to guest physical memory in a 32-bit / 4MB page table.
4202 *
4203 * @param pPool The pool.
4204 * @param pPage The page.
4205 * @param pShwPT The shadow page table (mapping of the page).
4206 */
4207DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4208{
4209 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4210 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4211 {
4212 Assert(!(pShwPT->a[i].u & RT_BIT_32(10)));
4213 if (pShwPT->a[i].n.u1Present)
4214 {
4215 Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4216 i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
4217 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys, i);
4218 if (!pPage->cPresent)
4219 break;
4220 }
4221 }
4222}
4223
4224
4225/**
4226 * Clear references to guest physical memory in a PAE / 2/4MB page table.
4227 *
4228 * @param pPool The pool.
4229 * @param pPage The page.
4230 * @param pShwPT The shadow page table (mapping of the page).
4231 */
4232DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT)
4233{
4234 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4235 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4236 {
4237 Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4238 || (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4239 if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4240 {
4241 Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4242 i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys));
4243 pgmPoolTracDerefGCPhys(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys, i);
4244 if (!pPage->cPresent)
4245 break;
4246 }
4247 }
4248}
4249
4250
4251/**
4252 * Clear references to shadowed pages in an EPT page table.
4253 *
4254 * @param pPool The pool.
4255 * @param pPage The page.
4256 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4257 */
4258DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4259{
4260 RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4261 for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4262 {
4263 Assert((pShwPT->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4264 if (pShwPT->a[i].n.u1Present)
4265 {
4266 Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4267 i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
4268 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys, i);
4269 if (!pPage->cPresent)
4270 break;
4271 }
4272 }
4273}
4274
4275
4276
4277/**
4278 * Clear references to shadowed pages in a 32 bits page directory.
4279 *
4280 * @param pPool The pool.
4281 * @param pPage The page.
4282 * @param pShwPD The shadow page directory (mapping of the page).
4283 */
4284DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4285{
4286 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4287 {
4288 Assert(!(pShwPD->a[i].u & RT_BIT_32(9)));
4289 if ( pShwPD->a[i].n.u1Present
4290 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
4291 )
4292 {
4293 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4294 if (pSubPage)
4295 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4296 else
4297 AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4298 }
4299 }
4300}
4301
4302/**
4303 * Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4304 *
4305 * @param pPool The pool.
4306 * @param pPage The page.
4307 * @param pShwPD The shadow page directory (mapping of the page).
4308 */
4309DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4310{
4311 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4312 {
4313 Assert((pShwPD->a[i].u & (X86_PDE_PAE_MBZ_MASK_NX | UINT64_C(0x7ff0000000000200))) == 0);
4314 if ( pShwPD->a[i].n.u1Present
4315 && !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING))
4316 {
4317#ifdef PGM_WITH_LARGE_PAGES
4318 if (pShwPD->a[i].b.u1Size)
4319 {
4320 Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
4321 i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4322 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys /* == base of 2 MB page */, i);
4323 }
4324 else
4325#endif
4326 {
4327 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
4328 if (pSubPage)
4329 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4330 else
4331 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
4332 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4333 }
4334 }
4335 }
4336}
4337
4338/**
4339 * Clear references to shadowed pages in a PAE page directory pointer table.
4340 *
4341 * @param pPool The pool.
4342 * @param pPage The page.
4343 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4344 */
4345DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4346{
4347 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4348 {
4349 Assert((pShwPDPT->a[i].u & (X86_PDPE_PAE_MBZ_MASK | UINT64_C(0x7ff0000000000200))) == 0);
4350 if ( pShwPDPT->a[i].n.u1Present
4351 && !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
4352 )
4353 {
4354 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4355 if (pSubPage)
4356 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4357 else
4358 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4359 }
4360 }
4361}
4362
4363
4364/**
4365 * Clear references to shadowed pages in a 64-bit page directory pointer table.
4366 *
4367 * @param pPool The pool.
4368 * @param pPage The page.
4369 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4370 */
4371DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4372{
4373 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4374 {
4375 Assert((pShwPDPT->a[i].u & (X86_PDPE_LM_MBZ_MASK_NX | UINT64_C(0x7ff0000000000200))) == 0);
4376 if (pShwPDPT->a[i].n.u1Present)
4377 {
4378 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
4379 if (pSubPage)
4380 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4381 else
4382 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
4383 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4384 }
4385 }
4386}
4387
4388
4389/**
4390 * Clear references to shadowed pages in a 64-bit level 4 page table.
4391 *
4392 * @param pPool The pool.
4393 * @param pPage The page.
4394 * @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4395 */
4396DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4397{
4398 for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4399 {
4400 Assert((pShwPML4->a[i].u & (X86_PML4E_MBZ_MASK_NX | UINT64_C(0x7ff0000000000200))) == 0);
4401 if (pShwPML4->a[i].n.u1Present)
4402 {
4403 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
4404 if (pSubPage)
4405 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4406 else
4407 AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
4408 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4409 }
4410 }
4411}
4412
4413
4414/**
4415 * Clear references to shadowed pages in an EPT page directory.
4416 *
4417 * @param pPool The pool.
4418 * @param pPage The page.
4419 * @param pShwPD The shadow page directory (mapping of the page).
4420 */
4421DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4422{
4423 for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4424 {
4425 Assert((pShwPD->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4426 if (pShwPD->a[i].n.u1Present)
4427 {
4428#ifdef PGM_WITH_LARGE_PAGES
4429 if (pShwPD->a[i].b.u1Size)
4430 {
4431 Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
4432 i, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4433 pgmPoolTracDerefGCPhys(pPool, pPage, pShwPD->a[i].u & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys /* == base of 2 MB page */, i);
4434 }
4435 else
4436#endif
4437 {
4438 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
4439 if (pSubPage)
4440 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4441 else
4442 AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4443 }
4444 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4445 }
4446 }
4447}
4448
4449
4450/**
4451 * Clear references to shadowed pages in an EPT page directory pointer table.
4452 *
4453 * @param pPool The pool.
4454 * @param pPage The page.
4455 * @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4456 */
4457DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4458{
4459 for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4460 {
4461 Assert((pShwPDPT->a[i].u & UINT64_C(0xfff0000000000f80)) == 0);
4462 if (pShwPDPT->a[i].n.u1Present)
4463 {
4464 PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
4465 if (pSubPage)
4466 pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4467 else
4468 AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
4469 /** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4470 }
4471 }
4472}
4473
4474
4475/**
4476 * Clears all references made by this page.
4477 *
4478 * This includes other shadow pages and GC physical addresses.
4479 *
4480 * @param pPool The pool.
4481 * @param pPage The page.
4482 */
4483static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4484{
4485 /*
4486 * Map the shadow page and take action according to the page kind.
4487 */
4488 PVM pVM = pPool->CTX_SUFF(pVM);
4489 void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4490 switch (pPage->enmKind)
4491 {
4492 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4493 {
4494 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4495 void *pvGst;
4496 int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4497 pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4498 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4499 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4500 break;
4501 }
4502
4503 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4504 {
4505 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4506 void *pvGst;
4507 int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4508 pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
4509 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4510 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4511 break;
4512 }
4513
4514 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4515 {
4516 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4517 void *pvGst;
4518 int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4519 pgmPoolTrackDerefPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
4520 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4521 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4522 break;
4523 }
4524
4525 case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4526 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4527 {
4528 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4529 pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4530 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4531 break;
4532 }
4533
4534 case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4535 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4536 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4537 {
4538 STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4539 pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PPGMSHWPTPAE)pvShw);
4540 STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4541 break;
4542 }
4543
4544 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4545 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4546 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4547 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4548 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4549 case PGMPOOLKIND_PAE_PD_PHYS:
4550 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4551 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4552 pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4553 break;
4554
4555 case PGMPOOLKIND_32BIT_PD_PHYS:
4556 case PGMPOOLKIND_32BIT_PD:
4557 pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4558 break;
4559
4560 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4561 case PGMPOOLKIND_PAE_PDPT:
4562 case PGMPOOLKIND_PAE_PDPT_PHYS:
4563 pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4564 break;
4565
4566 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4567 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4568 pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4569 break;
4570
4571 case PGMPOOLKIND_64BIT_PML4:
4572 pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4573 break;
4574
4575 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4576 pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4577 break;
4578
4579 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4580 pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4581 break;
4582
4583 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4584 pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4585 break;
4586
4587 default:
4588 AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4589 }
4590
4591 /* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4592 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4593 ASMMemZeroPage(pvShw);
4594 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4595 pPage->fZeroed = true;
4596 Assert(!pPage->cPresent);
4597 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
4598}
4599
4600/**
4601 * Flushes a pool page.
4602 *
4603 * This moves the page to the free list after removing all user references to it.
4604 *
4605 * @returns VBox status code.
4606 * @retval VINF_SUCCESS on success.
4607 * @param pPool The pool.
4608 * @param HCPhys The HC physical address of the shadow page.
4609 * @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
4610 */
4611int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush)
4612{
4613 PVM pVM = pPool->CTX_SUFF(pVM);
4614 bool fFlushRequired = false;
4615
4616 int rc = VINF_SUCCESS;
4617 STAM_PROFILE_START(&pPool->StatFlushPage, f);
4618 LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4619 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4620
4621 /*
4622 * Quietly reject any attempts at flushing any of the special root pages.
4623 */
4624 if (pPage->idx < PGMPOOL_IDX_FIRST)
4625 {
4626 AssertFailed(); /* can no longer happen */
4627 Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4628 return VINF_SUCCESS;
4629 }
4630
4631 pgmLock(pVM);
4632
4633 /*
4634 * Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4635 */
4636 if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
4637 {
4638 AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4639 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4640 || pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4641 || pPage->enmKind == PGMPOOLKIND_32BIT_PD
4642 || pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4643 || pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4644 || pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4645 || pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4646 || pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
4647 ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4648 Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4649 pgmUnlock(pVM);
4650 return VINF_SUCCESS;
4651 }
4652
4653#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4654 /* Start a subset so we won't run out of mapping space. */
4655 PVMCPU pVCpu = VMMGetCpu(pVM);
4656 uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
4657#endif
4658
4659 /*
4660 * Mark the page as being in need of an ASMMemZeroPage().
4661 */
4662 pPage->fZeroed = false;
4663
4664#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4665 if (pPage->fDirty)
4666 pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirty, false /* do not remove */);
4667#endif
4668
4669 /* If there are any users of this table, then we *must* issue a tlb flush on all VCPUs. */
4670 if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
4671 fFlushRequired = true;
4672
4673 /*
4674 * Clear the page.
4675 */
4676 pgmPoolTrackClearPageUsers(pPool, pPage);
4677 STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4678 pgmPoolTrackDeref(pPool, pPage);
4679 STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4680
4681 /*
4682 * Flush it from the cache.
4683 */
4684 pgmPoolCacheFlushPage(pPool, pPage);
4685
4686#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4687 /* Heavy stuff done. */
4688 PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
4689#endif
4690
4691 /*
4692 * Deregistering the monitoring.
4693 */
4694 if (pPage->fMonitored)
4695 rc = pgmPoolMonitorFlush(pPool, pPage);
4696
4697 /*
4698 * Free the page.
4699 */
4700 Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4701 pPage->iNext = pPool->iFreeHead;
4702 pPool->iFreeHead = pPage->idx;
4703 pPage->enmKind = PGMPOOLKIND_FREE;
4704 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4705 pPage->GCPhys = NIL_RTGCPHYS;
4706 pPage->fReusedFlushPending = false;
4707
4708 pPool->cUsedPages--;
4709
4710 /* Flush the TLBs of all VCPUs if required. */
4711 if ( fFlushRequired
4712 && fFlush)
4713 {
4714 PGM_INVL_ALL_VCPU_TLBS(pVM);
4715 }
4716
4717 pgmUnlock(pVM);
4718 STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4719 return rc;
4720}
4721
4722
4723/**
4724 * Frees a usage of a pool page.
4725 *
4726 * The caller is responsible to updating the user table so that it no longer
4727 * references the shadow page.
4728 *
4729 * @param pPool The pool.
4730 * @param HCPhys The HC physical address of the shadow page.
4731 * @param iUser The shadow page pool index of the user table.
4732 * @param iUserTable The index into the user table (shadowed).
4733 */
4734void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4735{
4736 PVM pVM = pPool->CTX_SUFF(pVM);
4737
4738 STAM_PROFILE_START(&pPool->StatFree, a);
4739 LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%d iUserTable=%#x\n",
4740 pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4741 Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
4742 pgmLock(pVM);
4743 pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4744 if (!pPage->fCached)
4745 pgmPoolFlushPage(pPool, pPage);
4746 pgmUnlock(pVM);
4747 STAM_PROFILE_STOP(&pPool->StatFree, a);
4748}
4749
4750
4751/**
4752 * Makes one or more free page free.
4753 *
4754 * @returns VBox status code.
4755 * @retval VINF_SUCCESS on success.
4756 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4757 *
4758 * @param pPool The pool.
4759 * @param enmKind Page table kind
4760 * @param iUser The user of the page.
4761 */
4762static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4763{
4764 PVM pVM = pPool->CTX_SUFF(pVM);
4765
4766 LogFlow(("pgmPoolMakeMoreFreePages: iUser=%d\n", iUser));
4767
4768 /*
4769 * If the pool isn't full grown yet, expand it.
4770 */
4771 if ( pPool->cCurPages < pPool->cMaxPages
4772#if defined(IN_RC)
4773 /* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
4774 && enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4775 && (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD || enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
4776#endif
4777 )
4778 {
4779 STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4780#ifdef IN_RING3
4781 int rc = PGMR3PoolGrow(pVM);
4782#else
4783 int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4784#endif
4785 if (RT_FAILURE(rc))
4786 return rc;
4787 STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4788 if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4789 return VINF_SUCCESS;
4790 }
4791
4792 /*
4793 * Free one cached page.
4794 */
4795 return pgmPoolCacheFreeOne(pPool, iUser);
4796}
4797
4798/**
4799 * Allocates a page from the pool.
4800 *
4801 * This page may actually be a cached page and not in need of any processing
4802 * on the callers part.
4803 *
4804 * @returns VBox status code.
4805 * @retval VINF_SUCCESS if a NEW page was allocated.
4806 * @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4807 * @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4808 * @param pVM The VM handle.
4809 * @param GCPhys The GC physical address of the page we're gonna shadow.
4810 * For 4MB and 2MB PD entries, it's the first address the
4811 * shadow PT is covering.
4812 * @param enmKind The kind of mapping.
4813 * @param enmAccess Access type for the mapping (only relevant for big pages)
4814 * @param iUser The shadow page pool index of the user table.
4815 * @param iUserTable The index into the user table (shadowed).
4816 * @param fLockPage Lock the page
4817 * @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4818 */
4819int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable,
4820 bool fLockPage, PPPGMPOOLPAGE ppPage)
4821{
4822 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4823 STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4824 LogFlow(("pgmPoolAllocEx: GCPhys=%RGp enmKind=%s iUser=%d iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4825 *ppPage = NULL;
4826 /** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4827 * (TRPMR3SyncIDT) because of FF priority. Try fix that?
4828 * Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
4829
4830 pgmLock(pVM);
4831
4832 if (pPool->fCacheEnabled)
4833 {
4834 int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4835 if (RT_SUCCESS(rc2))
4836 {
4837 if (fLockPage)
4838 pgmPoolLockPage(pPool, *ppPage);
4839 pgmUnlock(pVM);
4840 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4841 LogFlow(("pgmPoolAllocEx: cached returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, *ppPage, (*ppPage)->Core.Key, (*ppPage)->idx));
4842 return rc2;
4843 }
4844 }
4845
4846 /*
4847 * Allocate a new one.
4848 */
4849 int rc = VINF_SUCCESS;
4850 uint16_t iNew = pPool->iFreeHead;
4851 if (iNew == NIL_PGMPOOL_IDX)
4852 {
4853 rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4854 if (RT_FAILURE(rc))
4855 {
4856 pgmUnlock(pVM);
4857 Log(("pgmPoolAllocEx: returns %Rrc (Free)\n", rc));
4858 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4859 return rc;
4860 }
4861 iNew = pPool->iFreeHead;
4862 AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4863 }
4864
4865 /* unlink the free head */
4866 PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4867 pPool->iFreeHead = pPage->iNext;
4868 pPage->iNext = NIL_PGMPOOL_IDX;
4869
4870 /*
4871 * Initialize it.
4872 */
4873 pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4874 pPage->enmKind = enmKind;
4875 pPage->enmAccess = enmAccess;
4876 pPage->GCPhys = GCPhys;
4877 pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4878 pPage->fMonitored = false;
4879 pPage->fCached = false;
4880#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4881 pPage->fDirty = false;
4882#endif
4883 pPage->fReusedFlushPending = false;
4884 pPage->cModifications = 0;
4885 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4886 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4887 pPage->cLocked = 0;
4888 pPage->cPresent = 0;
4889 pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
4890 pPage->pvLastAccessHandlerFault = 0;
4891 pPage->cLastAccessHandlerCount = 0;
4892 pPage->pvLastAccessHandlerRip = 0;
4893
4894 /*
4895 * Insert into the tracking and cache. If this fails, free the page.
4896 */
4897 int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4898 if (RT_FAILURE(rc3))
4899 {
4900 pPool->cUsedPages--;
4901 pPage->enmKind = PGMPOOLKIND_FREE;
4902 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4903 pPage->GCPhys = NIL_RTGCPHYS;
4904 pPage->iNext = pPool->iFreeHead;
4905 pPool->iFreeHead = pPage->idx;
4906 pgmUnlock(pVM);
4907 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4908 Log(("pgmPoolAllocEx: returns %Rrc (Insert)\n", rc3));
4909 return rc3;
4910 }
4911
4912 /*
4913 * Commit the allocation, clear the page and return.
4914 */
4915#ifdef VBOX_WITH_STATISTICS
4916 if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4917 pPool->cUsedPagesHigh = pPool->cUsedPages;
4918#endif
4919
4920 if (!pPage->fZeroed)
4921 {
4922 STAM_PROFILE_START(&pPool->StatZeroPage, z);
4923 void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4924 ASMMemZeroPage(pv);
4925 STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4926 }
4927
4928 *ppPage = pPage;
4929 if (fLockPage)
4930 pgmPoolLockPage(pPool, pPage);
4931 pgmUnlock(pVM);
4932 LogFlow(("pgmPoolAllocEx: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4933 rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4934 STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4935 return rc;
4936}
4937
4938
4939/**
4940 * Frees a usage of a pool page.
4941 *
4942 * @param pVM The VM handle.
4943 * @param HCPhys The HC physical address of the shadow page.
4944 * @param iUser The shadow page pool index of the user table.
4945 * @param iUserTable The index into the user table (shadowed).
4946 */
4947void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4948{
4949 LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%d iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4950 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4951 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4952}
4953
4954/**
4955 * Internal worker for finding a 'in-use' shadow page give by it's physical address.
4956 *
4957 * @returns Pointer to the shadow page structure.
4958 * @param pPool The pool.
4959 * @param HCPhys The HC physical address of the shadow page.
4960 */
4961PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4962{
4963 PVM pVM = pPool->CTX_SUFF(pVM);
4964
4965 Assert(PGMIsLockOwner(pVM));
4966
4967 /*
4968 * Look up the page.
4969 */
4970 PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4971
4972 AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4973 return pPage;
4974}
4975
4976
4977/**
4978 * Internal worker for finding a page for debugging purposes, no assertions.
4979 *
4980 * @returns Pointer to the shadow page structure. NULL on if not found.
4981 * @param pPool The pool.
4982 * @param HCPhys The HC physical address of the shadow page.
4983 */
4984PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys)
4985{
4986 PVM pVM = pPool->CTX_SUFF(pVM);
4987 Assert(PGMIsLockOwner(pVM));
4988 return (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4989}
4990
4991
4992#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
4993/**
4994 * Flush the specified page if present
4995 *
4996 * @param pVM The VM handle.
4997 * @param GCPhys Guest physical address of the page to flush
4998 */
4999void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
5000{
5001 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5002
5003 VM_ASSERT_EMT(pVM);
5004
5005 /*
5006 * Look up the GCPhys in the hash.
5007 */
5008 GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
5009 unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
5010 if (i == NIL_PGMPOOL_IDX)
5011 return;
5012
5013 do
5014 {
5015 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5016 if (pPage->GCPhys - GCPhys < PAGE_SIZE)
5017 {
5018 switch (pPage->enmKind)
5019 {
5020 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5021 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5022 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5023 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5024 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5025 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5026 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5027 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5028 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5029 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5030 case PGMPOOLKIND_64BIT_PML4:
5031 case PGMPOOLKIND_32BIT_PD:
5032 case PGMPOOLKIND_PAE_PDPT:
5033 {
5034 Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
5035#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5036 if (pPage->fDirty)
5037 STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
5038 else
5039#endif
5040 STAM_COUNTER_INC(&pPool->StatForceFlushPage);
5041 Assert(!pgmPoolIsPageLocked(&pVM->pgm.s, pPage));
5042 pgmPoolMonitorChainFlush(pPool, pPage);
5043 return;
5044 }
5045
5046 /* ignore, no monitoring. */
5047 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5048 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5049 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5050 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5051 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5052 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5053 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5054 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5055 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5056 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5057 case PGMPOOLKIND_ROOT_NESTED:
5058 case PGMPOOLKIND_PAE_PD_PHYS:
5059 case PGMPOOLKIND_PAE_PDPT_PHYS:
5060 case PGMPOOLKIND_32BIT_PD_PHYS:
5061 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5062 break;
5063
5064 default:
5065 AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
5066 }
5067 }
5068
5069 /* next */
5070 i = pPage->iNext;
5071 } while (i != NIL_PGMPOOL_IDX);
5072 return;
5073}
5074#endif /* IN_RING3 */
5075
5076#ifdef IN_RING3
5077
5078
5079/**
5080 * Reset CPU on hot plugging.
5081 *
5082 * @param pVM The VM handle.
5083 * @param pVCpu The virtual CPU.
5084 */
5085void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
5086{
5087 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
5088
5089 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5090 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5091 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5092}
5093
5094
5095/**
5096 * Flushes the entire cache.
5097 *
5098 * It will assert a global CR3 flush (FF) and assumes the caller is aware of
5099 * this and execute this CR3 flush.
5100 *
5101 * @param pPool The pool.
5102 */
5103void pgmR3PoolReset(PVM pVM)
5104{
5105 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5106
5107 Assert(PGMIsLockOwner(pVM));
5108 STAM_PROFILE_START(&pPool->StatR3Reset, a);
5109 LogFlow(("pgmR3PoolReset:\n"));
5110
5111 /*
5112 * If there are no pages in the pool, there is nothing to do.
5113 */
5114 if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5115 {
5116 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5117 return;
5118 }
5119
5120 /*
5121 * Exit the shadow mode since we're going to clear everything,
5122 * including the root page.
5123 */
5124 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5125 {
5126 PVMCPU pVCpu = &pVM->aCpus[i];
5127 pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
5128 }
5129
5130 /*
5131 * Nuke the free list and reinsert all pages into it.
5132 */
5133 for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5134 {
5135 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5136
5137 Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
5138 if (pPage->fMonitored)
5139 pgmPoolMonitorFlush(pPool, pPage);
5140 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5141 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5142 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5143 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5144 pPage->cModifications = 0;
5145 pPage->GCPhys = NIL_RTGCPHYS;
5146 pPage->enmKind = PGMPOOLKIND_FREE;
5147 pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5148 Assert(pPage->idx == i);
5149 pPage->iNext = i + 1;
5150 pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5151 pPage->fSeenNonGlobal = false;
5152 pPage->fMonitored = false;
5153#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5154 pPage->fDirty = false;
5155#endif
5156 pPage->fCached = false;
5157 pPage->fReusedFlushPending = false;
5158 pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5159 pPage->iAgeNext = NIL_PGMPOOL_IDX;
5160 pPage->iAgePrev = NIL_PGMPOOL_IDX;
5161 pPage->cLocked = 0;
5162 }
5163 pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5164 pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5165 pPool->cUsedPages = 0;
5166
5167 /*
5168 * Zap and reinitialize the user records.
5169 */
5170 pPool->cPresent = 0;
5171 pPool->iUserFreeHead = 0;
5172 PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5173 const unsigned cMaxUsers = pPool->cMaxUsers;
5174 for (unsigned i = 0; i < cMaxUsers; i++)
5175 {
5176 paUsers[i].iNext = i + 1;
5177 paUsers[i].iUser = NIL_PGMPOOL_IDX;
5178 paUsers[i].iUserTable = 0xfffffffe;
5179 }
5180 paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5181
5182 /*
5183 * Clear all the GCPhys links and rebuild the phys ext free list.
5184 */
5185 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
5186 pRam;
5187 pRam = pRam->CTX_SUFF(pNext))
5188 {
5189 unsigned iPage = pRam->cb >> PAGE_SHIFT;
5190 while (iPage-- > 0)
5191 PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
5192 }
5193
5194 pPool->iPhysExtFreeHead = 0;
5195 PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5196 const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5197 for (unsigned i = 0; i < cMaxPhysExts; i++)
5198 {
5199 paPhysExts[i].iNext = i + 1;
5200 paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5201 paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5202 paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5203 paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5204 paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5205 paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5206 }
5207 paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5208
5209 /*
5210 * Just zap the modified list.
5211 */
5212 pPool->cModifiedPages = 0;
5213 pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5214
5215 /*
5216 * Clear the GCPhys hash and the age list.
5217 */
5218 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5219 pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5220 pPool->iAgeHead = NIL_PGMPOOL_IDX;
5221 pPool->iAgeTail = NIL_PGMPOOL_IDX;
5222
5223#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5224 /* Clear all dirty pages. */
5225 pPool->idxFreeDirtyPage = 0;
5226 pPool->cDirtyPages = 0;
5227 for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
5228 pPool->aDirtyPages[i].uIdx = NIL_PGMPOOL_IDX;
5229#endif
5230
5231 /*
5232 * Reinsert active pages into the hash and ensure monitoring chains are correct.
5233 */
5234 for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
5235 {
5236 PPGMPOOLPAGE pPage = &pPool->aPages[i];
5237 pPage->iNext = NIL_PGMPOOL_IDX;
5238 pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5239 pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5240 pPage->cModifications = 0;
5241 /* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
5242 pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5243 pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5244 if (pPage->fMonitored)
5245 {
5246 int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK,
5247 pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
5248 pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
5249 pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
5250 pPool->pszAccessHandler);
5251 AssertFatalRCSuccess(rc);
5252 pgmPoolHashInsert(pPool, pPage);
5253 }
5254 Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
5255 Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
5256 Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
5257 }
5258
5259 for (VMCPUID i = 0; i < pVM->cCpus; i++)
5260 {
5261 /*
5262 * Re-enter the shadowing mode and assert Sync CR3 FF.
5263 */
5264 PVMCPU pVCpu = &pVM->aCpus[i];
5265 pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5266 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5267 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5268 }
5269
5270 STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5271}
5272#endif /* IN_RING3 */
5273
5274#ifdef LOG_ENABLED
5275static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5276{
5277 switch(enmKind)
5278 {
5279 case PGMPOOLKIND_INVALID:
5280 return "PGMPOOLKIND_INVALID";
5281 case PGMPOOLKIND_FREE:
5282 return "PGMPOOLKIND_FREE";
5283 case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5284 return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5285 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5286 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5287 case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5288 return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5289 case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5290 return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5291 case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5292 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5293 case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5294 return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5295 case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5296 return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5297 case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5298 return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5299 case PGMPOOLKIND_32BIT_PD:
5300 return "PGMPOOLKIND_32BIT_PD";
5301 case PGMPOOLKIND_32BIT_PD_PHYS:
5302 return "PGMPOOLKIND_32BIT_PD_PHYS";
5303 case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5304 return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5305 case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5306 return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5307 case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5308 return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5309 case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5310 return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5311 case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5312 return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5313 case PGMPOOLKIND_PAE_PD_PHYS:
5314 return "PGMPOOLKIND_PAE_PD_PHYS";
5315 case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5316 return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5317 case PGMPOOLKIND_PAE_PDPT:
5318 return "PGMPOOLKIND_PAE_PDPT";
5319 case PGMPOOLKIND_PAE_PDPT_PHYS:
5320 return "PGMPOOLKIND_PAE_PDPT_PHYS";
5321 case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5322 return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5323 case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5324 return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5325 case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5326 return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5327 case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5328 return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5329 case PGMPOOLKIND_64BIT_PML4:
5330 return "PGMPOOLKIND_64BIT_PML4";
5331 case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5332 return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5333 case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5334 return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5335 case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5336 return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5337 case PGMPOOLKIND_ROOT_NESTED:
5338 return "PGMPOOLKIND_ROOT_NESTED";
5339 }
5340 return "Unknown kind!";
5341}
5342#endif /* LOG_ENABLED*/
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