PGMAllPool.cpp@ 86667

Last change on this file since 86667 was 86489, checked in by vboxsync, 4 years ago
VMM/PGM: Working on eliminating page table bitfield use (32-bit PTEs). bugref:9841 bugref:9746
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1	/* $Id: PGMAllPool.cpp 86489 2020-10-08 09:11:54Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PGM_POOL
23	#define VBOX_WITHOUT_PAGING_BIT_FIELDS /* 64-bit bitfields are just asking for trouble. See @bugref{9841} and others. */
24	#include <VBox/vmm/pgm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/em.h>
27	#include <VBox/vmm/cpum.h>
28	#include "PGMInternal.h"
29	#include <VBox/vmm/vmcc.h>
30	#include "PGMInline.h"
31	#include <VBox/disopcode.h>
32	#include <VBox/vmm/hm_vmx.h>
33
34	#include <VBox/log.h>
35	#include <VBox/err.h>
36	#include <iprt/asm.h>
37	#include <iprt/asm-amd64-x86.h>
38	#include <iprt/string.h>
39
40
41	/*********************************************************************************************************************************
42	* Internal Functions *
43	*********************************************************************************************************************************/
44	RT_C_DECLS_BEGIN
45	#if 0 /* unused */
46	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
47	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
48	#endif /* unused */
49	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
50	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
51	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
52	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
53	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
54	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
55	#endif
56	#if 0 /defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT)/
57	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT);
58	#endif
59
60	int pgmPoolTrackFlushGCPhysPTsSlow(PVMCC pVM, PPGMPAGE pPhysPage);
61	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
62	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
63	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
64
65	RT_C_DECLS_END
66
67
68	#if 0 /* unused */
69	/**
70	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
71	*
72	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
73	* @param enmKind The page kind.
74	*/
75	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
76	{
77	switch (enmKind)
78	{
79	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
80	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
81	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
82	return true;
83	default:
84	return false;
85	}
86	}
87	#endif /* unused */
88
89
90	/**
91	* Flushes a chain of pages sharing the same access monitor.
92	*
93	* @param pPool The pool.
94	* @param pPage A page in the chain.
95	*/
96	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
97	{
98	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
99
100	/*
101	* Find the list head.
102	*/
103	uint16_t idx = pPage->idx;
104	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
105	{
106	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
107	{
108	idx = pPage->iMonitoredPrev;
109	Assert(idx != pPage->idx);
110	pPage = &pPool->aPages[idx];
111	}
112	}
113
114	/*
115	* Iterate the list flushing each shadow page.
116	*/
117	for (;;)
118	{
119	idx = pPage->iMonitoredNext;
120	Assert(idx != pPage->idx);
121	if (pPage->idx >= PGMPOOL_IDX_FIRST)
122	{
123	int rc2 = pgmPoolFlushPage(pPool, pPage);
124	AssertRC(rc2);
125	}
126	/* next */
127	if (idx == NIL_PGMPOOL_IDX)
128	break;
129	pPage = &pPool->aPages[idx];
130	}
131	}
132
133
134	/**
135	* Wrapper for getting the current context pointer to the entry being modified.
136	*
137	* @returns VBox status code suitable for scheduling.
138	* @param pVM The cross context VM structure.
139	* @param pvDst Destination address
140	* @param pvSrc Pointer to the mapping of @a GCPhysSrc or NULL depending
141	* on the context (e.g. \#PF in R0 & RC).
142	* @param GCPhysSrc The source guest physical address.
143	* @param cb Size of data to read
144	*/
145	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVMCC pVM, void pvDst, void const pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
146	{
147	#if defined(IN_RING3)
148	NOREF(pVM); NOREF(GCPhysSrc);
149	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
150	return VINF_SUCCESS;
151	#else
152	/** @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
153	NOREF(pvSrc);
154	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
155	#endif
156	}
157
158
159	/**
160	* Process shadow entries before they are changed by the guest.
161	*
162	* For PT entries we will clear them. For PD entries, we'll simply check
163	* for mapping conflicts and set the SyncCR3 FF if found.
164	*
165	* @param pVCpu The cross context virtual CPU structure.
166	* @param pPool The pool.
167	* @param pPage The head page.
168	* @param GCPhysFault The guest physical fault address.
169	* @param pvAddress Pointer to the mapping of @a GCPhysFault or NULL
170	* depending on the context (e.g. \#PF in R0 & RC).
171	* @param cbWrite Write size; might be zero if the caller knows we're not crossing entry boundaries
172	*/
173	static void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault,
174	void const *pvAddress, unsigned cbWrite)
175	{
176	AssertMsg(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX, ("%u (idx=%u)\n", pPage->iMonitoredPrev, pPage->idx));
177	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
178	PVMCC pVM = pPool->CTX_SUFF(pVM);
179	NOREF(pVCpu);
180
181	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp cbWrite=%d\n",
182	(RTGCPTR)(CTXTYPE(RTGCPTR, uintptr_t, RTGCPTR))(uintptr_t)pvAddress, GCPhysFault, cbWrite));
183
184	for (;;)
185	{
186	union
187	{
188	void *pv;
189	PX86PT pPT;
190	PPGMSHWPTPAE pPTPae;
191	PX86PD pPD;
192	PX86PDPAE pPDPae;
193	PX86PDPT pPDPT;
194	PX86PML4 pPML4;
195	} uShw;
196
197	LogFlow(("pgmPoolMonitorChainChanging: page idx=%d phys=%RGp (next=%d) kind=%s write=%#x\n",
198	pPage->idx, pPage->GCPhys, pPage->iMonitoredNext, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
199
200	uShw.pv = NULL;
201	switch (pPage->enmKind)
202	{
203	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
204	{
205	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
206	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
207	const unsigned iShw = off / sizeof(X86PTE);
208	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
209	X86PGUINT const uPde = uShw.pPT->a[iShw].u;
210	if (uPde & X86_PTE_P)
211	{
212	X86PTE GstPte;
213	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
214	AssertRC(rc);
215	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uPde & X86_PTE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
216	pgmPoolTracDerefGCPhysHint(pPool, pPage, uPde & X86_PTE_PG_MASK, GstPte.u & X86_PTE_PG_MASK, iShw);
217	ASMAtomicWriteU32(&uShw.pPT->a[iShw].u, 0);
218	}
219	break;
220	}
221
222	/* page/2 sized */
223	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
224	{
225	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
226	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
227	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
228	{
229	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
230	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
231	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
232	{
233	X86PTE GstPte;
234	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
235	AssertRC(rc);
236
237	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
238	pgmPoolTracDerefGCPhysHint(pPool, pPage,
239	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
240	GstPte.u & X86_PTE_PG_MASK,
241	iShw);
242	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
243	}
244	}
245	break;
246	}
247
248	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
249	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
250	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
251	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
252	{
253	unsigned iGst = off / sizeof(X86PDE);
254	unsigned iShwPdpt = iGst / 256;
255	unsigned iShw = (iGst % 256) * 2;
256	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
257
258	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
259	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
260	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
261	{
262	for (unsigned i = 0; i < 2; i++)
263	{
264	X86PGPAEUINT const uPde = uShw.pPDPae->a[iShw + i].u;
265	if (uPde & X86_PDE_P)
266	{
267	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw + i, uPde));
268	pgmPoolFree(pVM, uPde & X86_PDE_PAE_PG_MASK, pPage->idx, iShw + i);
269	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw + i].u, 0);
270	}
271
272	/* paranoia / a bit assumptive. */
273	if ( (off & 3)
274	&& (off & 3) + cbWrite > 4)
275	{
276	const unsigned iShw2 = iShw + 2 + i;
277	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
278	{
279	X86PGPAEUINT const uPde2 = uShw.pPDPae->a[iShw2].u;
280	if (uPde2 & X86_PDE_P)
281	{
282	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uPde2));
283	pgmPoolFree(pVM, uPde2 & X86_PDE_PAE_PG_MASK, pPage->idx, iShw2);
284	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
285	}
286	}
287	}
288	}
289	}
290	break;
291	}
292
293	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
294	{
295	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
296	const unsigned iShw = off / sizeof(X86PTEPAE);
297	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPT));
298	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw]))
299	{
300	X86PTEPAE GstPte;
301	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
302	AssertRC(rc);
303
304	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]), GstPte.u & X86_PTE_PAE_PG_MASK));
305	pgmPoolTracDerefGCPhysHint(pPool, pPage,
306	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw]),
307	GstPte.u & X86_PTE_PAE_PG_MASK,
308	iShw);
309	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw], 0);
310	}
311
312	/* paranoia / a bit assumptive. */
313	if ( (off & 7)
314	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
315	{
316	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
317	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
318
319	if (PGMSHWPTEPAE_IS_P(uShw.pPTPae->a[iShw2]))
320	{
321	X86PTEPAE GstPte;
322	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte,
323	pvAddress ? (uint8_t const *)pvAddress + sizeof(GstPte) : NULL,
324	GCPhysFault + sizeof(GstPte), sizeof(GstPte));
325	AssertRC(rc);
326	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]), GstPte.u & X86_PTE_PAE_PG_MASK));
327	pgmPoolTracDerefGCPhysHint(pPool, pPage,
328	PGMSHWPTEPAE_GET_HCPHYS(uShw.pPTPae->a[iShw2]),
329	GstPte.u & X86_PTE_PAE_PG_MASK,
330	iShw2);
331	PGMSHWPTEPAE_ATOMIC_SET(uShw.pPTPae->a[iShw2], 0);
332	}
333	}
334	break;
335	}
336
337	case PGMPOOLKIND_32BIT_PD:
338	{
339	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
340	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
341
342	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
343	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
344	X86PGUINT const uPde = uShw.pPD->a[iShw].u;
345	if (uPde & X86_PDE_P)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uPde));
348	pgmPoolFree(pVM, uPde & X86_PDE_PG_MASK, pPage->idx, iShw);
349	ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
350	}
351
352	/* paranoia / a bit assumptive. */
353	if ( (off & 3)
354	&& (off & 3) + cbWrite > sizeof(X86PTE))
355	{
356	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
357	if ( iShw2 != iShw
358	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
359	{
360	X86PGUINT const uPde2 = uShw.pPD->a[iShw2].u;
361	if (uPde2 & X86_PDE_P)
362	{
363	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uPde2));
364	pgmPoolFree(pVM, uPde2 & X86_PDE_PG_MASK, pPage->idx, iShw2);
365	ASMAtomicWriteU32(&uShw.pPD->a[iShw2].u, 0);
366	}
367	}
368	}
369	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). - not working any longer... */
370	if ( uShw.pPD->a[iShw].n.u1Present
371	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
372	{
373	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
374	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
375	ASMAtomicWriteU32(&uShw.pPD->a[iShw].u, 0);
376	}
377	#endif
378	break;
379	}
380
381	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
382	{
383	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
384	const unsigned iShw = off / sizeof(X86PDEPAE);
385	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
386
387	/*
388	* Causes trouble when the guest uses a PDE to refer to the whole page table level
389	* structure. (Invalidate here; faults later on when it tries to change the page
390	* table entries -> recheck; probably only applies to the RC case.)
391	*/
392	X86PGPAEUINT const uPde = uShw.pPDPae->a[iShw].u;
393	if (uPde & X86_PDE_P)
394	{
395	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uPde));
396	pgmPoolFree(pVM, uPde & X86_PDE_PAE_PG_MASK, pPage->idx, iShw);
397	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
398	}
399
400	/* paranoia / a bit assumptive. */
401	if ( (off & 7)
402	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
403	{
404	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
405	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
406
407	X86PGPAEUINT const uPde2 = uShw.pPDPae->a[iShw2].u;
408	if (uPde2 & X86_PDE_P)
409	{
410	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uPde2));
411	pgmPoolFree(pVM, uPde2 & X86_PDE_PAE_PG_MASK, pPage->idx, iShw2);
412	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
413	}
414	}
415	break;
416	}
417
418	case PGMPOOLKIND_PAE_PDPT:
419	{
420	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
421	/*
422	* Hopefully this doesn't happen very often:
423	* - touching unused parts of the page
424	* - messing with the bits of pd pointers without changing the physical address
425	*/
426	/* PDPT roots are not page aligned; 32 byte only! */
427	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
428
429	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
430	const unsigned iShw = offPdpt / sizeof(X86PDPE);
431	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
432	{
433	X86PGPAEUINT const uPdpe = uShw.pPDPT->a[iShw].u;
434	if (uPdpe & X86_PDPE_P)
435	{
436	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
437	pgmPoolFree(pVM, uPdpe & X86_PDPE_PG_MASK, pPage->idx, iShw);
438	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
439	}
440
441	/* paranoia / a bit assumptive. */
442	if ( (offPdpt & 7)
443	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
444	{
445	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
446	if ( iShw2 != iShw
447	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
448	{
449	X86PGPAEUINT const uPdpe2 = uShw.pPDPT->a[iShw2].u;
450	if (uPdpe2 & X86_PDPE_P)
451	{
452	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
453	pgmPoolFree(pVM, uPdpe2 & X86_PDPE_PG_MASK, pPage->idx, iShw2);
454	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
455	}
456	}
457	}
458	}
459	break;
460	}
461
462	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
463	{
464	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPD));
465	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
466	const unsigned iShw = off / sizeof(X86PDEPAE);
467	X86PGPAEUINT const uPde = uShw.pPDPae->a[iShw].u;
468	#ifndef PGM_WITHOUT_MAPPINGS
469	Assert(!(uPde & PGM_PDFLAGS_MAPPING));
470	#endif
471	if (uPde & X86_PDE_P)
472	{
473	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uPde));
474	pgmPoolFree(pVM, uPde & X86_PDE_PAE_PG_MASK, pPage->idx, iShw);
475	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw].u, 0);
476	}
477
478	/* paranoia / a bit assumptive. */
479	if ( (off & 7)
480	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
481	{
482	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
483	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
484	X86PGPAEUINT const uPde2 = uShw.pPDPae->a[iShw2].u;
485	#ifndef PGM_WITHOUT_MAPPINGS
486	Assert(!(uPde2 & PGM_PDFLAGS_MAPPING));
487	#endif
488	if (uPde2 & X86_PDE_P)
489	{
490	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uPde2));
491	pgmPoolFree(pVM, uPde2 & X86_PDE_PAE_PG_MASK, pPage->idx, iShw2);
492	ASMAtomicWriteU64(&uShw.pPDPae->a[iShw2].u, 0);
493	}
494	}
495	break;
496	}
497
498	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
499	{
500	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPDPT));
501	/*
502	* Hopefully this doesn't happen very often:
503	* - messing with the bits of pd pointers without changing the physical address
504	*/
505	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
506	const unsigned iShw = off / sizeof(X86PDPE);
507	X86PGPAEUINT const uPdpe = uShw.pPDPT->a[iShw].u;
508	if (uPdpe & X86_PDPE_P)
509	{
510	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uPdpe));
511	pgmPoolFree(pVM, uPdpe & X86_PDPE_PG_MASK, pPage->idx, iShw);
512	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw].u, 0);
513	}
514	/* paranoia / a bit assumptive. */
515	if ( (off & 7)
516	&& (off & 7) + cbWrite > sizeof(X86PDPE))
517	{
518	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
519	X86PGPAEUINT const uPdpe2 = uShw.pPDPT->a[iShw2].u;
520	if (uPdpe2 & X86_PDPE_P)
521	{
522	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uPdpe2));
523	pgmPoolFree(pVM, uPdpe2 & X86_PDPE_PG_MASK, pPage->idx, iShw2);
524	ASMAtomicWriteU64(&uShw.pPDPT->a[iShw2].u, 0);
525	}
526	}
527	break;
528	}
529
530	case PGMPOOLKIND_64BIT_PML4:
531	{
532	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,FaultPML4));
533	/*
534	* Hopefully this doesn't happen very often:
535	* - messing with the bits of pd pointers without changing the physical address
536	*/
537	uShw.pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
538	const unsigned iShw = off / sizeof(X86PDPE);
539	X86PGPAEUINT const uPml4e = uShw.pPML4->a[iShw].u;
540	if (uPml4e & X86_PML4E_P)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uPml4e));
543	pgmPoolFree(pVM, uPml4e & X86_PML4E_PG_MASK, pPage->idx, iShw);
544	ASMAtomicWriteU64(&uShw.pPML4->a[iShw].u, 0);
545	}
546	/* paranoia / a bit assumptive. */
547	if ( (off & 7)
548	&& (off & 7) + cbWrite > sizeof(X86PDPE))
549	{
550	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
551	X86PGPAEUINT const uPml4e2 = uShw.pPML4->a[iShw2].u;
552	if (uPml4e2 & X86_PML4E_P)
553	{
554	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uPml4e2));
555	pgmPoolFree(pVM, uPml4e2 & X86_PML4E_PG_MASK, pPage->idx, iShw2);
556	ASMAtomicWriteU64(&uShw.pPML4->a[iShw2].u, 0);
557	}
558	}
559	break;
560	}
561
562	default:
563	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
564	}
565	PGM_DYNMAP_UNUSED_HINT_VM(pVM, uShw.pv);
566
567	/* next */
568	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
569	return;
570	pPage = &pPool->aPages[pPage->iMonitoredNext];
571	}
572	}
573
574	#ifndef IN_RING3
575
576	/**
577	* Checks if a access could be a fork operation in progress.
578	*
579	* Meaning, that the guest is setting up the parent process for Copy-On-Write.
580	*
581	* @returns true if it's likely that we're forking, otherwise false.
582	* @param pPool The pool.
583	* @param pDis The disassembled instruction.
584	* @param offFault The access offset.
585	*/
586	DECLINLINE(bool) pgmRZPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pDis, unsigned offFault)
587	{
588	/*
589	* i386 linux is using btr to clear X86_PTE_RW.
590	* The functions involved are (2.6.16 source inspection):
591	* clear_bit
592	* ptep_set_wrprotect
593	* copy_one_pte
594	* copy_pte_range
595	* copy_pmd_range
596	* copy_pud_range
597	* copy_page_range
598	* dup_mmap
599	* dup_mm
600	* copy_mm
601	* copy_process
602	* do_fork
603	*/
604	if ( pDis->pCurInstr->uOpcode == OP_BTR
605	&& !(offFault & 4)
606	/** @todo Validate that the bit index is X86_PTE_RW. */
607	)
608	{
609	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitorPf,Fork)); RT_NOREF_PV(pPool);
610	return true;
611	}
612	return false;
613	}
614
615
616	/**
617	* Determine whether the page is likely to have been reused.
618	*
619	* @returns true if we consider the page as being reused for a different purpose.
620	* @returns false if we consider it to still be a paging page.
621	* @param pVM The cross context VM structure.
622	* @param pVCpu The cross context virtual CPU structure.
623	* @param pRegFrame Trap register frame.
624	* @param pDis The disassembly info for the faulting instruction.
625	* @param pvFault The fault address.
626	* @param pPage The pool page being accessed.
627	*
628	* @remark The REP prefix check is left to the caller because of STOSD/W.
629	*/
630	DECLINLINE(bool) pgmRZPoolMonitorIsReused(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pDis, RTGCPTR pvFault,
631	PPGMPOOLPAGE pPage)
632	{
633	/* Locked (CR3, PDPTR*4) should not be reusable. Considering them as
634	such may cause loops booting tst-ubuntu-15_10-64-efi, ++. */
635	if (pPage->cLocked)
636	{
637	Log2(("pgmRZPoolMonitorIsReused: %RGv (%p) can't have been resued, because it's locked!\n", pvFault, pPage));
638	return false;
639	}
640
641	/** @todo could make this general, faulting close to rsp should be a safe reuse heuristic. */
642	if ( HMHasPendingIrq(pVM)
643	&& pRegFrame->rsp - pvFault < 32)
644	{
645	/* Fault caused by stack writes while trying to inject an interrupt event. */
646	Log(("pgmRZPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
647	return true;
648	}
649
650	LogFlow(("Reused instr %RGv %d at %RGv param1.fUse=%llx param1.reg=%d\n", pRegFrame->rip, pDis->pCurInstr->uOpcode, pvFault, pDis->Param1.fUse, pDis->Param1.Base.idxGenReg));
651
652	/* Non-supervisor mode write means it's used for something else. */
653	if (CPUMGetGuestCPL(pVCpu) == 3)
654	return true;
655
656	switch (pDis->pCurInstr->uOpcode)
657	{
658	/* call implies the actual push of the return address faulted */
659	case OP_CALL:
660	Log4(("pgmRZPoolMonitorIsReused: CALL\n"));
661	return true;
662	case OP_PUSH:
663	Log4(("pgmRZPoolMonitorIsReused: PUSH\n"));
664	return true;
665	case OP_PUSHF:
666	Log4(("pgmRZPoolMonitorIsReused: PUSHF\n"));
667	return true;
668	case OP_PUSHA:
669	Log4(("pgmRZPoolMonitorIsReused: PUSHA\n"));
670	return true;
671	case OP_FXSAVE:
672	Log4(("pgmRZPoolMonitorIsReused: FXSAVE\n"));
673	return true;
674	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
675	Log4(("pgmRZPoolMonitorIsReused: MOVNTI\n"));
676	return true;
677	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
678	Log4(("pgmRZPoolMonitorIsReused: MOVNTDQ\n"));
679	return true;
680	case OP_MOVSWD:
681	case OP_STOSWD:
682	if ( pDis->fPrefix == (DISPREFIX_REP\|DISPREFIX_REX)
683	&& pRegFrame->rcx >= 0x40
684	)
685	{
686	Assert(pDis->uCpuMode == DISCPUMODE_64BIT);
687
688	Log(("pgmRZPoolMonitorIsReused: OP_STOSQ\n"));
689	return true;
690	}
691	break;
692
693	default:
694	/*
695	* Anything having ESP on the left side means stack writes.
696	*/
697	if ( ( (pDis->Param1.fUse & DISUSE_REG_GEN32)
698	\|\| (pDis->Param1.fUse & DISUSE_REG_GEN64))
699	&& (pDis->Param1.Base.idxGenReg == DISGREG_ESP))
700	{
701	Log4(("pgmRZPoolMonitorIsReused: ESP\n"));
702	return true;
703	}
704	break;
705	}
706
707	/*
708	* Page table updates are very very unlikely to be crossing page boundraries,
709	* and we don't want to deal with that in pgmPoolMonitorChainChanging and such.
710	*/
711	uint32_t const cbWrite = DISGetParamSize(pDis, &pDis->Param1);
712	if ( (((uintptr_t)pvFault + cbWrite) >> X86_PAGE_SHIFT) != ((uintptr_t)pvFault >> X86_PAGE_SHIFT) )
713	{
714	Log4(("pgmRZPoolMonitorIsReused: cross page write\n"));
715	return true;
716	}
717
718	/*
719	* Nobody does an unaligned 8 byte write to a page table, right.
720	*/
721	if (cbWrite >= 8 && ((uintptr_t)pvFault & 7) != 0)
722	{
723	Log4(("pgmRZPoolMonitorIsReused: Unaligned 8+ byte write\n"));
724	return true;
725	}
726
727	return false;
728	}
729
730
731	/**
732	* Flushes the page being accessed.
733	*
734	* @returns VBox status code suitable for scheduling.
735	* @param pVM The cross context VM structure.
736	* @param pVCpu The cross context virtual CPU structure.
737	* @param pPool The pool.
738	* @param pPage The pool page (head).
739	* @param pDis The disassembly of the write instruction.
740	* @param pRegFrame The trap register frame.
741	* @param GCPhysFault The fault address as guest physical address.
742	* @param pvFault The fault address.
743	* @todo VBOXSTRICTRC
744	*/
745	static int pgmRZPoolAccessPfHandlerFlush(PVMCC pVM, PVMCPUCC pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
746	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
747	{
748	NOREF(pVM); NOREF(GCPhysFault);
749
750	/*
751	* First, do the flushing.
752	*/
753	pgmPoolMonitorChainFlush(pPool, pPage);
754
755	/*
756	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
757	* Must do this in raw mode (!); XP boot will fail otherwise.
758	*/
759	int rc = VINF_SUCCESS;
760	VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
761	if (rc2 == VINF_SUCCESS)
762	{ /* do nothing */ }
763	else if (rc2 == VINF_EM_RESCHEDULE)
764	{
765	rc = VBOXSTRICTRC_VAL(rc2);
766	# ifndef IN_RING3
767	VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
768	# endif
769	}
770	else if (rc2 == VERR_EM_INTERPRETER)
771	{
772	rc = VINF_EM_RAW_EMULATE_INSTR;
773	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitorPf,EmulateInstr));
774	}
775	else if (RT_FAILURE_NP(rc2))
776	rc = VBOXSTRICTRC_VAL(rc2);
777	else
778	AssertMsgFailed(("%Rrc\n", VBOXSTRICTRC_VAL(rc2))); /* ASSUMES no complicated stuff here. */
779
780	LogFlow(("pgmRZPoolAccessPfHandlerFlush: returns %Rrc (flushed)\n", rc));
781	return rc;
782	}
783
784
785	/**
786	* Handles the STOSD write accesses.
787	*
788	* @returns VBox status code suitable for scheduling.
789	* @param pVM The cross context VM structure.
790	* @param pPool The pool.
791	* @param pPage The pool page (head).
792	* @param pDis The disassembly of the write instruction.
793	* @param pRegFrame The trap register frame.
794	* @param GCPhysFault The fault address as guest physical address.
795	* @param pvFault The fault address.
796	*/
797	DECLINLINE(int) pgmRZPoolAccessPfHandlerSTOSD(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
798	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
799	{
800	unsigned uIncrement = pDis->Param1.cb;
801	NOREF(pVM);
802
803	Assert(pDis->uCpuMode == DISCPUMODE_32BIT \|\| pDis->uCpuMode == DISCPUMODE_64BIT);
804	Assert(pRegFrame->rcx <= 0x20);
805
806	# ifdef VBOX_STRICT
807	if (pDis->uOpMode == DISCPUMODE_32BIT)
808	Assert(uIncrement == 4);
809	else
810	Assert(uIncrement == 8);
811	# endif
812
813	Log3(("pgmRZPoolAccessPfHandlerSTOSD\n"));
814
815	/*
816	* Increment the modification counter and insert it into the list
817	* of modified pages the first time.
818	*/
819	if (!pPage->cModifications++)
820	pgmPoolMonitorModifiedInsert(pPool, pPage);
821
822	/*
823	* Execute REP STOSD.
824	*
825	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
826	* write situation, meaning that it's safe to write here.
827	*/
828	PVMCPUCC pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
829	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
830	while (pRegFrame->rcx)
831	{
832	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
833	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
834	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, NULL, uIncrement);
835	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
836	# else
837	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, NULL, uIncrement);
838	# endif
839	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->rax, uIncrement);
840	pu32 += uIncrement;
841	GCPhysFault += uIncrement;
842	pRegFrame->rdi += uIncrement;
843	pRegFrame->rcx--;
844	}
845	pRegFrame->rip += pDis->cbInstr;
846
847	LogFlow(("pgmRZPoolAccessPfHandlerSTOSD: returns\n"));
848	return VINF_SUCCESS;
849	}
850
851
852	/**
853	* Handles the simple write accesses.
854	*
855	* @returns VBox status code suitable for scheduling.
856	* @param pVM The cross context VM structure.
857	* @param pVCpu The cross context virtual CPU structure.
858	* @param pPool The pool.
859	* @param pPage The pool page (head).
860	* @param pDis The disassembly of the write instruction.
861	* @param pRegFrame The trap register frame.
862	* @param GCPhysFault The fault address as guest physical address.
863	* @param pvFault The fault address.
864	* @param pfReused Reused state (in/out)
865	*/
866	DECLINLINE(int) pgmRZPoolAccessPfHandlerSimple(PVMCC pVM, PVMCPUCC pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pDis,
867	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault, bool *pfReused)
868	{
869	Log3(("pgmRZPoolAccessPfHandlerSimple\n"));
870	NOREF(pVM);
871	NOREF(pfReused); /* initialized by caller */
872
873	/*
874	* Increment the modification counter and insert it into the list
875	* of modified pages the first time.
876	*/
877	if (!pPage->cModifications++)
878	pgmPoolMonitorModifiedInsert(pPool, pPage);
879
880	/*
881	* Clear all the pages. ASSUMES that pvFault is readable.
882	*/
883	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
884	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
885	# endif
886
887	uint32_t cbWrite = DISGetParamSize(pDis, &pDis->Param1);
888	if (cbWrite <= 8)
889	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, NULL, cbWrite);
890	else if (cbWrite <= 16)
891	{
892	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, NULL, 8);
893	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault + 8, NULL, cbWrite - 8);
894	}
895	else
896	{
897	Assert(cbWrite <= 32);
898	for (uint32_t off = 0; off < cbWrite; off += 8)
899	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault + off, NULL, RT_MIN(8, cbWrite - off));
900	}
901
902	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
903	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
904	# endif
905
906	/*
907	* Interpret the instruction.
908	*/
909	VBOXSTRICTRC rc = EMInterpretInstructionDisasState(pVCpu, pDis, pRegFrame, pvFault, EMCODETYPE_ALL);
910	if (RT_SUCCESS(rc))
911	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rc))); /* ASSUMES no complicated stuff here. */
912	else if (rc == VERR_EM_INTERPRETER)
913	{
914	LogFlow(("pgmRZPoolAccessPfHandlerSimple: Interpretation failed for %04x:%RGv - opcode=%d\n",
915	pRegFrame->cs.Sel, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode));
916	rc = VINF_EM_RAW_EMULATE_INSTR;
917	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitorPf,EmulateInstr));
918	}
919
920	# if 0 /* experimental code */
921	if (rc == VINF_SUCCESS)
922	{
923	switch (pPage->enmKind)
924	{
925	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
926	{
927	X86PTEPAE GstPte;
928	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvFault, GCPhysFault, sizeof(GstPte));
929	AssertRC(rc);
930
931	/* Check the new value written by the guest. If present and with a bogus physical address, then
932	* it's fairly safe to assume the guest is reusing the PT.
933	*/
934	if (GstPte.n.u1Present)
935	{
936	RTHCPHYS HCPhys = -1;
937	int rc = PGMPhysGCPhys2HCPhys(pVM, GstPte.u & X86_PTE_PAE_PG_MASK, &HCPhys);
938	if (rc != VINF_SUCCESS)
939	{
940	*pfReused = true;
941	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
942	}
943	}
944	break;
945	}
946	}
947	}
948	# endif
949
950	LogFlow(("pgmRZPoolAccessPfHandlerSimple: returns %Rrc\n", VBOXSTRICTRC_VAL(rc)));
951	return VBOXSTRICTRC_VAL(rc);
952	}
953
954
955	/**
956	* @callback_method_impl{FNPGMRZPHYSPFHANDLER,
957	* \#PF access handler callback for page table pages.}
958	*
959	* @remarks The @a pvUser argument points to the PGMPOOLPAGE.
960	*/
961	DECLEXPORT(VBOXSTRICTRC) pgmRZPoolAccessPfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
962	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
963	{
964	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->StatMonitorRZ, a);
965	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
966	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
967	unsigned cMaxModifications;
968	bool fForcedFlush = false;
969	NOREF(uErrorCode);
970
971	LogFlow(("pgmRZPoolAccessPfHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
972
973	pgmLock(pVM);
974	if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
975	{
976	/* Pool page changed while we were waiting for the lock; ignore. */
977	Log(("CPU%d: pgmRZPoolAccessPfHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
978	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->StatMonitorPfRZ, &pPool->StatMonitorPfRZHandled, a);
979	pgmUnlock(pVM);
980	return VINF_SUCCESS;
981	}
982	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
983	if (pPage->fDirty)
984	{
985	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH));
986	pgmUnlock(pVM);
987	return VINF_SUCCESS; /* SMP guest case where we were blocking on the pgm lock while the same page was being marked dirty. */
988	}
989	# endif
990
991	# if 0 /* test code defined(VBOX_STRICT) && defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) */
992	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
993	{
994	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
995	void *pvGst;
996	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
997	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
998	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
999	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1000	}
1001	# endif
1002
1003	/*
1004	* Disassemble the faulting instruction.
1005	*/
1006	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
1007	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
1008	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1009	{
1010	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("Unexpected rc %d\n", rc));
1011	pgmUnlock(pVM);
1012	return rc;
1013	}
1014
1015	Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1016
1017	/*
1018	* We should ALWAYS have the list head as user parameter. This
1019	* is because we use that page to record the changes.
1020	*/
1021	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1022
1023	# ifdef IN_RING0
1024	/* Maximum nr of modifications depends on the page type. */
1025	if ( pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1026	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1027	cMaxModifications = 4;
1028	else
1029	cMaxModifications = 24;
1030	# else
1031	cMaxModifications = 48;
1032	# endif
1033
1034	/*
1035	* Incremental page table updates should weigh more than random ones.
1036	* (Only applies when started from offset 0)
1037	*/
1038	pVCpu->pgm.s.cPoolAccessHandler++;
1039	if ( pPage->GCPtrLastAccessHandlerRip >= pRegFrame->rip - 0x40 /* observed loops in Windows 7 x64 */
1040	&& pPage->GCPtrLastAccessHandlerRip < pRegFrame->rip + 0x40
1041	&& pvFault == (pPage->GCPtrLastAccessHandlerFault + pDis->Param1.cb)
1042	&& pVCpu->pgm.s.cPoolAccessHandler == pPage->cLastAccessHandler + 1)
1043	{
1044	Log(("Possible page reuse cMods=%d -> %d (locked=%d type=%s)\n", pPage->cModifications, pPage->cModifications * 2, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1045	Assert(pPage->cModifications < 32000);
1046	pPage->cModifications = pPage->cModifications * 2;
1047	pPage->GCPtrLastAccessHandlerFault = pvFault;
1048	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1049	if (pPage->cModifications >= cMaxModifications)
1050	{
1051	STAM_COUNTER_INC(&pPool->StatMonitorPfRZFlushReinit);
1052	fForcedFlush = true;
1053	}
1054	}
1055
1056	if (pPage->cModifications >= cMaxModifications)
1057	Log(("Mod overflow %RGv cMods=%d (locked=%d type=%s)\n", pvFault, pPage->cModifications, pgmPoolIsPageLocked(pPage), pgmPoolPoolKindToStr(pPage->enmKind)));
1058
1059	/*
1060	* Check if it's worth dealing with.
1061	*/
1062	bool fReused = false;
1063	bool fNotReusedNotForking = false;
1064	if ( ( pPage->cModifications < cMaxModifications /** @todo \#define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1065	\|\| pgmPoolIsPageLocked(pPage)
1066	)
1067	&& !(fReused = pgmRZPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault, pPage))
1068	&& !pgmRZPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1069	{
1070	/*
1071	* Simple instructions, no REP prefix.
1072	*/
1073	if (!(pDis->fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
1074	{
1075	rc = pgmRZPoolAccessPfHandlerSimple(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault, &fReused);
1076	if (fReused)
1077	goto flushPage;
1078
1079	/* A mov instruction to change the first page table entry will be remembered so we can detect
1080	* full page table changes early on. This will reduce the amount of unnecessary traps we'll take.
1081	*/
1082	if ( rc == VINF_SUCCESS
1083	&& !pPage->cLocked /* only applies to unlocked pages as we can't free locked ones (e.g. cr3 root). */
1084	&& pDis->pCurInstr->uOpcode == OP_MOV
1085	&& (pvFault & PAGE_OFFSET_MASK) == 0)
1086	{
1087	pPage->GCPtrLastAccessHandlerFault = pvFault;
1088	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1089	pPage->GCPtrLastAccessHandlerRip = pRegFrame->rip;
1090	/* Make sure we don't kick out a page too quickly. */
1091	if (pPage->cModifications > 8)
1092	pPage->cModifications = 2;
1093	}
1094	else if (pPage->GCPtrLastAccessHandlerFault == pvFault)
1095	{
1096	/* ignore the 2nd write to this page table entry. */
1097	pPage->cLastAccessHandler = pVCpu->pgm.s.cPoolAccessHandler;
1098	}
1099	else
1100	{
1101	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
1102	pPage->GCPtrLastAccessHandlerRip = 0;
1103	}
1104
1105	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->StatMonitorPfRZ, &pPool->StatMonitorPfRZHandled, a);
1106	pgmUnlock(pVM);
1107	return rc;
1108	}
1109
1110	/*
1111	* Windows is frequently doing small memset() operations (netio test 4k+).
1112	* We have to deal with these or we'll kill the cache and performance.
1113	*/
1114	if ( pDis->pCurInstr->uOpcode == OP_STOSWD
1115	&& !pRegFrame->eflags.Bits.u1DF
1116	&& pDis->uOpMode == pDis->uCpuMode
1117	&& pDis->uAddrMode == pDis->uCpuMode)
1118	{
1119	bool fValidStosd = false;
1120
1121	if ( pDis->uCpuMode == DISCPUMODE_32BIT
1122	&& pDis->fPrefix == DISPREFIX_REP
1123	&& pRegFrame->ecx <= 0x20
1124	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1125	&& !((uintptr_t)pvFault & 3)
1126	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1127	)
1128	{
1129	fValidStosd = true;
1130	pRegFrame->rcx &= 0xffffffff; /* paranoia */
1131	}
1132	else
1133	if ( pDis->uCpuMode == DISCPUMODE_64BIT
1134	&& pDis->fPrefix == (DISPREFIX_REP \| DISPREFIX_REX)
1135	&& pRegFrame->rcx <= 0x20
1136	&& pRegFrame->rcx * 8 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1137	&& !((uintptr_t)pvFault & 7)
1138	&& (pRegFrame->rax == 0 \|\| pRegFrame->rax == 0x80) /* the two values observed. */
1139	)
1140	{
1141	fValidStosd = true;
1142	}
1143
1144	if (fValidStosd)
1145	{
1146	rc = pgmRZPoolAccessPfHandlerSTOSD(pVM, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1147	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->StatMonitorPfRZ, &pPool->StatMonitorPfRZRepStosd, a);
1148	pgmUnlock(pVM);
1149	return rc;
1150	}
1151	}
1152
1153	/* REP prefix, don't bother. */
1154	STAM_COUNTER_INC(&pPool->StatMonitorPfRZRepPrefix);
1155	Log4(("pgmRZPoolAccessPfHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1156	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, pDis->pCurInstr->uOpcode, pDis->fPrefix));
1157	fNotReusedNotForking = true;
1158	}
1159
1160	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) && defined(IN_RING0)
1161	/* E.g. Windows 7 x64 initializes page tables and touches some pages in the table during the process. This
1162	* leads to pgm pool trashing and an excessive amount of write faults due to page monitoring.
1163	*/
1164	if ( pPage->cModifications >= cMaxModifications
1165	&& !fForcedFlush
1166	&& (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT \|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1167	&& ( fNotReusedNotForking
1168	\|\| ( !pgmRZPoolMonitorIsReused(pVM, pVCpu, pRegFrame, pDis, pvFault, pPage)
1169	&& !pgmRZPoolMonitorIsForking(pPool, pDis, GCPhysFault & PAGE_OFFSET_MASK))
1170	)
1171	)
1172	{
1173	Assert(!pgmPoolIsPageLocked(pPage));
1174	Assert(pPage->fDirty == false);
1175
1176	/* Flush any monitored duplicates as we will disable write protection. */
1177	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1178	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1179	{
1180	PPGMPOOLPAGE pPageHead = pPage;
1181
1182	/* Find the monitor head. */
1183	while (pPageHead->iMonitoredPrev != NIL_PGMPOOL_IDX)
1184	pPageHead = &pPool->aPages[pPageHead->iMonitoredPrev];
1185
1186	while (pPageHead)
1187	{
1188	unsigned idxNext = pPageHead->iMonitoredNext;
1189
1190	if (pPageHead != pPage)
1191	{
1192	STAM_COUNTER_INC(&pPool->StatDirtyPageDupFlush);
1193	Log(("Flush duplicate page idx=%d GCPhys=%RGp type=%s\n", pPageHead->idx, pPageHead->GCPhys, pgmPoolPoolKindToStr(pPageHead->enmKind)));
1194	int rc2 = pgmPoolFlushPage(pPool, pPageHead);
1195	AssertRC(rc2);
1196	}
1197
1198	if (idxNext == NIL_PGMPOOL_IDX)
1199	break;
1200
1201	pPageHead = &pPool->aPages[idxNext];
1202	}
1203	}
1204
1205	/* The flushing above might fail for locked pages, so double check. */
1206	if ( pPage->iMonitoredNext == NIL_PGMPOOL_IDX
1207	&& pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1208	{
1209	pgmPoolAddDirtyPage(pVM, pPool, pPage);
1210
1211	/* Temporarily allow write access to the page table again. */
1212	rc = PGMHandlerPhysicalPageTempOff(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK, pPage->GCPhys & PAGE_BASE_GC_MASK);
1213	if (rc == VINF_SUCCESS)
1214	{
1215	rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
1216	AssertMsg(rc == VINF_SUCCESS
1217	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1218	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1219	\|\| rc == VERR_PAGE_NOT_PRESENT,
1220	("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", pvFault, rc));
1221	# ifdef VBOX_STRICT
1222	pPage->GCPtrDirtyFault = pvFault;
1223	# endif
1224
1225	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pPool)->StatMonitorPfRZ, a);
1226	pgmUnlock(pVM);
1227	return rc;
1228	}
1229	}
1230	}
1231	# endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT && IN_RING0 */
1232
1233	STAM_COUNTER_INC(&pPool->StatMonitorPfRZFlushModOverflow);
1234	flushPage:
1235	/*
1236	* Not worth it, so flush it.
1237	*
1238	* If we considered it to be reused, don't go back to ring-3
1239	* to emulate failed instructions since we usually cannot
1240	* interpret then. This may be a bit risky, in which case
1241	* the reuse detection must be fixed.
1242	*/
1243	rc = pgmRZPoolAccessPfHandlerFlush(pVM, pVCpu, pPool, pPage, pDis, pRegFrame, GCPhysFault, pvFault);
1244	if ( rc == VINF_EM_RAW_EMULATE_INSTR
1245	&& fReused)
1246	{
1247	/* Make sure that the current instruction still has shadow page backing, otherwise we'll end up in a loop. */
1248	if (PGMShwGetPage(pVCpu, pRegFrame->rip, NULL, NULL) == VINF_SUCCESS)
1249	rc = VINF_SUCCESS; /* safe to restart the instruction. */
1250	}
1251	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->StatMonitorPfRZ, &pPool->StatMonitorPfRZFlushPage, a);
1252	pgmUnlock(pVM);
1253	return rc;
1254	}
1255
1256	#endif /* !IN_RING3 */
1257
1258	/**
1259	* @callback_method_impl{FNPGMPHYSHANDLER,
1260	* Access handler for shadowed page table pages.}
1261	*
1262	* @remarks Only uses the VINF_PGM_HANDLER_DO_DEFAULT status.
1263	*/
1264	PGM_ALL_CB2_DECL(VBOXSTRICTRC)
1265	pgmPoolAccessHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
1266	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1267	{
1268	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1269	STAM_PROFILE_START(&pPool->CTX_SUFF_Z(StatMonitor), a);
1270	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1271	LogFlow(("PGM_ALL_CB_DECL: GCPhys=%RGp %p:{.Core=%RHp, .idx=%d, .GCPhys=%RGp, .enmType=%d}\n",
1272	GCPhys, pPage, pPage->Core.Key, pPage->idx, pPage->GCPhys, pPage->enmKind));
1273
1274	NOREF(pvPhys); NOREF(pvBuf); NOREF(enmAccessType);
1275
1276	pgmLock(pVM);
1277
1278	#ifdef VBOX_WITH_STATISTICS
1279	/*
1280	* Collect stats on the access.
1281	*/
1282	AssertCompile(RT_ELEMENTS(pPool->CTX_MID_Z(aStatMonitor,Sizes)) == 19);
1283	if (cbBuf <= 16 && cbBuf > 0)
1284	STAM_COUNTER_INC(&pPool->CTX_MID_Z(aStatMonitor,Sizes)[cbBuf - 1]);
1285	else if (cbBuf >= 17 && cbBuf < 32)
1286	STAM_COUNTER_INC(&pPool->CTX_MID_Z(aStatMonitor,Sizes)[16]);
1287	else if (cbBuf >= 32 && cbBuf < 64)
1288	STAM_COUNTER_INC(&pPool->CTX_MID_Z(aStatMonitor,Sizes)[17]);
1289	else if (cbBuf >= 64)
1290	STAM_COUNTER_INC(&pPool->CTX_MID_Z(aStatMonitor,Sizes)[18]);
1291
1292	uint8_t cbAlign;
1293	switch (pPage->enmKind)
1294	{
1295	default:
1296	cbAlign = 7;
1297	break;
1298	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1299	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1300	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1301	case PGMPOOLKIND_32BIT_PD:
1302	case PGMPOOLKIND_32BIT_PD_PHYS:
1303	cbAlign = 3;
1304	break;
1305	}
1306	AssertCompile(RT_ELEMENTS(pPool->CTX_MID_Z(aStatMonitor,Misaligned)) == 7);
1307	if ((uint8_t)GCPhys & cbAlign)
1308	STAM_COUNTER_INC(&pPool->CTX_MID_Z(aStatMonitor,Misaligned)[((uint8_t)GCPhys & cbAlign) - 1]);
1309	#endif
1310
1311	/*
1312	* Make sure the pool page wasn't modified by a different CPU.
1313	*/
1314	if (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(pPage->GCPhys))
1315	{
1316	Assert(pPage->enmKind != PGMPOOLKIND_FREE);
1317
1318	/* The max modification count before flushing depends on the context and page type. */
1319	#ifdef IN_RING3
1320	uint16_t const cMaxModifications = 96; /* it's cheaper here, right? */
1321	#else
1322	uint16_t cMaxModifications;
1323	if ( pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1324	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1325	cMaxModifications = 4;
1326	else
1327	cMaxModifications = 24;
1328	#endif
1329
1330	/*
1331	* We don't have to be very sophisticated about this since there are relativly few calls here.
1332	* However, we must try our best to detect any non-cpu accesses (disk / networking).
1333	*/
1334	if ( ( pPage->cModifications < cMaxModifications
1335	\|\| pgmPoolIsPageLocked(pPage) )
1336	&& enmOrigin != PGMACCESSORIGIN_DEVICE
1337	&& cbBuf <= 16)
1338	{
1339	/* Clear the shadow entry. */
1340	if (!pPage->cModifications++)
1341	pgmPoolMonitorModifiedInsert(pPool, pPage);
1342
1343	if (cbBuf <= 8)
1344	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhys, pvBuf, (uint32_t)cbBuf);
1345	else
1346	{
1347	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhys, pvBuf, 8);
1348	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhys + 8, (uint8_t *)pvBuf + 8, (uint32_t)cbBuf - 8);
1349	}
1350	}
1351	else
1352	pgmPoolMonitorChainFlush(pPool, pPage);
1353
1354	STAM_PROFILE_STOP_EX(&pPool->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1355	}
1356	else
1357	Log(("CPU%d: PGM_ALL_CB_DECL pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhys), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1358	pgmUnlock(pVM);
1359	return VINF_PGM_HANDLER_DO_DEFAULT;
1360	}
1361
1362
1363	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1364
1365	# if defined(VBOX_STRICT) && !defined(IN_RING3)
1366
1367	/**
1368	* Check references to guest physical memory in a PAE / PAE page table.
1369	*
1370	* @param pPool The pool.
1371	* @param pPage The page.
1372	* @param pShwPT The shadow page table (mapping of the page).
1373	* @param pGstPT The guest page table.
1374	*/
1375	static void pgmPoolTrackCheckPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
1376	{
1377	unsigned cErrors = 0;
1378	int LastRc = -1; /* initialized to shut up gcc */
1379	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1380	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1381	PVMCC pVM = pPool->CTX_SUFF(pVM);
1382
1383	# ifdef VBOX_STRICT
1384	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1385	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1386	# endif
1387	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1388	{
1389	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1390	{
1391	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1392	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1393	if ( rc != VINF_SUCCESS
1394	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1395	{
1396	Log(("rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1397	LastPTE = i;
1398	LastRc = rc;
1399	LastHCPhys = HCPhys;
1400	cErrors++;
1401
1402	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1403	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1404	AssertRC(rc);
1405
1406	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1407	{
1408	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1409
1410	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1411	{
1412	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1413
1414	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1415	{
1416	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1417	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1418	{
1419	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1420	}
1421	}
1422
1423	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1424	}
1425	}
1426	}
1427	}
1428	}
1429	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %RX64 shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1430	}
1431
1432
1433	/**
1434	* Check references to guest physical memory in a PAE / 32-bit page table.
1435	*
1436	* @param pPool The pool.
1437	* @param pPage The page.
1438	* @param pShwPT The shadow page table (mapping of the page).
1439	* @param pGstPT The guest page table.
1440	*/
1441	static void pgmPoolTrackCheckPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
1442	{
1443	unsigned cErrors = 0;
1444	int LastRc = -1; /* initialized to shut up gcc */
1445	unsigned LastPTE = ~0U; /* initialized to shut up gcc */
1446	RTHCPHYS LastHCPhys = NIL_RTHCPHYS; /* initialized to shut up gcc */
1447	PVMCC pVM = pPool->CTX_SUFF(pVM);
1448
1449	# ifdef VBOX_STRICT
1450	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1451	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1452	# endif
1453	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1454	{
1455	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1456	{
1457	RTHCPHYS HCPhys = NIL_RTHCPHYS;
1458	int rc = PGMPhysGCPhys2HCPhys(pVM, pGstPT->a[i].u & X86_PTE_PG_MASK, &HCPhys);
1459	if ( rc != VINF_SUCCESS
1460	\|\| PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) != HCPhys)
1461	{
1462	Log(("rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", rc, i, pGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1463	LastPTE = i;
1464	LastRc = rc;
1465	LastHCPhys = HCPhys;
1466	cErrors++;
1467
1468	RTHCPHYS HCPhysPT = NIL_RTHCPHYS;
1469	rc = PGMPhysGCPhys2HCPhys(pVM, pPage->GCPhys, &HCPhysPT);
1470	AssertRC(rc);
1471
1472	for (unsigned iPage = 0; iPage < pPool->cCurPages; iPage++)
1473	{
1474	PPGMPOOLPAGE pTempPage = &pPool->aPages[iPage];
1475
1476	if (pTempPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_32BIT_PT)
1477	{
1478	PPGMSHWPTPAE pShwPT2 = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pTempPage);
1479
1480	for (unsigned j = 0; j < RT_ELEMENTS(pShwPT->a); j++)
1481	{
1482	if ( PGMSHWPTEPAE_IS_P_RW(pShwPT2->a[j])
1483	&& PGMSHWPTEPAE_GET_HCPHYS(pShwPT2->a[j]) == HCPhysPT)
1484	{
1485	Log(("GCPhys=%RGp idx=%d %RX64 vs %RX64\n", pTempPage->GCPhys, j, PGMSHWPTEPAE_GET_LOG(pShwPT->a[j]), PGMSHWPTEPAE_GET_LOG(pShwPT2->a[j])));
1486	}
1487	}
1488
1489	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPT2);
1490	}
1491	}
1492	}
1493	}
1494	}
1495	AssertMsg(!cErrors, ("cErrors=%d: last rc=%d idx=%d guest %x shw=%RX64 vs %RHp\n", cErrors, LastRc, LastPTE, pGstPT->a[LastPTE].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[LastPTE]), LastHCPhys));
1496	}
1497
1498	# endif /* VBOX_STRICT && !IN_RING3 */
1499
1500	/**
1501	* Clear references to guest physical memory in a PAE / PAE page table.
1502	*
1503	* @returns nr of changed PTEs
1504	* @param pPool The pool.
1505	* @param pPage The page.
1506	* @param pShwPT The shadow page table (mapping of the page).
1507	* @param pGstPT The guest page table.
1508	* @param pOldGstPT The old cached guest page table.
1509	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1510	* @param pfFlush Flush reused page table (out)
1511	*/
1512	DECLINLINE(unsigned) pgmPoolTrackFlushPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT,
1513	PCX86PTPAE pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1514	{
1515	unsigned cChanged = 0;
1516
1517	# ifdef VBOX_STRICT
1518	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1519	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1520	# endif
1521	*pfFlush = false;
1522
1523	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1524	{
1525	/* Check the new value written by the guest. If present and with a bogus physical address, then
1526	* it's fairly safe to assume the guest is reusing the PT.
1527	*/
1528	if ( fAllowRemoval
1529	&& (pGstPT->a[i].u & X86_PTE_P))
1530	{
1531	if (!PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1532	{
1533	*pfFlush = true;
1534	return ++cChanged;
1535	}
1536	}
1537	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1538	{
1539	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1540	if ((pGstPT->a[i].u & X86_PTE_PAE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK))
1541	{
1542	# ifdef VBOX_STRICT
1543	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1544	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK, &HCPhys);
1545	AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %RX64 old %RX64 shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1546	# endif
1547	uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1548	bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1549	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G \| X86_PTE_PAE_NX);
1550	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1551
1552	if ( uHostAttr == uGuestAttr
1553	&& fHostRW <= fGuestRW)
1554	continue;
1555	}
1556	cChanged++;
1557	/* Something was changed, so flush it. */
1558	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%RX64\n",
1559	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
1560	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PAE_PG_MASK, i);
1561	PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1562	}
1563	}
1564	return cChanged;
1565	}
1566
1567
1568	/**
1569	* Clear references to guest physical memory in a PAE / PAE page table.
1570	*
1571	* @returns nr of changed PTEs
1572	* @param pPool The pool.
1573	* @param pPage The page.
1574	* @param pShwPT The shadow page table (mapping of the page).
1575	* @param pGstPT The guest page table.
1576	* @param pOldGstPT The old cached guest page table.
1577	* @param fAllowRemoval Bail out as soon as we encounter an invalid PTE
1578	* @param pfFlush Flush reused page table (out)
1579	*/
1580	DECLINLINE(unsigned) pgmPoolTrackFlushPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT,
1581	PCX86PT pOldGstPT, bool fAllowRemoval, bool *pfFlush)
1582	{
1583	unsigned cChanged = 0;
1584
1585	# ifdef VBOX_STRICT
1586	for (unsigned i = 0; i < RT_MIN(RT_ELEMENTS(pShwPT->a), pPage->iFirstPresent); i++)
1587	AssertMsg(!PGMSHWPTEPAE_IS_P(pShwPT->a[i]), ("Unexpected PTE: idx=%d %RX64 (first=%d)\n", i, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), pPage->iFirstPresent));
1588	# endif
1589	*pfFlush = false;
1590
1591	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
1592	{
1593	/* Check the new value written by the guest. If present and with a bogus physical address, then
1594	* it's fairly safe to assume the guest is reusing the PT. */
1595	if (fAllowRemoval)
1596	{
1597	X86PGUINT const uPte = pGstPT->a[i].u;
1598	if ( (uPte & X86_PTE_P)
1599	&& !PGMPhysIsGCPhysValid(pPool->CTX_SUFF(pVM), uPte & X86_PTE_PG_MASK))
1600	{
1601	*pfFlush = true;
1602	return ++cChanged;
1603	}
1604	}
1605	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
1606	{
1607	/* If the old cached PTE is identical, then there's no need to flush the shadow copy. */
1608	if ((pGstPT->a[i].u & X86_PTE_PG_MASK) == (pOldGstPT->a[i].u & X86_PTE_PG_MASK))
1609	{
1610	# ifdef VBOX_STRICT
1611	RTHCPHYS HCPhys = NIL_RTGCPHYS;
1612	int rc = PGMPhysGCPhys2HCPhys(pPool->CTX_SUFF(pVM), pGstPT->a[i].u & X86_PTE_PG_MASK, &HCPhys);
1613	AssertMsg(rc == VINF_SUCCESS && PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]) == HCPhys, ("rc=%d guest %x old %x shw=%RX64 vs %RHp\n", rc, pGstPT->a[i].u, pOldGstPT->a[i].u, PGMSHWPTEPAE_GET_LOG(pShwPT->a[i]), HCPhys));
1614	# endif
1615	uint64_t uHostAttr = PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G);
1616	bool fHostRW = !!(PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & X86_PTE_RW);
1617	uint64_t uGuestAttr = pGstPT->a[i].u & (X86_PTE_P \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D \| X86_PTE_G);
1618	bool fGuestRW = !!(pGstPT->a[i].u & X86_PTE_RW);
1619
1620	if ( uHostAttr == uGuestAttr
1621	&& fHostRW <= fGuestRW)
1622	continue;
1623	}
1624	cChanged++;
1625	/* Something was changed, so flush it. */
1626	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX64 hint=%x\n",
1627	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK));
1628	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pOldGstPT->a[i].u & X86_PTE_PG_MASK, i);
1629	PGMSHWPTEPAE_ATOMIC_SET(pShwPT->a[i], 0);
1630	}
1631	}
1632	return cChanged;
1633	}
1634
1635
1636	/**
1637	* Flush a dirty page
1638	*
1639	* @param pVM The cross context VM structure.
1640	* @param pPool The pool.
1641	* @param idxSlot Dirty array slot index
1642	* @param fAllowRemoval Allow a reused page table to be removed
1643	*/
1644	static void pgmPoolFlushDirtyPage(PVMCC pVM, PPGMPOOL pPool, unsigned idxSlot, bool fAllowRemoval = false)
1645	{
1646	AssertCompile(RT_ELEMENTS(pPool->aidxDirtyPages) == RT_ELEMENTS(pPool->aDirtyPages));
1647
1648	Assert(idxSlot < RT_ELEMENTS(pPool->aDirtyPages));
1649	unsigned idxPage = pPool->aidxDirtyPages[idxSlot];
1650	if (idxPage == NIL_PGMPOOL_IDX)
1651	return;
1652
1653	PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1654	Assert(pPage->idx == idxPage);
1655	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1656
1657	AssertMsg(pPage->fDirty, ("Page %RGp (slot=%d) not marked dirty!", pPage->GCPhys, idxSlot));
1658	Log(("Flush dirty page %RGp cMods=%d\n", pPage->GCPhys, pPage->cModifications));
1659
1660	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1661	PVMCPU pVCpu = VMMGetCpu(pVM);
1662	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
1663	# endif
1664
1665	/* First write protect the page again to catch all write accesses. (before checking for changes -> SMP) */
1666	int rc = PGMHandlerPhysicalReset(pVM, pPage->GCPhys & PAGE_BASE_GC_MASK);
1667	Assert(rc == VINF_SUCCESS);
1668	pPage->fDirty = false;
1669
1670	# ifdef VBOX_STRICT
1671	uint64_t fFlags = 0;
1672	RTHCPHYS HCPhys;
1673	rc = PGMShwGetPage(VMMGetCpu(pVM), pPage->GCPtrDirtyFault, &fFlags, &HCPhys);
1674	AssertMsg( ( rc == VINF_SUCCESS
1675	&& (!(fFlags & X86_PTE_RW) \|\| HCPhys != pPage->Core.Key))
1676	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
1677	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
1678	\|\| rc == VERR_PAGE_NOT_PRESENT,
1679	("PGMShwGetPage -> GCPtr=%RGv rc=%d flags=%RX64\n", pPage->GCPtrDirtyFault, rc, fFlags));
1680	# endif
1681
1682	/* Flush those PTEs that have changed. */
1683	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
1684	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1685	void *pvGst;
1686	rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1687	bool fFlush;
1688	unsigned cChanges;
1689
1690	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1691	cChanges = pgmPoolTrackFlushPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst,
1692	(PCX86PTPAE)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1693	else
1694	cChanges = pgmPoolTrackFlushPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst,
1695	(PCX86PT)&pPool->aDirtyPages[idxSlot].aPage[0], fAllowRemoval, &fFlush);
1696
1697	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1698	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1699	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
1700	/* Note: we might want to consider keeping the dirty page active in case there were many changes. */
1701
1702	/* This page is likely to be modified again, so reduce the nr of modifications just a bit here. */
1703	Assert(pPage->cModifications);
1704	if (cChanges < 4)
1705	pPage->cModifications = 1; /* must use > 0 here */
1706	else
1707	pPage->cModifications = RT_MAX(1, pPage->cModifications / 2);
1708
1709	STAM_COUNTER_INC(&pPool->StatResetDirtyPages);
1710	if (pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages))
1711	pPool->idxFreeDirtyPage = idxSlot;
1712
1713	pPool->cDirtyPages--;
1714	pPool->aidxDirtyPages[idxSlot] = NIL_PGMPOOL_IDX;
1715	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1716	if (fFlush)
1717	{
1718	Assert(fAllowRemoval);
1719	Log(("Flush reused page table!\n"));
1720	pgmPoolFlushPage(pPool, pPage);
1721	STAM_COUNTER_INC(&pPool->StatForceFlushReused);
1722	}
1723	else
1724	Log(("Removed dirty page %RGp cMods=%d cChanges=%d\n", pPage->GCPhys, pPage->cModifications, cChanges));
1725
1726	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1727	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
1728	# endif
1729	}
1730
1731
1732	# ifndef IN_RING3
1733	/**
1734	* Add a new dirty page
1735	*
1736	* @param pVM The cross context VM structure.
1737	* @param pPool The pool.
1738	* @param pPage The page.
1739	*/
1740	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1741	{
1742	PGM_LOCK_ASSERT_OWNER(pVM);
1743	AssertCompile(RT_ELEMENTS(pPool->aDirtyPages) == 8 \|\| RT_ELEMENTS(pPool->aDirtyPages) == 16);
1744	Assert(!pPage->fDirty);
1745
1746	unsigned idxFree = pPool->idxFreeDirtyPage;
1747	Assert(idxFree < RT_ELEMENTS(pPool->aDirtyPages));
1748	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX && pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1749
1750	if (pPool->cDirtyPages >= RT_ELEMENTS(pPool->aDirtyPages))
1751	{
1752	STAM_COUNTER_INC(&pPool->StatDirtyPageOverFlowFlush);
1753	pgmPoolFlushDirtyPage(pVM, pPool, idxFree, true /* allow removal of reused page tables*/);
1754	}
1755	Assert(pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages));
1756	AssertMsg(pPool->aidxDirtyPages[idxFree] == NIL_PGMPOOL_IDX, ("idxFree=%d cDirtyPages=%d\n", idxFree, pPool->cDirtyPages));
1757
1758	Log(("Add dirty page %RGp (slot=%d)\n", pPage->GCPhys, idxFree));
1759
1760	/*
1761	* Make a copy of the guest page table as we require valid GCPhys addresses
1762	* when removing references to physical pages.
1763	* (The HCPhys linear lookup is extremely expensive!)
1764	*/
1765	void *pvGst;
1766	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
1767	memcpy(&pPool->aDirtyPages[idxFree].aPage[0], pvGst, (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT) ? PAGE_SIZE : PAGE_SIZE/2);
1768	# ifdef VBOX_STRICT
1769	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
1770	if (pPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PAE_PT)
1771	pgmPoolTrackCheckPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
1772	else
1773	pgmPoolTrackCheckPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
1774	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
1775	# endif
1776	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
1777
1778	STAM_COUNTER_INC(&pPool->StatDirtyPage);
1779	pPage->fDirty = true;
1780	pPage->idxDirtyEntry = (uint8_t)idxFree; Assert(pPage->idxDirtyEntry == idxFree);
1781	pPool->aidxDirtyPages[idxFree] = pPage->idx;
1782	pPool->cDirtyPages++;
1783
1784	pPool->idxFreeDirtyPage = (pPool->idxFreeDirtyPage + 1) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1785	if ( pPool->cDirtyPages < RT_ELEMENTS(pPool->aDirtyPages)
1786	&& pPool->aidxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1787	{
1788	unsigned i;
1789	for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1790	{
1791	idxFree = (pPool->idxFreeDirtyPage + i) & (RT_ELEMENTS(pPool->aDirtyPages) - 1);
1792	if (pPool->aidxDirtyPages[idxFree] == NIL_PGMPOOL_IDX)
1793	{
1794	pPool->idxFreeDirtyPage = idxFree;
1795	break;
1796	}
1797	}
1798	Assert(i != RT_ELEMENTS(pPool->aDirtyPages));
1799	}
1800
1801	Assert(pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages) \|\| pPool->aidxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX);
1802
1803	/*
1804	* Clear all references to this shadow table. See @bugref{7298}.
1805	*/
1806	pgmPoolTrackClearPageUsers(pPool, pPage);
1807	}
1808	# endif /* !IN_RING3 */
1809
1810
1811	/**
1812	* Check if the specified page is dirty (not write monitored)
1813	*
1814	* @return dirty or not
1815	* @param pVM The cross context VM structure.
1816	* @param GCPhys Guest physical address
1817	*/
1818	bool pgmPoolIsDirtyPageSlow(PVM pVM, RTGCPHYS GCPhys)
1819	{
1820	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1821	PGM_LOCK_ASSERT_OWNER(pVM);
1822	if (!pPool->cDirtyPages)
1823	return false;
1824
1825	GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1826
1827	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1828	{
1829	unsigned idxPage = pPool->aidxDirtyPages[i];
1830	if (idxPage != NIL_PGMPOOL_IDX)
1831	{
1832	PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1833	if (pPage->GCPhys == GCPhys)
1834	return true;
1835	}
1836	}
1837	return false;
1838	}
1839
1840
1841	/**
1842	* Reset all dirty pages by reinstating page monitoring.
1843	*
1844	* @param pVM The cross context VM structure.
1845	*/
1846	void pgmPoolResetDirtyPages(PVMCC pVM)
1847	{
1848	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1849	PGM_LOCK_ASSERT_OWNER(pVM);
1850	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1851
1852	if (!pPool->cDirtyPages)
1853	return;
1854
1855	Log(("pgmPoolResetDirtyPages\n"));
1856	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1857	pgmPoolFlushDirtyPage(pVM, pPool, i, true /* allow removal of reused page tables*/);
1858
1859	pPool->idxFreeDirtyPage = 0;
1860	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1861	&& pPool->aidxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1862	{
1863	unsigned i;
1864	for (i = 1; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1865	{
1866	if (pPool->aidxDirtyPages[i] == NIL_PGMPOOL_IDX)
1867	{
1868	pPool->idxFreeDirtyPage = i;
1869	break;
1870	}
1871	}
1872	AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1873	}
1874
1875	Assert(pPool->aidxDirtyPages[pPool->idxFreeDirtyPage] == NIL_PGMPOOL_IDX \|\| pPool->cDirtyPages == RT_ELEMENTS(pPool->aDirtyPages));
1876	return;
1877	}
1878
1879
1880	/**
1881	* Invalidate the PT entry for the specified page
1882	*
1883	* @param pVM The cross context VM structure.
1884	* @param GCPtrPage Guest page to invalidate
1885	*/
1886	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage)
1887	{
1888	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1889	PGM_LOCK_ASSERT_OWNER(pVM);
1890	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1891
1892	if (!pPool->cDirtyPages)
1893	return;
1894
1895	Log(("pgmPoolResetDirtyPage %RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
1896	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1897	{
1898	/** @todo What was intended here??? This looks incomplete... */
1899	}
1900	}
1901
1902
1903	/**
1904	* Reset all dirty pages by reinstating page monitoring.
1905	*
1906	* @param pVM The cross context VM structure.
1907	* @param GCPhysPT Physical address of the page table
1908	*/
1909	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT)
1910	{
1911	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1912	PGM_LOCK_ASSERT_OWNER(pVM);
1913	Assert(pPool->cDirtyPages <= RT_ELEMENTS(pPool->aDirtyPages));
1914	unsigned idxDirtyPage = RT_ELEMENTS(pPool->aDirtyPages);
1915
1916	if (!pPool->cDirtyPages)
1917	return;
1918
1919	GCPhysPT = GCPhysPT & ~(RTGCPHYS)PAGE_OFFSET_MASK;
1920
1921	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1922	{
1923	unsigned idxPage = pPool->aidxDirtyPages[i];
1924	if (idxPage != NIL_PGMPOOL_IDX)
1925	{
1926	PPGMPOOLPAGE pPage = &pPool->aPages[idxPage];
1927	if (pPage->GCPhys == GCPhysPT)
1928	{
1929	idxDirtyPage = i;
1930	break;
1931	}
1932	}
1933	}
1934
1935	if (idxDirtyPage != RT_ELEMENTS(pPool->aDirtyPages))
1936	{
1937	pgmPoolFlushDirtyPage(pVM, pPool, idxDirtyPage, true /* allow removal of reused page tables*/);
1938	if ( pPool->cDirtyPages != RT_ELEMENTS(pPool->aDirtyPages)
1939	&& pPool->aidxDirtyPages[pPool->idxFreeDirtyPage] != NIL_PGMPOOL_IDX)
1940	{
1941	unsigned i;
1942	for (i = 0; i < RT_ELEMENTS(pPool->aDirtyPages); i++)
1943	{
1944	if (pPool->aidxDirtyPages[i] == NIL_PGMPOOL_IDX)
1945	{
1946	pPool->idxFreeDirtyPage = i;
1947	break;
1948	}
1949	}
1950	AssertMsg(i != RT_ELEMENTS(pPool->aDirtyPages), ("cDirtyPages %d", pPool->cDirtyPages));
1951	}
1952	}
1953	}
1954
1955	#endif /* PGMPOOL_WITH_OPTIMIZED_DIRTY_PT */
1956
1957	/**
1958	* Inserts a page into the GCPhys hash table.
1959	*
1960	* @param pPool The pool.
1961	* @param pPage The page.
1962	*/
1963	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1964	{
1965	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1966	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1967	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1968	pPage->iNext = pPool->aiHash[iHash];
1969	pPool->aiHash[iHash] = pPage->idx;
1970	}
1971
1972
1973	/**
1974	* Removes a page from the GCPhys hash table.
1975	*
1976	* @param pPool The pool.
1977	* @param pPage The page.
1978	*/
1979	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1980	{
1981	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1982	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1983	if (pPool->aiHash[iHash] == pPage->idx)
1984	pPool->aiHash[iHash] = pPage->iNext;
1985	else
1986	{
1987	uint16_t iPrev = pPool->aiHash[iHash];
1988	for (;;)
1989	{
1990	const int16_t i = pPool->aPages[iPrev].iNext;
1991	if (i == pPage->idx)
1992	{
1993	pPool->aPages[iPrev].iNext = pPage->iNext;
1994	break;
1995	}
1996	if (i == NIL_PGMPOOL_IDX)
1997	{
1998	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%d\n", pPage->GCPhys, pPage->idx));
1999	break;
2000	}
2001	iPrev = i;
2002	}
2003	}
2004	pPage->iNext = NIL_PGMPOOL_IDX;
2005	}
2006
2007
2008	/**
2009	* Frees up one cache page.
2010	*
2011	* @returns VBox status code.
2012	* @retval VINF_SUCCESS on success.
2013	* @param pPool The pool.
2014	* @param iUser The user index.
2015	*/
2016	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
2017	{
2018	const PVMCC pVM = pPool->CTX_SUFF(pVM);
2019	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
2020	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
2021
2022	/*
2023	* Select one page from the tail of the age list.
2024	*/
2025	PPGMPOOLPAGE pPage;
2026	for (unsigned iLoop = 0; ; iLoop++)
2027	{
2028	uint16_t iToFree = pPool->iAgeTail;
2029	if (iToFree == iUser && iUser != NIL_PGMPOOL_IDX)
2030	iToFree = pPool->aPages[iToFree].iAgePrev;
2031	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
2032	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
2033	{
2034	uint16_t i = pPool->aPages[iToFree].iAgePrev;
2035	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
2036	{
2037	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
2038	continue;
2039	iToFree = i;
2040	break;
2041	}
2042	}
2043	*/
2044	Assert(iToFree != iUser);
2045	AssertReleaseMsg(iToFree != NIL_PGMPOOL_IDX,
2046	("iToFree=%#x (iAgeTail=%#x) iUser=%#x iLoop=%u - pPool=%p LB %#zx\n",
2047	iToFree, pPool->iAgeTail, iUser, iLoop, pPool,
2048	RT_UOFFSETOF_DYN(PGMPOOL, aPages[pPool->cMaxPages])
2049	+ pPool->cMaxUsers * sizeof(PGMPOOLUSER)
2050	+ pPool->cMaxPhysExts * sizeof(PGMPOOLPHYSEXT) ));
2051
2052	pPage = &pPool->aPages[iToFree];
2053
2054	/*
2055	* Reject any attempts at flushing the currently active shadow CR3 mapping.
2056	* Call pgmPoolCacheUsed to move the page to the head of the age list.
2057	*/
2058	if ( !pgmPoolIsPageLocked(pPage)
2059	&& pPage->idx >= PGMPOOL_IDX_FIRST /* paranoia (#6349) */)
2060	break;
2061	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
2062	pgmPoolCacheUsed(pPool, pPage);
2063	AssertLogRelReturn(iLoop < 8192, VERR_PGM_POOL_TOO_MANY_LOOPS);
2064	}
2065
2066	/*
2067	* Found a usable page, flush it and return.
2068	*/
2069	int rc = pgmPoolFlushPage(pPool, pPage);
2070	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
2071	/** @todo find out why this is necessary; pgmPoolFlushPage should trigger a flush if one is really needed. */
2072	if (rc == VINF_SUCCESS)
2073	PGM_INVL_ALL_VCPU_TLBS(pVM);
2074	return rc;
2075	}
2076
2077
2078	/**
2079	* Checks if a kind mismatch is really a page being reused
2080	* or if it's just normal remappings.
2081	*
2082	* @returns true if reused and the cached page (enmKind1) should be flushed
2083	* @returns false if not reused.
2084	* @param enmKind1 The kind of the cached page.
2085	* @param enmKind2 The kind of the requested page.
2086	*/
2087	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
2088	{
2089	switch (enmKind1)
2090	{
2091	/*
2092	* Never reuse them. There is no remapping in non-paging mode.
2093	*/
2094	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2095	case PGMPOOLKIND_32BIT_PD_PHYS:
2096	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2097	case PGMPOOLKIND_PAE_PD_PHYS:
2098	case PGMPOOLKIND_PAE_PDPT_PHYS:
2099	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2100	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2101	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2102	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2103	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2104	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
2105	return false;
2106
2107	/*
2108	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2109	*/
2110	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2111	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2112	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2113	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2114	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2115	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2116	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2117	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2118	case PGMPOOLKIND_32BIT_PD:
2119	case PGMPOOLKIND_PAE_PDPT:
2120	switch (enmKind2)
2121	{
2122	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2123	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2124	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2125	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2126	case PGMPOOLKIND_64BIT_PML4:
2127	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2128	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2129	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2130	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2131	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2132	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2133	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2134	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2135	return true;
2136	default:
2137	return false;
2138	}
2139
2140	/*
2141	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
2142	*/
2143	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2144	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2145	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2146	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2147	case PGMPOOLKIND_64BIT_PML4:
2148	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2149	switch (enmKind2)
2150	{
2151	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2152	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2153	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2154	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2155	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2156	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2157	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2158	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2159	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2160	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2161	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2162	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2163	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2164	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2165	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2166	return true;
2167	default:
2168	return false;
2169	}
2170
2171	/*
2172	* These cannot be flushed, and it's common to reuse the PDs as PTs.
2173	*/
2174	case PGMPOOLKIND_ROOT_NESTED:
2175	return false;
2176
2177	default:
2178	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
2179	}
2180	}
2181
2182
2183	/**
2184	* Attempts to satisfy a pgmPoolAlloc request from the cache.
2185	*
2186	* @returns VBox status code.
2187	* @retval VINF_PGM_CACHED_PAGE on success.
2188	* @retval VERR_FILE_NOT_FOUND if not found.
2189	* @param pPool The pool.
2190	* @param GCPhys The GC physical address of the page we're gonna shadow.
2191	* @param enmKind The kind of mapping.
2192	* @param enmAccess Access type for the mapping (only relevant for big pages)
2193	* @param fA20Enabled Whether the CPU has the A20 gate enabled.
2194	* @param iUser The shadow page pool index of the user table. This is
2195	* NIL_PGMPOOL_IDX for root pages.
2196	* @param iUserTable The index into the user table (shadowed). Ignored if
2197	* root page
2198	* @param ppPage Where to store the pointer to the page.
2199	*/
2200	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
2201	uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
2202	{
2203	/*
2204	* Look up the GCPhys in the hash.
2205	*/
2206	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2207	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%d iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
2208	if (i != NIL_PGMPOOL_IDX)
2209	{
2210	do
2211	{
2212	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2213	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
2214	if (pPage->GCPhys == GCPhys)
2215	{
2216	if ( (PGMPOOLKIND)pPage->enmKind == enmKind
2217	&& (PGMPOOLACCESS)pPage->enmAccess == enmAccess
2218	&& pPage->fA20Enabled == fA20Enabled)
2219	{
2220	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
2221	* doesn't flush it in case there are no more free use records.
2222	*/
2223	pgmPoolCacheUsed(pPool, pPage);
2224
2225	int rc = VINF_SUCCESS;
2226	if (iUser != NIL_PGMPOOL_IDX)
2227	rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
2228	if (RT_SUCCESS(rc))
2229	{
2230	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
2231	*ppPage = pPage;
2232	if (pPage->cModifications)
2233	pPage->cModifications = 1; /* reset counter (can't use 0, or else it will be reinserted in the modified list) */
2234	STAM_COUNTER_INC(&pPool->StatCacheHits);
2235	return VINF_PGM_CACHED_PAGE;
2236	}
2237	return rc;
2238	}
2239
2240	if ((PGMPOOLKIND)pPage->enmKind != enmKind)
2241	{
2242	/*
2243	* The kind is different. In some cases we should now flush the page
2244	* as it has been reused, but in most cases this is normal remapping
2245	* of PDs as PT or big pages using the GCPhys field in a slightly
2246	* different way than the other kinds.
2247	*/
2248	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
2249	{
2250	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
2251	pgmPoolFlushPage(pPool, pPage);
2252	break;
2253	}
2254	}
2255	}
2256
2257	/* next */
2258	i = pPage->iNext;
2259	} while (i != NIL_PGMPOOL_IDX);
2260	}
2261
2262	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
2263	STAM_COUNTER_INC(&pPool->StatCacheMisses);
2264	return VERR_FILE_NOT_FOUND;
2265	}
2266
2267
2268	/**
2269	* Inserts a page into the cache.
2270	*
2271	* @param pPool The pool.
2272	* @param pPage The cached page.
2273	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
2274	*/
2275	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
2276	{
2277	/*
2278	* Insert into the GCPhys hash if the page is fit for that.
2279	*/
2280	Assert(!pPage->fCached);
2281	if (fCanBeCached)
2282	{
2283	pPage->fCached = true;
2284	pgmPoolHashInsert(pPool, pPage);
2285	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2286	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2287	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
2288	}
2289	else
2290	{
2291	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
2292	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
2293	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
2294	}
2295
2296	/*
2297	* Insert at the head of the age list.
2298	*/
2299	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2300	pPage->iAgeNext = pPool->iAgeHead;
2301	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
2302	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
2303	else
2304	pPool->iAgeTail = pPage->idx;
2305	pPool->iAgeHead = pPage->idx;
2306	}
2307
2308
2309	/**
2310	* Flushes a cached page.
2311	*
2312	* @param pPool The pool.
2313	* @param pPage The cached page.
2314	*/
2315	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2316	{
2317	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
2318
2319	/*
2320	* Remove the page from the hash.
2321	*/
2322	if (pPage->fCached)
2323	{
2324	pPage->fCached = false;
2325	pgmPoolHashRemove(pPool, pPage);
2326	}
2327	else
2328	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
2329
2330	/*
2331	* Remove it from the age list.
2332	*/
2333	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
2334	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
2335	else
2336	pPool->iAgeTail = pPage->iAgePrev;
2337	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
2338	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
2339	else
2340	pPool->iAgeHead = pPage->iAgeNext;
2341	pPage->iAgeNext = NIL_PGMPOOL_IDX;
2342	pPage->iAgePrev = NIL_PGMPOOL_IDX;
2343	}
2344
2345
2346	/**
2347	* Looks for pages sharing the monitor.
2348	*
2349	* @returns Pointer to the head page.
2350	* @returns NULL if not found.
2351	* @param pPool The Pool
2352	* @param pNewPage The page which is going to be monitored.
2353	*/
2354	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
2355	{
2356	/*
2357	* Look up the GCPhys in the hash.
2358	*/
2359	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2360	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
2361	if (i == NIL_PGMPOOL_IDX)
2362	return NULL;
2363	do
2364	{
2365	PPGMPOOLPAGE pPage = &pPool->aPages[i];
2366	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
2367	&& pPage != pNewPage)
2368	{
2369	switch (pPage->enmKind)
2370	{
2371	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2372	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2373	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2374	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2375	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2376	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2377	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2378	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2379	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2380	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2381	case PGMPOOLKIND_64BIT_PML4:
2382	case PGMPOOLKIND_32BIT_PD:
2383	case PGMPOOLKIND_PAE_PDPT:
2384	{
2385	/* find the head */
2386	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2387	{
2388	Assert(pPage->iMonitoredPrev != pPage->idx);
2389	pPage = &pPool->aPages[pPage->iMonitoredPrev];
2390	}
2391	return pPage;
2392	}
2393
2394	/* ignore, no monitoring. */
2395	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2396	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2397	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2398	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2399	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2400	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2401	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2402	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2403	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2404	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2405	case PGMPOOLKIND_ROOT_NESTED:
2406	case PGMPOOLKIND_PAE_PD_PHYS:
2407	case PGMPOOLKIND_PAE_PDPT_PHYS:
2408	case PGMPOOLKIND_32BIT_PD_PHYS:
2409	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2410	break;
2411	default:
2412	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
2413	}
2414	}
2415
2416	/* next */
2417	i = pPage->iNext;
2418	} while (i != NIL_PGMPOOL_IDX);
2419	return NULL;
2420	}
2421
2422
2423	/**
2424	* Enabled write monitoring of a guest page.
2425	*
2426	* @returns VBox status code.
2427	* @retval VINF_SUCCESS on success.
2428	* @param pPool The pool.
2429	* @param pPage The cached page.
2430	*/
2431	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2432	{
2433	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK));
2434
2435	/*
2436	* Filter out the relevant kinds.
2437	*/
2438	switch (pPage->enmKind)
2439	{
2440	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2441	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2442	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2443	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2444	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2445	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2446	case PGMPOOLKIND_64BIT_PML4:
2447	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2448	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2449	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2450	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2451	case PGMPOOLKIND_32BIT_PD:
2452	case PGMPOOLKIND_PAE_PDPT:
2453	break;
2454
2455	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2456	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2457	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2458	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2459	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2460	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2461	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2462	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2463	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2464	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2465	case PGMPOOLKIND_ROOT_NESTED:
2466	/* Nothing to monitor here. */
2467	return VINF_SUCCESS;
2468
2469	case PGMPOOLKIND_32BIT_PD_PHYS:
2470	case PGMPOOLKIND_PAE_PDPT_PHYS:
2471	case PGMPOOLKIND_PAE_PD_PHYS:
2472	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2473	/* Nothing to monitor here. */
2474	return VINF_SUCCESS;
2475	default:
2476	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2477	}
2478
2479	/*
2480	* Install handler.
2481	*/
2482	int rc;
2483	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
2484	if (pPageHead)
2485	{
2486	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
2487	Assert(pPageHead->iMonitoredPrev != pPage->idx);
2488
2489	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2490	if (pPageHead->fDirty)
2491	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPageHead->idxDirtyEntry, false /* do not remove */);
2492	#endif
2493
2494	pPage->iMonitoredPrev = pPageHead->idx;
2495	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
2496	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
2497	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
2498	pPageHead->iMonitoredNext = pPage->idx;
2499	rc = VINF_SUCCESS;
2500	}
2501	else
2502	{
2503	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
2504	PVMCC pVM = pPool->CTX_SUFF(pVM);
2505	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
2506	rc = PGMHandlerPhysicalRegister(pVM, GCPhysPage, GCPhysPage + PAGE_OFFSET_MASK, pPool->hAccessHandlerType,
2507	MMHyperCCToR3(pVM, pPage), MMHyperCCToR0(pVM, pPage), MMHyperCCToRC(pVM, pPage),
2508	NIL_RTR3PTR /pszDesc/);
2509	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
2510	* the heap size should suffice. */
2511	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
2512	PVMCPU pVCpu = VMMGetCpu(pVM);
2513	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), ("fSyncFlags=%x syncff=%d\n", pVCpu->pgm.s.fSyncFlags, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
2514	}
2515	pPage->fMonitored = true;
2516	return rc;
2517	}
2518
2519
2520	/**
2521	* Disables write monitoring of a guest page.
2522	*
2523	* @returns VBox status code.
2524	* @retval VINF_SUCCESS on success.
2525	* @param pPool The pool.
2526	* @param pPage The cached page.
2527	*/
2528	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2529	{
2530	/*
2531	* Filter out the relevant kinds.
2532	*/
2533	switch (pPage->enmKind)
2534	{
2535	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2536	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2537	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2538	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2539	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2540	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2541	case PGMPOOLKIND_64BIT_PML4:
2542	case PGMPOOLKIND_32BIT_PD:
2543	case PGMPOOLKIND_PAE_PDPT:
2544	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2545	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2546	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2547	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2548	break;
2549
2550	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2551	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2552	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2553	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2554	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2555	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2556	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2557	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2558	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2559	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2560	case PGMPOOLKIND_ROOT_NESTED:
2561	case PGMPOOLKIND_PAE_PD_PHYS:
2562	case PGMPOOLKIND_PAE_PDPT_PHYS:
2563	case PGMPOOLKIND_32BIT_PD_PHYS:
2564	/* Nothing to monitor here. */
2565	Assert(!pPage->fMonitored);
2566	return VINF_SUCCESS;
2567
2568	default:
2569	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
2570	}
2571	Assert(pPage->fMonitored);
2572
2573	/*
2574	* Remove the page from the monitored list or uninstall it if last.
2575	*/
2576	const PVMCC pVM = pPool->CTX_SUFF(pVM);
2577	int rc;
2578	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
2579	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
2580	{
2581	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
2582	{
2583	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
2584	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
2585	rc = PGMHandlerPhysicalChangeUserArgs(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK,
2586	MMHyperCCToR3(pVM, pNewHead), MMHyperCCToR0(pVM, pNewHead));
2587
2588	AssertFatalRCSuccess(rc);
2589	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2590	}
2591	else
2592	{
2593	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
2594	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
2595	{
2596	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
2597	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
2598	}
2599	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
2600	rc = VINF_SUCCESS;
2601	}
2602	}
2603	else
2604	{
2605	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
2606	AssertFatalRC(rc);
2607	PVMCPU pVCpu = VMMGetCpu(pVM);
2608	AssertFatalMsg(!(pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3),
2609	("%#x %#x\n", pVCpu->pgm.s.fSyncFlags, pVM->fGlobalForcedActions));
2610	}
2611	pPage->fMonitored = false;
2612
2613	/*
2614	* Remove it from the list of modified pages (if in it).
2615	*/
2616	pgmPoolMonitorModifiedRemove(pPool, pPage);
2617
2618	return rc;
2619	}
2620
2621
2622	/**
2623	* Inserts the page into the list of modified pages.
2624	*
2625	* @param pPool The pool.
2626	* @param pPage The page.
2627	*/
2628	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2629	{
2630	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
2631	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
2632	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
2633	&& pPool->iModifiedHead != pPage->idx,
2634	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
2635	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
2636	pPool->iModifiedHead, pPool->cModifiedPages));
2637
2638	pPage->iModifiedNext = pPool->iModifiedHead;
2639	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
2640	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
2641	pPool->iModifiedHead = pPage->idx;
2642	pPool->cModifiedPages++;
2643	#ifdef VBOX_WITH_STATISTICS
2644	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
2645	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
2646	#endif
2647	}
2648
2649
2650	/**
2651	* Removes the page from the list of modified pages and resets the
2652	* modification counter.
2653	*
2654	* @param pPool The pool.
2655	* @param pPage The page which is believed to be in the list of modified pages.
2656	*/
2657	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2658	{
2659	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
2660	if (pPool->iModifiedHead == pPage->idx)
2661	{
2662	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2663	pPool->iModifiedHead = pPage->iModifiedNext;
2664	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2665	{
2666	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
2667	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2668	}
2669	pPool->cModifiedPages--;
2670	}
2671	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
2672	{
2673	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
2674	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
2675	{
2676	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
2677	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2678	}
2679	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2680	pPool->cModifiedPages--;
2681	}
2682	else
2683	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
2684	pPage->cModifications = 0;
2685	}
2686
2687
2688	/**
2689	* Zaps the list of modified pages, resetting their modification counters in the process.
2690	*
2691	* @param pVM The cross context VM structure.
2692	*/
2693	static void pgmPoolMonitorModifiedClearAll(PVMCC pVM)
2694	{
2695	pgmLock(pVM);
2696	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2697	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
2698
2699	unsigned cPages = 0; NOREF(cPages);
2700
2701	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2702	pgmPoolResetDirtyPages(pVM);
2703	#endif
2704
2705	uint16_t idx = pPool->iModifiedHead;
2706	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2707	while (idx != NIL_PGMPOOL_IDX)
2708	{
2709	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
2710	idx = pPage->iModifiedNext;
2711	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2712	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2713	pPage->cModifications = 0;
2714	Assert(++cPages);
2715	}
2716	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
2717	pPool->cModifiedPages = 0;
2718	pgmUnlock(pVM);
2719	}
2720
2721
2722	/**
2723	* Handle SyncCR3 pool tasks
2724	*
2725	* @returns VBox status code.
2726	* @retval VINF_SUCCESS if successfully added.
2727	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2728	* @param pVCpu The cross context virtual CPU structure.
2729	* @remark Should only be used when monitoring is available, thus placed in
2730	* the PGMPOOL_WITH_MONITORING \#ifdef.
2731	*/
2732	int pgmPoolSyncCR3(PVMCPUCC pVCpu)
2733	{
2734	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2735	LogFlow(("pgmPoolSyncCR3 fSyncFlags=%x\n", pVCpu->pgm.s.fSyncFlags));
2736
2737	/*
2738	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2739	* Occasionally we will have to clear all the shadow page tables because we wanted
2740	* to monitor a page which was mapped by too many shadowed page tables. This operation
2741	* sometimes referred to as a 'lightweight flush'.
2742	*/
2743	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2744	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2745	pgmR3PoolClearAll(pVM, false /fFlushRemTlb/);
2746	# else /* !IN_RING3 */
2747	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2748	{
2749	Log(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2750	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2751
2752	/* Make sure all other VCPUs return to ring 3. */
2753	if (pVM->cCpus > 1)
2754	{
2755	VM_FF_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING);
2756	PGM_INVL_ALL_VCPU_TLBS(pVM);
2757	}
2758	return VINF_PGM_SYNC_CR3;
2759	}
2760	# endif /* !IN_RING3 */
2761	else
2762	{
2763	pgmPoolMonitorModifiedClearAll(pVM);
2764
2765	/* pgmPoolMonitorModifiedClearAll can cause a pgm pool flush (dirty page clearing), so make sure we handle this! */
2766	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)
2767	{
2768	Log(("pgmPoolMonitorModifiedClearAll caused a pgm flush -> call pgmPoolSyncCR3 again!\n"));
2769	return pgmPoolSyncCR3(pVCpu);
2770	}
2771	}
2772	return VINF_SUCCESS;
2773	}
2774
2775
2776	/**
2777	* Frees up at least one user entry.
2778	*
2779	* @returns VBox status code.
2780	* @retval VINF_SUCCESS if successfully added.
2781	*
2782	* @param pPool The pool.
2783	* @param iUser The user index.
2784	*/
2785	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2786	{
2787	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2788	/*
2789	* Just free cached pages in a braindead fashion.
2790	*/
2791	/** @todo walk the age list backwards and free the first with usage. */
2792	int rc = VINF_SUCCESS;
2793	do
2794	{
2795	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2796	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2797	rc = rc2;
2798	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2799	return rc;
2800	}
2801
2802
2803	/**
2804	* Inserts a page into the cache.
2805	*
2806	* This will create user node for the page, insert it into the GCPhys
2807	* hash, and insert it into the age list.
2808	*
2809	* @returns VBox status code.
2810	* @retval VINF_SUCCESS if successfully added.
2811	*
2812	* @param pPool The pool.
2813	* @param pPage The cached page.
2814	* @param GCPhys The GC physical address of the page we're gonna shadow.
2815	* @param iUser The user index.
2816	* @param iUserTable The user table index.
2817	*/
2818	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2819	{
2820	int rc = VINF_SUCCESS;
2821	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2822
2823	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser=%d iUserTable=%x\n", GCPhys, iUser, iUserTable)); RT_NOREF_PV(GCPhys);
2824
2825	if (iUser != NIL_PGMPOOL_IDX)
2826	{
2827	#ifdef VBOX_STRICT
2828	/*
2829	* Check that the entry doesn't already exists.
2830	*/
2831	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2832	{
2833	uint16_t i = pPage->iUserHead;
2834	do
2835	{
2836	Assert(i < pPool->cMaxUsers);
2837	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2838	i = paUsers[i].iNext;
2839	} while (i != NIL_PGMPOOL_USER_INDEX);
2840	}
2841	#endif
2842
2843	/*
2844	* Find free a user node.
2845	*/
2846	uint16_t i = pPool->iUserFreeHead;
2847	if (i == NIL_PGMPOOL_USER_INDEX)
2848	{
2849	rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2850	if (RT_FAILURE(rc))
2851	return rc;
2852	i = pPool->iUserFreeHead;
2853	}
2854
2855	/*
2856	* Unlink the user node from the free list,
2857	* initialize and insert it into the user list.
2858	*/
2859	pPool->iUserFreeHead = paUsers[i].iNext;
2860	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2861	paUsers[i].iUser = iUser;
2862	paUsers[i].iUserTable = iUserTable;
2863	pPage->iUserHead = i;
2864	}
2865	else
2866	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
2867
2868
2869	/*
2870	* Insert into cache and enable monitoring of the guest page if enabled.
2871	*
2872	* Until we implement caching of all levels, including the CR3 one, we'll
2873	* have to make sure we don't try monitor & cache any recursive reuse of
2874	* a monitored CR3 page. Because all windows versions are doing this we'll
2875	* have to be able to do combined access monitoring, CR3 + PT and
2876	* PD + PT (guest PAE).
2877	*
2878	* Update:
2879	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2880	*/
2881	const bool fCanBeMonitored = true;
2882	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2883	if (fCanBeMonitored)
2884	{
2885	rc = pgmPoolMonitorInsert(pPool, pPage);
2886	AssertRC(rc);
2887	}
2888	return rc;
2889	}
2890
2891
2892	/**
2893	* Adds a user reference to a page.
2894	*
2895	* This will move the page to the head of the
2896	*
2897	* @returns VBox status code.
2898	* @retval VINF_SUCCESS if successfully added.
2899	*
2900	* @param pPool The pool.
2901	* @param pPage The cached page.
2902	* @param iUser The user index.
2903	* @param iUserTable The user table.
2904	*/
2905	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2906	{
2907	Log3(("pgmPoolTrackAddUser: GCPhys=%RGp iUser=%x iUserTable=%x\n", pPage->GCPhys, iUser, iUserTable));
2908	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2909	Assert(iUser != NIL_PGMPOOL_IDX);
2910
2911	# ifdef VBOX_STRICT
2912	/*
2913	* Check that the entry doesn't already exists. We only allow multiple
2914	* users of top-level paging structures (SHW_POOL_ROOT_IDX).
2915	*/
2916	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2917	{
2918	uint16_t i = pPage->iUserHead;
2919	do
2920	{
2921	Assert(i < pPool->cMaxUsers);
2922	/** @todo this assertion looks odd... Shouldn't it be && here? */
2923	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2924	i = paUsers[i].iNext;
2925	} while (i != NIL_PGMPOOL_USER_INDEX);
2926	}
2927	# endif
2928
2929	/*
2930	* Allocate a user node.
2931	*/
2932	uint16_t i = pPool->iUserFreeHead;
2933	if (i == NIL_PGMPOOL_USER_INDEX)
2934	{
2935	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2936	if (RT_FAILURE(rc))
2937	return rc;
2938	i = pPool->iUserFreeHead;
2939	}
2940	pPool->iUserFreeHead = paUsers[i].iNext;
2941
2942	/*
2943	* Initialize the user node and insert it.
2944	*/
2945	paUsers[i].iNext = pPage->iUserHead;
2946	paUsers[i].iUser = iUser;
2947	paUsers[i].iUserTable = iUserTable;
2948	pPage->iUserHead = i;
2949
2950	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
2951	if (pPage->fDirty)
2952	pgmPoolFlushDirtyPage(pPool->CTX_SUFF(pVM), pPool, pPage->idxDirtyEntry, false /* do not remove */);
2953	# endif
2954
2955	/*
2956	* Tell the cache to update its replacement stats for this page.
2957	*/
2958	pgmPoolCacheUsed(pPool, pPage);
2959	return VINF_SUCCESS;
2960	}
2961
2962
2963	/**
2964	* Frees a user record associated with a page.
2965	*
2966	* This does not clear the entry in the user table, it simply replaces the
2967	* user record to the chain of free records.
2968	*
2969	* @param pPool The pool.
2970	* @param pPage The shadow page.
2971	* @param iUser The shadow page pool index of the user table.
2972	* @param iUserTable The index into the user table (shadowed).
2973	*
2974	* @remarks Don't call this for root pages.
2975	*/
2976	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2977	{
2978	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2979	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2980	Assert(iUser != NIL_PGMPOOL_IDX);
2981
2982	/*
2983	* Unlink and free the specified user entry.
2984	*/
2985
2986	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2987	uint16_t i = pPage->iUserHead;
2988	if ( i != NIL_PGMPOOL_USER_INDEX
2989	&& paUsers[i].iUser == iUser
2990	&& paUsers[i].iUserTable == iUserTable)
2991	{
2992	pPage->iUserHead = paUsers[i].iNext;
2993
2994	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2995	paUsers[i].iNext = pPool->iUserFreeHead;
2996	pPool->iUserFreeHead = i;
2997	return;
2998	}
2999
3000	/* General: Linear search. */
3001	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
3002	while (i != NIL_PGMPOOL_USER_INDEX)
3003	{
3004	if ( paUsers[i].iUser == iUser
3005	&& paUsers[i].iUserTable == iUserTable)
3006	{
3007	if (iPrev != NIL_PGMPOOL_USER_INDEX)
3008	paUsers[iPrev].iNext = paUsers[i].iNext;
3009	else
3010	pPage->iUserHead = paUsers[i].iNext;
3011
3012	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3013	paUsers[i].iNext = pPool->iUserFreeHead;
3014	pPool->iUserFreeHead = i;
3015	return;
3016	}
3017	iPrev = i;
3018	i = paUsers[i].iNext;
3019	}
3020
3021	/* Fatal: didn't find it */
3022	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%d iUserTable=%#x GCPhys=%RGp\n",
3023	iUser, iUserTable, pPage->GCPhys));
3024	}
3025
3026
3027	#if 0 /* unused */
3028	/**
3029	* Gets the entry size of a shadow table.
3030	*
3031	* @param enmKind The kind of page.
3032	*
3033	* @returns The size of the entry in bytes. That is, 4 or 8.
3034	* @returns If the kind is not for a table, an assertion is raised and 0 is
3035	* returned.
3036	*/
3037	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
3038	{
3039	switch (enmKind)
3040	{
3041	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3042	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3043	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3044	case PGMPOOLKIND_32BIT_PD:
3045	case PGMPOOLKIND_32BIT_PD_PHYS:
3046	return 4;
3047
3048	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3049	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3050	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3051	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3052	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3053	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3054	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3055	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3056	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3057	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3058	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3059	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3060	case PGMPOOLKIND_64BIT_PML4:
3061	case PGMPOOLKIND_PAE_PDPT:
3062	case PGMPOOLKIND_ROOT_NESTED:
3063	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3064	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3065	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3066	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3067	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3068	case PGMPOOLKIND_PAE_PD_PHYS:
3069	case PGMPOOLKIND_PAE_PDPT_PHYS:
3070	return 8;
3071
3072	default:
3073	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3074	}
3075	}
3076	#endif /* unused */
3077
3078	#if 0 /* unused */
3079	/**
3080	* Gets the entry size of a guest table.
3081	*
3082	* @param enmKind The kind of page.
3083	*
3084	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
3085	* @returns If the kind is not for a table, an assertion is raised and 0 is
3086	* returned.
3087	*/
3088	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
3089	{
3090	switch (enmKind)
3091	{
3092	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3093	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3094	case PGMPOOLKIND_32BIT_PD:
3095	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3096	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3097	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3098	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3099	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3100	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3101	return 4;
3102
3103	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3104	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3105	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3106	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3107	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3108	case PGMPOOLKIND_64BIT_PML4:
3109	case PGMPOOLKIND_PAE_PDPT:
3110	return 8;
3111
3112	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3113	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3114	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3115	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3116	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3117	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3118	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3119	case PGMPOOLKIND_ROOT_NESTED:
3120	case PGMPOOLKIND_PAE_PD_PHYS:
3121	case PGMPOOLKIND_PAE_PDPT_PHYS:
3122	case PGMPOOLKIND_32BIT_PD_PHYS:
3123	/** @todo can we return 0? (nobody is calling this...) */
3124	AssertFailed();
3125	return 0;
3126
3127	default:
3128	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
3129	}
3130	}
3131	#endif /* unused */
3132
3133
3134	/**
3135	* Checks one shadow page table entry for a mapping of a physical page.
3136	*
3137	* @returns true / false indicating removal of all relevant PTEs
3138	*
3139	* @param pVM The cross context VM structure.
3140	* @param pPhysPage The guest page in question.
3141	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3142	* @param iShw The shadow page table.
3143	* @param iPte Page table entry or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown
3144	*/
3145	static bool pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw, uint16_t iPte)
3146	{
3147	LogFlow(("pgmPoolTrackFlushGCPhysPTInt: pPhysPage=%RHp iShw=%d iPte=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw, iPte));
3148	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3149	bool fRet = false;
3150
3151	/*
3152	* Assert sanity.
3153	*/
3154	Assert(iPte != NIL_PGMPOOL_PHYSEXT_IDX_PTE);
3155	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
3156	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
3157
3158	/*
3159	* Then, clear the actual mappings to the page in the shadow PT.
3160	*/
3161	switch (pPage->enmKind)
3162	{
3163	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3164	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3165	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3166	{
3167	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3168	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3169	uint32_t u32AndMask = 0;
3170	uint32_t u32OrMask = 0;
3171
3172	if (!fFlushPTEs)
3173	{
3174	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3175	{
3176	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /* No handler installed. */
3177	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /* Monitoring is temporarily disabled. */
3178	u32OrMask = X86_PTE_RW;
3179	u32AndMask = UINT32_MAX;
3180	fRet = true;
3181	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3182	break;
3183
3184	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /* Write access is monitored. */
3185	u32OrMask = 0;
3186	u32AndMask = ~X86_PTE_RW;
3187	fRet = true;
3188	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3189	break;
3190	default:
3191	/* (shouldn't be here, will assert below) */
3192	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3193	break;
3194	}
3195	}
3196	else
3197	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3198
3199	/* Update the counter if we're removing references. */
3200	if (!u32AndMask)
3201	{
3202	Assert(pPage->cPresent);
3203	Assert(pPool->cPresent);
3204	pPage->cPresent--;
3205	pPool->cPresent--;
3206	}
3207
3208	if ((pPT->a[iPte].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3209	{
3210	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32\n", iPte, pPT->a[iPte]));
3211	X86PTE Pte;
3212	Pte.u = (pPT->a[iPte].u & u32AndMask) \| u32OrMask;
3213	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3214	Pte.u &= ~(X86PGUINT)X86_PTE_RW; /* need to disallow writes when dirty bit tracking is still active. */
3215	ASMAtomicWriteU32(&pPT->a[iPte].u, Pte.u);
3216	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3217	return fRet;
3218	}
3219	#ifdef LOG_ENABLED
3220	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3221	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3222	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
3223	{
3224	Log(("i=%d cFound=%d\n", i, ++cFound));
3225	}
3226	#endif
3227	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u32=%RX32 poolkind=%x\n", pPage->iFirstPresent, pPage->cPresent, u32, pPage->enmKind));
3228	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);/
3229	break;
3230	}
3231
3232	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3233	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3234	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3235	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3236	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3237	case PGMPOOLKIND_EPT_PT_FOR_PHYS: /* physical mask the same as PAE; RW bit as well; be careful! */
3238	{
3239	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
3240	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3241	uint64_t u64OrMask = 0;
3242	uint64_t u64AndMask = 0;
3243
3244	if (!fFlushPTEs)
3245	{
3246	switch (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage))
3247	{
3248	case PGM_PAGE_HNDL_PHYS_STATE_NONE: /* No handler installed. */
3249	case PGM_PAGE_HNDL_PHYS_STATE_DISABLED: /* Monitoring is temporarily disabled. */
3250	u64OrMask = X86_PTE_RW;
3251	u64AndMask = UINT64_MAX;
3252	fRet = true;
3253	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3254	break;
3255
3256	case PGM_PAGE_HNDL_PHYS_STATE_WRITE: /* Write access is monitored. */
3257	u64OrMask = 0;
3258	u64AndMask = ~(uint64_t)X86_PTE_RW;
3259	fRet = true;
3260	STAM_COUNTER_INC(&pPool->StatTrackFlushEntryKeep);
3261	break;
3262
3263	default:
3264	/* (shouldn't be here, will assert below) */
3265	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3266	break;
3267	}
3268	}
3269	else
3270	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3271
3272	/* Update the counter if we're removing references. */
3273	if (!u64AndMask)
3274	{
3275	Assert(pPage->cPresent);
3276	Assert(pPool->cPresent);
3277	pPage->cPresent--;
3278	pPool->cPresent--;
3279	}
3280
3281	if ((PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3282	{
3283	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64\n", iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3284	X86PTEPAE Pte;
3285	Pte.u = (PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & u64AndMask) \| u64OrMask;
3286	if (Pte.u & PGM_PTFLAGS_TRACK_DIRTY)
3287	Pte.u &= ~(X86PGPAEUINT)X86_PTE_RW; /* need to disallow writes when dirty bit tracking is still active. */
3288
3289	PGMSHWPTEPAE_ATOMIC_SET(pPT->a[iPte], Pte.u);
3290	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3291	return fRet;
3292	}
3293	#ifdef LOG_ENABLED
3294	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3295	Log(("Found %RX64 expected %RX64\n", PGMSHWPTEPAE_GET_U(pPT->a[iPte]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX), u64));
3296	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPT->a); i++)
3297	if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & (X86_PTE_PAE_PG_MASK \| X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == u64)
3298	Log(("i=%d cFound=%d\n", i, ++cFound));
3299	#endif
3300	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d u64=%RX64 poolkind=%x iPte=%d PT=%RX64\n", pPage->iFirstPresent, pPage->cPresent, u64, pPage->enmKind, iPte, PGMSHWPTEPAE_GET_LOG(pPT->a[iPte])));
3301	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);/
3302	break;
3303	}
3304
3305	#ifdef PGM_WITH_LARGE_PAGES
3306	/* Large page case only. */
3307	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3308	{
3309	Assert(pVM->pgm.s.fNestedPaging);
3310
3311	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3312	PEPTPD pPD = (PEPTPD)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3313
3314	if ((pPD->a[iPte].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3315	{
3316	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3317	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3318	pPD->a[iPte].u = 0;
3319	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3320
3321	/* Update the counter as we're removing references. */
3322	Assert(pPage->cPresent);
3323	Assert(pPool->cPresent);
3324	pPage->cPresent--;
3325	pPool->cPresent--;
3326
3327	return fRet;
3328	}
3329	# ifdef LOG_ENABLED
3330	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3331	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3332	if ((pPD->a[i].u & (EPT_PDE2M_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3333	Log(("i=%d cFound=%d\n", i, ++cFound));
3334	# endif
3335	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3336	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);/
3337	break;
3338	}
3339
3340	/* AMD-V nested paging / /* @todo merge with EPT as we only check the parts that are identical. */
3341	case PGMPOOLKIND_PAE_PD_PHYS:
3342	{
3343	Assert(pVM->pgm.s.fNestedPaging);
3344
3345	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PDE4M_P \| X86_PDE4M_PS;
3346	PX86PDPAE pPD = (PX86PDPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3347
3348	if ((pPD->a[iPte].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3349	{
3350	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pde=%RX64\n", iPte, pPD->a[iPte]));
3351	STAM_COUNTER_INC(&pPool->StatTrackFlushEntry);
3352	pPD->a[iPte].u = 0;
3353	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);
3354
3355	/* Update the counter as we're removing references. */
3356	Assert(pPage->cPresent);
3357	Assert(pPool->cPresent);
3358	pPage->cPresent--;
3359	pPool->cPresent--;
3360	return fRet;
3361	}
3362	# ifdef LOG_ENABLED
3363	Log(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3364	for (unsigned i = 0, cFound = 0; i < RT_ELEMENTS(pPD->a); i++)
3365	if ((pPD->a[i].u & (X86_PDE2M_PAE_PG_MASK \| X86_PDE4M_P \| X86_PDE4M_PS)) == u64)
3366	Log(("i=%d cFound=%d\n", i, ++cFound));
3367	# endif
3368	AssertFatalMsgFailed(("iFirstPresent=%d cPresent=%d\n", pPage->iFirstPresent, pPage->cPresent));
3369	/PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPD);/
3370	break;
3371	}
3372	#endif /* PGM_WITH_LARGE_PAGES */
3373
3374	default:
3375	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
3376	}
3377
3378	/* not reached. */
3379	#ifndef _MSC_VER
3380	return fRet;
3381	#endif
3382	}
3383
3384
3385	/**
3386	* Scans one shadow page table for mappings of a physical page.
3387	*
3388	* @param pVM The cross context VM structure.
3389	* @param pPhysPage The guest page in question.
3390	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3391	* @param iShw The shadow page table.
3392	*/
3393	static void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iShw)
3394	{
3395	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3396
3397	/* We should only come here with when there's only one reference to this physical page. */
3398	Assert(PGMPOOL_TD_GET_CREFS(PGM_PAGE_GET_TRACKING(pPhysPage)) == 1);
3399
3400	Log2(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%RHp iShw=%d\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iShw));
3401	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
3402	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, iShw, PGM_PAGE_GET_PTE_INDEX(pPhysPage));
3403	if (!fKeptPTEs)
3404	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3405	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
3406	}
3407
3408
3409	/**
3410	* Flushes a list of shadow page tables mapping the same physical page.
3411	*
3412	* @param pVM The cross context VM structure.
3413	* @param pPhysPage The guest page in question.
3414	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3415	* @param iPhysExt The physical cross reference extent list to flush.
3416	*/
3417	static void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, bool fFlushPTEs, uint16_t iPhysExt)
3418	{
3419	PGM_LOCK_ASSERT_OWNER(pVM);
3420	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3421	bool fKeepList = false;
3422
3423	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
3424	Log2(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%RHp iPhysExt=%u\n", PGM_PAGE_GET_HCPHYS(pPhysPage), iPhysExt));
3425
3426	const uint16_t iPhysExtStart = iPhysExt;
3427	PPGMPOOLPHYSEXT pPhysExt;
3428	do
3429	{
3430	Assert(iPhysExt < pPool->cMaxPhysExts);
3431	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3432	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3433	{
3434	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
3435	{
3436	bool fKeptPTEs = pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, fFlushPTEs, pPhysExt->aidx[i], pPhysExt->apte[i]);
3437	if (!fKeptPTEs)
3438	{
3439	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3440	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3441	}
3442	else
3443	fKeepList = true;
3444	}
3445	}
3446	/* next */
3447	iPhysExt = pPhysExt->iNext;
3448	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3449
3450	if (!fKeepList)
3451	{
3452	/* insert the list into the free list and clear the ram range entry. */
3453	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3454	pPool->iPhysExtFreeHead = iPhysExtStart;
3455	/* Invalidate the tracking data. */
3456	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3457	}
3458
3459	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
3460	}
3461
3462
3463	/**
3464	* Flushes all shadow page table mappings of the given guest page.
3465	*
3466	* This is typically called when the host page backing the guest one has been
3467	* replaced or when the page protection was changed due to a guest access
3468	* caught by the monitoring.
3469	*
3470	* @returns VBox status code.
3471	* @retval VINF_SUCCESS if all references has been successfully cleared.
3472	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
3473	* pool cleaning. FF and sync flags are set.
3474	*
3475	* @param pVM The cross context VM structure.
3476	* @param GCPhysPage GC physical address of the page in question
3477	* @param pPhysPage The guest page in question.
3478	* @param fFlushPTEs Flush PTEs or allow them to be updated (e.g. in case of an RW bit change)
3479	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
3480	* flushed, it is NOT touched if this isn't necessary.
3481	* The caller MUST initialized this to @a false.
3482	*/
3483	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs)
3484	{
3485	PVMCPUCC pVCpu = VMMGetCpu(pVM);
3486	pgmLock(pVM);
3487	int rc = VINF_SUCCESS;
3488
3489	#ifdef PGM_WITH_LARGE_PAGES
3490	/* Is this page part of a large page? */
3491	if (PGM_PAGE_GET_PDE_TYPE(pPhysPage) == PGM_PAGE_PDE_TYPE_PDE)
3492	{
3493	RTGCPHYS GCPhysBase = GCPhysPage & X86_PDE2M_PAE_PG_MASK;
3494	GCPhysPage &= X86_PDE_PAE_PG_MASK;
3495
3496	/* Fetch the large page base. */
3497	PPGMPAGE pLargePage;
3498	if (GCPhysBase != GCPhysPage)
3499	{
3500	pLargePage = pgmPhysGetPage(pVM, GCPhysBase);
3501	AssertFatal(pLargePage);
3502	}
3503	else
3504	pLargePage = pPhysPage;
3505
3506	Log(("pgmPoolTrackUpdateGCPhys: update large page PDE for %RGp (%RGp)\n", GCPhysBase, GCPhysPage));
3507
3508	if (PGM_PAGE_GET_PDE_TYPE(pLargePage) == PGM_PAGE_PDE_TYPE_PDE)
3509	{
3510	/* Mark the large page as disabled as we need to break it up to change a single page in the 2 MB range. */
3511	PGM_PAGE_SET_PDE_TYPE(pVM, pLargePage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3512	pVM->pgm.s.cLargePagesDisabled++;
3513
3514	/* Update the base as that only that one has a reference and there's only one PDE to clear. */
3515	rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysBase, pLargePage, fFlushPTEs, pfFlushTLBs);
3516
3517	*pfFlushTLBs = true;
3518	pgmUnlock(pVM);
3519	return rc;
3520	}
3521	}
3522	#else
3523	NOREF(GCPhysPage);
3524	#endif /* PGM_WITH_LARGE_PAGES */
3525
3526	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
3527	if (u16)
3528	{
3529	/*
3530	* The zero page is currently screwing up the tracking and we'll
3531	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3532	* is defined, zero pages won't normally be mapped. Some kind of solution
3533	* will be needed for this problem of course, but it will have to wait...
3534	*/
3535	if ( PGM_PAGE_IS_ZERO(pPhysPage)
3536	\|\| PGM_PAGE_IS_BALLOONED(pPhysPage))
3537	rc = VINF_PGM_GCPHYS_ALIASED;
3538	else
3539	{
3540	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 /** @todo we can drop this now. */
3541	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
3542	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
3543	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
3544	# endif
3545
3546	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3547	{
3548	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3549	pgmPoolTrackFlushGCPhysPT(pVM,
3550	pPhysPage,
3551	fFlushPTEs,
3552	PGMPOOL_TD_GET_IDX(u16));
3553	}
3554	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3555	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, fFlushPTEs, PGMPOOL_TD_GET_IDX(u16));
3556	else
3557	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
3558	*pfFlushTLBs = true;
3559
3560	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3561	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
3562	# endif
3563	}
3564	}
3565
3566	if (rc == VINF_PGM_GCPHYS_ALIASED)
3567	{
3568	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_CLEAR_PGM_POOL;
3569	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3570	rc = VINF_PGM_SYNC_CR3;
3571	}
3572	pgmUnlock(pVM);
3573	return rc;
3574	}
3575
3576
3577	/**
3578	* Scans all shadow page tables for mappings of a physical page.
3579	*
3580	* This may be slow, but it's most likely more efficient than cleaning
3581	* out the entire page pool / cache.
3582	*
3583	* @returns VBox status code.
3584	* @retval VINF_SUCCESS if all references has been successfully cleared.
3585	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
3586	* a page pool cleaning.
3587	*
3588	* @param pVM The cross context VM structure.
3589	* @param pPhysPage The guest page in question.
3590	*/
3591	int pgmPoolTrackFlushGCPhysPTsSlow(PVMCC pVM, PPGMPAGE pPhysPage)
3592	{
3593	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3594	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3595	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
3596	pPool->cUsedPages, pPool->cPresent, pPhysPage));
3597
3598	/*
3599	* There is a limit to what makes sense.
3600	*/
3601	if ( pPool->cPresent > 1024
3602	&& pVM->cCpus == 1)
3603	{
3604	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3605	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3606	return VINF_PGM_GCPHYS_ALIASED;
3607	}
3608
3609	/*
3610	* Iterate all the pages until we've encountered all that in use.
3611	* This is simple but not quite optimal solution.
3612	*/
3613	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage);
3614	unsigned cLeft = pPool->cUsedPages;
3615	unsigned iPage = pPool->cCurPages;
3616	while (--iPage >= PGMPOOL_IDX_FIRST)
3617	{
3618	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
3619	if ( pPage->GCPhys != NIL_RTGCPHYS
3620	&& pPage->cPresent)
3621	{
3622	switch (pPage->enmKind)
3623	{
3624	/*
3625	* We only care about shadow page tables.
3626	*/
3627	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3628	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3629	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3630	{
3631	const uint32_t u32 = (uint32_t)u64;
3632	unsigned cPresent = pPage->cPresent;
3633	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3634	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3635	{
3636	const X86PGUINT uPte = pPT->a[i].u;
3637	if (uPte & X86_PTE_P)
3638	{
3639	if ((uPte & X86_PTE_PG_MASK) == u32)
3640	{
3641	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
3642	ASMAtomicWriteU32(&pPT->a[i].u, 0);
3643
3644	/* Update the counter as we're removing references. */
3645	Assert(pPage->cPresent);
3646	Assert(pPool->cPresent);
3647	pPage->cPresent--;
3648	pPool->cPresent--;
3649	}
3650	if (!--cPresent)
3651	break;
3652	}
3653	}
3654	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3655	break;
3656	}
3657
3658	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3659	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3660	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3661	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3662	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3663	{
3664	unsigned cPresent = pPage->cPresent;
3665	PPGMSHWPTPAE pPT = (PPGMSHWPTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3666	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3667	if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
3668	{
3669	if ((PGMSHWPTEPAE_GET_U(pPT->a[i]) & X86_PTE_PAE_PG_MASK) == u64)
3670	{
3671	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3672	PGMSHWPTEPAE_ATOMIC_SET(pPT->a[i], 0); /// @todo why not atomic?
3673
3674	/* Update the counter as we're removing references. */
3675	Assert(pPage->cPresent);
3676	Assert(pPool->cPresent);
3677	pPage->cPresent--;
3678	pPool->cPresent--;
3679	}
3680	if (!--cPresent)
3681	break;
3682	}
3683	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3684	break;
3685	}
3686
3687	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3688	{
3689	unsigned cPresent = pPage->cPresent;
3690	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
3691	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
3692	{
3693	X86PGPAEUINT const uPte = pPT->a[i].u;
3694	if (uPte & EPT_E_READ)
3695	{
3696	if ((uPte & EPT_PTE_PG_MASK) == u64)
3697	{
3698	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
3699	ASMAtomicWriteU64(&pPT->a[i].u, 0);
3700
3701	/* Update the counter as we're removing references. */
3702	Assert(pPage->cPresent);
3703	Assert(pPool->cPresent);
3704	pPage->cPresent--;
3705	pPool->cPresent--;
3706	}
3707	if (!--cPresent)
3708	break;
3709	}
3710	}
3711	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pPT);
3712	break;
3713	}
3714	}
3715
3716	if (!--cLeft)
3717	break;
3718	}
3719	}
3720
3721	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
3722	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
3723
3724	/*
3725	* There is a limit to what makes sense. The above search is very expensive, so force a pgm pool flush.
3726	*/
3727	if (pPool->cPresent > 1024)
3728	{
3729	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
3730	return VINF_PGM_GCPHYS_ALIASED;
3731	}
3732
3733	return VINF_SUCCESS;
3734	}
3735
3736
3737	/**
3738	* Clears the user entry in a user table.
3739	*
3740	* This is used to remove all references to a page when flushing it.
3741	*/
3742	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
3743	{
3744	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
3745	Assert(pUser->iUser < pPool->cCurPages);
3746	uint32_t iUserTable = pUser->iUserTable;
3747
3748	/*
3749	* Map the user page. Ignore references made by fictitious pages.
3750	*/
3751	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
3752	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
3753	union
3754	{
3755	uint64_t *pau64;
3756	uint32_t *pau32;
3757	} u;
3758	if (pUserPage->idx < PGMPOOL_IDX_FIRST)
3759	{
3760	Assert(!pUserPage->pvPageR3);
3761	return;
3762	}
3763	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
3764
3765
3766	/* Safety precaution in case we change the paging for other modes too in the future. */
3767	Assert(!pgmPoolIsPageLocked(pPage)); RT_NOREF_PV(pPage);
3768
3769	#ifdef VBOX_STRICT
3770	/*
3771	* Some sanity checks.
3772	*/
3773	switch (pUserPage->enmKind)
3774	{
3775	case PGMPOOLKIND_32BIT_PD:
3776	case PGMPOOLKIND_32BIT_PD_PHYS:
3777	Assert(iUserTable < X86_PG_ENTRIES);
3778	break;
3779	case PGMPOOLKIND_PAE_PDPT:
3780	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3781	case PGMPOOLKIND_PAE_PDPT_PHYS:
3782	Assert(iUserTable < 4);
3783	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3784	break;
3785	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3786	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3787	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3788	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3789	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3790	case PGMPOOLKIND_PAE_PD_PHYS:
3791	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3792	break;
3793	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3794	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3795	#ifndef PGM_WITHOUT_MAPPINGS
3796	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
3797	#endif
3798	break;
3799	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3800	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3801	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3802	break;
3803	case PGMPOOLKIND_64BIT_PML4:
3804	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
3805	/* GCPhys >> PAGE_SHIFT is the index here */
3806	break;
3807	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3808	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3809	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3810	break;
3811
3812	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3813	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3814	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3815	break;
3816
3817	case PGMPOOLKIND_ROOT_NESTED:
3818	Assert(iUserTable < X86_PG_PAE_ENTRIES);
3819	break;
3820
3821	default:
3822	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
3823	break;
3824	}
3825	#endif /* VBOX_STRICT */
3826
3827	/*
3828	* Clear the entry in the user page.
3829	*/
3830	switch (pUserPage->enmKind)
3831	{
3832	/* 32-bit entries */
3833	case PGMPOOLKIND_32BIT_PD:
3834	case PGMPOOLKIND_32BIT_PD_PHYS:
3835	ASMAtomicWriteU32(&u.pau32[iUserTable], 0);
3836	break;
3837
3838	/* 64-bit entries */
3839	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3840	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3841	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3842	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3843	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3844	case PGMPOOLKIND_PAE_PD_PHYS:
3845	case PGMPOOLKIND_PAE_PDPT_PHYS:
3846	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3847	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3848	case PGMPOOLKIND_64BIT_PML4:
3849	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3850	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3851	case PGMPOOLKIND_PAE_PDPT:
3852	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3853	case PGMPOOLKIND_ROOT_NESTED:
3854	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3855	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3856	ASMAtomicWriteU64(&u.pau64[iUserTable], 0);
3857	break;
3858
3859	default:
3860	AssertFatalMsgFailed(("enmKind=%d iUser=%d iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
3861	}
3862	PGM_DYNMAP_UNUSED_HINT_VM(pPool->CTX_SUFF(pVM), u.pau64);
3863	}
3864
3865
3866	/**
3867	* Clears all users of a page.
3868	*/
3869	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3870	{
3871	/*
3872	* Free all the user records.
3873	*/
3874	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3875
3876	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3877	uint16_t i = pPage->iUserHead;
3878	while (i != NIL_PGMPOOL_USER_INDEX)
3879	{
3880	/* Clear enter in user table. */
3881	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3882
3883	/* Free it. */
3884	const uint16_t iNext = paUsers[i].iNext;
3885	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3886	paUsers[i].iNext = pPool->iUserFreeHead;
3887	pPool->iUserFreeHead = i;
3888
3889	/* Next. */
3890	i = iNext;
3891	}
3892	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3893	}
3894
3895
3896	/**
3897	* Allocates a new physical cross reference extent.
3898	*
3899	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3900	* @param pVM The cross context VM structure.
3901	* @param piPhysExt Where to store the phys ext index.
3902	*/
3903	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3904	{
3905	PGM_LOCK_ASSERT_OWNER(pVM);
3906	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3907	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3908	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3909	{
3910	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3911	return NULL;
3912	}
3913	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3914	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3915	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3916	*piPhysExt = iPhysExt;
3917	return pPhysExt;
3918	}
3919
3920
3921	/**
3922	* Frees a physical cross reference extent.
3923	*
3924	* @param pVM The cross context VM structure.
3925	* @param iPhysExt The extent to free.
3926	*/
3927	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3928	{
3929	PGM_LOCK_ASSERT_OWNER(pVM);
3930	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3931	Assert(iPhysExt < pPool->cMaxPhysExts);
3932	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3933	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3934	{
3935	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3936	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3937	}
3938	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3939	pPool->iPhysExtFreeHead = iPhysExt;
3940	}
3941
3942
3943	/**
3944	* Frees a physical cross reference extent.
3945	*
3946	* @param pVM The cross context VM structure.
3947	* @param iPhysExt The extent to free.
3948	*/
3949	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3950	{
3951	PGM_LOCK_ASSERT_OWNER(pVM);
3952	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3953
3954	const uint16_t iPhysExtStart = iPhysExt;
3955	PPGMPOOLPHYSEXT pPhysExt;
3956	do
3957	{
3958	Assert(iPhysExt < pPool->cMaxPhysExts);
3959	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3960	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3961	{
3962	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3963	pPhysExt->apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
3964	}
3965
3966	/* next */
3967	iPhysExt = pPhysExt->iNext;
3968	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3969
3970	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3971	pPool->iPhysExtFreeHead = iPhysExtStart;
3972	}
3973
3974
3975	/**
3976	* Insert a reference into a list of physical cross reference extents.
3977	*
3978	* @returns The new tracking data for PGMPAGE.
3979	*
3980	* @param pVM The cross context VM structure.
3981	* @param iPhysExt The physical extent index of the list head.
3982	* @param iShwPT The shadow page table index.
3983	* @param iPte Page table entry
3984	*
3985	*/
3986	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT, uint16_t iPte)
3987	{
3988	PGM_LOCK_ASSERT_OWNER(pVM);
3989	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3990	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3991
3992	/*
3993	* Special common cases.
3994	*/
3995	if (paPhysExts[iPhysExt].aidx[1] == NIL_PGMPOOL_IDX)
3996	{
3997	paPhysExts[iPhysExt].aidx[1] = iShwPT;
3998	paPhysExts[iPhysExt].apte[1] = iPte;
3999	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4000	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,%d pte %d,}\n", iPhysExt, iShwPT, iPte));
4001	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4002	}
4003	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
4004	{
4005	paPhysExts[iPhysExt].aidx[2] = iShwPT;
4006	paPhysExts[iPhysExt].apte[2] = iPte;
4007	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4008	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{,,%d pte %d}\n", iPhysExt, iShwPT, iPte));
4009	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4010	}
4011	AssertCompile(RT_ELEMENTS(paPhysExts[iPhysExt].aidx) == 3);
4012
4013	/*
4014	* General treatment.
4015	*/
4016	const uint16_t iPhysExtStart = iPhysExt;
4017	unsigned cMax = 15;
4018	for (;;)
4019	{
4020	Assert(iPhysExt < pPool->cMaxPhysExts);
4021	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4022	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
4023	{
4024	paPhysExts[iPhysExt].aidx[i] = iShwPT;
4025	paPhysExts[iPhysExt].apte[i] = iPte;
4026	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedMany);
4027	LogFlow(("pgmPoolTrackPhysExtInsert: %d:{%d pte %d} i=%d cMax=%d\n", iPhysExt, iShwPT, iPte, i, cMax));
4028	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
4029	}
4030	if (!--cMax)
4031	{
4032	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackOverflows);
4033	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
4034	LogFlow(("pgmPoolTrackPhysExtInsert: overflow (1) iShwPT=%d\n", iShwPT));
4035	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4036	}
4037
4038	/* advance */
4039	iPhysExt = paPhysExts[iPhysExt].iNext;
4040	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
4041	break;
4042	}
4043
4044	/*
4045	* Add another extent to the list.
4046	*/
4047	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
4048	if (!pNew)
4049	{
4050	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackNoExtentsLeft);
4051	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
4052	LogFlow(("pgmPoolTrackPhysExtInsert: pgmPoolTrackPhysExtAlloc failed iShwPT=%d\n", iShwPT));
4053	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4054	}
4055	pNew->iNext = iPhysExtStart;
4056	pNew->aidx[0] = iShwPT;
4057	pNew->apte[0] = iPte;
4058	LogFlow(("pgmPoolTrackPhysExtInsert: added new extent %d:{%d pte %d}->%d\n", iPhysExt, iShwPT, iPte, iPhysExtStart));
4059	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4060	}
4061
4062
4063	/**
4064	* Add a reference to guest physical page where extents are in use.
4065	*
4066	* @returns The new tracking data for PGMPAGE.
4067	*
4068	* @param pVM The cross context VM structure.
4069	* @param pPhysPage Pointer to the aPages entry in the ram range.
4070	* @param u16 The ram range flags (top 16-bits).
4071	* @param iShwPT The shadow page table index.
4072	* @param iPte Page table entry
4073	*/
4074	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte)
4075	{
4076	pgmLock(pVM);
4077	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
4078	{
4079	/*
4080	* Convert to extent list.
4081	*/
4082	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
4083	uint16_t iPhysExt;
4084	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
4085	if (pPhysExt)
4086	{
4087	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
4088	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliased);
4089	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
4090	pPhysExt->apte[0] = PGM_PAGE_GET_PTE_INDEX(pPhysPage);
4091	pPhysExt->aidx[1] = iShwPT;
4092	pPhysExt->apte[1] = iPte;
4093	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
4094	}
4095	else
4096	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
4097	}
4098	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
4099	{
4100	/*
4101	* Insert into the extent list.
4102	*/
4103	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT, iPte);
4104	}
4105	else
4106	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackAliasedLots);
4107	pgmUnlock(pVM);
4108	return u16;
4109	}
4110
4111
4112	/**
4113	* Clear references to guest physical memory.
4114	*
4115	* @param pPool The pool.
4116	* @param pPage The page.
4117	* @param pPhysPage Pointer to the aPages entry in the ram range.
4118	* @param iPte Shadow PTE index
4119	*/
4120	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage, uint16_t iPte)
4121	{
4122	PVMCC pVM = pPool->CTX_SUFF(pVM);
4123	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
4124	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
4125
4126	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
4127	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
4128	{
4129	pgmLock(pVM);
4130
4131	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
4132	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4133	do
4134	{
4135	Assert(iPhysExt < pPool->cMaxPhysExts);
4136
4137	/*
4138	* Look for the shadow page and check if it's all freed.
4139	*/
4140	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4141	{
4142	if ( paPhysExts[iPhysExt].aidx[i] == pPage->idx
4143	&& paPhysExts[iPhysExt].apte[i] == iPte)
4144	{
4145	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
4146	paPhysExts[iPhysExt].apte[i] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
4147
4148	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
4149	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
4150	{
4151	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
4152	pgmUnlock(pVM);
4153	return;
4154	}
4155
4156	/* we can free the node. */
4157	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
4158	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
4159	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
4160	{
4161	/* lonely node */
4162	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4163	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
4164	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, 0);
4165	}
4166	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
4167	{
4168	/* head */
4169	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
4170	PGM_PAGE_SET_TRACKING(pVM, pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
4171	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4172	}
4173	else
4174	{
4175	/* in list */
4176	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d in list\n", pPhysPage, pPage->idx));
4177	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
4178	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
4179	}
4180	iPhysExt = iPhysExtNext;
4181	pgmUnlock(pVM);
4182	return;
4183	}
4184	}
4185
4186	/* next */
4187	iPhysExtPrev = iPhysExt;
4188	iPhysExt = paPhysExts[iPhysExt].iNext;
4189	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
4190
4191	pgmUnlock(pVM);
4192	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
4193	}
4194	else /* nothing to do */
4195	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
4196	}
4197
4198	/**
4199	* Clear references to guest physical memory.
4200	*
4201	* This is the same as pgmPoolTracDerefGCPhysHint except that the guest
4202	* physical address is assumed to be correct, so the linear search can be
4203	* skipped and we can assert at an earlier point.
4204	*
4205	* @param pPool The pool.
4206	* @param pPage The page.
4207	* @param HCPhys The host physical address corresponding to the guest page.
4208	* @param GCPhys The guest physical address corresponding to HCPhys.
4209	* @param iPte Shadow PTE index
4210	*/
4211	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys, uint16_t iPte)
4212	{
4213	/*
4214	* Lookup the page and check if it checks out before derefing it.
4215	*/
4216	PVMCC pVM = pPool->CTX_SUFF(pVM);
4217	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhys);
4218	if (pPhysPage)
4219	{
4220	Assert(PGM_PAGE_GET_HCPHYS(pPhysPage));
4221	#ifdef LOG_ENABLED
4222	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(pPhysPage);
4223	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
4224	#endif
4225	if (PGM_PAGE_GET_HCPHYS(pPhysPage) == HCPhys)
4226	{
4227	Assert(pPage->cPresent);
4228	Assert(pPool->cPresent);
4229	pPage->cPresent--;
4230	pPool->cPresent--;
4231	pgmTrackDerefGCPhys(pPool, pPage, pPhysPage, iPte);
4232	return;
4233	}
4234
4235	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp; found page has HCPhys=%RHp\n",
4236	HCPhys, GCPhys, PGM_PAGE_GET_HCPHYS(pPhysPage)));
4237	}
4238	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
4239	}
4240
4241
4242	/**
4243	* Clear references to guest physical memory.
4244	*
4245	* @param pPool The pool.
4246	* @param pPage The page.
4247	* @param HCPhys The host physical address corresponding to the guest page.
4248	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
4249	* @param iPte Shadow pte index
4250	*/
4251	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte)
4252	{
4253	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
4254
4255	/*
4256	* Try the hint first.
4257	*/
4258	RTHCPHYS HCPhysHinted;
4259	PVMCC pVM = pPool->CTX_SUFF(pVM);
4260	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysHint);
4261	if (pPhysPage)
4262	{
4263	HCPhysHinted = PGM_PAGE_GET_HCPHYS(pPhysPage);
4264	Assert(HCPhysHinted);
4265	if (HCPhysHinted == HCPhys)
4266	{
4267	Assert(pPage->cPresent);
4268	Assert(pPool->cPresent);
4269	pPage->cPresent--;
4270	pPool->cPresent--;
4271	pgmTrackDerefGCPhys(pPool, pPage, pPhysPage, iPte);
4272	return;
4273	}
4274	}
4275	else
4276	HCPhysHinted = UINT64_C(0xdeadbeefdeadbeef);
4277
4278	/*
4279	* Damn, the hint didn't work. We'll have to do an expensive linear search.
4280	*/
4281	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
4282	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRangesX);
4283	while (pRam)
4284	{
4285	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4286	while (iPage-- > 0)
4287	{
4288	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
4289	{
4290	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
4291	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
4292	Assert(pPage->cPresent);
4293	Assert(pPool->cPresent);
4294	pPage->cPresent--;
4295	pPool->cPresent--;
4296	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage], iPte);
4297	return;
4298	}
4299	}
4300	pRam = pRam->CTX_SUFF(pNext);
4301	}
4302
4303	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp (Hinted page has HCPhys = %RHp)\n", HCPhys, GCPhysHint, HCPhysHinted));
4304	}
4305
4306
4307	/**
4308	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
4309	*
4310	* @param pPool The pool.
4311	* @param pPage The page.
4312	* @param pShwPT The shadow page table (mapping of the page).
4313	* @param pGstPT The guest page table.
4314	*/
4315	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
4316	{
4317	RTGCPHYS32 const fPgMask = pPage->fA20Enabled ? X86_PTE_PG_MASK : X86_PTE_PG_MASK & ~RT_BIT_32(20);
4318	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4319	{
4320	const X86PGUINT uPte = pShwPT->a[i].u;
4321	Assert(!(uPte & RT_BIT_32(10)));
4322	if (uPte & X86_PTE_P)
4323	{
4324	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
4325	i, uPte & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
4326	pgmPoolTracDerefGCPhysHint(pPool, pPage, uPte & X86_PTE_PG_MASK, pGstPT->a[i].u & fPgMask, i);
4327	if (!pPage->cPresent)
4328	break;
4329	}
4330	}
4331	}
4332
4333
4334	/**
4335	* Clear references to guest physical memory in a PAE / 32-bit page table.
4336	*
4337	* @param pPool The pool.
4338	* @param pPage The page.
4339	* @param pShwPT The shadow page table (mapping of the page).
4340	* @param pGstPT The guest page table (just a half one).
4341	*/
4342	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PT pGstPT)
4343	{
4344	RTGCPHYS32 const fPgMask = pPage->fA20Enabled ? X86_PTE_PG_MASK : X86_PTE_PG_MASK & ~RT_BIT_32(20);
4345	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4346	{
4347	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4348	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4349	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4350	{
4351	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
4352	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PG_MASK));
4353	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
4354	if (!pPage->cPresent)
4355	break;
4356	}
4357	}
4358	}
4359
4360
4361	/**
4362	* Clear references to guest physical memory in a PAE / PAE page table.
4363	*
4364	* @param pPool The pool.
4365	* @param pPage The page.
4366	* @param pShwPT The shadow page table (mapping of the page).
4367	* @param pGstPT The guest page table.
4368	*/
4369	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT, PCX86PTPAE pGstPT)
4370	{
4371	RTGCPHYS const fPgMask = pPage->fA20Enabled ? X86_PTE_PAE_PG_MASK : X86_PTE_PAE_PG_MASK & ~RT_BIT_64(20);
4372	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
4373	{
4374	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4375	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4376	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4377	{
4378	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
4379	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
4380	pgmPoolTracDerefGCPhysHint(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), pGstPT->a[i].u & fPgMask, i);
4381	if (!pPage->cPresent)
4382	break;
4383	}
4384	}
4385	}
4386
4387
4388	/**
4389	* Clear references to guest physical memory in a 32-bit / 4MB page table.
4390	*
4391	* @param pPool The pool.
4392	* @param pPage The page.
4393	* @param pShwPT The shadow page table (mapping of the page).
4394	*/
4395	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
4396	{
4397	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4398	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4399	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4400	{
4401	const X86PGUINT uPte = pShwPT->a[i].u;
4402	Assert(!(uPte & RT_BIT_32(10)));
4403	if (uPte & X86_PTE_P)
4404	{
4405	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
4406	i, uPte & X86_PTE_PG_MASK, GCPhys));
4407	pgmPoolTracDerefGCPhys(pPool, pPage, uPte & X86_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
4408	if (!pPage->cPresent)
4409	break;
4410	}
4411	}
4412	}
4413
4414
4415	/**
4416	* Clear references to guest physical memory in a PAE / 2/4MB page table.
4417	*
4418	* @param pPool The pool.
4419	* @param pPage The page.
4420	* @param pShwPT The shadow page table (mapping of the page).
4421	*/
4422	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMSHWPTPAE pShwPT)
4423	{
4424	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4425	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4426	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4427	{
4428	Assert( (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == 0
4429	\|\| (PGMSHWPTEPAE_GET_U(pShwPT->a[i]) & UINT64_C(0x7ff0000000000400)) == UINT64_C(0x7ff0000000000000));
4430	if (PGMSHWPTEPAE_IS_P(pShwPT->a[i]))
4431	{
4432	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
4433	i, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys));
4434	pgmPoolTracDerefGCPhys(pPool, pPage, PGMSHWPTEPAE_GET_HCPHYS(pShwPT->a[i]), GCPhys & GCPhysA20Mask, i);
4435	if (!pPage->cPresent)
4436	break;
4437	}
4438	}
4439	}
4440
4441
4442	/**
4443	* Clear references to shadowed pages in an EPT page table.
4444	*
4445	* @param pPool The pool.
4446	* @param pPage The page.
4447	* @param pShwPT The shadow page directory pointer table (mapping of the
4448	* page).
4449	*/
4450	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
4451	{
4452	RTGCPHYS const GCPhysA20Mask = pPage->fA20Enabled ? UINT64_MAX : ~RT_BIT_64(20);
4453	RTGCPHYS GCPhys = pPage->GCPhys + PAGE_SIZE * pPage->iFirstPresent;
4454	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
4455	{
4456	X86PGPAEUINT const uPte = pShwPT->a[i].u;
4457	Assert((uPte & UINT64_C(0xfff0000000000f80)) == 0);
4458	if (uPte & EPT_E_READ)
4459	{
4460	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
4461	i, uPte & EPT_PTE_PG_MASK, pPage->GCPhys));
4462	pgmPoolTracDerefGCPhys(pPool, pPage, uPte & EPT_PTE_PG_MASK, GCPhys & GCPhysA20Mask, i);
4463	if (!pPage->cPresent)
4464	break;
4465	}
4466	}
4467	}
4468
4469
4470	/**
4471	* Clear references to shadowed pages in a 32 bits page directory.
4472	*
4473	* @param pPool The pool.
4474	* @param pPage The page.
4475	* @param pShwPD The shadow page directory (mapping of the page).
4476	*/
4477	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
4478	{
4479	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4480	{
4481	X86PGUINT const uPde = pShwPD->a[i].u;
4482	#ifndef PGM_WITHOUT_MAPPINGS
4483	if ((uPde & (X86_PDE_P \| PGM_PDFLAGS_MAPPING)) == X86_PDE_P)
4484	#else
4485	if (uPde & X86_PDE_P)
4486	#endif
4487	{
4488	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
4489	if (pSubPage)
4490	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4491	else
4492	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
4493	}
4494	}
4495	}
4496
4497
4498	/**
4499	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
4500	*
4501	* @param pPool The pool.
4502	* @param pPage The page.
4503	* @param pShwPD The shadow page directory (mapping of the page).
4504	*/
4505	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
4506	{
4507	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4508	{
4509	X86PGPAEUINT const uPde = pShwPD->a[i].u;
4510	#ifndef PGM_WITHOUT_MAPPINGS
4511	if ((uPde & (X86_PDE_P \| PGM_PDFLAGS_MAPPING)) == X86_PDE_P)
4512	#else
4513	if (uPde & X86_PDE_P)
4514	#endif
4515	{
4516	#ifdef PGM_WITH_LARGE_PAGES
4517	if (uPde & X86_PDE_PS)
4518	{
4519	Log4(("pgmPoolTrackDerefPDPae: i=%d pde=%RX64 GCPhys=%RX64\n",
4520	i, uPde & X86_PDE2M_PAE_PG_MASK, pPage->GCPhys));
4521	pgmPoolTracDerefGCPhys(pPool, pPage, uPde & X86_PDE2M_PAE_PG_MASK,
4522	pPage->GCPhys + i * 2 * _1M /* pPage->GCPhys = base address of the memory described by the PD */,
4523	i);
4524	}
4525	else
4526	#endif
4527	{
4528	Assert((uPde & (X86_PDE_PAE_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000000))) == 0);
4529	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, uPde & X86_PDE_PAE_PG_MASK);
4530	if (pSubPage)
4531	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4532	else
4533	AssertFatalMsgFailed(("%RX64\n", uPde & X86_PDE_PAE_PG_MASK));
4534	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4535	}
4536	}
4537	}
4538	}
4539
4540
4541	/**
4542	* Clear references to shadowed pages in a PAE page directory pointer table.
4543	*
4544	* @param pPool The pool.
4545	* @param pPage The page.
4546	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4547	*/
4548	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4549	{
4550	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4551	{
4552	X86PGPAEUINT const uPdpe = pShwPDPT->a[i].u;
4553	Assert((uPdpe & (X86_PDPE_PAE_MBZ_MASK \| UINT64_C(0x7ff0000000000200))) == 0);
4554	if ( uPdpe & X86_PDPE_P
4555	#ifndef PGM_WITHOUT_MAPPINGS
4556	&& !(uPdpe & PGM_PLXFLAGS_MAPPING)
4557	#endif
4558	)
4559	{
4560	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, uPdpe & X86_PDPE_PG_MASK);
4561	if (pSubPage)
4562	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4563	else
4564	AssertFatalMsgFailed(("%RX64\n", uPdpe & X86_PDPE_PG_MASK));
4565	}
4566	}
4567	}
4568
4569
4570	/**
4571	* Clear references to shadowed pages in a 64-bit page directory pointer table.
4572	*
4573	* @param pPool The pool.
4574	* @param pPage The page.
4575	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4576	*/
4577	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
4578	{
4579	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4580	{
4581	X86PGPAEUINT const uPdpe = pShwPDPT->a[i].u;
4582	Assert((uPdpe & (X86_PDPE_LM_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4583	if (uPdpe & X86_PDPE_P)
4584	{
4585	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, uPdpe & X86_PDPE_PG_MASK);
4586	if (pSubPage)
4587	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4588	else
4589	AssertFatalMsgFailed(("%RX64\n", uPdpe & X86_PDPE_PG_MASK));
4590	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4591	}
4592	}
4593	}
4594
4595
4596	/**
4597	* Clear references to shadowed pages in a 64-bit level 4 page table.
4598	*
4599	* @param pPool The pool.
4600	* @param pPage The page.
4601	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
4602	*/
4603	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
4604	{
4605	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
4606	{
4607	X86PGPAEUINT const uPml4e = pShwPML4->a[i].u;
4608	Assert((uPml4e & (X86_PML4E_MBZ_MASK_NX \| UINT64_C(0x7ff0000000000200))) == 0);
4609	if (uPml4e & X86_PML4E_P)
4610	{
4611	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, uPml4e & X86_PDPE_PG_MASK);
4612	if (pSubPage)
4613	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4614	else
4615	AssertFatalMsgFailed(("%RX64\n", uPml4e & X86_PML4E_PG_MASK));
4616	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4617	}
4618	}
4619	}
4620
4621
4622	/**
4623	* Clear references to shadowed pages in an EPT page directory.
4624	*
4625	* @param pPool The pool.
4626	* @param pPage The page.
4627	* @param pShwPD The shadow page directory (mapping of the page).
4628	*/
4629	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
4630	{
4631	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
4632	{
4633	X86PGPAEUINT const uPde = pShwPD->a[i].u;
4634	Assert((uPde & UINT64_C(0xfff0000000000f80)) == 0);
4635	if (uPde & EPT_E_READ)
4636	{
4637	#ifdef PGM_WITH_LARGE_PAGES
4638	if (uPde & EPT_E_LEAF)
4639	{
4640	Log4(("pgmPoolTrackDerefPDEPT: i=%d pde=%RX64 GCPhys=%RX64\n",
4641	i, uPde & EPT_PDE2M_PG_MASK, pPage->GCPhys));
4642	pgmPoolTracDerefGCPhys(pPool, pPage, uPde & EPT_PDE2M_PG_MASK,
4643	pPage->GCPhys + i * 2 * _1M /* pPage->GCPhys = base address of the memory described by the PD */,
4644	i);
4645	}
4646	else
4647	#endif
4648	{
4649	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, uPde & EPT_PDE_PG_MASK);
4650	if (pSubPage)
4651	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4652	else
4653	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
4654	}
4655	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4656	}
4657	}
4658	}
4659
4660
4661	/**
4662	* Clear references to shadowed pages in an EPT page directory pointer table.
4663	*
4664	* @param pPool The pool.
4665	* @param pPage The page.
4666	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
4667	*/
4668	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
4669	{
4670	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
4671	{
4672	X86PGPAEUINT const uPdpe = pShwPDPT->a[i].u;
4673	Assert((uPdpe & UINT64_C(0xfff0000000000f80)) == 0);
4674	if (uPdpe & EPT_E_READ)
4675	{
4676	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, uPdpe & EPT_PDPTE_PG_MASK);
4677	if (pSubPage)
4678	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
4679	else
4680	AssertFatalMsgFailed(("%RX64\n", uPdpe & EPT_PDPTE_PG_MASK));
4681	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
4682	}
4683	}
4684	}
4685
4686
4687	/**
4688	* Clears all references made by this page.
4689	*
4690	* This includes other shadow pages and GC physical addresses.
4691	*
4692	* @param pPool The pool.
4693	* @param pPage The page.
4694	*/
4695	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4696	{
4697	/*
4698	* Map the shadow page and take action according to the page kind.
4699	*/
4700	PVMCC pVM = pPool->CTX_SUFF(pVM);
4701	void *pvShw = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4702	switch (pPage->enmKind)
4703	{
4704	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4705	{
4706	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4707	void *pvGst;
4708	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4709	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
4710	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4711	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4712	break;
4713	}
4714
4715	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4716	{
4717	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4718	void *pvGst;
4719	int rc = PGM_GCPHYS_2_PTR_EX(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4720	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PT)pvGst);
4721	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4722	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4723	break;
4724	}
4725
4726	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4727	{
4728	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4729	void *pvGst;
4730	int rc = PGM_GCPHYS_2_PTR(pVM, pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
4731	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PPGMSHWPTPAE)pvShw, (PCX86PTPAE)pvGst);
4732	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvGst);
4733	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4734	break;
4735	}
4736
4737	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
4738	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4739	{
4740	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4741	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
4742	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4743	break;
4744	}
4745
4746	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
4747	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4748	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4749	{
4750	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
4751	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PPGMSHWPTPAE)pvShw);
4752	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
4753	break;
4754	}
4755
4756	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4757	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4758	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4759	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4760	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4761	case PGMPOOLKIND_PAE_PD_PHYS:
4762	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4763	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4764	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
4765	break;
4766
4767	case PGMPOOLKIND_32BIT_PD_PHYS:
4768	case PGMPOOLKIND_32BIT_PD:
4769	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
4770	break;
4771
4772	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4773	case PGMPOOLKIND_PAE_PDPT:
4774	case PGMPOOLKIND_PAE_PDPT_PHYS:
4775	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
4776	break;
4777
4778	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4779	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4780	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
4781	break;
4782
4783	case PGMPOOLKIND_64BIT_PML4:
4784	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
4785	break;
4786
4787	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4788	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
4789	break;
4790
4791	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4792	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
4793	break;
4794
4795	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4796	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
4797	break;
4798
4799	default:
4800	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
4801	}
4802
4803	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
4804	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4805	ASMMemZeroPage(pvShw);
4806	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4807	pPage->fZeroed = true;
4808	Assert(!pPage->cPresent);
4809	PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvShw);
4810	}
4811
4812
4813	/**
4814	* Flushes a pool page.
4815	*
4816	* This moves the page to the free list after removing all user references to it.
4817	*
4818	* @returns VBox status code.
4819	* @retval VINF_SUCCESS on success.
4820	* @param pPool The pool.
4821	* @param pPage The shadow page.
4822	* @param fFlush Flush the TLBS when required (should only be false in very specific use cases!!)
4823	*/
4824	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush)
4825	{
4826	PVMCC pVM = pPool->CTX_SUFF(pVM);
4827	bool fFlushRequired = false;
4828
4829	int rc = VINF_SUCCESS;
4830	STAM_PROFILE_START(&pPool->StatFlushPage, f);
4831	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
4832	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
4833
4834	/*
4835	* Reject any attempts at flushing any of the special root pages (shall
4836	* not happen).
4837	*/
4838	AssertMsgReturn(pPage->idx >= PGMPOOL_IDX_FIRST,
4839	("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n",
4840	pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx),
4841	VINF_SUCCESS);
4842
4843	pgmLock(pVM);
4844
4845	/*
4846	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
4847	*/
4848	if (pgmPoolIsPageLocked(pPage))
4849	{
4850	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
4851	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
4852	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
4853	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
4854	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
4855	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
4856	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
4857	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
4858	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD
4859	\|\| pPage->enmKind == PGMPOOLKIND_ROOT_NESTED,
4860	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
4861	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
4862	pgmUnlock(pVM);
4863	return VINF_SUCCESS;
4864	}
4865
4866	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4867	/* Start a subset so we won't run out of mapping space. */
4868	PVMCPU pVCpu = VMMGetCpu(pVM);
4869	uint32_t iPrevSubset = PGMRZDynMapPushAutoSubset(pVCpu);
4870	#endif
4871
4872	/*
4873	* Mark the page as being in need of an ASMMemZeroPage().
4874	*/
4875	pPage->fZeroed = false;
4876
4877	#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4878	if (pPage->fDirty)
4879	pgmPoolFlushDirtyPage(pVM, pPool, pPage->idxDirtyEntry, false /* do not remove */);
4880	#endif
4881
4882	/* If there are any users of this table, then we must issue a tlb flush on all VCPUs. */
4883	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
4884	fFlushRequired = true;
4885
4886	/*
4887	* Clear the page.
4888	*/
4889	pgmPoolTrackClearPageUsers(pPool, pPage);
4890	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
4891	pgmPoolTrackDeref(pPool, pPage);
4892	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
4893
4894	/*
4895	* Flush it from the cache.
4896	*/
4897	pgmPoolCacheFlushPage(pPool, pPage);
4898
4899	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4900	/* Heavy stuff done. */
4901	PGMRZDynMapPopAutoSubset(pVCpu, iPrevSubset);
4902	#endif
4903
4904	/*
4905	* Deregistering the monitoring.
4906	*/
4907	if (pPage->fMonitored)
4908	rc = pgmPoolMonitorFlush(pPool, pPage);
4909
4910	/*
4911	* Free the page.
4912	*/
4913	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
4914	pPage->iNext = pPool->iFreeHead;
4915	pPool->iFreeHead = pPage->idx;
4916	pPage->enmKind = PGMPOOLKIND_FREE;
4917	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4918	pPage->GCPhys = NIL_RTGCPHYS;
4919	pPage->fReusedFlushPending = false;
4920
4921	pPool->cUsedPages--;
4922
4923	/* Flush the TLBs of all VCPUs if required. */
4924	if ( fFlushRequired
4925	&& fFlush)
4926	{
4927	PGM_INVL_ALL_VCPU_TLBS(pVM);
4928	}
4929
4930	pgmUnlock(pVM);
4931	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
4932	return rc;
4933	}
4934
4935
4936	/**
4937	* Frees a usage of a pool page.
4938	*
4939	* The caller is responsible to updating the user table so that it no longer
4940	* references the shadow page.
4941	*
4942	* @param pPool The pool.
4943	* @param pPage The shadow page.
4944	* @param iUser The shadow page pool index of the user table.
4945	* NIL_PGMPOOL_IDX for root pages.
4946	* @param iUserTable The index into the user table (shadowed). Ignored if
4947	* root page.
4948	*/
4949	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
4950	{
4951	PVMCC pVM = pPool->CTX_SUFF(pVM);
4952
4953	STAM_PROFILE_START(&pPool->StatFree, a);
4954	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%d iUserTable=%#x\n",
4955	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
4956	AssertReturnVoid(pPage->idx >= PGMPOOL_IDX_FIRST); /* paranoia (#6349) */
4957
4958	pgmLock(pVM);
4959	if (iUser != NIL_PGMPOOL_IDX)
4960	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
4961	if (!pPage->fCached)
4962	pgmPoolFlushPage(pPool, pPage);
4963	pgmUnlock(pVM);
4964	STAM_PROFILE_STOP(&pPool->StatFree, a);
4965	}
4966
4967
4968	/**
4969	* Makes one or more free page free.
4970	*
4971	* @returns VBox status code.
4972	* @retval VINF_SUCCESS on success.
4973	*
4974	* @param pPool The pool.
4975	* @param enmKind Page table kind
4976	* @param iUser The user of the page.
4977	*/
4978	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
4979	{
4980	PVMCC pVM = pPool->CTX_SUFF(pVM);
4981	LogFlow(("pgmPoolMakeMoreFreePages: enmKind=%d iUser=%d\n", enmKind, iUser));
4982	NOREF(enmKind);
4983
4984	/*
4985	* If the pool isn't full grown yet, expand it.
4986	*/
4987	if (pPool->cCurPages < pPool->cMaxPages)
4988	{
4989	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
4990	#ifdef IN_RING3
4991	int rc = PGMR3PoolGrow(pVM, VMMGetCpu(pVM));
4992	#else
4993	int rc = VMMRZCallRing3NoCpu(pVM, VMMCALLRING3_PGM_POOL_GROW, 0);
4994	#endif
4995	if (RT_FAILURE(rc))
4996	return rc;
4997	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4998	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4999	return VINF_SUCCESS;
5000	}
5001
5002	/*
5003	* Free one cached page.
5004	*/
5005	return pgmPoolCacheFreeOne(pPool, iUser);
5006	}
5007
5008
5009	/**
5010	* Allocates a page from the pool.
5011	*
5012	* This page may actually be a cached page and not in need of any processing
5013	* on the callers part.
5014	*
5015	* @returns VBox status code.
5016	* @retval VINF_SUCCESS if a NEW page was allocated.
5017	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
5018	*
5019	* @param pVM The cross context VM structure.
5020	* @param GCPhys The GC physical address of the page we're gonna shadow.
5021	* For 4MB and 2MB PD entries, it's the first address the
5022	* shadow PT is covering.
5023	* @param enmKind The kind of mapping.
5024	* @param enmAccess Access type for the mapping (only relevant for big pages)
5025	* @param fA20Enabled Whether the A20 gate is enabled or not.
5026	* @param iUser The shadow page pool index of the user table. Root
5027	* pages should pass NIL_PGMPOOL_IDX.
5028	* @param iUserTable The index into the user table (shadowed). Ignored for
5029	* root pages (iUser == NIL_PGMPOOL_IDX).
5030	* @param fLockPage Lock the page
5031	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
5032	*/
5033	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
5034	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage)
5035	{
5036	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5037	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
5038	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%d iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
5039	*ppPage = NULL;
5040	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
5041	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
5042	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)); */
5043
5044	pgmLock(pVM);
5045
5046	if (pPool->fCacheEnabled)
5047	{
5048	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, fA20Enabled, iUser, iUserTable, ppPage);
5049	if (RT_SUCCESS(rc2))
5050	{
5051	if (fLockPage)
5052	pgmPoolLockPage(pPool, *ppPage);
5053	pgmUnlock(pVM);
5054	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5055	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
5056	return rc2;
5057	}
5058	}
5059
5060	/*
5061	* Allocate a new one.
5062	*/
5063	int rc = VINF_SUCCESS;
5064	uint16_t iNew = pPool->iFreeHead;
5065	if (iNew == NIL_PGMPOOL_IDX)
5066	{
5067	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
5068	if (RT_FAILURE(rc))
5069	{
5070	pgmUnlock(pVM);
5071	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
5072	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5073	return rc;
5074	}
5075	iNew = pPool->iFreeHead;
5076	AssertReleaseMsgReturn(iNew != NIL_PGMPOOL_IDX, ("iNew=%#x\n", iNew), VERR_PGM_POOL_IPE);
5077	}
5078
5079	/* unlink the free head */
5080	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
5081	pPool->iFreeHead = pPage->iNext;
5082	pPage->iNext = NIL_PGMPOOL_IDX;
5083
5084	/*
5085	* Initialize it.
5086	*/
5087	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
5088	pPage->enmKind = enmKind;
5089	pPage->enmAccess = enmAccess;
5090	pPage->GCPhys = GCPhys;
5091	pPage->fA20Enabled = fA20Enabled;
5092	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
5093	pPage->fMonitored = false;
5094	pPage->fCached = false;
5095	pPage->fDirty = false;
5096	pPage->fReusedFlushPending = false;
5097	pPage->cModifications = 0;
5098	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5099	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5100	pPage->cPresent = 0;
5101	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
5102	pPage->idxDirtyEntry = 0;
5103	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
5104	pPage->GCPtrLastAccessHandlerRip = NIL_RTGCPTR;
5105	pPage->cLastAccessHandler = 0;
5106	pPage->cLocked = 0;
5107	# ifdef VBOX_STRICT
5108	pPage->GCPtrDirtyFault = NIL_RTGCPTR;
5109	# endif
5110
5111	/*
5112	* Insert into the tracking and cache. If this fails, free the page.
5113	*/
5114	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
5115	if (RT_FAILURE(rc3))
5116	{
5117	pPool->cUsedPages--;
5118	pPage->enmKind = PGMPOOLKIND_FREE;
5119	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5120	pPage->GCPhys = NIL_RTGCPHYS;
5121	pPage->iNext = pPool->iFreeHead;
5122	pPool->iFreeHead = pPage->idx;
5123	pgmUnlock(pVM);
5124	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5125	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
5126	return rc3;
5127	}
5128
5129	/*
5130	* Commit the allocation, clear the page and return.
5131	*/
5132	#ifdef VBOX_WITH_STATISTICS
5133	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
5134	pPool->cUsedPagesHigh = pPool->cUsedPages;
5135	#endif
5136
5137	if (!pPage->fZeroed)
5138	{
5139	STAM_PROFILE_START(&pPool->StatZeroPage, z);
5140	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
5141	ASMMemZeroPage(pv);
5142	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
5143	}
5144
5145	*ppPage = pPage;
5146	if (fLockPage)
5147	pgmPoolLockPage(pPool, pPage);
5148	pgmUnlock(pVM);
5149	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
5150	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
5151	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
5152	return rc;
5153	}
5154
5155
5156	/**
5157	* Frees a usage of a pool page.
5158	*
5159	* @param pVM The cross context VM structure.
5160	* @param HCPhys The HC physical address of the shadow page.
5161	* @param iUser The shadow page pool index of the user table.
5162	* NIL_PGMPOOL_IDX if root page.
5163	* @param iUserTable The index into the user table (shadowed). Ignored if
5164	* root page.
5165	*/
5166	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
5167	{
5168	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%d iUserTable=%#x\n", HCPhys, iUser, iUserTable));
5169	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5170	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
5171	}
5172
5173
5174	/**
5175	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
5176	*
5177	* @returns Pointer to the shadow page structure.
5178	* @param pPool The pool.
5179	* @param HCPhys The HC physical address of the shadow page.
5180	*/
5181	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
5182	{
5183	PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
5184
5185	/*
5186	* Look up the page.
5187	*/
5188	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5189
5190	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
5191	return pPage;
5192	}
5193
5194
5195	/**
5196	* Internal worker for finding a page for debugging purposes, no assertions.
5197	*
5198	* @returns Pointer to the shadow page structure. NULL on if not found.
5199	* @param pPool The pool.
5200	* @param HCPhys The HC physical address of the shadow page.
5201	*/
5202	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys)
5203	{
5204	PGM_LOCK_ASSERT_OWNER(pPool->CTX_SUFF(pVM));
5205	return (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5206	}
5207
5208
5209	/**
5210	* Internal worker for PGM_HCPHYS_2_PTR.
5211	*
5212	* @returns VBox status code.
5213	* @param pVM The cross context VM structure.
5214	* @param HCPhys The HC physical address of the shadow page.
5215	* @param ppv Where to return the address.
5216	*/
5217	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv)
5218	{
5219	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pVM->pgm.s.CTX_SUFF(pPool)->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
5220	AssertMsgReturn(pPage && pPage->enmKind != PGMPOOLKIND_FREE,
5221	("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0),
5222	VERR_PGM_POOL_GET_PAGE_FAILED);
5223	ppv = (uint8_t )pPage->CTX_SUFF(pvPage) + (HCPhys & PAGE_OFFSET_MASK);
5224	return VINF_SUCCESS;
5225	}
5226
5227	#ifdef IN_RING3 /* currently only used in ring 3; save some space in the R0 & GC modules (left it here as we might need it elsewhere later on) */
5228
5229	/**
5230	* Flush the specified page if present
5231	*
5232	* @param pVM The cross context VM structure.
5233	* @param GCPhys Guest physical address of the page to flush
5234	*/
5235	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys)
5236	{
5237	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5238
5239	VM_ASSERT_EMT(pVM);
5240
5241	/*
5242	* Look up the GCPhys in the hash.
5243	*/
5244	GCPhys = GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
5245	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
5246	if (i == NIL_PGMPOOL_IDX)
5247	return;
5248
5249	do
5250	{
5251	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5252	if (pPage->GCPhys - GCPhys < PAGE_SIZE)
5253	{
5254	switch (pPage->enmKind)
5255	{
5256	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5257	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5258	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5259	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5260	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5261	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5262	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5263	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5264	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5265	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5266	case PGMPOOLKIND_64BIT_PML4:
5267	case PGMPOOLKIND_32BIT_PD:
5268	case PGMPOOLKIND_PAE_PDPT:
5269	{
5270	Log(("PGMPoolFlushPage: found pgm pool pages for %RGp\n", GCPhys));
5271	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5272	if (pPage->fDirty)
5273	STAM_COUNTER_INC(&pPool->StatForceFlushDirtyPage);
5274	else
5275	# endif
5276	STAM_COUNTER_INC(&pPool->StatForceFlushPage);
5277	Assert(!pgmPoolIsPageLocked(pPage));
5278	pgmPoolMonitorChainFlush(pPool, pPage);
5279	return;
5280	}
5281
5282	/* ignore, no monitoring. */
5283	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5284	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5285	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5286	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5287	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5288	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5289	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5290	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5291	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5292	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5293	case PGMPOOLKIND_ROOT_NESTED:
5294	case PGMPOOLKIND_PAE_PD_PHYS:
5295	case PGMPOOLKIND_PAE_PDPT_PHYS:
5296	case PGMPOOLKIND_32BIT_PD_PHYS:
5297	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5298	break;
5299
5300	default:
5301	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
5302	}
5303	}
5304
5305	/* next */
5306	i = pPage->iNext;
5307	} while (i != NIL_PGMPOOL_IDX);
5308	return;
5309	}
5310
5311
5312	/**
5313	* Reset CPU on hot plugging.
5314	*
5315	* @param pVM The cross context VM structure.
5316	* @param pVCpu The cross context virtual CPU structure.
5317	*/
5318	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
5319	{
5320	pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
5321
5322	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5323	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5324	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5325	}
5326
5327
5328	/**
5329	* Flushes the entire cache.
5330	*
5331	* It will assert a global CR3 flush (FF) and assumes the caller is aware of
5332	* this and execute this CR3 flush.
5333	*
5334	* @param pVM The cross context VM structure.
5335	*/
5336	void pgmR3PoolReset(PVM pVM)
5337	{
5338	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5339
5340	PGM_LOCK_ASSERT_OWNER(pVM);
5341	STAM_PROFILE_START(&pPool->StatR3Reset, a);
5342	LogFlow(("pgmR3PoolReset:\n"));
5343
5344	/*
5345	* If there are no pages in the pool, there is nothing to do.
5346	*/
5347	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
5348	{
5349	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5350	return;
5351	}
5352
5353	/*
5354	* Exit the shadow mode since we're going to clear everything,
5355	* including the root page.
5356	*/
5357	VMCC_FOR_EACH_VMCPU(pVM)
5358	pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
5359	VMCC_FOR_EACH_VMCPU_END(pVM);
5360
5361
5362	/*
5363	* Nuke the free list and reinsert all pages into it.
5364	*/
5365	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
5366	{
5367	PPGMPOOLPAGE pPage = &pPool->aPages[i];
5368
5369	if (pPage->fMonitored)
5370	pgmPoolMonitorFlush(pPool, pPage);
5371	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
5372	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
5373	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
5374	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
5375	pPage->GCPhys = NIL_RTGCPHYS;
5376	pPage->enmKind = PGMPOOLKIND_FREE;
5377	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
5378	Assert(pPage->idx == i);
5379	pPage->iNext = i + 1;
5380	pPage->fA20Enabled = true;
5381	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
5382	pPage->fSeenNonGlobal = false;
5383	pPage->fMonitored = false;
5384	pPage->fDirty = false;
5385	pPage->fCached = false;
5386	pPage->fReusedFlushPending = false;
5387	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
5388	pPage->cPresent = 0;
5389	pPage->iFirstPresent = NIL_PGMPOOL_PRESENT_INDEX;
5390	pPage->cModifications = 0;
5391	pPage->iAgeNext = NIL_PGMPOOL_IDX;
5392	pPage->iAgePrev = NIL_PGMPOOL_IDX;
5393	pPage->idxDirtyEntry = 0;
5394	pPage->GCPtrLastAccessHandlerRip = NIL_RTGCPTR;
5395	pPage->GCPtrLastAccessHandlerFault = NIL_RTGCPTR;
5396	pPage->cLastAccessHandler = 0;
5397	pPage->cLocked = 0;
5398	# ifdef VBOX_STRICT
5399	pPage->GCPtrDirtyFault = NIL_RTGCPTR;
5400	# endif
5401	}
5402	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
5403	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
5404	pPool->cUsedPages = 0;
5405
5406	/*
5407	* Zap and reinitialize the user records.
5408	*/
5409	pPool->cPresent = 0;
5410	pPool->iUserFreeHead = 0;
5411	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
5412	const unsigned cMaxUsers = pPool->cMaxUsers;
5413	for (unsigned i = 0; i < cMaxUsers; i++)
5414	{
5415	paUsers[i].iNext = i + 1;
5416	paUsers[i].iUser = NIL_PGMPOOL_IDX;
5417	paUsers[i].iUserTable = 0xfffffffe;
5418	}
5419	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
5420
5421	/*
5422	* Clear all the GCPhys links and rebuild the phys ext free list.
5423	*/
5424	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
5425	pRam;
5426	pRam = pRam->CTX_SUFF(pNext))
5427	{
5428	unsigned iPage = pRam->cb >> PAGE_SHIFT;
5429	while (iPage-- > 0)
5430	PGM_PAGE_SET_TRACKING(pVM, &pRam->aPages[iPage], 0);
5431	}
5432
5433	pPool->iPhysExtFreeHead = 0;
5434	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
5435	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
5436	for (unsigned i = 0; i < cMaxPhysExts; i++)
5437	{
5438	paPhysExts[i].iNext = i + 1;
5439	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
5440	paPhysExts[i].apte[0] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5441	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
5442	paPhysExts[i].apte[1] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5443	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
5444	paPhysExts[i].apte[2] = NIL_PGMPOOL_PHYSEXT_IDX_PTE;
5445	}
5446	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
5447
5448	/*
5449	* Just zap the modified list.
5450	*/
5451	pPool->cModifiedPages = 0;
5452	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
5453
5454	/*
5455	* Clear the GCPhys hash and the age list.
5456	*/
5457	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
5458	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
5459	pPool->iAgeHead = NIL_PGMPOOL_IDX;
5460	pPool->iAgeTail = NIL_PGMPOOL_IDX;
5461
5462	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5463	/* Clear all dirty pages. */
5464	pPool->idxFreeDirtyPage = 0;
5465	pPool->cDirtyPages = 0;
5466	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aidxDirtyPages); i++)
5467	pPool->aidxDirtyPages[i] = NIL_PGMPOOL_IDX;
5468	# endif
5469
5470	/*
5471	* Reinsert active pages into the hash and ensure monitoring chains are correct.
5472	*/
5473	VMCC_FOR_EACH_VMCPU(pVM)
5474	{
5475	/*
5476	* Re-enter the shadowing mode and assert Sync CR3 FF.
5477	*/
5478	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
5479	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
5480	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
5481	}
5482	VMCC_FOR_EACH_VMCPU_END(pVM);
5483
5484	STAM_PROFILE_STOP(&pPool->StatR3Reset, a);
5485	}
5486
5487	#endif /* IN_RING3 */
5488
5489	#if defined(LOG_ENABLED) \|\| defined(VBOX_STRICT)
5490	/**
5491	* Stringifies a PGMPOOLKIND value.
5492	*/
5493	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
5494	{
5495	switch ((PGMPOOLKIND)enmKind)
5496	{
5497	case PGMPOOLKIND_INVALID:
5498	return "PGMPOOLKIND_INVALID";
5499	case PGMPOOLKIND_FREE:
5500	return "PGMPOOLKIND_FREE";
5501	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
5502	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
5503	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
5504	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
5505	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
5506	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
5507	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
5508	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
5509	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
5510	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
5511	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
5512	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
5513	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
5514	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
5515	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
5516	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
5517	case PGMPOOLKIND_32BIT_PD:
5518	return "PGMPOOLKIND_32BIT_PD";
5519	case PGMPOOLKIND_32BIT_PD_PHYS:
5520	return "PGMPOOLKIND_32BIT_PD_PHYS";
5521	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
5522	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
5523	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
5524	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
5525	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
5526	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
5527	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
5528	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
5529	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
5530	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
5531	case PGMPOOLKIND_PAE_PD_PHYS:
5532	return "PGMPOOLKIND_PAE_PD_PHYS";
5533	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
5534	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
5535	case PGMPOOLKIND_PAE_PDPT:
5536	return "PGMPOOLKIND_PAE_PDPT";
5537	case PGMPOOLKIND_PAE_PDPT_PHYS:
5538	return "PGMPOOLKIND_PAE_PDPT_PHYS";
5539	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
5540	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
5541	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
5542	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
5543	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
5544	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
5545	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
5546	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
5547	case PGMPOOLKIND_64BIT_PML4:
5548	return "PGMPOOLKIND_64BIT_PML4";
5549	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
5550	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
5551	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
5552	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
5553	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
5554	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
5555	case PGMPOOLKIND_ROOT_NESTED:
5556	return "PGMPOOLKIND_ROOT_NESTED";
5557	}
5558	return "Unknown kind!";
5559	}
5560	#endif /* LOG_ENABLED \|\| VBOX_STRICT */
5561

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 86667

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