VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 19087

Last change on this file since 19087 was 18992, checked in by vboxsync, 16 years ago

More PGM api changes

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1/* $Id: PGMAllShw.h 18992 2009-04-17 13:51:56Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Defined Constants And Macros *
24*******************************************************************************/
25#undef SHWPT
26#undef PSHWPT
27#undef SHWPTE
28#undef PSHWPTE
29#undef SHWPD
30#undef PSHWPD
31#undef SHWPDE
32#undef PSHWPDE
33#undef SHW_PDE_PG_MASK
34#undef SHW_PD_SHIFT
35#undef SHW_PD_MASK
36#undef SHW_PTE_PG_MASK
37#undef SHW_PT_SHIFT
38#undef SHW_PT_MASK
39#undef SHW_TOTAL_PD_ENTRIES
40#undef SHW_PDPT_SHIFT
41#undef SHW_PDPT_MASK
42#undef SHW_PDPE_PG_MASK
43#undef SHW_POOL_ROOT_IDX
44
45#if PGM_SHW_TYPE == PGM_TYPE_32BIT
46# define SHWPT X86PT
47# define PSHWPT PX86PT
48# define SHWPTE X86PTE
49# define PSHWPTE PX86PTE
50# define SHWPD X86PD
51# define PSHWPD PX86PD
52# define SHWPDE X86PDE
53# define PSHWPDE PX86PDE
54# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
55# define SHW_PD_SHIFT X86_PD_SHIFT
56# define SHW_PD_MASK X86_PD_MASK
57# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
58# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
59# define SHW_PT_SHIFT X86_PT_SHIFT
60# define SHW_PT_MASK X86_PT_MASK
61# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
62
63#elif PGM_SHW_TYPE == PGM_TYPE_EPT
64# define SHWPT EPTPT
65# define PSHWPT PEPTPT
66# define SHWPTE EPTPTE
67# define PSHWPTE PEPTPTE
68# define SHWPD EPTPD
69# define PSHWPD PEPTPD
70# define SHWPDE EPTPDE
71# define PSHWPDE PEPTPDE
72# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
73# define SHW_PD_SHIFT EPT_PD_SHIFT
74# define SHW_PD_MASK EPT_PD_MASK
75# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
76# define SHW_PT_SHIFT EPT_PT_SHIFT
77# define SHW_PT_MASK EPT_PT_MASK
78# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
79# define SHW_PDPT_MASK EPT_PDPT_MASK
80# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
81# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
82# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
83
84#else
85# define SHWPT X86PTPAE
86# define PSHWPT PX86PTPAE
87# define SHWPTE X86PTEPAE
88# define PSHWPTE PX86PTEPAE
89# define SHWPD X86PDPAE
90# define PSHWPD PX86PDPAE
91# define SHWPDE X86PDEPAE
92# define PSHWPDE PX86PDEPAE
93# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
94# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
95# define SHW_PD_MASK X86_PD_PAE_MASK
96# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
97# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
98# define SHW_PT_MASK X86_PT_PAE_MASK
99
100# if PGM_SHW_TYPE == PGM_TYPE_AMD64
101# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
102# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
103# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
104# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
105# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_AMD64_CR3
106
107# else /* 32 bits PAE mode */
108# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
109# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
110# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
111# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
112# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PDPT
113
114# endif
115#endif
116
117
118
119/*******************************************************************************
120* Internal Functions *
121*******************************************************************************/
122__BEGIN_DECLS
123PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
124PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
125__END_DECLS
126
127
128
129/**
130 * Gets effective page information (from the VMM page directory).
131 *
132 * @returns VBox status.
133 * @param pVCpu The VMCPU handle.
134 * @param GCPtr Guest Context virtual address of the page.
135 * @param pfFlags Where to store the flags. These are X86_PTE_*.
136 * @param pHCPhys Where to store the HC physical address of the page.
137 * This is page aligned.
138 * @remark You should use PGMMapGetPage() for pages in a mapping.
139 */
140PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
141{
142#if PGM_SHW_TYPE == PGM_TYPE_NESTED
143 return VERR_PAGE_TABLE_NOT_PRESENT;
144
145#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
146 PVM pVM = pVCpu->CTX_SUFF(pVM);
147
148 /*
149 * Get the PDE.
150 */
151# if PGM_SHW_TYPE == PGM_TYPE_AMD64
152 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
153 X86PDEPAE Pde;
154
155 /* PML4 */
156 X86PML4E Pml4e = pgmShwGetLongModePML4E(&pVCpu->pgm.s, GCPtr);
157 if (!Pml4e.n.u1Present)
158 return VERR_PAGE_TABLE_NOT_PRESENT;
159
160 /* PDPT */
161 PX86PDPT pPDPT;
162 int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
163 if (RT_FAILURE(rc))
164 return rc;
165 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
166 X86PDPE Pdpe = pPDPT->a[iPDPT];
167 if (!Pdpe.n.u1Present)
168 return VERR_PAGE_TABLE_NOT_PRESENT;
169
170 /* PD */
171 PX86PDPAE pPd;
172 rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
173 if (RT_FAILURE(rc))
174 return rc;
175 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
176 Pde = pPd->a[iPd];
177
178 /* Merge accessed, write, user and no-execute bits into the PDE. */
179 Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
180 Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
181 Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
182 Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
183
184# elif PGM_SHW_TYPE == PGM_TYPE_PAE
185 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
186 X86PDEPAE Pde = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtr);
187
188# elif PGM_SHW_TYPE == PGM_TYPE_EPT
189 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
190 PEPTPD pPDDst;
191 EPTPDE Pde;
192
193 int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
194 if (rc != VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
195 {
196 AssertRC(rc);
197 return rc;
198 }
199 Assert(pPDDst);
200 Pde = pPDDst->a[iPd];
201
202# else /* PGM_TYPE_32BIT */
203 X86PDE Pde = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtr);
204# endif
205 if (!Pde.n.u1Present)
206 return VERR_PAGE_TABLE_NOT_PRESENT;
207
208 Assert(!Pde.b.u1Size);
209
210 /*
211 * Get PT entry.
212 */
213 PSHWPT pPT;
214 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
215 {
216 int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
217 if (RT_FAILURE(rc))
218 return rc;
219 }
220 else /* mapping: */
221 {
222# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
223 || PGM_SHW_TYPE == PGM_TYPE_EPT
224 AssertFailed(); /* can't happen */
225# else
226 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
227
228 PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
229 AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_INTERNAL_ERROR);
230# if PGM_SHW_TYPE == PGM_TYPE_32BIT
231 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
232# else /* PAE */
233 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
234# endif
235# endif
236 }
237 const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
238 SHWPTE Pte = pPT->a[iPt];
239 if (!Pte.n.u1Present)
240 return VERR_PAGE_NOT_PRESENT;
241
242 /*
243 * Store the results.
244 * RW and US flags depend on the entire page translation hierarchy - except for
245 * legacy PAE which has a simplified PDPE.
246 */
247 if (pfFlags)
248 {
249 *pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
250 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
251# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
252 /* The NX bit is determined by a bitwise OR between the PT and PD */
253 if (fNoExecuteBitValid)
254 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
255# endif
256 }
257
258 if (pHCPhys)
259 *pHCPhys = Pte.u & SHW_PTE_PG_MASK;
260
261 return VINF_SUCCESS;
262#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
263}
264
265
266/**
267 * Modify page flags for a range of pages in the shadow context.
268 *
269 * The existing flags are ANDed with the fMask and ORed with the fFlags.
270 *
271 * @returns VBox status code.
272 * @param pVCpu The VMCPU handle.
273 * @param GCPtr Virtual address of the first page in the range. Page aligned!
274 * @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
275 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
276 * @param fMask The AND mask - page flags X86_PTE_*.
277 * Be extremely CAREFUL with ~'ing values because they can be 32-bit!
278 * @remark You must use PGMMapModifyPage() for pages in a mapping.
279 */
280PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
281{
282# if PGM_SHW_TYPE == PGM_TYPE_NESTED
283 return VERR_PAGE_TABLE_NOT_PRESENT;
284
285# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
286 PVM pVM = pVCpu->CTX_SUFF(pVM);
287 int rc;
288
289 /*
290 * Walk page tables and pages till we're done.
291 */
292 for (;;)
293 {
294 /*
295 * Get the PDE.
296 */
297# if PGM_SHW_TYPE == PGM_TYPE_AMD64
298 X86PDEPAE Pde;
299 /* PML4 */
300 X86PML4E Pml4e = pgmShwGetLongModePML4E(&pVCpu->pgm.s, GCPtr);
301 if (!Pml4e.n.u1Present)
302 return VERR_PAGE_TABLE_NOT_PRESENT;
303
304 /* PDPT */
305 PX86PDPT pPDPT;
306 rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
307 if (RT_FAILURE(rc))
308 return rc;
309 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
310 X86PDPE Pdpe = pPDPT->a[iPDPT];
311 if (!Pdpe.n.u1Present)
312 return VERR_PAGE_TABLE_NOT_PRESENT;
313
314 /* PD */
315 PX86PDPAE pPd;
316 rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
317 if (RT_FAILURE(rc))
318 return rc;
319 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
320 Pde = pPd->a[iPd];
321
322# elif PGM_SHW_TYPE == PGM_TYPE_PAE
323 X86PDEPAE Pde = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtr);
324
325# elif PGM_SHW_TYPE == PGM_TYPE_EPT
326 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
327 PEPTPD pPDDst;
328 EPTPDE Pde;
329
330 rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
331 if (rc != VINF_SUCCESS)
332 {
333 AssertRC(rc);
334 return rc;
335 }
336 Assert(pPDDst);
337 Pde = pPDDst->a[iPd];
338
339# else /* PGM_TYPE_32BIT */
340 X86PDE Pde = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtr);
341# endif
342 if (!Pde.n.u1Present)
343 return VERR_PAGE_TABLE_NOT_PRESENT;
344
345 /*
346 * Map the page table.
347 */
348 PSHWPT pPT;
349 rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
350 if (RT_FAILURE(rc))
351 return rc;
352
353 unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
354 while (iPTE < RT_ELEMENTS(pPT->a))
355 {
356 if (pPT->a[iPTE].n.u1Present)
357 {
358 pPT->a[iPTE].u = (pPT->a[iPTE].u & (fMask | SHW_PTE_PG_MASK)) | (fFlags & ~SHW_PTE_PG_MASK);
359 Assert(pPT->a[iPTE].n.u1Present);
360# if PGM_SHW_TYPE == PGM_TYPE_EPT
361 HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
362# else
363 PGM_INVL_PG(GCPtr);
364# endif
365 }
366
367 /* next page */
368 cb -= PAGE_SIZE;
369 if (!cb)
370 return VINF_SUCCESS;
371 GCPtr += PAGE_SIZE;
372 iPTE++;
373 }
374 }
375# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
376}
377
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