PGMAllShw.h@ 9029

Last change on this file since 9029 was 9023, checked in by vboxsync, 17 years ago
Fixed some runtime assertions
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 10.9 KB

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1	/* $Id: PGMAllShw.h 9023 2008-05-21 14:48:23Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Defined Constants And Macros *
24	*******************************************************************************/
25	#undef SHWPT
26	#undef PSHWPT
27	#undef SHWPTE
28	#undef PSHWPTE
29	#undef SHWPD
30	#undef PSHWPD
31	#undef SHWPDE
32	#undef PSHWPDE
33	#undef SHW_PDE_PG_MASK
34	#undef SHW_PD_SHIFT
35	#undef SHW_PD_MASK
36	#undef SHW_PTE_PG_MASK
37	#undef SHW_PT_SHIFT
38	#undef SHW_PT_MASK
39	#undef SHW_TOTAL_PD_ENTRIES
40	#undef SHW_PDPT_SHIFT
41	#undef SHW_PDPT_MASK
42	#undef SHW_POOL_ROOT_IDX
43
44	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
45	# define SHWPT X86PT
46	# define PSHWPT PX86PT
47	# define SHWPTE X86PTE
48	# define PSHWPTE PX86PTE
49	# define SHWPD X86PD
50	# define PSHWPD PX86PD
51	# define SHWPDE X86PDE
52	# define PSHWPDE PX86PDE
53	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
54	# define SHW_PD_SHIFT X86_PD_SHIFT
55	# define SHW_PD_MASK X86_PD_MASK
56	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
57	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
58	# define SHW_PT_SHIFT X86_PT_SHIFT
59	# define SHW_PT_MASK X86_PT_MASK
60	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
61	#else
62	# define SHWPT X86PTPAE
63	# define PSHWPT PX86PTPAE
64	# define SHWPTE X86PTEPAE
65	# define PSHWPTE PX86PTEPAE
66	# define SHWPD X86PDPAE
67	# define PSHWPD PX86PDPAE
68	# define SHWPDE X86PDEPAE
69	# define PSHWPDE PX86PDEPAE
70	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
71	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
72	# define SHW_PD_MASK X86_PD_PAE_MASK
73	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
74	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
75	# define SHW_PT_MASK X86_PT_PAE_MASK
76	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
77	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
78	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
79	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
80	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PML4
81	#else /* 32 bits PAE mode */
82	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
83	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
84	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
85	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD
86	#endif
87	#endif
88
89
90
91	/*******************************************************************************
92	* Internal Functions *
93	*******************************************************************************/
94	__BEGIN_DECLS
95	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
96	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
97	__END_DECLS
98
99
100
101	/**
102	* Gets effective page information (from the VMM page directory).
103	*
104	* @returns VBox status.
105	* @param pVM VM Handle.
106	* @param GCPtr Guest Context virtual address of the page.
107	* @param pfFlags Where to store the flags. These are X86_PTE_*.
108	* @param pHCPhys Where to store the HC physical address of the page.
109	* This is page aligned.
110	* @remark You should use PGMMapGetPage() for pages in a mapping.
111	*/
112	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
113	{
114	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
115	return VERR_PAGE_TABLE_NOT_PRESENT;
116	#else
117	/*
118	* Get the PDE.
119	*/
120	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
121	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
122	X86PDEPAE Pde;
123
124	/* PML4 */
125	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
126	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
127	if (!Pml4e.n.u1Present)
128	return VERR_PAGE_TABLE_NOT_PRESENT;
129
130	/* PDPT */
131	PX86PDPT pPDPT;
132	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
133	if (VBOX_FAILURE(rc))
134	return rc;
135	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
136	X86PDPE Pdpe = pPDPT->a[iPDPT];
137	if (!Pdpe.n.u1Present)
138	return VERR_PAGE_TABLE_NOT_PRESENT;
139
140	/* PD */
141	PX86PDPAE pPd;
142	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
143	if (VBOX_FAILURE(rc))
144	return rc;
145	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
146	Pde = pPd->a[iPd];
147
148	/* Merge accessed, write, user and no-execute bits into the PDE. */
149	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
150	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
151	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
152	Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
153
154	#elif PGM_SHW_TYPE == PGM_TYPE_PAE
155	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
156	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
157	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
158	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
159
160	#else /* PGM_TYPE_32BIT */
161	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
162	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
163	#endif
164	if (!Pde.n.u1Present)
165	return VERR_PAGE_TABLE_NOT_PRESENT;
166
167	Assert(!Pde.b.u1Size);
168
169	/*
170	* Get PT entry.
171	*/
172	PSHWPT pPT;
173	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
174	{
175	int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
176	if (VBOX_FAILURE(rc))
177	return rc;
178	}
179	else /* mapping: */
180	{
181	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
182	AssertFailed(); /* can't happen */
183	#else
184	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
185
186	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
187	AssertMsgReturn(pMap, ("GCPtr=%VGv\n", GCPtr), VERR_INTERNAL_ERROR);
188	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
189	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTXALLSUFF(pPT);
190	# else /* PAE */
191	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTXALLSUFF(paPaePTs);
192	# endif
193	#endif
194	}
195	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
196	SHWPTE Pte = pPT->a[iPt];
197	if (!Pte.n.u1Present)
198	return VERR_PAGE_NOT_PRESENT;
199
200	/*
201	* Store the results.
202	* RW and US flags depend on the entire page translation hierarchy - except for
203	* legacy PAE which has a simplified PDPE.
204	*/
205	if (pfFlags)
206	{
207	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
208	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
209	# if PGM_WITH_NX(PGM_SHW_TYPE)
210	/* The NX bit is determined by a bitwise OR between the PT and PD */
211	if (fNoExecuteBitValid)
212	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
213	# endif
214	}
215
216	if (pHCPhys)
217	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
218
219	return VINF_SUCCESS;
220	#endif /* PGM_SHW_TYPE == PGM_TYPE_NESTED */
221	}
222
223
224	/**
225	* Modify page flags for a range of pages in the shadow context.
226	*
227	* The existing flags are ANDed with the fMask and ORed with the fFlags.
228	*
229	* @returns VBox status code.
230	* @param pVM VM handle.
231	* @param GCPtr Virtual address of the first page in the range. Page aligned!
232	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
233	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
234	* @param fMask The AND mask - page flags X86_PTE_*.
235	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
236	* @remark You must use PGMMapModifyPage() for pages in a mapping.
237	*/
238	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
239	{
240	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
241	return VERR_PAGE_TABLE_NOT_PRESENT;
242	#else
243	int rc;
244
245	/*
246	* Walk page tables and pages till we're done.
247	*/
248	for (;;)
249	{
250	/*
251	* Get the PDE.
252	*/
253	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
254	X86PDEPAE Pde;
255	/* PML4 */
256	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
257	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
258	if (!Pml4e.n.u1Present)
259	return VERR_PAGE_TABLE_NOT_PRESENT;
260
261	/* PDPT */
262	PX86PDPT pPDPT;
263	rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
264	if (VBOX_FAILURE(rc))
265	return rc;
266	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
267	X86PDPE Pdpe = pPDPT->a[iPDPT];
268	if (!Pdpe.n.u1Present)
269	return VERR_PAGE_TABLE_NOT_PRESENT;
270
271	/* PD */
272	PX86PDPAE pPd;
273	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
274	if (VBOX_FAILURE(rc))
275	return rc;
276	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
277	Pde = pPd->a[iPd];
278
279	#elif PGM_SHW_TYPE == PGM_TYPE_PAE
280	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
281	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
282	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
283
284	#else /* PGM_TYPE_32BIT */
285	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
286	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
287	#endif
288	if (!Pde.n.u1Present)
289	return VERR_PAGE_TABLE_NOT_PRESENT;
290
291	/*
292	* Map the page table.
293	*/
294	PSHWPT pPT;
295	rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
296	if (VBOX_FAILURE(rc))
297	return rc;
298
299	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
300	while (iPTE < ELEMENTS(pPT->a))
301	{
302	if (pPT->a[iPTE].n.u1Present)
303	{
304	pPT->a[iPTE].u = (pPT->a[iPTE].u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
305	Assert(pPT->a[iPTE].n.u1Present);
306	PGM_INVL_PG(GCPtr);
307	}
308
309	/* next page */
310	cb -= PAGE_SIZE;
311	if (!cb)
312	return VINF_SUCCESS;
313	GCPtr += PAGE_SIZE;
314	iPTE++;
315	}
316	}
317	#endif /* PGM_SHW_TYPE == PGM_TYPE_NESTED */
318	}
319

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 9029

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