PGMAllShw.h@ 10502

Last change on this file since 10502 was 9893, checked in by vboxsync, 16 years ago
Attempt to fix PAE (can't verify now). AMD64 paging updates.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 11.2 KB

Line
1	/* $Id: PGMAllShw.h 9893 2008-06-24 15:56:57Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Defined Constants And Macros *
24	*******************************************************************************/
25	#undef SHWPT
26	#undef PSHWPT
27	#undef SHWPTE
28	#undef PSHWPTE
29	#undef SHWPD
30	#undef PSHWPD
31	#undef SHWPDE
32	#undef PSHWPDE
33	#undef SHW_PDE_PG_MASK
34	#undef SHW_PD_SHIFT
35	#undef SHW_PD_MASK
36	#undef SHW_PTE_PG_MASK
37	#undef SHW_PT_SHIFT
38	#undef SHW_PT_MASK
39	#undef SHW_TOTAL_PD_ENTRIES
40	#undef SHW_PDPT_SHIFT
41	#undef SHW_PDPT_MASK
42	#undef SHW_PDPE_PG_MASK
43	#undef SHW_POOL_ROOT_IDX
44
45	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
46	# define SHWPT X86PT
47	# define PSHWPT PX86PT
48	# define SHWPTE X86PTE
49	# define PSHWPTE PX86PTE
50	# define SHWPD X86PD
51	# define PSHWPD PX86PD
52	# define SHWPDE X86PDE
53	# define PSHWPDE PX86PDE
54	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
55	# define SHW_PD_SHIFT X86_PD_SHIFT
56	# define SHW_PD_MASK X86_PD_MASK
57	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
58	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
59	# define SHW_PT_SHIFT X86_PT_SHIFT
60	# define SHW_PT_MASK X86_PT_MASK
61	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
62	#else
63	# define SHWPT X86PTPAE
64	# define PSHWPT PX86PTPAE
65	# define SHWPTE X86PTEPAE
66	# define PSHWPTE PX86PTEPAE
67	# define SHWPD X86PDPAE
68	# define PSHWPD PX86PDPAE
69	# define SHWPDE X86PDEPAE
70	# define PSHWPDE PX86PDEPAE
71	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
72	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
73	# define SHW_PD_MASK X86_PD_PAE_MASK
74	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
75	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
76	# define SHW_PT_MASK X86_PT_PAE_MASK
77	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
78	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
79	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
80	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
81	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
82	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD /* do not use! exception is real mode & protected mode without paging. */
83	#else /* 32 bits PAE mode */
84	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
85	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
86	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
87	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
88	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD
89	#endif
90	#endif
91
92
93
94	/*******************************************************************************
95	* Internal Functions *
96	*******************************************************************************/
97	__BEGIN_DECLS
98	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
99	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
100	__END_DECLS
101
102
103
104	/**
105	* Gets effective page information (from the VMM page directory).
106	*
107	* @returns VBox status.
108	* @param pVM VM Handle.
109	* @param GCPtr Guest Context virtual address of the page.
110	* @param pfFlags Where to store the flags. These are X86_PTE_*.
111	* @param pHCPhys Where to store the HC physical address of the page.
112	* This is page aligned.
113	* @remark You should use PGMMapGetPage() for pages in a mapping.
114	*/
115	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
116	{
117	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
118	return VERR_PAGE_TABLE_NOT_PRESENT;
119
120	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
121	/*
122	* Get the PDE.
123	*/
124	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
125	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
126	X86PDEPAE Pde;
127
128	/* PML4 */
129	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
130	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
131	if (!Pml4e.n.u1Present)
132	return VERR_PAGE_TABLE_NOT_PRESENT;
133
134	/* PDPT */
135	PX86PDPT pPDPT;
136	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
137	if (VBOX_FAILURE(rc))
138	return rc;
139	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
140	X86PDPE Pdpe = pPDPT->a[iPDPT];
141	if (!Pdpe.n.u1Present)
142	return VERR_PAGE_TABLE_NOT_PRESENT;
143
144	/* PD */
145	PX86PDPAE pPd;
146	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
147	if (VBOX_FAILURE(rc))
148	return rc;
149	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
150	Pde = pPd->a[iPd];
151
152	/* Merge accessed, write, user and no-execute bits into the PDE. */
153	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
154	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
155	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
156	Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
157
158	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
159	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
160	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
161	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
162	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
163
164	# else /* PGM_TYPE_32BIT */
165	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
166	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
167	# endif
168	if (!Pde.n.u1Present)
169	return VERR_PAGE_TABLE_NOT_PRESENT;
170
171	Assert(!Pde.b.u1Size);
172
173	/*
174	* Get PT entry.
175	*/
176	PSHWPT pPT;
177	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
178	{
179	int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
180	if (VBOX_FAILURE(rc))
181	return rc;
182	}
183	else /* mapping: */
184	{
185	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
186	AssertFailed(); /* can't happen */
187	# else
188	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
189
190	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
191	AssertMsgReturn(pMap, ("GCPtr=%VGv\n", GCPtr), VERR_INTERNAL_ERROR);
192	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
193	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTXALLSUFF(pPT);
194	# else /* PAE */
195	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTXALLSUFF(paPaePTs);
196	# endif
197	# endif
198	}
199	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
200	SHWPTE Pte = pPT->a[iPt];
201	if (!Pte.n.u1Present)
202	return VERR_PAGE_NOT_PRESENT;
203
204	/*
205	* Store the results.
206	* RW and US flags depend on the entire page translation hierarchy - except for
207	* legacy PAE which has a simplified PDPE.
208	*/
209	if (pfFlags)
210	{
211	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
212	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
213	# if PGM_WITH_NX(PGM_SHW_TYPE)
214	/* The NX bit is determined by a bitwise OR between the PT and PD */
215	if (fNoExecuteBitValid)
216	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
217	# endif
218	}
219
220	if (pHCPhys)
221	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
222
223	return VINF_SUCCESS;
224	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
225	}
226
227
228	/**
229	* Modify page flags for a range of pages in the shadow context.
230	*
231	* The existing flags are ANDed with the fMask and ORed with the fFlags.
232	*
233	* @returns VBox status code.
234	* @param pVM VM handle.
235	* @param GCPtr Virtual address of the first page in the range. Page aligned!
236	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
237	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
238	* @param fMask The AND mask - page flags X86_PTE_*.
239	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
240	* @remark You must use PGMMapModifyPage() for pages in a mapping.
241	*/
242	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
243	{
244	# if PGM_SHW_TYPE == PGM_TYPE_NESTED
245	return VERR_PAGE_TABLE_NOT_PRESENT;
246
247	# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
248	int rc;
249
250	/*
251	* Walk page tables and pages till we're done.
252	*/
253	for (;;)
254	{
255	/*
256	* Get the PDE.
257	*/
258	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
259	X86PDEPAE Pde;
260	/* PML4 */
261	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
262	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
263	if (!Pml4e.n.u1Present)
264	return VERR_PAGE_TABLE_NOT_PRESENT;
265
266	/* PDPT */
267	PX86PDPT pPDPT;
268	rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
269	if (VBOX_FAILURE(rc))
270	return rc;
271	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
272	X86PDPE Pdpe = pPDPT->a[iPDPT];
273	if (!Pdpe.n.u1Present)
274	return VERR_PAGE_TABLE_NOT_PRESENT;
275
276	/* PD */
277	PX86PDPAE pPd;
278	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
279	if (VBOX_FAILURE(rc))
280	return rc;
281	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
282	Pde = pPd->a[iPd];
283
284	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
285	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
286	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
287	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
288
289	# else /* PGM_TYPE_32BIT */
290	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
291	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
292	# endif
293	if (!Pde.n.u1Present)
294	return VERR_PAGE_TABLE_NOT_PRESENT;
295
296	/*
297	* Map the page table.
298	*/
299	PSHWPT pPT;
300	rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
301	if (VBOX_FAILURE(rc))
302	return rc;
303
304	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
305	while (iPTE < ELEMENTS(pPT->a))
306	{
307	if (pPT->a[iPTE].n.u1Present)
308	{
309	pPT->a[iPTE].u = (pPT->a[iPTE].u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
310	Assert(pPT->a[iPTE].n.u1Present);
311	PGM_INVL_PG(GCPtr);
312	}
313
314	/* next page */
315	cb -= PAGE_SIZE;
316	if (!cb)
317	return VINF_SUCCESS;
318	GCPtr += PAGE_SIZE;
319	iPTE++;
320	}
321	}
322	# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
323	}
324

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 10502

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