PGMAllShw.h@ 13152

Last change on this file since 13152 was 13019, checked in by vboxsync, 16 years ago
#1865: PGM ...
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1	/* $Id: PGMAllShw.h 13019 2008-10-06 16:21:01Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Defined Constants And Macros *
24	*******************************************************************************/
25	#undef SHWPT
26	#undef PSHWPT
27	#undef SHWPTE
28	#undef PSHWPTE
29	#undef SHWPD
30	#undef PSHWPD
31	#undef SHWPDE
32	#undef PSHWPDE
33	#undef SHW_PDE_PG_MASK
34	#undef SHW_PD_SHIFT
35	#undef SHW_PD_MASK
36	#undef SHW_PTE_PG_MASK
37	#undef SHW_PT_SHIFT
38	#undef SHW_PT_MASK
39	#undef SHW_TOTAL_PD_ENTRIES
40	#undef SHW_PDPT_SHIFT
41	#undef SHW_PDPT_MASK
42	#undef SHW_PDPE_PG_MASK
43	#undef SHW_POOL_ROOT_IDX
44
45	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
46	# define SHWPT X86PT
47	# define PSHWPT PX86PT
48	# define SHWPTE X86PTE
49	# define PSHWPTE PX86PTE
50	# define SHWPD X86PD
51	# define PSHWPD PX86PD
52	# define SHWPDE X86PDE
53	# define PSHWPDE PX86PDE
54	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
55	# define SHW_PD_SHIFT X86_PD_SHIFT
56	# define SHW_PD_MASK X86_PD_MASK
57	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
58	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
59	# define SHW_PT_SHIFT X86_PT_SHIFT
60	# define SHW_PT_MASK X86_PT_MASK
61	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
62	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
63	# define SHWPT EPTPT
64	# define PSHWPT PEPTPT
65	# define SHWPTE EPTPTE
66	# define PSHWPTE PEPTPTE
67	# define SHWPD EPTPD
68	# define PSHWPD PEPTPD
69	# define SHWPDE EPTPDE
70	# define PSHWPDE PEPTPDE
71	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
72	# define SHW_PD_SHIFT EPT_PD_SHIFT
73	# define SHW_PD_MASK EPT_PD_MASK
74	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
75	# define SHW_PT_SHIFT EPT_PT_SHIFT
76	# define SHW_PT_MASK EPT_PT_MASK
77	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
78	# define SHW_PDPT_MASK EPT_PDPT_MASK
79	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
80	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
81	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
82	#else
83	# define SHWPT X86PTPAE
84	# define PSHWPT PX86PTPAE
85	# define SHWPTE X86PTEPAE
86	# define PSHWPTE PX86PTEPAE
87	# define SHWPD X86PDPAE
88	# define PSHWPD PX86PDPAE
89	# define SHWPDE X86PDEPAE
90	# define PSHWPDE PX86PDEPAE
91	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
92	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
93	# define SHW_PD_MASK X86_PD_PAE_MASK
94	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
95	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
96	# define SHW_PT_MASK X86_PT_PAE_MASK
97	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
98	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
99	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
100	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
101	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
102	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD /* do not use! exception is real mode & protected mode without paging. */
103	#else /* 32 bits PAE mode */
104	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
105	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
106	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
107	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
108	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD
109	#endif
110	#endif
111
112
113
114	/*******************************************************************************
115	* Internal Functions *
116	*******************************************************************************/
117	__BEGIN_DECLS
118	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
119	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
120	__END_DECLS
121
122
123
124	/**
125	* Gets effective page information (from the VMM page directory).
126	*
127	* @returns VBox status.
128	* @param pVM VM Handle.
129	* @param GCPtr Guest Context virtual address of the page.
130	* @param pfFlags Where to store the flags. These are X86_PTE_*.
131	* @param pHCPhys Where to store the HC physical address of the page.
132	* This is page aligned.
133	* @remark You should use PGMMapGetPage() for pages in a mapping.
134	*/
135	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
136	{
137	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
138	return VERR_PAGE_TABLE_NOT_PRESENT;
139
140	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
141	/*
142	* Get the PDE.
143	*/
144	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
145	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
146	X86PDEPAE Pde;
147
148	/* PML4 */
149	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
150	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
151	if (!Pml4e.n.u1Present)
152	return VERR_PAGE_TABLE_NOT_PRESENT;
153
154	/* PDPT */
155	PX86PDPT pPDPT;
156	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
157	if (VBOX_FAILURE(rc))
158	return rc;
159	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
160	X86PDPE Pdpe = pPDPT->a[iPDPT];
161	if (!Pdpe.n.u1Present)
162	return VERR_PAGE_TABLE_NOT_PRESENT;
163
164	/* PD */
165	PX86PDPAE pPd;
166	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
167	if (VBOX_FAILURE(rc))
168	return rc;
169	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
170	Pde = pPd->a[iPd];
171
172	/* Merge accessed, write, user and no-execute bits into the PDE. */
173	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
174	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
175	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
176	Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
177
178	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
179	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
180	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
181	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
182	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
183
184	# else /* PGM_TYPE_32BIT */
185	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
186	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
187	# endif
188	if (!Pde.n.u1Present)
189	return VERR_PAGE_TABLE_NOT_PRESENT;
190
191	Assert(!Pde.b.u1Size);
192
193	/*
194	* Get PT entry.
195	*/
196	PSHWPT pPT;
197	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
198	{
199	int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
200	if (VBOX_FAILURE(rc))
201	return rc;
202	}
203	else /* mapping: */
204	{
205	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
206	AssertFailed(); /* can't happen */
207	# else
208	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
209
210	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
211	AssertMsgReturn(pMap, ("GCPtr=%VGv\n", GCPtr), VERR_INTERNAL_ERROR);
212	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
213	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
214	# else /* PAE */
215	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
216	# endif
217	# endif
218	}
219	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
220	SHWPTE Pte = pPT->a[iPt];
221	if (!Pte.n.u1Present)
222	return VERR_PAGE_NOT_PRESENT;
223
224	/*
225	* Store the results.
226	* RW and US flags depend on the entire page translation hierarchy - except for
227	* legacy PAE which has a simplified PDPE.
228	*/
229	if (pfFlags)
230	{
231	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
232	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
233	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
234	/* The NX bit is determined by a bitwise OR between the PT and PD */
235	if (fNoExecuteBitValid)
236	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
237	# endif
238	}
239
240	if (pHCPhys)
241	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
242
243	return VINF_SUCCESS;
244	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
245	}
246
247
248	/**
249	* Modify page flags for a range of pages in the shadow context.
250	*
251	* The existing flags are ANDed with the fMask and ORed with the fFlags.
252	*
253	* @returns VBox status code.
254	* @param pVM VM handle.
255	* @param GCPtr Virtual address of the first page in the range. Page aligned!
256	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
257	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
258	* @param fMask The AND mask - page flags X86_PTE_*.
259	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
260	* @remark You must use PGMMapModifyPage() for pages in a mapping.
261	*/
262	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
263	{
264	# if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
265	return VERR_PAGE_TABLE_NOT_PRESENT;
266
267	# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
268	int rc;
269
270	/*
271	* Walk page tables and pages till we're done.
272	*/
273	for (;;)
274	{
275	/*
276	* Get the PDE.
277	*/
278	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
279	X86PDEPAE Pde;
280	/* PML4 */
281	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
282	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
283	if (!Pml4e.n.u1Present)
284	return VERR_PAGE_TABLE_NOT_PRESENT;
285
286	/* PDPT */
287	PX86PDPT pPDPT;
288	rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
289	if (VBOX_FAILURE(rc))
290	return rc;
291	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
292	X86PDPE Pdpe = pPDPT->a[iPDPT];
293	if (!Pdpe.n.u1Present)
294	return VERR_PAGE_TABLE_NOT_PRESENT;
295
296	/* PD */
297	PX86PDPAE pPd;
298	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
299	if (VBOX_FAILURE(rc))
300	return rc;
301	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
302	Pde = pPd->a[iPd];
303
304	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
305	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
306	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
307	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
308
309	# else /* PGM_TYPE_32BIT */
310	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
311	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
312	# endif
313	if (!Pde.n.u1Present)
314	return VERR_PAGE_TABLE_NOT_PRESENT;
315
316	/*
317	* Map the page table.
318	*/
319	PSHWPT pPT;
320	rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
321	if (VBOX_FAILURE(rc))
322	return rc;
323
324	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
325	while (iPTE < RT_ELEMENTS(pPT->a))
326	{
327	if (pPT->a[iPTE].n.u1Present)
328	{
329	pPT->a[iPTE].u = (pPT->a[iPTE].u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
330	Assert(pPT->a[iPTE].n.u1Present);
331	PGM_INVL_PG(GCPtr);
332	}
333
334	/* next page */
335	cb -= PAGE_SIZE;
336	if (!cb)
337	return VINF_SUCCESS;
338	GCPtr += PAGE_SIZE;
339	iPTE++;
340	}
341	}
342	# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
343	}
344

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 13152

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