VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 13796

Last change on this file since 13796 was 13415, checked in by vboxsync, 16 years ago

VMM: a couple of comments.

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1/* $Id: PGMAllShw.h 13415 2008-10-20 23:22:47Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow Paging Template - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Defined Constants And Macros *
24*******************************************************************************/
25#undef SHWPT
26#undef PSHWPT
27#undef SHWPTE
28#undef PSHWPTE
29#undef SHWPD
30#undef PSHWPD
31#undef SHWPDE
32#undef PSHWPDE
33#undef SHW_PDE_PG_MASK
34#undef SHW_PD_SHIFT
35#undef SHW_PD_MASK
36#undef SHW_PTE_PG_MASK
37#undef SHW_PT_SHIFT
38#undef SHW_PT_MASK
39#undef SHW_TOTAL_PD_ENTRIES
40#undef SHW_PDPT_SHIFT
41#undef SHW_PDPT_MASK
42#undef SHW_PDPE_PG_MASK
43#undef SHW_POOL_ROOT_IDX
44
45#if PGM_SHW_TYPE == PGM_TYPE_32BIT
46# define SHWPT X86PT
47# define PSHWPT PX86PT
48# define SHWPTE X86PTE
49# define PSHWPTE PX86PTE
50# define SHWPD X86PD
51# define PSHWPD PX86PD
52# define SHWPDE X86PDE
53# define PSHWPDE PX86PDE
54# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
55# define SHW_PD_SHIFT X86_PD_SHIFT
56# define SHW_PD_MASK X86_PD_MASK
57# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
58# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
59# define SHW_PT_SHIFT X86_PT_SHIFT
60# define SHW_PT_MASK X86_PT_MASK
61# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
62
63#elif PGM_SHW_TYPE == PGM_TYPE_EPT
64# define SHWPT EPTPT
65# define PSHWPT PEPTPT
66# define SHWPTE EPTPTE
67# define PSHWPTE PEPTPTE
68# define SHWPD EPTPD
69# define PSHWPD PEPTPD
70# define SHWPDE EPTPDE
71# define PSHWPDE PEPTPDE
72# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
73# define SHW_PD_SHIFT EPT_PD_SHIFT
74# define SHW_PD_MASK EPT_PD_MASK
75# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
76# define SHW_PT_SHIFT EPT_PT_SHIFT
77# define SHW_PT_MASK EPT_PT_MASK
78# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
79# define SHW_PDPT_MASK EPT_PDPT_MASK
80# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
81# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
82# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
83
84#else
85# define SHWPT X86PTPAE
86# define PSHWPT PX86PTPAE
87# define SHWPTE X86PTEPAE
88# define PSHWPTE PX86PTEPAE
89# define SHWPD X86PDPAE
90# define PSHWPD PX86PDPAE
91# define SHWPDE X86PDEPAE
92# define PSHWPDE PX86PDEPAE
93# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
94# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
95# define SHW_PD_MASK X86_PD_PAE_MASK
96# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
97# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
98# define SHW_PT_MASK X86_PT_PAE_MASK
99# if PGM_SHW_TYPE == PGM_TYPE_AMD64
100# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
101# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
102# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
103# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
104# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD /* do not use! exception is real mode & protected mode without paging. */
105# else /* 32 bits PAE mode */
106# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
107# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
108# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
109# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
110# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD
111# endif
112#endif
113
114
115
116/*******************************************************************************
117* Internal Functions *
118*******************************************************************************/
119__BEGIN_DECLS
120PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
121PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
122__END_DECLS
123
124
125
126/**
127 * Gets effective page information (from the VMM page directory).
128 *
129 * @returns VBox status.
130 * @param pVM VM Handle.
131 * @param GCPtr Guest Context virtual address of the page.
132 * @param pfFlags Where to store the flags. These are X86_PTE_*.
133 * @param pHCPhys Where to store the HC physical address of the page.
134 * This is page aligned.
135 * @remark You should use PGMMapGetPage() for pages in a mapping.
136 */
137PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
138{
139#if PGM_SHW_TYPE == PGM_TYPE_NESTED
140 return VERR_PAGE_TABLE_NOT_PRESENT;
141
142#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
143 /*
144 * Get the PDE.
145 */
146# if PGM_SHW_TYPE == PGM_TYPE_AMD64
147 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
148 X86PDEPAE Pde;
149
150 /* PML4 */
151 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
152 X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
153 if (!Pml4e.n.u1Present)
154 return VERR_PAGE_TABLE_NOT_PRESENT;
155
156 /* PDPT */
157 PX86PDPT pPDPT;
158 int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
159 if (VBOX_FAILURE(rc))
160 return rc;
161 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
162 X86PDPE Pdpe = pPDPT->a[iPDPT];
163 if (!Pdpe.n.u1Present)
164 return VERR_PAGE_TABLE_NOT_PRESENT;
165
166 /* PD */
167 PX86PDPAE pPd;
168 rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
169 if (VBOX_FAILURE(rc))
170 return rc;
171 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
172 Pde = pPd->a[iPd];
173
174 /* Merge accessed, write, user and no-execute bits into the PDE. */
175 Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
176 Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
177 Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
178 Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
179
180# elif PGM_SHW_TYPE == PGM_TYPE_PAE
181 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
182 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
183 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
184 X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
185
186# elif PGM_SHW_TYPE == PGM_TYPE_EPT
187 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
188 PEPTPD pPDDst;
189 EPTPDE Pde;
190
191 int rc = PGMShwGetEPTPDPtr(pVM, GCPtr, NULL, &pPDDst);
192 if (rc != VINF_SUCCESS)
193 {
194 AssertRC(rc);
195 return rc;
196 }
197 Assert(pPDDst);
198 Pde = pPDDst->a[iPd];
199
200# else /* PGM_TYPE_32BIT */
201 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
202 X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
203# endif
204 if (!Pde.n.u1Present)
205 return VERR_PAGE_TABLE_NOT_PRESENT;
206
207 Assert(!Pde.b.u1Size);
208
209 /*
210 * Get PT entry.
211 */
212 PSHWPT pPT;
213 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
214 {
215 int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
216 if (VBOX_FAILURE(rc))
217 return rc;
218 }
219 else /* mapping: */
220 {
221# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
222 || PGM_SHW_TYPE == PGM_TYPE_EPT
223 AssertFailed(); /* can't happen */
224# else
225 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
226
227 PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
228 AssertMsgReturn(pMap, ("GCPtr=%VGv\n", GCPtr), VERR_INTERNAL_ERROR);
229# if PGM_SHW_TYPE == PGM_TYPE_32BIT
230 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
231# else /* PAE */
232 pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
233# endif
234# endif
235 }
236 const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
237 SHWPTE Pte = pPT->a[iPt];
238 if (!Pte.n.u1Present)
239 return VERR_PAGE_NOT_PRESENT;
240
241 /*
242 * Store the results.
243 * RW and US flags depend on the entire page translation hierarchy - except for
244 * legacy PAE which has a simplified PDPE.
245 */
246 if (pfFlags)
247 {
248 *pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
249 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
250# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
251 /* The NX bit is determined by a bitwise OR between the PT and PD */
252 if (fNoExecuteBitValid)
253 *pfFlags |= (Pte.u & Pde.u & X86_PTE_PAE_NX);
254# endif
255 }
256
257 if (pHCPhys)
258 *pHCPhys = Pte.u & SHW_PTE_PG_MASK;
259
260 return VINF_SUCCESS;
261#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
262}
263
264
265/**
266 * Modify page flags for a range of pages in the shadow context.
267 *
268 * The existing flags are ANDed with the fMask and ORed with the fFlags.
269 *
270 * @returns VBox status code.
271 * @param pVM VM handle.
272 * @param GCPtr Virtual address of the first page in the range. Page aligned!
273 * @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
274 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
275 * @param fMask The AND mask - page flags X86_PTE_*.
276 * Be extremely CAREFUL with ~'ing values because they can be 32-bit!
277 * @remark You must use PGMMapModifyPage() for pages in a mapping.
278 */
279PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
280{
281# if PGM_SHW_TYPE == PGM_TYPE_NESTED
282 return VERR_PAGE_TABLE_NOT_PRESENT;
283
284# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
285 int rc;
286
287 /*
288 * Walk page tables and pages till we're done.
289 */
290 for (;;)
291 {
292 /*
293 * Get the PDE.
294 */
295# if PGM_SHW_TYPE == PGM_TYPE_AMD64
296 X86PDEPAE Pde;
297 /* PML4 */
298 const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
299 X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
300 if (!Pml4e.n.u1Present)
301 return VERR_PAGE_TABLE_NOT_PRESENT;
302
303 /* PDPT */
304 PX86PDPT pPDPT;
305 rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
306 if (VBOX_FAILURE(rc))
307 return rc;
308 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
309 X86PDPE Pdpe = pPDPT->a[iPDPT];
310 if (!Pdpe.n.u1Present)
311 return VERR_PAGE_TABLE_NOT_PRESENT;
312
313 /* PD */
314 PX86PDPAE pPd;
315 rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
316 if (VBOX_FAILURE(rc))
317 return rc;
318 const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
319 Pde = pPd->a[iPd];
320
321# elif PGM_SHW_TYPE == PGM_TYPE_PAE
322 const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
323 const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
324 X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
325
326# elif PGM_SHW_TYPE == PGM_TYPE_EPT
327 const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
328 PEPTPD pPDDst;
329 EPTPDE Pde;
330
331 rc = PGMShwGetEPTPDPtr(pVM, GCPtr, NULL, &pPDDst);
332 if (rc != VINF_SUCCESS)
333 {
334 AssertRC(rc);
335 return rc;
336 }
337 Assert(pPDDst);
338 Pde = pPDDst->a[iPd];
339
340# else /* PGM_TYPE_32BIT */
341 const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
342 X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
343# endif
344 if (!Pde.n.u1Present)
345 return VERR_PAGE_TABLE_NOT_PRESENT;
346
347 /*
348 * Map the page table.
349 */
350 PSHWPT pPT;
351 rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
352 if (VBOX_FAILURE(rc))
353 return rc;
354
355 unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
356 while (iPTE < RT_ELEMENTS(pPT->a))
357 {
358 if (pPT->a[iPTE].n.u1Present)
359 {
360 pPT->a[iPTE].u = (pPT->a[iPTE].u & (fMask | SHW_PTE_PG_MASK)) | (fFlags & ~SHW_PTE_PG_MASK);
361/** @todo r=bird: I think this may break assumptions in page pool GCPhys
362 * tracking, and I seems to recall putting it here to prevent API users from
363 * making anything !P. The assertion is kind of useless now, as it
364 * won't hit anything any longer... */
365 Assert(pPT->a[iPTE].n.u1Present || !(fMask & X86_PTE_P));
366# if PGM_SHW_TYPE == PGM_TYPE_EPT
367 HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
368# else
369 PGM_INVL_PG(GCPtr);
370# endif
371 }
372
373 /* next page */
374 cb -= PAGE_SIZE;
375 if (!cb)
376 return VINF_SUCCESS;
377 GCPtr += PAGE_SIZE;
378 iPTE++;
379 }
380 }
381# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
382}
383
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