PGMAllShw.h@ 29561

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1	/* $Id: PGMAllShw.h 28800 2010-04-27 08:22:32Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Defined Constants And Macros *
20	*******************************************************************************/
21	#undef SHWPT
22	#undef PSHWPT
23	#undef SHWPTE
24	#undef PSHWPTE
25	#undef SHWPD
26	#undef PSHWPD
27	#undef SHWPDE
28	#undef PSHWPDE
29	#undef SHW_PDE_PG_MASK
30	#undef SHW_PD_SHIFT
31	#undef SHW_PD_MASK
32	#undef SHW_PTE_PG_MASK
33	#undef SHW_PT_SHIFT
34	#undef SHW_PT_MASK
35	#undef SHW_TOTAL_PD_ENTRIES
36	#undef SHW_PDPT_SHIFT
37	#undef SHW_PDPT_MASK
38	#undef SHW_PDPE_PG_MASK
39	#undef SHW_POOL_ROOT_IDX
40
41	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
42	# define SHWPT X86PT
43	# define PSHWPT PX86PT
44	# define SHWPTE X86PTE
45	# define PSHWPTE PX86PTE
46	# define SHWPD X86PD
47	# define PSHWPD PX86PD
48	# define SHWPDE X86PDE
49	# define PSHWPDE PX86PDE
50	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
51	# define SHW_PD_SHIFT X86_PD_SHIFT
52	# define SHW_PD_MASK X86_PD_MASK
53	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
54	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
55	# define SHW_PT_SHIFT X86_PT_SHIFT
56	# define SHW_PT_MASK X86_PT_MASK
57	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
58
59	#elif PGM_SHW_TYPE == PGM_TYPE_EPT
60	# define SHWPT EPTPT
61	# define PSHWPT PEPTPT
62	# define SHWPTE EPTPTE
63	# define PSHWPTE PEPTPTE
64	# define SHWPD EPTPD
65	# define PSHWPD PEPTPD
66	# define SHWPDE EPTPDE
67	# define PSHWPDE PEPTPDE
68	# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
69	# define SHW_PD_SHIFT EPT_PD_SHIFT
70	# define SHW_PD_MASK EPT_PD_MASK
71	# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
72	# define SHW_PT_SHIFT EPT_PT_SHIFT
73	# define SHW_PT_MASK EPT_PT_MASK
74	# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
75	# define SHW_PDPT_MASK EPT_PDPT_MASK
76	# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
77	# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
78	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
79
80	#else
81	# define SHWPT X86PTPAE
82	# define PSHWPT PX86PTPAE
83	# define SHWPTE X86PTEPAE
84	# define PSHWPTE PX86PTEPAE
85	# define SHWPD X86PDPAE
86	# define PSHWPD PX86PDPAE
87	# define SHWPDE X86PDEPAE
88	# define PSHWPDE PX86PDEPAE
89	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
90	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
91	# define SHW_PD_MASK X86_PD_PAE_MASK
92	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
93	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
94	# define SHW_PT_MASK X86_PT_PAE_MASK
95
96	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
97	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
98	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
99	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
100	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
101	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_AMD64_CR3
102
103	# else /* 32 bits PAE mode */
104	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
105	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
106	# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
107	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
108	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PDPT
109
110	# endif
111	#endif
112
113
114
115	/*******************************************************************************
116	* Internal Functions *
117	*******************************************************************************/
118	RT_C_DECLS_BEGIN
119	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
120	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
121	RT_C_DECLS_END
122
123
124
125	/**
126	* Gets effective page information (from the VMM page directory).
127	*
128	* @returns VBox status.
129	* @param pVCpu The VMCPU handle.
130	* @param GCPtr Guest Context virtual address of the page.
131	* @param pfFlags Where to store the flags. These are X86_PTE_*.
132	* @param pHCPhys Where to store the HC physical address of the page.
133	* This is page aligned.
134	* @remark You should use PGMMapGetPage() for pages in a mapping.
135	*/
136	PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
137	{
138	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
139	return VERR_PAGE_TABLE_NOT_PRESENT;
140
141	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
142	PVM pVM = pVCpu->CTX_SUFF(pVM);
143
144	Assert(PGMIsLockOwner(pVM));
145
146	/*
147	* Get the PDE.
148	*/
149	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
150	X86PDEPAE Pde;
151
152	/* PML4 */
153	X86PML4E Pml4e = pgmShwGetLongModePML4E(&pVCpu->pgm.s, GCPtr);
154	if (!Pml4e.n.u1Present)
155	return VERR_PAGE_TABLE_NOT_PRESENT;
156
157	/* PDPT */
158	PX86PDPT pPDPT;
159	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
160	if (RT_FAILURE(rc))
161	return rc;
162	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
163	X86PDPE Pdpe = pPDPT->a[iPDPT];
164	if (!Pdpe.n.u1Present)
165	return VERR_PAGE_TABLE_NOT_PRESENT;
166
167	/* PD */
168	PX86PDPAE pPd;
169	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
170	if (RT_FAILURE(rc))
171	return rc;
172	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
173	Pde = pPd->a[iPd];
174
175	/* Merge accessed, write, user and no-execute bits into the PDE. */
176	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
177	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
178	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
179	Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
180
181	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
182	X86PDEPAE Pde = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtr);
183
184	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
185	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
186	PEPTPD pPDDst;
187	EPTPDE Pde;
188
189	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
190	if (rc != VINF_SUCCESS) /** @todo this function isn't expected to return informational status codes. Check callers / fix. */
191	{
192	AssertRC(rc);
193	return rc;
194	}
195	Assert(pPDDst);
196	Pde = pPDDst->a[iPd];
197
198	# else /* PGM_TYPE_32BIT */
199	X86PDE Pde = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtr);
200	# endif
201	if (!Pde.n.u1Present)
202	return VERR_PAGE_TABLE_NOT_PRESENT;
203
204	Assert(!Pde.b.u1Size);
205
206	/*
207	* Get PT entry.
208	*/
209	PSHWPT pPT;
210	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
211	{
212	int rc2 = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
213	if (RT_FAILURE(rc2))
214	return rc2;
215	}
216	else /* mapping: */
217	{
218	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \
219	\|\| PGM_SHW_TYPE == PGM_TYPE_EPT
220	AssertFailed(); /* can't happen */
221	# else
222	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
223
224	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
225	AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_INTERNAL_ERROR);
226	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
227	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
228	# else /* PAE */
229	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
230	# endif
231	# endif
232	}
233	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
234	SHWPTE Pte = pPT->a[iPt];
235	if (!Pte.n.u1Present)
236	return VERR_PAGE_NOT_PRESENT;
237
238	/*
239	* Store the results.
240	* RW and US flags depend on the entire page translation hierarchy - except for
241	* legacy PAE which has a simplified PDPE.
242	*/
243	if (pfFlags)
244	{
245	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
246	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
247	# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
248	/* The NX bit is determined by a bitwise OR between the PT and PD */
249	if ((Pte.u & Pde.u & X86_PTE_PAE_NX) && CPUMIsGuestNXEnabled(pVCpu)) /** @todo the code is ANDing not ORing NX like the comment says... */
250	*pfFlags \|= X86_PTE_PAE_NX;
251	# endif
252	}
253
254	if (pHCPhys)
255	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
256
257	return VINF_SUCCESS;
258	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
259	}
260
261
262	/**
263	* Modify page flags for a range of pages in the shadow context.
264	*
265	* The existing flags are ANDed with the fMask and ORed with the fFlags.
266	*
267	* @returns VBox status code.
268	* @param pVCpu The VMCPU handle.
269	* @param GCPtr Virtual address of the first page in the range. Page aligned!
270	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
271	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
272	* @param fMask The AND mask - page flags X86_PTE_*.
273	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
274	* @remark You must use PGMMapModifyPage() for pages in a mapping.
275	*/
276	PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
277	{
278	# if PGM_SHW_TYPE == PGM_TYPE_NESTED
279	return VERR_PAGE_TABLE_NOT_PRESENT;
280
281	# else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
282	PVM pVM = pVCpu->CTX_SUFF(pVM);
283	int rc;
284
285	Assert(PGMIsLockOwner(pVM));
286	/*
287	* Walk page tables and pages till we're done.
288	*/
289	for (;;)
290	{
291	/*
292	* Get the PDE.
293	*/
294	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
295	X86PDEPAE Pde;
296	/* PML4 */
297	X86PML4E Pml4e = pgmShwGetLongModePML4E(&pVCpu->pgm.s, GCPtr);
298	if (!Pml4e.n.u1Present)
299	return VERR_PAGE_TABLE_NOT_PRESENT;
300
301	/* PDPT */
302	PX86PDPT pPDPT;
303	rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
304	if (RT_FAILURE(rc))
305	return rc;
306	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
307	X86PDPE Pdpe = pPDPT->a[iPDPT];
308	if (!Pdpe.n.u1Present)
309	return VERR_PAGE_TABLE_NOT_PRESENT;
310
311	/* PD */
312	PX86PDPAE pPd;
313	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
314	if (RT_FAILURE(rc))
315	return rc;
316	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
317	Pde = pPd->a[iPd];
318
319	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
320	X86PDEPAE Pde = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtr);
321
322	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
323	const unsigned iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
324	PEPTPD pPDDst;
325	EPTPDE Pde;
326
327	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtr, NULL, &pPDDst);
328	if (rc != VINF_SUCCESS)
329	{
330	AssertRC(rc);
331	return rc;
332	}
333	Assert(pPDDst);
334	Pde = pPDDst->a[iPd];
335
336	# else /* PGM_TYPE_32BIT */
337	X86PDE Pde = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtr);
338	# endif
339	if (!Pde.n.u1Present)
340	return VERR_PAGE_TABLE_NOT_PRESENT;
341
342	/*
343	* Map the page table.
344	*/
345	PSHWPT pPT;
346	rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
347	if (RT_FAILURE(rc))
348	return rc;
349
350	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
351	while (iPTE < RT_ELEMENTS(pPT->a))
352	{
353	if (pPT->a[iPTE].n.u1Present)
354	{
355	SHWPTE Pte;
356
357	Pte.u = (pPT->a[iPTE].u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
358	ASMAtomicWriteSize(&pPT->a[iPTE], Pte.u);
359	Assert(pPT->a[iPTE].n.u1Present);
360	# if PGM_SHW_TYPE == PGM_TYPE_EPT
361	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
362	# else
363	PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
364	# endif
365	}
366
367	/* next page */
368	cb -= PAGE_SIZE;
369	if (!cb)
370	return VINF_SUCCESS;
371	GCPtr += PAGE_SIZE;
372	iPTE++;
373	}
374	}
375	# endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
376	}
377

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 29561

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