PGMAllShw.h@ 8861

Last change on this file since 8861 was 8557, checked in by vboxsync, 17 years ago
Updates for 64 bits paging. Removed unused ShwGet/Set/ModifyPDEByIndex functions.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 10.7 KB

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1	/* $Id: PGMAllShw.h 8557 2008-05-05 10:00:33Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow Paging Template - All context code.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Defined Constants And Macros *
24	*******************************************************************************/
25	#undef SHWPT
26	#undef PSHWPT
27	#undef SHWPTE
28	#undef PSHWPTE
29	#undef SHWPD
30	#undef PSHWPD
31	#undef SHWPDE
32	#undef PSHWPDE
33	#undef SHW_PDE_PG_MASK
34	#undef SHW_PD_SHIFT
35	#undef SHW_PD_MASK
36	#undef SHW_PTE_PG_MASK
37	#undef SHW_PT_SHIFT
38	#undef SHW_PT_MASK
39	#undef SHW_TOTAL_PD_ENTRIES
40	#undef SHW_PDPT_SHIFT
41	#undef SHW_PDPT_MASK
42	#undef SHW_POOL_ROOT_IDX
43
44	#if PGM_SHW_TYPE == PGM_TYPE_32BIT
45	# define SHWPT X86PT
46	# define PSHWPT PX86PT
47	# define SHWPTE X86PTE
48	# define PSHWPTE PX86PTE
49	# define SHWPD X86PD
50	# define PSHWPD PX86PD
51	# define SHWPDE X86PDE
52	# define PSHWPDE PX86PDE
53	# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
54	# define SHW_PD_SHIFT X86_PD_SHIFT
55	# define SHW_PD_MASK X86_PD_MASK
56	# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
57	# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
58	# define SHW_PT_SHIFT X86_PT_SHIFT
59	# define SHW_PT_MASK X86_PT_MASK
60	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
61	#else
62	# define SHWPT X86PTPAE
63	# define PSHWPT PX86PTPAE
64	# define SHWPTE X86PTEPAE
65	# define PSHWPTE PX86PTEPAE
66	# define SHWPD X86PDPAE
67	# define PSHWPD PX86PDPAE
68	# define SHWPDE X86PDEPAE
69	# define PSHWPDE PX86PDEPAE
70	# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
71	# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
72	# define SHW_PD_MASK X86_PD_PAE_MASK
73	# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
74	# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
75	# define SHW_PT_MASK X86_PT_PAE_MASK
76	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
77	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
78	# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
79	# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
80	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PML4
81	#else /* 32 bits PAE mode */
82	# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
83	# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
84	# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
85	# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PAE_PD
86	#endif
87	#endif
88
89
90
91	/*******************************************************************************
92	* Internal Functions *
93	*******************************************************************************/
94	__BEGIN_DECLS
95	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
96	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
97	__END_DECLS
98
99
100
101	/**
102	* Gets effective page information (from the VMM page directory).
103	*
104	* @returns VBox status.
105	* @param pVM VM Handle.
106	* @param GCPtr Guest Context virtual address of the page.
107	* @param pfFlags Where to store the flags. These are X86_PTE_*.
108	* @param pHCPhys Where to store the HC physical address of the page.
109	* This is page aligned.
110	* @remark You should use PGMMapGetPage() for pages in a mapping.
111	*/
112	PGM_SHW_DECL(int, GetPage)(PVM pVM, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
113	{
114	/*
115	* Get the PDE.
116	*/
117	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
118	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
119	X86PDEPAE Pde;
120
121	/* PML4 */
122	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
123	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
124	if (!Pml4e.n.u1Present)
125	return VERR_PAGE_TABLE_NOT_PRESENT;
126
127	/* PDPT */
128	PX86PDPT pPDPT;
129	int rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
130	if (VBOX_FAILURE(rc))
131	return rc;
132	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
133	X86PDPE Pdpe = pPDPT->a[iPDPT];
134	if (!Pdpe.n.u1Present)
135	return VERR_PAGE_TABLE_NOT_PRESENT;
136
137	/* PD */
138	PX86PDPAE pPd;
139	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
140	if (VBOX_FAILURE(rc))
141	return rc;
142	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
143	Pde = pPd->a[iPd];
144
145	/* Merge accessed, write, user and no-execute bits into the PDE. */
146	Pde.n.u1Accessed &= Pml4e.n.u1Accessed & Pdpe.lm.u1Accessed;
147	Pde.n.u1Write &= Pml4e.n.u1Write & Pdpe.lm.u1Write;
148	Pde.n.u1User &= Pml4e.n.u1User & Pdpe.lm.u1User;
149	Pde.n.u1NoExecute &= Pml4e.n.u1NoExecute & Pdpe.lm.u1NoExecute;
150
151	#elif PGM_SHW_TYPE == PGM_TYPE_PAE
152	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
153	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
154	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
155	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
156
157	#else /* PGM_TYPE_32BIT */
158	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
159	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
160	#endif
161	if (!Pde.n.u1Present)
162	return VERR_PAGE_TABLE_NOT_PRESENT;
163
164	Assert(!Pde.b.u1Size);
165
166	/*
167	* Get PT entry.
168	*/
169	PSHWPT pPT;
170	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
171	{
172	int rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
173	if (VBOX_FAILURE(rc))
174	return rc;
175	}
176	else /* mapping: */
177	{
178	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
179	AssertFailed(); /* can't happen */
180	#else
181	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
182
183	PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
184	AssertMsgReturn(pMap, ("GCPtr=%VGv\n", GCPtr), VERR_INTERNAL_ERROR);
185	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
186	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTXALLSUFF(pPT);
187	# else /* PAE */
188	pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTXALLSUFF(paPaePTs);
189	# endif
190	#endif
191	}
192	const unsigned iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
193	SHWPTE Pte = pPT->a[iPt];
194	if (!Pte.n.u1Present)
195	return VERR_PAGE_NOT_PRESENT;
196
197	/*
198	* Store the results.
199	* RW and US flags depend on the entire page translation hierarchy - except for
200	* legacy PAE which has a simplified PDPE.
201	*/
202	if (pfFlags)
203	{
204	*pfFlags = (Pte.u & ~SHW_PTE_PG_MASK)
205	& ((Pde.u & (X86_PTE_RW \| X86_PTE_US)) \| ~(uint64_t)(X86_PTE_RW \| X86_PTE_US));
206	# if PGM_WITH_NX(PGM_SHW_TYPE)
207	/* The NX bit is determined by a bitwise OR between the PT and PD */
208	if (fNoExecuteBitValid)
209	*pfFlags \|= (Pte.u & Pde.u & X86_PTE_PAE_NX);
210	# endif
211	}
212
213	if (pHCPhys)
214	*pHCPhys = Pte.u & SHW_PTE_PG_MASK;
215
216	return VINF_SUCCESS;
217	}
218
219
220	/**
221	* Modify page flags for a range of pages in the shadow context.
222	*
223	* The existing flags are ANDed with the fMask and ORed with the fFlags.
224	*
225	* @returns VBox status code.
226	* @param pVM VM handle.
227	* @param GCPtr Virtual address of the first page in the range. Page aligned!
228	* @param cb Size (in bytes) of the range to apply the modification to. Page aligned!
229	* @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
230	* @param fMask The AND mask - page flags X86_PTE_*.
231	* Be extremely CAREFUL with ~'ing values because they can be 32-bit!
232	* @remark You must use PGMMapModifyPage() for pages in a mapping.
233	*/
234	PGM_SHW_DECL(int, ModifyPage)(PVM pVM, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
235	{
236	int rc;
237
238	/*
239	* Walk page tables and pages till we're done.
240	*/
241	for (;;)
242	{
243	/*
244	* Get the PDE.
245	*/
246	#if PGM_SHW_TYPE == PGM_TYPE_AMD64
247	X86PDEPAE Pde;
248	/* PML4 */
249	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
250	X86PML4E Pml4e = CTXMID(pVM->pgm.s.p,PaePML4)->a[iPml4];
251	if (!Pml4e.n.u1Present)
252	return VERR_PAGE_TABLE_NOT_PRESENT;
253
254	/* PDPT */
255	PX86PDPT pPDPT;
256	rc = PGM_HCPHYS_2_PTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, &pPDPT);
257	if (VBOX_FAILURE(rc))
258	return rc;
259	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
260	X86PDPE Pdpe = pPDPT->a[iPDPT];
261	if (!Pdpe.n.u1Present)
262	return VERR_PAGE_TABLE_NOT_PRESENT;
263
264	/* PD */
265	PX86PDPAE pPd;
266	rc = PGM_HCPHYS_2_PTR(pVM, Pdpe.u & X86_PDPE_PG_MASK, &pPd);
267	if (VBOX_FAILURE(rc))
268	return rc;
269	const unsigned iPd = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
270	Pde = pPd->a[iPd];
271
272	#elif PGM_SHW_TYPE == PGM_TYPE_PAE
273	const unsigned iPDPT = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
274	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
275	X86PDEPAE Pde = CTXMID(pVM->pgm.s.ap,PaePDs)[iPDPT]->a[iPd];
276
277	#else /* PGM_TYPE_32BIT */
278	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
279	X86PDE Pde = CTXMID(pVM->pgm.s.p,32BitPD)->a[iPd];
280	#endif
281	if (!Pde.n.u1Present)
282	return VERR_PAGE_TABLE_NOT_PRESENT;
283
284	/*
285	* Map the page table.
286	*/
287	PSHWPT pPT;
288	rc = PGM_HCPHYS_2_PTR(pVM, Pde.u & SHW_PDE_PG_MASK, &pPT);
289	if (VBOX_FAILURE(rc))
290	return rc;
291
292	unsigned iPTE = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
293	while (iPTE < ELEMENTS(pPT->a))
294	{
295	if (pPT->a[iPTE].n.u1Present)
296	{
297	pPT->a[iPTE].u = (pPT->a[iPTE].u & (fMask \| SHW_PTE_PG_MASK)) \| (fFlags & ~SHW_PTE_PG_MASK);
298	Assert(pPT->a[iPTE].n.u1Present);
299	PGM_INVL_PG(GCPtr);
300	}
301
302	/* next page */
303	cb -= PAGE_SIZE;
304	if (!cb)
305	return VINF_SUCCESS;
306	GCPtr += PAGE_SIZE;
307	iPTE++;
308	}
309	}
310	}
311

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllShw.h@ 8861

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