SELMAll.cpp@ 38025

Last change on this file since 38025 was 37955, checked in by vboxsync, 13 years ago
Moved VBox/x86.h/mac to iprt/x86.h/mac.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 39.4 KB

Line
1	/* $Id: SELMAll.cpp 37955 2011-07-14 12:23:02Z vboxsync $ */
2	/** @file
3	* SELM All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_SELM
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/pgm.h>
27	#include "SELMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/err.h>
30	#include <VBox/param.h>
31	#include <iprt/assert.h>
32	#include <VBox/log.h>
33	#include <VBox/vmm/vmm.h>
34	#include <iprt/x86.h>
35
36
37
38	#ifndef IN_RING0
39
40	/**
41	* Converts a GC selector based address to a flat address.
42	*
43	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
44	* for that.
45	*
46	* @returns Flat address.
47	* @param pVM VM Handle.
48	* @param Sel Selector part.
49	* @param Addr Address part.
50	* @remarks Don't use when in long mode.
51	*/
52	VMMDECL(RTGCPTR) SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr)
53	{
54	Assert(pVM->cCpus == 1 && !CPUMIsGuestInLongMode(VMMGetCpu(pVM))); /* DON'T USE! */
55
56	/** @todo check the limit. */
57	X86DESC Desc;
58	if (!(Sel & X86_SEL_LDT))
59	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
60	else
61	{
62	/** @todo handle LDT pages not present! */
63	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
64	Desc = paLDT[Sel >> X86_SEL_SHIFT];
65	}
66
67	return (RTGCPTR)(((RTGCUINTPTR)Addr + X86DESC_BASE(Desc)) & 0xffffffff);
68	}
69	#endif /* !IN_RING0 */
70
71
72	/**
73	* Converts a GC selector based address to a flat address.
74	*
75	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
76	* for that.
77	*
78	* @returns Flat address.
79	* @param pVM VM Handle.
80	* @param SelReg Selector register
81	* @param pCtxCore CPU context
82	* @param Addr Address part.
83	*/
84	VMMDECL(RTGCPTR) SELMToFlat(PVM pVM, DIS_SELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr)
85	{
86	PCPUMSELREGHID pHiddenSel;
87	RTSEL Sel;
88	int rc;
89	PVMCPU pVCpu = VMMGetCpu(pVM);
90
91	rc = DISFetchRegSegEx(pCtxCore, SelReg, &Sel, &pHiddenSel); AssertRC(rc);
92
93	/*
94	* Deal with real & v86 mode first.
95	*/
96	if ( pCtxCore->eflags.Bits.u1VM
97	\|\| CPUMIsGuestInRealMode(pVCpu))
98	{
99	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
100	if (CPUMAreHiddenSelRegsValid(pVCpu))
101	uFlat += pHiddenSel->u64Base;
102	else
103	uFlat += ((RTGCUINTPTR)Sel << 4);
104	return (RTGCPTR)uFlat;
105	}
106
107	#ifdef IN_RING0
108	Assert(CPUMAreHiddenSelRegsValid(pVCpu));
109	#else
110	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
111	if (!CPUMAreHiddenSelRegsValid(pVCpu))
112	return SELMToFlatBySel(pVM, Sel, Addr);
113	#endif
114
115	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
116	if ( pCtxCore->csHid.Attr.n.u1Long
117	&& CPUMIsGuestInLongMode(pVCpu))
118	{
119	switch (SelReg)
120	{
121	case DIS_SELREG_FS:
122	case DIS_SELREG_GS:
123	return (RTGCPTR)(pHiddenSel->u64Base + Addr);
124
125	default:
126	return Addr; /* base 0 */
127	}
128	}
129
130	/* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
131	Assert(pHiddenSel->u64Base <= 0xffffffff);
132	return ((pHiddenSel->u64Base + (RTGCUINTPTR)Addr) & 0xffffffff);
133	}
134
135
136	/**
137	* Converts a GC selector based address to a flat address.
138	*
139	* Some basic checking is done, but not all kinds yet.
140	*
141	* @returns VBox status
142	* @param pVM VM Handle.
143	* @param SelReg Selector register
144	* @param pCtxCore CPU context
145	* @param Addr Address part.
146	* @param fFlags SELMTOFLAT_FLAGS_*
147	* GDT entires are valid.
148	* @param ppvGC Where to store the GC flat address.
149	*/
150	VMMDECL(int) SELMToFlatEx(PVM pVM, DIS_SELREG SelReg, PCCPUMCTXCORE pCtxCore, RTGCPTR Addr, unsigned fFlags, PRTGCPTR ppvGC)
151	{
152	/*
153	* Fetch the selector first.
154	*/
155	PCPUMSELREGHID pHiddenSel;
156	RTSEL Sel;
157	PVMCPU pVCpu = VMMGetCpu(pVM);
158
159	int rc = DISFetchRegSegEx(pCtxCore, SelReg, &Sel, &pHiddenSel);
160	AssertRC(rc);
161
162	/*
163	* Deal with real & v86 mode first.
164	*/
165	if ( pCtxCore->eflags.Bits.u1VM
166	\|\| CPUMIsGuestInRealMode(pVCpu))
167	{
168	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
169	if (ppvGC)
170	{
171	if ( pHiddenSel
172	&& CPUMAreHiddenSelRegsValid(pVCpu))
173	*ppvGC = (RTGCPTR)(pHiddenSel->u64Base + uFlat);
174	else
175	*ppvGC = (RTGCPTR)(((RTGCUINTPTR)Sel << 4) + uFlat);
176	}
177	return VINF_SUCCESS;
178	}
179
180
181	uint32_t u32Limit;
182	RTGCPTR pvFlat;
183	uint32_t u1Present, u1DescType, u1Granularity, u4Type;
184
185	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
186	#ifndef IN_RC
187	if ( pHiddenSel
188	&& CPUMAreHiddenSelRegsValid(pVCpu))
189	{
190	bool fCheckLimit = true;
191
192	u1Present = pHiddenSel->Attr.n.u1Present;
193	u1Granularity = pHiddenSel->Attr.n.u1Granularity;
194	u1DescType = pHiddenSel->Attr.n.u1DescType;
195	u4Type = pHiddenSel->Attr.n.u4Type;
196	u32Limit = pHiddenSel->u32Limit;
197
198	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
199	if ( pCtxCore->csHid.Attr.n.u1Long
200	&& CPUMIsGuestInLongMode(pVCpu))
201	{
202	fCheckLimit = false;
203	switch (SelReg)
204	{
205	case DIS_SELREG_FS:
206	case DIS_SELREG_GS:
207	pvFlat = (pHiddenSel->u64Base + Addr);
208	break;
209
210	default:
211	pvFlat = Addr;
212	break;
213	}
214	}
215	else
216	{
217	/* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
218	Assert(pHiddenSel->u64Base <= 0xffffffff);
219	pvFlat = (RTGCPTR)((pHiddenSel->u64Base + (RTGCUINTPTR)Addr) & 0xffffffff);
220	}
221
222	/*
223	* Check if present.
224	*/
225	if (u1Present)
226	{
227	/*
228	* Type check.
229	*/
230	switch (u4Type)
231	{
232
233	/** Read only selector type. */
234	case X86_SEL_TYPE_RO:
235	case X86_SEL_TYPE_RO_ACC:
236	case X86_SEL_TYPE_RW:
237	case X86_SEL_TYPE_RW_ACC:
238	case X86_SEL_TYPE_EO:
239	case X86_SEL_TYPE_EO_ACC:
240	case X86_SEL_TYPE_ER:
241	case X86_SEL_TYPE_ER_ACC:
242	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
243	{
244	/** @todo fix this mess */
245	}
246	/* check limit. */
247	if (fCheckLimit && (RTGCUINTPTR)Addr > u32Limit)
248	return VERR_OUT_OF_SELECTOR_BOUNDS;
249	/* ok */
250	if (ppvGC)
251	*ppvGC = pvFlat;
252	return VINF_SUCCESS;
253
254	case X86_SEL_TYPE_EO_CONF:
255	case X86_SEL_TYPE_EO_CONF_ACC:
256	case X86_SEL_TYPE_ER_CONF:
257	case X86_SEL_TYPE_ER_CONF_ACC:
258	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
259	{
260	/** @todo fix this mess */
261	}
262	/* check limit. */
263	if (fCheckLimit && (RTGCUINTPTR)Addr > u32Limit)
264	return VERR_OUT_OF_SELECTOR_BOUNDS;
265	/* ok */
266	if (ppvGC)
267	*ppvGC = pvFlat;
268	return VINF_SUCCESS;
269
270	case X86_SEL_TYPE_RO_DOWN:
271	case X86_SEL_TYPE_RO_DOWN_ACC:
272	case X86_SEL_TYPE_RW_DOWN:
273	case X86_SEL_TYPE_RW_DOWN_ACC:
274	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
275	{
276	/** @todo fix this mess */
277	}
278	/* check limit. */
279	if (fCheckLimit)
280	{
281	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
282	return VERR_OUT_OF_SELECTOR_BOUNDS;
283	if ((RTGCUINTPTR)Addr <= u32Limit)
284	return VERR_OUT_OF_SELECTOR_BOUNDS;
285	}
286	/* ok */
287	if (ppvGC)
288	*ppvGC = pvFlat;
289	return VINF_SUCCESS;
290
291	default:
292	return VERR_INVALID_SELECTOR;
293
294	}
295	}
296	}
297	# ifndef IN_RING0
298	else
299	# endif
300	#endif /* !IN_RC */
301	#ifndef IN_RING0
302	{
303	X86DESC Desc;
304
305	if (!(Sel & X86_SEL_LDT))
306	{
307	if ( !(fFlags & SELMTOFLAT_FLAGS_HYPER)
308	&& (unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.GuestGdtr.cbGdt)
309	return VERR_INVALID_SELECTOR;
310	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
311	}
312	else
313	{
314	if ((unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.cbLdtLimit)
315	return VERR_INVALID_SELECTOR;
316
317	/** @todo handle LDT page(s) not present! */
318	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
319	Desc = paLDT[Sel >> X86_SEL_SHIFT];
320	}
321
322	/* calc limit. */
323	u32Limit = X86DESC_LIMIT(Desc);
324	if (Desc.Gen.u1Granularity)
325	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
326
327	/* calc address assuming straight stuff. */
328	pvFlat = (RTGCPTR)((RTGCUINTPTR)Addr + X86DESC_BASE(Desc));
329
330	/* Cut the address to 32 bits. */
331	Assert(!CPUMIsGuestInLongMode(pVCpu));
332	pvFlat &= 0xffffffff;
333
334	u1Present = Desc.Gen.u1Present;
335	u1Granularity = Desc.Gen.u1Granularity;
336	u1DescType = Desc.Gen.u1DescType;
337	u4Type = Desc.Gen.u4Type;
338
339	/*
340	* Check if present.
341	*/
342	if (u1Present)
343	{
344	/*
345	* Type check.
346	*/
347	# define BOTH(a, b) ((a << 16) \| b)
348	switch (BOTH(u1DescType, u4Type))
349	{
350
351	/** Read only selector type. */
352	case BOTH(1,X86_SEL_TYPE_RO):
353	case BOTH(1,X86_SEL_TYPE_RO_ACC):
354	case BOTH(1,X86_SEL_TYPE_RW):
355	case BOTH(1,X86_SEL_TYPE_RW_ACC):
356	case BOTH(1,X86_SEL_TYPE_EO):
357	case BOTH(1,X86_SEL_TYPE_EO_ACC):
358	case BOTH(1,X86_SEL_TYPE_ER):
359	case BOTH(1,X86_SEL_TYPE_ER_ACC):
360	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
361	{
362	/** @todo fix this mess */
363	}
364	/* check limit. */
365	if ((RTGCUINTPTR)Addr > u32Limit)
366	return VERR_OUT_OF_SELECTOR_BOUNDS;
367	/* ok */
368	if (ppvGC)
369	*ppvGC = pvFlat;
370	return VINF_SUCCESS;
371
372	case BOTH(1,X86_SEL_TYPE_EO_CONF):
373	case BOTH(1,X86_SEL_TYPE_EO_CONF_ACC):
374	case BOTH(1,X86_SEL_TYPE_ER_CONF):
375	case BOTH(1,X86_SEL_TYPE_ER_CONF_ACC):
376	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
377	{
378	/** @todo fix this mess */
379	}
380	/* check limit. */
381	if ((RTGCUINTPTR)Addr > u32Limit)
382	return VERR_OUT_OF_SELECTOR_BOUNDS;
383	/* ok */
384	if (ppvGC)
385	*ppvGC = pvFlat;
386	return VINF_SUCCESS;
387
388	case BOTH(1,X86_SEL_TYPE_RO_DOWN):
389	case BOTH(1,X86_SEL_TYPE_RO_DOWN_ACC):
390	case BOTH(1,X86_SEL_TYPE_RW_DOWN):
391	case BOTH(1,X86_SEL_TYPE_RW_DOWN_ACC):
392	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
393	{
394	/** @todo fix this mess */
395	}
396	/* check limit. */
397	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
398	return VERR_OUT_OF_SELECTOR_BOUNDS;
399	if ((RTGCUINTPTR)Addr <= u32Limit)
400	return VERR_OUT_OF_SELECTOR_BOUNDS;
401
402	/* ok */
403	if (ppvGC)
404	*ppvGC = pvFlat;
405	return VINF_SUCCESS;
406
407	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_AVAIL):
408	case BOTH(0,X86_SEL_TYPE_SYS_LDT):
409	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_BUSY):
410	case BOTH(0,X86_SEL_TYPE_SYS_286_CALL_GATE):
411	case BOTH(0,X86_SEL_TYPE_SYS_TASK_GATE):
412	case BOTH(0,X86_SEL_TYPE_SYS_286_INT_GATE):
413	case BOTH(0,X86_SEL_TYPE_SYS_286_TRAP_GATE):
414	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_AVAIL):
415	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_BUSY):
416	case BOTH(0,X86_SEL_TYPE_SYS_386_CALL_GATE):
417	case BOTH(0,X86_SEL_TYPE_SYS_386_INT_GATE):
418	case BOTH(0,X86_SEL_TYPE_SYS_386_TRAP_GATE):
419	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
420	{
421	/** @todo fix this mess */
422	}
423	/* check limit. */
424	if ((RTGCUINTPTR)Addr > u32Limit)
425	return VERR_OUT_OF_SELECTOR_BOUNDS;
426	/* ok */
427	if (ppvGC)
428	*ppvGC = pvFlat;
429	return VINF_SUCCESS;
430
431	default:
432	return VERR_INVALID_SELECTOR;
433
434	}
435	# undef BOTH
436	}
437	}
438	#endif /* !IN_RING0 */
439	return VERR_SELECTOR_NOT_PRESENT;
440	}
441
442
443	#ifndef IN_RING0
444	/**
445	* Converts a GC selector based address to a flat address.
446	*
447	* Some basic checking is done, but not all kinds yet.
448	*
449	* @returns VBox status
450	* @param pVM VM Handle.
451	* @param eflags Current eflags
452	* @param Sel Selector part.
453	* @param Addr Address part.
454	* @param pHiddenSel Hidden selector register (can be NULL)
455	* @param fFlags SELMTOFLAT_FLAGS_*
456	* GDT entires are valid.
457	* @param ppvGC Where to store the GC flat address.
458	* @param pcb Where to store the bytes from *ppvGC which can be accessed according to
459	* the selector. NULL is allowed.
460	* @remarks Don't use when in long mode.
461	*/
462	VMMDECL(int) SELMToFlatBySelEx(PVM pVM, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr, PCCPUMSELREGHID pHiddenSel, unsigned fFlags, PRTGCPTR ppvGC, uint32_t *pcb)
463	{
464	PVMCPU pVCpu = VMMGetCpu(pVM);
465
466	Assert(!CPUMIsGuestInLongMode(pVCpu)); /* DON'T USE! */
467
468	/*
469	* Deal with real & v86 mode first.
470	*/
471	if ( eflags.Bits.u1VM
472	\|\| CPUMIsGuestInRealMode(pVCpu))
473	{
474	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
475	if (ppvGC)
476	{
477	if ( pHiddenSel
478	&& CPUMAreHiddenSelRegsValid(pVCpu))
479	*ppvGC = (RTGCPTR)(pHiddenSel->u64Base + uFlat);
480	else
481	*ppvGC = (RTGCPTR)(((RTGCUINTPTR)Sel << 4) + uFlat);
482	}
483	if (pcb)
484	*pcb = 0x10000 - uFlat;
485	return VINF_SUCCESS;
486	}
487
488
489	uint32_t u32Limit;
490	RTGCPTR pvFlat;
491	uint32_t u1Present, u1DescType, u1Granularity, u4Type;
492
493	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
494	if ( pHiddenSel
495	&& CPUMAreHiddenSelRegsValid(pVCpu))
496	{
497	u1Present = pHiddenSel->Attr.n.u1Present;
498	u1Granularity = pHiddenSel->Attr.n.u1Granularity;
499	u1DescType = pHiddenSel->Attr.n.u1DescType;
500	u4Type = pHiddenSel->Attr.n.u4Type;
501
502	u32Limit = pHiddenSel->u32Limit;
503	pvFlat = (RTGCPTR)(pHiddenSel->u64Base + (RTGCUINTPTR)Addr);
504
505	if ( !pHiddenSel->Attr.n.u1Long
506	\|\| !CPUMIsGuestInLongMode(pVCpu))
507	{
508	/* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
509	pvFlat &= 0xffffffff;
510	}
511	}
512	else
513	{
514	X86DESC Desc;
515
516	if (!(Sel & X86_SEL_LDT))
517	{
518	if ( !(fFlags & SELMTOFLAT_FLAGS_HYPER)
519	&& (unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.GuestGdtr.cbGdt)
520	return VERR_INVALID_SELECTOR;
521	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
522	}
523	else
524	{
525	if ((unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.cbLdtLimit)
526	return VERR_INVALID_SELECTOR;
527
528	/** @todo handle LDT page(s) not present! */
529	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
530	Desc = paLDT[Sel >> X86_SEL_SHIFT];
531	}
532
533	/* calc limit. */
534	u32Limit = X86DESC_LIMIT(Desc);
535	if (Desc.Gen.u1Granularity)
536	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
537
538	/* calc address assuming straight stuff. */
539	pvFlat = (RTGCPTR)((RTGCUINTPTR)Addr + X86DESC_BASE(Desc));
540
541	/* Cut the address to 32 bits. */
542	Assert(!CPUMIsGuestInLongMode(pVCpu));
543	pvFlat &= 0xffffffff;
544
545	u1Present = Desc.Gen.u1Present;
546	u1Granularity = Desc.Gen.u1Granularity;
547	u1DescType = Desc.Gen.u1DescType;
548	u4Type = Desc.Gen.u4Type;
549	}
550
551	/*
552	* Check if present.
553	*/
554	if (u1Present)
555	{
556	/*
557	* Type check.
558	*/
559	#define BOTH(a, b) ((a << 16) \| b)
560	switch (BOTH(u1DescType, u4Type))
561	{
562
563	/** Read only selector type. */
564	case BOTH(1,X86_SEL_TYPE_RO):
565	case BOTH(1,X86_SEL_TYPE_RO_ACC):
566	case BOTH(1,X86_SEL_TYPE_RW):
567	case BOTH(1,X86_SEL_TYPE_RW_ACC):
568	case BOTH(1,X86_SEL_TYPE_EO):
569	case BOTH(1,X86_SEL_TYPE_EO_ACC):
570	case BOTH(1,X86_SEL_TYPE_ER):
571	case BOTH(1,X86_SEL_TYPE_ER_ACC):
572	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
573	{
574	/** @todo fix this mess */
575	}
576	/* check limit. */
577	if ((RTGCUINTPTR)Addr > u32Limit)
578	return VERR_OUT_OF_SELECTOR_BOUNDS;
579	/* ok */
580	if (ppvGC)
581	*ppvGC = pvFlat;
582	if (pcb)
583	*pcb = u32Limit - (uint32_t)Addr + 1;
584	return VINF_SUCCESS;
585
586	case BOTH(1,X86_SEL_TYPE_EO_CONF):
587	case BOTH(1,X86_SEL_TYPE_EO_CONF_ACC):
588	case BOTH(1,X86_SEL_TYPE_ER_CONF):
589	case BOTH(1,X86_SEL_TYPE_ER_CONF_ACC):
590	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
591	{
592	/** @todo fix this mess */
593	}
594	/* check limit. */
595	if ((RTGCUINTPTR)Addr > u32Limit)
596	return VERR_OUT_OF_SELECTOR_BOUNDS;
597	/* ok */
598	if (ppvGC)
599	*ppvGC = pvFlat;
600	if (pcb)
601	*pcb = u32Limit - (uint32_t)Addr + 1;
602	return VINF_SUCCESS;
603
604	case BOTH(1,X86_SEL_TYPE_RO_DOWN):
605	case BOTH(1,X86_SEL_TYPE_RO_DOWN_ACC):
606	case BOTH(1,X86_SEL_TYPE_RW_DOWN):
607	case BOTH(1,X86_SEL_TYPE_RW_DOWN_ACC):
608	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
609	{
610	/** @todo fix this mess */
611	}
612	/* check limit. */
613	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
614	return VERR_OUT_OF_SELECTOR_BOUNDS;
615	if ((RTGCUINTPTR)Addr <= u32Limit)
616	return VERR_OUT_OF_SELECTOR_BOUNDS;
617
618	/* ok */
619	if (ppvGC)
620	*ppvGC = pvFlat;
621	if (pcb)
622	*pcb = (RTGCUINTPTR)(u1Granularity ? 0xffffffff : 0xffff) - (RTGCUINTPTR)Addr + 1;
623	return VINF_SUCCESS;
624
625	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_AVAIL):
626	case BOTH(0,X86_SEL_TYPE_SYS_LDT):
627	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_BUSY):
628	case BOTH(0,X86_SEL_TYPE_SYS_286_CALL_GATE):
629	case BOTH(0,X86_SEL_TYPE_SYS_TASK_GATE):
630	case BOTH(0,X86_SEL_TYPE_SYS_286_INT_GATE):
631	case BOTH(0,X86_SEL_TYPE_SYS_286_TRAP_GATE):
632	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_AVAIL):
633	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_BUSY):
634	case BOTH(0,X86_SEL_TYPE_SYS_386_CALL_GATE):
635	case BOTH(0,X86_SEL_TYPE_SYS_386_INT_GATE):
636	case BOTH(0,X86_SEL_TYPE_SYS_386_TRAP_GATE):
637	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
638	{
639	/** @todo fix this mess */
640	}
641	/* check limit. */
642	if ((RTGCUINTPTR)Addr > u32Limit)
643	return VERR_OUT_OF_SELECTOR_BOUNDS;
644	/* ok */
645	if (ppvGC)
646	*ppvGC = pvFlat;
647	if (pcb)
648	pcb = 0xffffffff - (RTGCUINTPTR)pvFlat + 1; / Depends on the type.. fixme if we care. */
649	return VINF_SUCCESS;
650
651	default:
652	return VERR_INVALID_SELECTOR;
653
654	}
655	#undef BOTH
656	}
657	return VERR_SELECTOR_NOT_PRESENT;
658	}
659	#endif /* !IN_RING0 */
660
661
662	/**
663	* Validates and converts a GC selector based code address to a flat
664	* address when in real or v8086 mode.
665	*
666	* @returns VINF_SUCCESS.
667	* @param pVCpu The Virtual CPU handle.
668	* @param SelCS Selector part.
669	* @param pHidCS The hidden CS register part. Optional.
670	* @param Addr Address part.
671	* @param ppvFlat Where to store the flat address.
672	*/
673	DECLINLINE(int) selmValidateAndConvertCSAddrRealMode(PVMCPU pVCpu, RTSEL SelCS, PCCPUMSELREGHID pHidCS, RTGCPTR Addr,
674	PRTGCPTR ppvFlat)
675	{
676	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
677	if (!pHidCS \|\| !CPUMAreHiddenSelRegsValid(pVCpu))
678	uFlat += ((RTGCUINTPTR)SelCS << 4);
679	else
680	uFlat += pHidCS->u64Base;
681	*ppvFlat = (RTGCPTR)uFlat;
682	return VINF_SUCCESS;
683	}
684
685
686	#ifndef IN_RING0
687	/**
688	* Validates and converts a GC selector based code address to a flat
689	* address when in protected/long mode using the standard algorithm.
690	*
691	* @returns VBox status code.
692	* @param pVM VM Handle.
693	* @param pVCpu The virtual CPU handle.
694	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
695	* A full selector can be passed, we'll only use the RPL part.
696	* @param SelCS Selector part.
697	* @param Addr Address part.
698	* @param ppvFlat Where to store the flat address.
699	* @param pcBits Where to store the segment bitness (16/32/64). Optional.
700	*/
701	DECLINLINE(int) selmValidateAndConvertCSAddrStd(PVM pVM, PVMCPU pVCpu, RTSEL SelCPL, RTSEL SelCS, RTGCPTR Addr,
702	PRTGCPTR ppvFlat, uint32_t *pcBits)
703	{
704	/** @todo validate limit! */
705	X86DESC Desc;
706	if (!(SelCS & X86_SEL_LDT))
707	Desc = pVM->selm.s.CTX_SUFF(paGdt)[SelCS >> X86_SEL_SHIFT];
708	else
709	{
710	/** @todo handle LDT page(s) not present! */
711	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
712	Desc = paLDT[SelCS >> X86_SEL_SHIFT];
713	}
714
715	/*
716	* Check if present.
717	*/
718	if (Desc.Gen.u1Present)
719	{
720	/*
721	* Type check.
722	*/
723	if ( Desc.Gen.u1DescType == 1
724	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
725	{
726	/*
727	* Check level.
728	*/
729	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
730	if ( !(Desc.Gen.u4Type & X86_SEL_TYPE_CONF)
731	? uLevel <= Desc.Gen.u2Dpl
732	: uLevel >= Desc.Gen.u2Dpl /* hope I got this right now... */
733	)
734	{
735	/*
736	* Limit check.
737	*/
738	uint32_t u32Limit = X86DESC_LIMIT(Desc);
739	if (Desc.Gen.u1Granularity)
740	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
741	if ((RTGCUINTPTR)Addr <= u32Limit)
742	{
743	*ppvFlat = (RTGCPTR)((RTGCUINTPTR)Addr + X86DESC_BASE(Desc));
744	/* Cut the address to 32 bits. */
745	*ppvFlat &= 0xffffffff;
746
747	if (pcBits)
748	pcBits = Desc.Gen.u1DefBig ? 32 : 16; /* @todo GUEST64 */
749	return VINF_SUCCESS;
750	}
751	return VERR_OUT_OF_SELECTOR_BOUNDS;
752	}
753	return VERR_INVALID_RPL;
754	}
755	return VERR_NOT_CODE_SELECTOR;
756	}
757	return VERR_SELECTOR_NOT_PRESENT;
758	}
759	#endif /* !IN_RING0 */
760
761
762	/**
763	* Validates and converts a GC selector based code address to a flat
764	* address when in protected/long mode using the standard algorithm.
765	*
766	* @returns VBox status code.
767	* @param pVCpu VMCPU Handle.
768	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
769	* A full selector can be passed, we'll only use the RPL part.
770	* @param SelCS Selector part.
771	* @param Addr Address part.
772	* @param ppvFlat Where to store the flat address.
773	*/
774	DECLINLINE(int) selmValidateAndConvertCSAddrHidden(PVMCPU pVCpu, RTSEL SelCPL, RTSEL SelCS, PCCPUMSELREGHID pHidCS,
775	RTGCPTR Addr, PRTGCPTR ppvFlat)
776	{
777	/*
778	* Check if present.
779	*/
780	if (pHidCS->Attr.n.u1Present)
781	{
782	/*
783	* Type check.
784	*/
785	if ( pHidCS->Attr.n.u1DescType == 1
786	&& (pHidCS->Attr.n.u4Type & X86_SEL_TYPE_CODE))
787	{
788	/*
789	* Check level.
790	*/
791	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
792	if ( !(pHidCS->Attr.n.u4Type & X86_SEL_TYPE_CONF)
793	? uLevel <= pHidCS->Attr.n.u2Dpl
794	: uLevel >= pHidCS->Attr.n.u2Dpl /* hope I got this right now... */
795	)
796	{
797	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
798	if ( pHidCS->Attr.n.u1Long
799	&& CPUMIsGuestInLongMode(pVCpu))
800	{
801	*ppvFlat = Addr;
802	return VINF_SUCCESS;
803	}
804
805	/*
806	* Limit check. Note that the limit in the hidden register is the
807	* final value. The granularity bit was included in its calculation.
808	*/
809	uint32_t u32Limit = pHidCS->u32Limit;
810	if ((RTGCUINTPTR)Addr <= u32Limit)
811	{
812	*ppvFlat = (RTGCPTR)( (RTGCUINTPTR)Addr + pHidCS->u64Base );
813	return VINF_SUCCESS;
814	}
815	return VERR_OUT_OF_SELECTOR_BOUNDS;
816	}
817	Log(("Invalid RPL Attr.n.u4Type=%x cpl=%x dpl=%x\n", pHidCS->Attr.n.u4Type, uLevel, pHidCS->Attr.n.u2Dpl));
818	return VERR_INVALID_RPL;
819	}
820	return VERR_NOT_CODE_SELECTOR;
821	}
822	return VERR_SELECTOR_NOT_PRESENT;
823	}
824
825
826	#ifdef IN_RC
827	/**
828	* Validates and converts a GC selector based code address to a flat address.
829	*
830	* This is like SELMValidateAndConvertCSAddr + SELMIsSelector32Bit but with
831	* invalid hidden CS data. It's customized for dealing efficiently with CS
832	* at GC trap time.
833	*
834	* @returns VBox status code.
835	* @param pVM VM Handle.
836	* @param eflags Current eflags
837	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
838	* A full selector can be passed, we'll only use the RPL part.
839	* @param SelCS Selector part.
840	* @param Addr Address part.
841	* @param ppvFlat Where to store the flat address.
842	* @param pcBits Where to store the 64-bit/32-bit/16-bit indicator.
843	*/
844	VMMDECL(int) SELMValidateAndConvertCSAddrGCTrap(PVM pVM, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS, RTGCPTR Addr, PRTGCPTR ppvFlat, uint32_t *pcBits)
845	{
846	Assert(pVM->cCpus == 1);
847	PVMCPU pVCpu = &pVM->aCpus[0];
848
849	if ( eflags.Bits.u1VM
850	\|\| CPUMIsGuestInRealMode(pVCpu))
851	{
852	*pcBits = 16;
853	return selmValidateAndConvertCSAddrRealMode(pVCpu, SelCS, NULL, Addr, ppvFlat);
854	}
855	Assert(!CPUMAreHiddenSelRegsValid(pVCpu));
856	return selmValidateAndConvertCSAddrStd(pVM, pVCpu, SelCPL, SelCS, Addr, ppvFlat, pcBits);
857	}
858	#endif /* IN_RC */
859
860
861	/**
862	* Validates and converts a GC selector based code address to a flat address.
863	*
864	* @returns VBox status code.
865	* @param pVM VM Handle.
866	* @param eflags Current eflags
867	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
868	* A full selector can be passed, we'll only use the RPL part.
869	* @param SelCS Selector part.
870	* @param pHiddenSel The hidden CS selector register.
871	* @param Addr Address part.
872	* @param ppvFlat Where to store the flat address.
873	*/
874	VMMDECL(int) SELMValidateAndConvertCSAddr(PVM pVM, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS, PCCPUMSELREGHID pHiddenCSSel,
875	RTGCPTR Addr, PRTGCPTR ppvFlat)
876	{
877	PVMCPU pVCpu = VMMGetCpu(pVM);
878
879	if ( eflags.Bits.u1VM
880	\|\| CPUMIsGuestInRealMode(pVCpu))
881	return selmValidateAndConvertCSAddrRealMode(pVCpu, SelCS, pHiddenCSSel, Addr, ppvFlat);
882
883	#ifdef IN_RING0
884	Assert(CPUMAreHiddenSelRegsValid(pVCpu));
885	#else
886	/** @todo when we're in 16 bits mode, we should cut off the address as well? (like in selmValidateAndConvertCSAddrRealMode) */
887	if (!CPUMAreHiddenSelRegsValid(pVCpu) \|\| !pHiddenCSSel)
888	return selmValidateAndConvertCSAddrStd(pVM, pVCpu, SelCPL, SelCS, Addr, ppvFlat, NULL);
889	#endif
890	return selmValidateAndConvertCSAddrHidden(pVCpu, SelCPL, SelCS, pHiddenCSSel, Addr, ppvFlat);
891	}
892
893
894	#ifndef IN_RING0
895	/**
896	* Return the cpu mode corresponding to the (CS) selector
897	*
898	* @returns DISCPUMODE according to the selector type (16, 32 or 64 bits)
899	* @param pVM VM Handle.
900	* @param pVCpu The virtual CPU handle.
901	* @param Sel The selector.
902	*/
903	static DISCPUMODE selmGetCpuModeFromSelector(PVM pVM, PVMCPU pVCpu, RTSEL Sel)
904	{
905	Assert(!CPUMAreHiddenSelRegsValid(pVCpu));
906
907	/** @todo validate limit! */
908	X86DESC Desc;
909	if (!(Sel & X86_SEL_LDT))
910	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
911	else
912	{
913	/** @todo handle LDT page(s) not present! */
914	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
915	Desc = paLDT[Sel >> X86_SEL_SHIFT];
916	}
917	return (Desc.Gen.u1DefBig) ? CPUMODE_32BIT : CPUMODE_16BIT;
918	}
919	#endif /* !IN_RING0 */
920
921
922	/**
923	* Return the cpu mode corresponding to the (CS) selector
924	*
925	* @returns DISCPUMODE according to the selector type (16, 32 or 64 bits)
926	* @param pVM VM Handle.
927	* @param eflags Current eflags register
928	* @param Sel The selector.
929	* @param pHiddenSel The hidden selector register.
930	*/
931	VMMDECL(DISCPUMODE) SELMGetCpuModeFromSelector(PVM pVM, X86EFLAGS eflags, RTSEL Sel, PCCPUMSELREGHID pHiddenSel)
932	{
933	PVMCPU pVCpu = VMMGetCpu(pVM);
934	#ifdef IN_RING0
935	Assert(CPUMAreHiddenSelRegsValid(pVCpu));
936	#else /* !IN_RING0 */
937	if (!CPUMAreHiddenSelRegsValid(pVCpu))
938	{
939	/*
940	* Deal with real & v86 mode first.
941	*/
942	if ( eflags.Bits.u1VM
943	\|\| CPUMIsGuestInRealMode(pVCpu))
944	return CPUMODE_16BIT;
945
946	return selmGetCpuModeFromSelector(pVM, pVCpu, Sel);
947	}
948	#endif /* !IN_RING0 */
949	if ( pHiddenSel->Attr.n.u1Long
950	&& CPUMIsGuestInLongMode(pVCpu))
951	return CPUMODE_64BIT;
952
953	/* Else compatibility or 32 bits mode. */
954	return pHiddenSel->Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
955	}
956
957
958	/**
959	* Returns Hypervisor's Trap 08 (\#DF) selector.
960	*
961	* @returns Hypervisor's Trap 08 (\#DF) selector.
962	* @param pVM VM Handle.
963	*/
964	VMMDECL(RTSEL) SELMGetTrap8Selector(PVM pVM)
965	{
966	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
967	}
968
969
970	/**
971	* Sets EIP of Hypervisor's Trap 08 (\#DF) TSS.
972	*
973	* @param pVM VM Handle.
974	* @param u32EIP EIP of Trap 08 handler.
975	*/
976	VMMDECL(void) SELMSetTrap8EIP(PVM pVM, uint32_t u32EIP)
977	{
978	pVM->selm.s.TssTrap08.eip = u32EIP;
979	}
980
981
982	/**
983	* Sets ss:esp for ring1 in main Hypervisor's TSS.
984	*
985	* @param pVM VM Handle.
986	* @param ss Ring1 SS register value. Pass 0 if invalid.
987	* @param esp Ring1 ESP register value.
988	*/
989	void selmSetRing1Stack(PVM pVM, uint32_t ss, RTGCPTR32 esp)
990	{
991	Assert((ss & 1) \|\| esp == 0);
992	pVM->selm.s.Tss.ss1 = ss;
993	pVM->selm.s.Tss.esp1 = (uint32_t)esp;
994	}
995
996
997	#ifndef IN_RING0
998	/**
999	* Gets ss:esp for ring1 in main Hypervisor's TSS.
1000	*
1001	* Returns SS=0 if the ring-1 stack isn't valid.
1002	*
1003	* @returns VBox status code.
1004	* @param pVM VM Handle.
1005	* @param pSS Ring1 SS register value.
1006	* @param pEsp Ring1 ESP register value.
1007	*/
1008	VMMDECL(int) SELMGetRing1Stack(PVM pVM, uint32_t *pSS, PRTGCPTR32 pEsp)
1009	{
1010	Assert(pVM->cCpus == 1);
1011	PVMCPU pVCpu = &pVM->aCpus[0];
1012
1013	if (pVM->selm.s.fSyncTSSRing0Stack)
1014	{
1015	RTGCPTR GCPtrTss = pVM->selm.s.GCPtrGuestTss;
1016	int rc;
1017	VBOXTSS tss;
1018
1019	Assert(pVM->selm.s.GCPtrGuestTss && pVM->selm.s.cbMonitoredGuestTss);
1020
1021	# ifdef IN_RC
1022	bool fTriedAlready = false;
1023
1024	l_tryagain:
1025	PVBOXTSS pTss = (PVBOXTSS)(uintptr_t)GCPtrTss;
1026	rc = MMGCRamRead(pVM, &tss.ss0, &pTss->ss0, sizeof(tss.ss0));
1027	rc \|= MMGCRamRead(pVM, &tss.esp0, &pTss->esp0, sizeof(tss.esp0));
1028	# ifdef DEBUG
1029	rc \|= MMGCRamRead(pVM, &tss.offIoBitmap, &pTss->offIoBitmap, sizeof(tss.offIoBitmap));
1030	# endif
1031
1032	if (RT_FAILURE(rc))
1033	{
1034	if (!fTriedAlready)
1035	{
1036	/* Shadow page might be out of sync. Sync and try again */
1037	/** @todo might cross page boundary */
1038	fTriedAlready = true;
1039	rc = PGMPrefetchPage(pVCpu, (RTGCPTR)GCPtrTss);
1040	if (rc != VINF_SUCCESS)
1041	return rc;
1042	goto l_tryagain;
1043	}
1044	AssertMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
1045	return rc;
1046	}
1047
1048	# else /* !IN_RC */
1049	/* Reading too much. Could be cheaper than two separate calls though. */
1050	rc = PGMPhysSimpleReadGCPtr(pVCpu, &tss, GCPtrTss, sizeof(VBOXTSS));
1051	if (RT_FAILURE(rc))
1052	{
1053	AssertReleaseMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
1054	return rc;
1055	}
1056	# endif /* !IN_RC */
1057
1058	# ifdef LOG_ENABLED
1059	uint32_t ssr0 = pVM->selm.s.Tss.ss1;
1060	uint32_t espr0 = pVM->selm.s.Tss.esp1;
1061	ssr0 &= ~1;
1062
1063	if (ssr0 != tss.ss0 \|\| espr0 != tss.esp0)
1064	Log(("SELMGetRing1Stack: Updating TSS ring 0 stack to %04X:%08X\n", tss.ss0, tss.esp0));
1065
1066	Log(("offIoBitmap=%#x\n", tss.offIoBitmap));
1067	# endif
1068	/* Update our TSS structure for the guest's ring 1 stack */
1069	selmSetRing1Stack(pVM, tss.ss0 \| 1, (RTGCPTR32)tss.esp0);
1070	pVM->selm.s.fSyncTSSRing0Stack = false;
1071	}
1072
1073	*pSS = pVM->selm.s.Tss.ss1;
1074	*pEsp = (RTGCPTR32)pVM->selm.s.Tss.esp1;
1075
1076	return VINF_SUCCESS;
1077	}
1078	#endif /* !IN_RING0 */
1079
1080
1081	/**
1082	* Returns Guest TSS pointer
1083	*
1084	* @returns Pointer to the guest TSS, RTRCPTR_MAX if not being monitored.
1085	* @param pVM VM Handle.
1086	*/
1087	VMMDECL(RTGCPTR) SELMGetGuestTSS(PVM pVM)
1088	{
1089	return (RTGCPTR)pVM->selm.s.GCPtrGuestTss;
1090	}
1091
1092
1093	#ifndef IN_RING0
1094
1095	/**
1096	* Gets the hypervisor code selector (CS).
1097	* @returns CS selector.
1098	* @param pVM The VM handle.
1099	*/
1100	VMMDECL(RTSEL) SELMGetHyperCS(PVM pVM)
1101	{
1102	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
1103	}
1104
1105
1106	/**
1107	* Gets the 64-mode hypervisor code selector (CS64).
1108	* @returns CS selector.
1109	* @param pVM The VM handle.
1110	*/
1111	VMMDECL(RTSEL) SELMGetHyperCS64(PVM pVM)
1112	{
1113	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64];
1114	}
1115
1116
1117	/**
1118	* Gets the hypervisor data selector (DS).
1119	* @returns DS selector.
1120	* @param pVM The VM handle.
1121	*/
1122	VMMDECL(RTSEL) SELMGetHyperDS(PVM pVM)
1123	{
1124	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
1125	}
1126
1127
1128	/**
1129	* Gets the hypervisor TSS selector.
1130	* @returns TSS selector.
1131	* @param pVM The VM handle.
1132	*/
1133	VMMDECL(RTSEL) SELMGetHyperTSS(PVM pVM)
1134	{
1135	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS];
1136	}
1137
1138
1139	/**
1140	* Gets the hypervisor TSS Trap 8 selector.
1141	* @returns TSS Trap 8 selector.
1142	* @param pVM The VM handle.
1143	*/
1144	VMMDECL(RTSEL) SELMGetHyperTSSTrap08(PVM pVM)
1145	{
1146	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1147	}
1148
1149	/**
1150	* Gets the address for the hypervisor GDT.
1151	*
1152	* @returns The GDT address.
1153	* @param pVM The VM handle.
1154	* @remark This is intended only for very special use, like in the world
1155	* switchers. Don't exploit this API!
1156	*/
1157	VMMDECL(RTRCPTR) SELMGetHyperGDT(PVM pVM)
1158	{
1159	/*
1160	* Always convert this from the HC pointer since we can be
1161	* called before the first relocation and have to work correctly
1162	* without having dependencies on the relocation order.
1163	*/
1164	return (RTRCPTR)MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3);
1165	}
1166
1167	#endif /* !IN_RING0 */
1168
1169	/**
1170	* Gets info about the current TSS.
1171	*
1172	* @returns VBox status code.
1173	* @retval VINF_SUCCESS if we've got a TSS loaded.
1174	* @retval VERR_SELM_NO_TSS if we haven't got a TSS (rather unlikely).
1175	*
1176	* @param pVM The VM handle.
1177	* @param pVCpu VMCPU Handle.
1178	* @param pGCPtrTss Where to store the TSS address.
1179	* @param pcbTss Where to store the TSS size limit.
1180	* @param pfCanHaveIOBitmap Where to store the can-have-I/O-bitmap indicator. (optional)
1181	*/
1182	VMMDECL(int) SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap)
1183	{
1184	/*
1185	* The TR hidden register is always valid.
1186	*/
1187	CPUMSELREGHID trHid;
1188	RTSEL tr = CPUMGetGuestTR(pVCpu, &trHid);
1189	if (!(tr & X86_SEL_MASK))
1190	return VERR_SELM_NO_TSS;
1191
1192	*pGCPtrTss = trHid.u64Base;
1193	pcbTss = trHid.u32Limit + (trHid.u32Limit != UINT32_MAX); / be careful. */
1194	if (pfCanHaveIOBitmap)
1195	*pfCanHaveIOBitmap = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1196	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1197	return VINF_SUCCESS;
1198	}
1199
1200
1201
1202	/**
1203	* Notification callback which is called whenever there is a chance that a CR3
1204	* value might have changed.
1205	* This is called by PGM.
1206	*
1207	* @param pVM The VM handle
1208	* @param pVCpu The VMCPU handle
1209	*/
1210	VMMDECL(void) SELMShadowCR3Changed(PVM pVM, PVMCPU pVCpu)
1211	{
1212	/** @todo SMP support!! */
1213	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
1214	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu);
1215	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/SELMAll.cpp@ 38025

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