SELMAll.cpp@ 2295

Last change on this file since 2295 was 2267, checked in by vboxsync, 18 years ago
Updated assertion
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1	/* $Id: SELMAll.cpp 2267 2007-04-20 12:56:15Z vboxsync $ */
2	/** @file
3	* SELM All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_SELM
27	#include <VBox/selm.h>
28	#include <VBox/stam.h>
29	#include <VBox/mm.h>
30	#include <VBox/pgm.h>
31	#include "SELMInternal.h"
32	#include <VBox/vm.h>
33	#include <VBox/x86.h>
34	#include <VBox/err.h>
35	#include <VBox/param.h>
36	#include <iprt/assert.h>
37	#include <VBox/log.h>
38
39
40
41	/**
42	* Converts a GC selector based address to a flat address.
43	*
44	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
45	* for that.
46	*
47	* @returns Flat address.
48	* @param pVM VM Handle.
49	* @param Sel Selector part.
50	* @param Addr Address part.
51	*/
52	static RTGCPTR selmToFlat(PVM pVM, RTSEL Sel, RTGCPTR Addr)
53	{
54	Assert(!CPUMAreHiddenSelRegsValid(pVM));
55
56	/** @todo check the limit. */
57	VBOXDESC Desc;
58	if (!(Sel & X86_SEL_LDT))
59	Desc = pVM->selm.s.CTXSUFF(paGdt)[Sel >> X86_SEL_SHIFT];
60	else
61	{
62	/** @todo handle LDT pages not present! */
63	#ifdef IN_GC
64	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.GCPtrLdt + pVM->selm.s.offLdtHyper);
65	#else
66	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.HCPtrLdt + pVM->selm.s.offLdtHyper);
67	#endif
68	Desc = paLDT[Sel >> X86_SEL_SHIFT];
69	}
70
71	return (RTGCPTR)( (RTGCUINTPTR)Addr
72	+ ( (Desc.Gen.u8BaseHigh2 << 24)
73	\| (Desc.Gen.u8BaseHigh1 << 16)
74	\| Desc.Gen.u16BaseLow));
75	}
76
77
78	/**
79	* Converts a GC selector based address to a flat address.
80	*
81	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
82	* for that.
83	*
84	* @returns Flat address.
85	* @param pVM VM Handle.
86	* @param eflags Current eflags
87	* @param Sel Selector part.
88	* @param pHiddenSel Hidden selector register
89	* @param Addr Address part.
90	*/
91	SELMDECL(RTGCPTR) SELMToFlat(PVM pVM, X86EFLAGS eflags, RTSEL Sel, CPUMSELREGHID *pHiddenSel, RTGCPTR Addr)
92	{
93	Assert(pHiddenSel \|\| !CPUMAreHiddenSelRegsValid(pVM));
94
95	/*
96	* Deal with real & v86 mode first.
97	*/
98	if ( CPUMIsGuestInRealMode(pVM)
99	\|\| eflags.Bits.u1VM)
100	{
101	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
102
103	if (CPUMAreHiddenSelRegsValid(pVM))
104	uFlat += pHiddenSel->u32Base;
105	else
106	uFlat += ((RTGCUINTPTR)Sel << 4);
107	return (RTGCPTR)uFlat;
108	}
109
110	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
111	if (!CPUMAreHiddenSelRegsValid(pVM))
112	return selmToFlat(pVM, Sel, Addr);
113	else
114	return (RTGCPTR)(pHiddenSel->u32Base + (RTGCUINTPTR)Addr);
115	}
116
117
118	/**
119	* Converts a GC selector based address to a flat address.
120	*
121	* Some basic checking is done, but not all kinds yet.
122	*
123	* @returns VBox status
124	* @param pVM VM Handle.
125	* @param eflags Current eflags
126	* @param Sel Selector part.
127	* @param Addr Address part.
128	* @param pHiddenSel Hidden selector register (can be NULL)
129	* @param fFlags SELMTOFLAT_FLAGS_*
130	* GDT entires are valid.
131	* @param ppvGC Where to store the GC flat address.
132	* @param pcb Where to store the bytes from *ppvGC which can be accessed according to
133	* the selector. NULL is allowed.
134	*/
135	SELMDECL(int) SELMToFlatEx(PVM pVM, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr, CPUMSELREGHID pHiddenSel, unsigned fFlags, PRTGCPTR ppvGC, uint32_t pcb)
136	{
137	/*
138	* Deal with real & v86 mode first.
139	*/
140	if ( CPUMIsGuestInRealMode(pVM)
141	\|\| eflags.Bits.u1VM)
142	{
143	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
144	if (ppvGC)
145	{
146	if ( pHiddenSel
147	&& CPUMAreHiddenSelRegsValid(pVM))
148	*ppvGC = (RTGCPTR)(pHiddenSel->u32Base + uFlat);
149	else
150	*ppvGC = (RTGCPTR)(((RTGCUINTPTR)Sel << 4) + uFlat);
151	}
152	if (pcb)
153	*pcb = 0x10000 - uFlat;
154	return VINF_SUCCESS;
155	}
156
157
158	uint32_t u32Limit;
159	RTGCPTR pvFlat;
160	uint32_t u1Present, u1DescType, u1Granularity, u4Type;
161
162	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
163	if ( pHiddenSel
164	&& CPUMAreHiddenSelRegsValid(pVM))
165	{
166	u1Present = pHiddenSel->Attr.n.u1Present;
167	u1Granularity = pHiddenSel->Attr.n.u1Granularity;
168	u1DescType = pHiddenSel->Attr.n.u1DescType;
169	u4Type = pHiddenSel->Attr.n.u4Type;
170
171	u32Limit = pHiddenSel->u32Limit;
172	pvFlat = (RTGCPTR)(pHiddenSel->u32Base + (RTGCUINTPTR)Addr);
173	}
174	else
175	{
176	VBOXDESC Desc;
177
178	if (!(Sel & X86_SEL_LDT))
179	{
180	if ( !(fFlags & SELMTOFLAT_FLAGS_HYPER)
181	&& (unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.GuestGdtr.cbGdt)
182	return VERR_INVALID_SELECTOR;
183	Desc = pVM->selm.s.CTXSUFF(paGdt)[Sel >> X86_SEL_SHIFT];
184	}
185	else
186	{
187	if ((unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.cbLdtLimit)
188	return VERR_INVALID_SELECTOR;
189
190	/** @todo handle LDT page(s) not present! */
191	#ifdef IN_GC
192	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.GCPtrLdt + pVM->selm.s.offLdtHyper);
193	#else
194	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.HCPtrLdt + pVM->selm.s.offLdtHyper);
195	#endif
196	Desc = paLDT[Sel >> X86_SEL_SHIFT];
197	}
198
199	/* calc limit. */
200	u32Limit = Desc.Gen.u4LimitHigh << 16 \| Desc.Gen.u16LimitLow;
201	if (Desc.Gen.u1Granularity)
202	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
203
204	/* calc address assuming straight stuff. */
205	pvFlat = (RTGCPTR)( (RTGCUINTPTR)Addr
206	+ ( (Desc.Gen.u8BaseHigh2 << 24)
207	\| (Desc.Gen.u8BaseHigh1 << 16)
208	\| Desc.Gen.u16BaseLow )
209	);
210
211	u1Present = Desc.Gen.u1Present;
212	u1Granularity = Desc.Gen.u1Granularity;
213	u1DescType = Desc.Gen.u1DescType;
214	u4Type = Desc.Gen.u4Type;
215	}
216
217	/*
218	* Check if present.
219	*/
220	if (u1Present)
221	{
222	/*
223	* Type check.
224	*/
225	#define BOTH(a, b) ((a << 16) \| b)
226	switch (BOTH(u1DescType, u4Type))
227	{
228
229	/** Read only selector type. */
230	case BOTH(1,X86_SEL_TYPE_RO):
231	case BOTH(1,X86_SEL_TYPE_RO_ACC):
232	case BOTH(1,X86_SEL_TYPE_RW):
233	case BOTH(1,X86_SEL_TYPE_RW_ACC):
234	case BOTH(1,X86_SEL_TYPE_EO):
235	case BOTH(1,X86_SEL_TYPE_EO_ACC):
236	case BOTH(1,X86_SEL_TYPE_ER):
237	case BOTH(1,X86_SEL_TYPE_ER_ACC):
238	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
239	{
240	/** @todo fix this mess */
241	}
242	/* check limit. */
243	if ((RTGCUINTPTR)Addr > u32Limit)
244	return VERR_OUT_OF_SELECTOR_BOUNDS;
245	/* ok */
246	if (ppvGC)
247	*ppvGC = pvFlat;
248	if (pcb)
249	*pcb = u32Limit - (uint32_t)Addr + 1;
250	return VINF_SUCCESS;
251
252	case BOTH(1,X86_SEL_TYPE_EO_CONF):
253	case BOTH(1,X86_SEL_TYPE_EO_CONF_ACC):
254	case BOTH(1,X86_SEL_TYPE_ER_CONF):
255	case BOTH(1,X86_SEL_TYPE_ER_CONF_ACC):
256	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
257	{
258	/** @todo fix this mess */
259	}
260	/* check limit. */
261	if ((RTGCUINTPTR)Addr > u32Limit)
262	return VERR_OUT_OF_SELECTOR_BOUNDS;
263	/* ok */
264	if (ppvGC)
265	*ppvGC = pvFlat;
266	if (pcb)
267	*pcb = u32Limit - (uint32_t)Addr + 1;
268	return VINF_SUCCESS;
269
270	case BOTH(1,X86_SEL_TYPE_RO_DOWN):
271	case BOTH(1,X86_SEL_TYPE_RO_DOWN_ACC):
272	case BOTH(1,X86_SEL_TYPE_RW_DOWN):
273	case BOTH(1,X86_SEL_TYPE_RW_DOWN_ACC):
274	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
275	{
276	/** @todo fix this mess */
277	}
278	/* check limit. */
279	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
280	return VERR_OUT_OF_SELECTOR_BOUNDS;
281	if ((RTGCUINTPTR)Addr <= u32Limit)
282	return VERR_OUT_OF_SELECTOR_BOUNDS;
283
284	/* ok */
285	if (ppvGC)
286	*ppvGC = pvFlat;
287	if (pcb)
288	*pcb = (u1Granularity ? 0xffffffff : 0xffff) - (RTGCUINTPTR)Addr + 1;
289	return VINF_SUCCESS;
290
291	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_AVAIL):
292	case BOTH(0,X86_SEL_TYPE_SYS_LDT):
293	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_BUSY):
294	case BOTH(0,X86_SEL_TYPE_SYS_286_CALL_GATE):
295	case BOTH(0,X86_SEL_TYPE_SYS_TASK_GATE):
296	case BOTH(0,X86_SEL_TYPE_SYS_286_INT_GATE):
297	case BOTH(0,X86_SEL_TYPE_SYS_286_TRAP_GATE):
298	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_AVAIL):
299	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_BUSY):
300	case BOTH(0,X86_SEL_TYPE_SYS_386_CALL_GATE):
301	case BOTH(0,X86_SEL_TYPE_SYS_386_INT_GATE):
302	case BOTH(0,X86_SEL_TYPE_SYS_386_TRAP_GATE):
303	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
304	{
305	/** @todo fix this mess */
306	}
307	/* check limit. */
308	if ((RTGCUINTPTR)Addr > u32Limit)
309	return VERR_OUT_OF_SELECTOR_BOUNDS;
310	/* ok */
311	if (ppvGC)
312	*ppvGC = pvFlat;
313	if (pcb)
314	pcb = 0xffffffff - (RTGCUINTPTR)pvFlat + 1; / Depends on the type.. fixme if we care. */
315	return VINF_SUCCESS;
316
317	default:
318	return VERR_INVALID_SELECTOR;
319
320	}
321	#undef BOTH
322	}
323	return VERR_SELECTOR_NOT_PRESENT;
324	}
325
326
327	/**
328	* Validates and converts a GC selector based code address to a flat address.
329	*
330	* @returns Flat address.
331	* @param pVM VM Handle.
332	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
333	* A full selector can be passed, we'll only use the RPL part.
334	* @param SelCS Selector part.
335	* @param Addr Address part.
336	* @param ppvFlat Where to store the flat address.
337	*/
338	static int selmValidateAndConvertCSAddr(PVM pVM, RTSEL SelCPL, RTSEL SelCS, RTGCPTR Addr, PRTGCPTR ppvFlat)
339	{
340	Assert(!CPUMAreHiddenSelRegsValid(pVM));
341
342	/** @todo validate limit! */
343	VBOXDESC Desc;
344	if (!(SelCS & X86_SEL_LDT))
345	Desc = pVM->selm.s.CTXSUFF(paGdt)[SelCS >> X86_SEL_SHIFT];
346	else
347	{
348	/** @todo handle LDT page(s) not present! */
349	#ifdef IN_GC
350	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.GCPtrLdt + pVM->selm.s.offLdtHyper);
351	#else
352	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.HCPtrLdt + pVM->selm.s.offLdtHyper);
353	#endif
354	Desc = paLDT[SelCS >> X86_SEL_SHIFT];
355	}
356
357	/*
358	* Check if present.
359	*/
360	if (Desc.Gen.u1Present)
361	{
362	/*
363	* Type check.
364	*/
365	if ( Desc.Gen.u1DescType == 1
366	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
367	{
368	/*
369	* Check level.
370	*/
371	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
372	if ( !(Desc.Gen.u4Type & X86_SEL_TYPE_CONF)
373	? uLevel <= Desc.Gen.u2Dpl
374	: uLevel >= Desc.Gen.u2Dpl /* hope I got this right now... */
375	)
376	{
377	/*
378	* Limit check.
379	*/
380	uint32_t u32Limit = Desc.Gen.u4LimitHigh << 16 \| Desc.Gen.u16LimitLow;
381	if (Desc.Gen.u1Granularity)
382	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
383	if ((RTGCUINTPTR)Addr <= u32Limit)
384	{
385	if (ppvFlat)
386	*ppvFlat = (RTGCPTR)( (RTGCUINTPTR)Addr
387	+ ( (Desc.Gen.u8BaseHigh2 << 24)
388	\| (Desc.Gen.u8BaseHigh1 << 16)
389	\| Desc.Gen.u16BaseLow)
390	);
391	return VINF_SUCCESS;
392	}
393	return VERR_OUT_OF_SELECTOR_BOUNDS;
394	}
395	return VERR_INVALID_RPL;
396	}
397	return VERR_NOT_CODE_SELECTOR;
398	}
399	return VERR_SELECTOR_NOT_PRESENT;
400	}
401
402
403	/**
404	* Validates and converts a GC selector based code address to a flat address.
405	*
406	* @returns Flat address.
407	* @param pVM VM Handle.
408	* @param eflags Current eflags
409	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
410	* A full selector can be passed, we'll only use the RPL part.
411	* @param SelCS Selector part.
412	* @param pHiddenSel The hidden CS selector register.
413	* @param Addr Address part.
414	* @param ppvFlat Where to store the flat address.
415	*/
416	SELMDECL(int) SELMValidateAndConvertCSAddr(PVM pVM, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS, CPUMSELREGHID *pHiddenCSSel, RTGCPTR Addr, PRTGCPTR ppvFlat)
417	{
418	/*
419	* Deal with real & v86 mode first.
420	*/
421	if ( CPUMIsGuestInRealMode(pVM)
422	\|\| eflags.Bits.u1VM)
423	{
424	if (ppvFlat)
425	{
426	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
427
428	if (!CPUMAreHiddenSelRegsValid(pVM))
429	uFlat += ((RTGCUINTPTR)SelCS << 4);
430	else
431	uFlat += pHiddenCSSel->u32Base;
432
433	*ppvFlat = (RTGCPTR)uFlat;
434	}
435	return VINF_SUCCESS;
436	}
437
438	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
439
440	if (!CPUMAreHiddenSelRegsValid(pVM))
441	return selmValidateAndConvertCSAddr(pVM, SelCPL, SelCS, Addr, ppvFlat);
442
443	/*
444	* Check if present.
445	*/
446	if (pHiddenCSSel->Attr.n.u1Present)
447	{
448	/*
449	* Type check.
450	*/
451	if ( pHiddenCSSel->Attr.n.u1DescType == 1
452	&& (pHiddenCSSel->Attr.n.u4Type & X86_SEL_TYPE_CODE))
453	{
454	/*
455	* Check level.
456	*/
457	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
458	if ( !(pHiddenCSSel->Attr.n.u4Type & X86_SEL_TYPE_CONF)
459	? uLevel <= pHiddenCSSel->Attr.n.u2Dpl
460	: uLevel >= pHiddenCSSel->Attr.n.u2Dpl /* hope I got this right now... */
461	)
462	{
463	/*
464	* Limit check.
465	*/
466	uint32_t u32Limit = pHiddenCSSel->u32Limit;
467	/** @todo correct with hidden limit value?? */
468	if (pHiddenCSSel->Attr.n.u1Granularity)
469	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
470	if ((RTGCUINTPTR)Addr <= u32Limit)
471	{
472	if (ppvFlat)
473	*ppvFlat = (RTGCPTR)( (RTGCUINTPTR)Addr + pHiddenCSSel->u32Base );
474
475	return VINF_SUCCESS;
476	}
477	return VERR_OUT_OF_SELECTOR_BOUNDS;
478	}
479	return VERR_INVALID_RPL;
480	}
481	return VERR_NOT_CODE_SELECTOR;
482	}
483	return VERR_SELECTOR_NOT_PRESENT;
484	}
485
486
487	/**
488	* Checks if a selector is 32-bit or 16-bit.
489	*
490	* @returns True if it is 32-bit.
491	* @returns False if it is 16-bit.
492	* @param pVM VM Handle.
493	* @param Sel The selector.
494	*/
495	static bool selmIsSelector32Bit(PVM pVM, RTSEL Sel)
496	{
497	Assert(!CPUMAreHiddenSelRegsValid(pVM));
498
499	/** @todo validate limit! */
500	VBOXDESC Desc;
501	if (!(Sel & X86_SEL_LDT))
502	Desc = pVM->selm.s.CTXSUFF(paGdt)[Sel >> X86_SEL_SHIFT];
503	else
504	{
505	/** @todo handle LDT page(s) not present! */
506	PVBOXDESC paLDT = (PVBOXDESC)((char *)pVM->selm.s.CTXMID(,PtrLdt) + pVM->selm.s.offLdtHyper);
507	Desc = paLDT[Sel >> X86_SEL_SHIFT];
508	}
509	return Desc.Gen.u1DefBig;
510	}
511
512
513	/**
514	* Checks if a selector is 32-bit or 16-bit.
515	*
516	* @returns True if it is 32-bit.
517	* @returns False if it is 16-bit.
518	* @param pVM VM Handle.
519	* @param eflags Current eflags register
520	* @param Sel The selector.
521	* @param pHiddenSel The hidden selector register.
522	*/
523	SELMDECL(bool) SELMIsSelector32Bit(PVM pVM, X86EFLAGS eflags, RTSEL Sel, CPUMSELREGHID *pHiddenSel)
524	{
525	if (!CPUMAreHiddenSelRegsValid(pVM))
526	{
527	/*
528	* Deal with real & v86 mode first.
529	*/
530	if ( CPUMIsGuestInRealMode(pVM)
531	\|\| eflags.Bits.u1VM)
532	return false;
533
534	return selmIsSelector32Bit(pVM, Sel);
535	}
536	return pHiddenSel->Attr.n.u1DefBig;
537	}
538
539
540	/**
541	* Returns Hypervisor's Trap 08 (\#DF) selector.
542	*
543	* @returns Hypervisor's Trap 08 (\#DF) selector.
544	* @param pVM VM Handle.
545	*/
546	SELMDECL(RTSEL) SELMGetTrap8Selector(PVM pVM)
547	{
548	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
549	}
550
551
552	/**
553	* Sets EIP of Hypervisor's Trap 08 (\#DF) TSS.
554	*
555	* @param pVM VM Handle.
556	* @param u32EIP EIP of Trap 08 handler.
557	*/
558	SELMDECL(void) SELMSetTrap8EIP(PVM pVM, uint32_t u32EIP)
559	{
560	pVM->selm.s.TssTrap08.eip = u32EIP;
561	}
562
563
564	/**
565	* Sets ss:esp for ring1 in main Hypervisor's TSS.
566	*
567	* @param pVM VM Handle.
568	* @param ss Ring1 SS register value.
569	* @param esp Ring1 ESP register value.
570	*/
571	SELMDECL(void) SELMSetRing1Stack(PVM pVM, uint32_t ss, uint32_t esp)
572	{
573	pVM->selm.s.Tss.ss1 = ss;
574	pVM->selm.s.Tss.esp1 = esp;
575	}
576
577
578	/**
579	* Gets ss:esp for ring1 in main Hypervisor's TSS.
580	*
581	* @returns VBox status code.
582	* @param pVM VM Handle.
583	* @param pSS Ring1 SS register value.
584	* @param pEsp Ring1 ESP register value.
585	*/
586	SELMDECL(int) SELMGetRing1Stack(PVM pVM, uint32_t pSS, uint32_t pEsp)
587	{
588	if (pVM->selm.s.fSyncTSSRing0Stack)
589	{
590	GCPTRTYPE(uint8_t ) GCPtrTss = (GCPTRTYPE(uint8_t ))pVM->selm.s.GCPtrGuestTss;
591	int rc;
592	VBOXTSS tss;
593
594	Assert(pVM->selm.s.GCPtrGuestTss && pVM->selm.s.cbMonitoredGuestTss);
595
596	#ifdef IN_GC
597	bool fTriedAlready = false;
598
599	l_tryagain:
600	rc = MMGCRamRead(pVM, &tss.ss0, GCPtrTss + RT_OFFSETOF(VBOXTSS, ss0), sizeof(tss.ss0));
601	rc \|= MMGCRamRead(pVM, &tss.esp0, GCPtrTss + RT_OFFSETOF(VBOXTSS, esp0), sizeof(tss.esp0));
602	#ifdef DEBUG
603	rc \|= MMGCRamRead(pVM, &tss.offIoBitmap, GCPtrTss + RT_OFFSETOF(VBOXTSS, offIoBitmap), sizeof(tss.offIoBitmap));
604	#endif
605
606	if (VBOX_FAILURE(rc))
607	{
608	if (!fTriedAlready)
609	{
610	/* Shadow page might be out of sync. Sync and try again */
611	/** @todo might cross page boundary */
612	fTriedAlready = true;
613	rc = PGMPrefetchPage(pVM, GCPtrTss);
614	if (rc != VINF_SUCCESS)
615	return rc;
616	goto l_tryagain;
617	}
618	AssertMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
619	return rc;
620	}
621
622	#else /* !IN_GC */
623	/* Reading too much. Could be cheaper than two seperate calls though. */
624	rc = PGMPhysReadGCPtr(pVM, &tss, GCPtrTss, sizeof(VBOXTSS));
625	if (VBOX_FAILURE(rc))
626	{
627	AssertReleaseMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
628	return rc;
629	}
630	#endif /* !IN_GC */
631
632	#ifdef LOG_ENABLED
633	uint32_t ssr0 = pVM->selm.s.Tss.ss1;
634	uint32_t espr0 = pVM->selm.s.Tss.esp1;
635	ssr0 &= ~1;
636
637	if (ssr0 != tss.ss0 \|\| espr0 != tss.esp0)
638	Log(("SELMGetRing1Stack: Updating TSS ring 0 stack to %04X:%08X\n", tss.ss0, tss.esp0));
639
640	Log(("offIoBitmap=%#x\n", tss.offIoBitmap));
641	#endif
642	/* Update our TSS structure for the guest's ring 1 stack */
643	SELMSetRing1Stack(pVM, tss.ss0 \| 1, tss.esp0);
644	pVM->selm.s.fSyncTSSRing0Stack = false;
645	}
646
647	*pSS = pVM->selm.s.Tss.ss1;
648	*pEsp = pVM->selm.s.Tss.esp1;
649
650	return VINF_SUCCESS;
651	}
652
653
654	/**
655	* Returns Guest TSS pointer
656	*
657	* @param pVM VM Handle.
658	*/
659	SELMDECL(RTGCPTR) SELMGetGuestTSS(PVM pVM)
660	{
661	return (RTGCPTR)pVM->selm.s.GCPtrGuestTss;
662	}
663
664
665	/**
666	* Validates a CS selector.
667	*
668	* @returns VBox status code.
669	* @param pSelInfo Pointer to the selector information for the CS selector.
670	* @param SelCPL The selector defining the CPL (SS).
671	*/
672	SELMDECL(int) SELMSelInfoValidateCS(PCSELMSELINFO pSelInfo, RTSEL SelCPL)
673	{
674	/*
675	* Check if present.
676	*/
677	if (pSelInfo->Raw.Gen.u1Present)
678	{
679	/*
680	* Type check.
681	*/
682	if ( pSelInfo->Raw.Gen.u1DescType == 1
683	&& (pSelInfo->Raw.Gen.u4Type & X86_SEL_TYPE_CODE))
684	{
685	/*
686	* Check level.
687	*/
688	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, pSelInfo->Sel & X86_SEL_RPL);
689	if ( !(pSelInfo->Raw.Gen.u4Type & X86_SEL_TYPE_CONF)
690	? uLevel <= pSelInfo->Raw.Gen.u2Dpl
691	: uLevel >= pSelInfo->Raw.Gen.u2Dpl /* hope I got this right now... */
692	)
693	return VINF_SUCCESS;
694	return VERR_INVALID_RPL;
695	}
696	return VERR_NOT_CODE_SELECTOR;
697	}
698	return VERR_SELECTOR_NOT_PRESENT;
699	}
700
701
702	/**
703	* Gets the hypervisor code selector (CS).
704	* @returns CS selector.
705	* @param pVM The VM handle.
706	*/
707	SELMDECL(RTSEL) SELMGetHyperCS(PVM pVM)
708	{
709	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
710	}
711
712
713	/**
714	* Gets the 64-mode hypervisor code selector (CS64).
715	* @returns CS selector.
716	* @param pVM The VM handle.
717	*/
718	SELMDECL(RTSEL) SELMGetHyperCS64(PVM pVM)
719	{
720	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64];
721	}
722
723
724	/**
725	* Gets the hypervisor data selector (DS).
726	* @returns DS selector.
727	* @param pVM The VM handle.
728	*/
729	SELMDECL(RTSEL) SELMGetHyperDS(PVM pVM)
730	{
731	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
732	}
733
734
735	/**
736	* Gets the hypervisor TSS selector.
737	* @returns TSS selector.
738	* @param pVM The VM handle.
739	*/
740	SELMDECL(RTSEL) SELMGetHyperTSS(PVM pVM)
741	{
742	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS];
743	}
744
745
746	/**
747	* Gets the hypervisor TSS Trap 8 selector.
748	* @returns TSS Trap 8 selector.
749	* @param pVM The VM handle.
750	*/
751	SELMDECL(RTSEL) SELMGetHyperTSSTrap08(PVM pVM)
752	{
753	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
754	}
755
756
757	/**
758	* Gets the address for the hypervisor GDT.
759	*
760	* @returns The GDT address.
761	* @param pVM The VM handle.
762	* @remark This is intended only for very special use, like in the world
763	* switchers. Don't exploit this API!
764	*/
765	SELMDECL(RTGCPTR) SELMGetHyperGDT(PVM pVM)
766	{
767	/*
768	* Always convert this from the HC pointer since. We're can be
769	* called before the first relocation and have to work correctly
770	* without having dependencies on the relocation order.
771	*/
772	return MMHyperHC2GC(pVM, pVM->selm.s.paGdtHC);
773	}
774
775
776	/**
777	* Gets info about the current TSS.
778	*
779	* @returns VBox status code.
780	* @retval VINF_SUCCESS if we've got a TSS loaded.
781	* @retval VERR_SELM_NO_TSS if we haven't got a TSS (rather unlikely).
782	*
783	* @param pVM The VM handle.
784	* @param pGCPtrTss Where to store the TSS address.
785	* @param pcbTss Where to store the TSS size limit.
786	* @param pfCanHaveIOBitmap Where to store the can-have-I/O-bitmap indicator. (optional)
787	*/
788	SELMDECL(int) SELMGetTSSInfo(PVM pVM, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap)
789	{
790	if (!CPUMAreHiddenSelRegsValid(pVM))
791	{
792	/*
793	* Do we have a valid TSS?
794	*/
795	if ( pVM->selm.s.GCSelTss == (RTSEL)~0
796	\|\| !pVM->selm.s.fGuestTss32Bit)
797	return VERR_SELM_NO_TSS;
798
799	/*
800	* Fill in return values.
801	*/
802	*pGCPtrTss = (RTGCUINTPTR)pVM->selm.s.GCPtrGuestTss;
803	*pcbTss = pVM->selm.s.cbGuestTss;
804	if (pfCanHaveIOBitmap)
805	*pfCanHaveIOBitmap = pVM->selm.s.fGuestTss32Bit;
806	}
807	else
808	{
809	CPUMSELREGHID *pHiddenTRReg;
810
811	pHiddenTRReg = CPUMGetGuestTRHid(pVM);
812
813	*pGCPtrTss = pHiddenTRReg->u32Base;
814	*pcbTss = pHiddenTRReg->u32Limit;
815
816	if (pfCanHaveIOBitmap)
817	*pfCanHaveIOBitmap = pHiddenTRReg->Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
818	\|\| pHiddenTRReg->Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
819	}
820	return VINF_SUCCESS;
821	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/SELMAll.cpp@ 2295

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