SELMAll.cpp@ 41829

Last change on this file since 41829 was 41803, checked in by vboxsync, 12 years ago
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1	/* $Id: SELMAll.cpp 41803 2012-06-17 17:20:33Z vboxsync $ */
2	/** @file
3	* SELM All contexts.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_SELM
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/pgm.h>
27	#include "SELMInternal.h"
28	#include <VBox/vmm/vm.h>
29	#include <VBox/err.h>
30	#include <VBox/param.h>
31	#include <iprt/assert.h>
32	#include <VBox/log.h>
33	#include <VBox/vmm/vmm.h>
34	#include <iprt/x86.h>
35
36
37
38	#ifndef IN_RING0
39
40	/**
41	* Converts a GC selector based address to a flat address.
42	*
43	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
44	* for that.
45	*
46	* @returns Flat address.
47	* @param pVM Pointer to the VM.
48	* @param Sel Selector part.
49	* @param Addr Address part.
50	* @remarks Don't use when in long mode.
51	*/
52	VMMDECL(RTGCPTR) SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr)
53	{
54	Assert(pVM->cCpus == 1 && !CPUMIsGuestInLongMode(VMMGetCpu(pVM))); /* DON'T USE! */
55
56	/** @todo check the limit. */
57	X86DESC Desc;
58	if (!(Sel & X86_SEL_LDT))
59	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
60	else
61	{
62	/** @todo handle LDT pages not present! */
63	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
64	Desc = paLDT[Sel >> X86_SEL_SHIFT];
65	}
66
67	return (RTGCPTR)(((RTGCUINTPTR)Addr + X86DESC_BASE(Desc)) & 0xffffffff);
68	}
69	#endif /* !IN_RING0 */
70
71
72	/**
73	* Converts a GC selector based address to a flat address.
74	*
75	* No limit checks are done. Use the SELMToFlat() or SELMValidate() functions
76	* for that.
77	*
78	* @returns Flat address.
79	* @param pVM Pointer to the VM.
80	* @param SelReg Selector register
81	* @param pCtxCore CPU context
82	* @param Addr Address part.
83	*/
84	VMMDECL(RTGCPTR) SELMToFlat(PVM pVM, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr)
85	{
86	PCPUMSELREGHID pHiddenSel;
87	RTSEL Sel;
88	int rc;
89	PVMCPU pVCpu = VMMGetCpu(pVM);
90
91	rc = DISFetchRegSegEx(pCtxCore, SelReg, &Sel, &pHiddenSel); AssertRC(rc);
92
93	/*
94	* Deal with real & v86 mode first.
95	*/
96	if ( pCtxCore->eflags.Bits.u1VM
97	\|\| CPUMIsGuestInRealMode(pVCpu))
98	{
99	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
100	if (CPUMAreHiddenSelRegsValid(pVCpu))
101	uFlat += pHiddenSel->u64Base;
102	else
103	uFlat += ((RTGCUINTPTR)Sel << 4);
104	return (RTGCPTR)uFlat;
105	}
106
107	#ifdef IN_RING0
108	Assert(CPUMAreHiddenSelRegsValid(pVCpu));
109	#else
110	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
111	if (!CPUMAreHiddenSelRegsValid(pVCpu))
112	return SELMToFlatBySel(pVM, Sel, Addr);
113	#endif
114
115	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
116	if ( pCtxCore->csHid.Attr.n.u1Long
117	&& CPUMIsGuestInLongMode(pVCpu))
118	{
119	switch (SelReg)
120	{
121	case DISSELREG_FS:
122	case DISSELREG_GS:
123	return (RTGCPTR)(pHiddenSel->u64Base + Addr);
124
125	default:
126	return Addr; /* base 0 */
127	}
128	}
129
130	/* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
131	Assert(pHiddenSel->u64Base <= 0xffffffff);
132	return ((pHiddenSel->u64Base + (RTGCUINTPTR)Addr) & 0xffffffff);
133	}
134
135
136	/**
137	* Converts a GC selector based address to a flat address.
138	*
139	* Some basic checking is done, but not all kinds yet.
140	*
141	* @returns VBox status
142	* @param pVCpu Pointer to the VMCPU.
143	* @param SelReg Selector register.
144	* @param pCtxCore CPU context.
145	* @param Addr Address part.
146	* @param fFlags SELMTOFLAT_FLAGS_*
147	* GDT entires are valid.
148	* @param ppvGC Where to store the GC flat address.
149	*/
150	VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCCPUMCTXCORE pCtxCore, RTGCPTR Addr, unsigned fFlags, PRTGCPTR ppvGC)
151	{
152	/*
153	* Fetch the selector first.
154	*/
155	PCPUMSELREGHID pHiddenSel;
156	RTSEL Sel;
157
158	int rc = DISFetchRegSegEx(pCtxCore, SelReg, &Sel, &pHiddenSel);
159	AssertRC(rc);
160
161	/*
162	* Deal with real & v86 mode first.
163	*/
164	if ( pCtxCore->eflags.Bits.u1VM
165	\|\| CPUMIsGuestInRealMode(pVCpu))
166	{
167	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
168	if (ppvGC)
169	{
170	if ( pHiddenSel
171	&& CPUMAreHiddenSelRegsValid(pVCpu))
172	*ppvGC = (RTGCPTR)(pHiddenSel->u64Base + uFlat);
173	else
174	*ppvGC = (RTGCPTR)(((RTGCUINTPTR)Sel << 4) + uFlat);
175	}
176	return VINF_SUCCESS;
177	}
178
179
180	uint32_t u32Limit;
181	RTGCPTR pvFlat;
182	uint32_t u1Present, u1DescType, u1Granularity, u4Type;
183
184	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
185	#ifndef IN_RC
186	if ( pHiddenSel
187	&& CPUMAreHiddenSelRegsValid(pVCpu))
188	{
189	bool fCheckLimit = true;
190
191	u1Present = pHiddenSel->Attr.n.u1Present;
192	u1Granularity = pHiddenSel->Attr.n.u1Granularity;
193	u1DescType = pHiddenSel->Attr.n.u1DescType;
194	u4Type = pHiddenSel->Attr.n.u4Type;
195	u32Limit = pHiddenSel->u32Limit;
196
197	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
198	if ( pCtxCore->csHid.Attr.n.u1Long
199	&& CPUMIsGuestInLongMode(pVCpu))
200	{
201	fCheckLimit = false;
202	switch (SelReg)
203	{
204	case DISSELREG_FS:
205	case DISSELREG_GS:
206	pvFlat = (pHiddenSel->u64Base + Addr);
207	break;
208
209	default:
210	pvFlat = Addr;
211	break;
212	}
213	}
214	else
215	{
216	/* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
217	Assert(pHiddenSel->u64Base <= 0xffffffff);
218	pvFlat = (RTGCPTR)((pHiddenSel->u64Base + (RTGCUINTPTR)Addr) & 0xffffffff);
219	}
220
221	/*
222	* Check if present.
223	*/
224	if (u1Present)
225	{
226	/*
227	* Type check.
228	*/
229	switch (u4Type)
230	{
231
232	/** Read only selector type. */
233	case X86_SEL_TYPE_RO:
234	case X86_SEL_TYPE_RO_ACC:
235	case X86_SEL_TYPE_RW:
236	case X86_SEL_TYPE_RW_ACC:
237	case X86_SEL_TYPE_EO:
238	case X86_SEL_TYPE_EO_ACC:
239	case X86_SEL_TYPE_ER:
240	case X86_SEL_TYPE_ER_ACC:
241	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
242	{
243	/** @todo fix this mess */
244	}
245	/* check limit. */
246	if (fCheckLimit && (RTGCUINTPTR)Addr > u32Limit)
247	return VERR_OUT_OF_SELECTOR_BOUNDS;
248	/* ok */
249	if (ppvGC)
250	*ppvGC = pvFlat;
251	return VINF_SUCCESS;
252
253	case X86_SEL_TYPE_EO_CONF:
254	case X86_SEL_TYPE_EO_CONF_ACC:
255	case X86_SEL_TYPE_ER_CONF:
256	case X86_SEL_TYPE_ER_CONF_ACC:
257	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
258	{
259	/** @todo fix this mess */
260	}
261	/* check limit. */
262	if (fCheckLimit && (RTGCUINTPTR)Addr > u32Limit)
263	return VERR_OUT_OF_SELECTOR_BOUNDS;
264	/* ok */
265	if (ppvGC)
266	*ppvGC = pvFlat;
267	return VINF_SUCCESS;
268
269	case X86_SEL_TYPE_RO_DOWN:
270	case X86_SEL_TYPE_RO_DOWN_ACC:
271	case X86_SEL_TYPE_RW_DOWN:
272	case X86_SEL_TYPE_RW_DOWN_ACC:
273	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
274	{
275	/** @todo fix this mess */
276	}
277	/* check limit. */
278	if (fCheckLimit)
279	{
280	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
281	return VERR_OUT_OF_SELECTOR_BOUNDS;
282	if ((RTGCUINTPTR)Addr <= u32Limit)
283	return VERR_OUT_OF_SELECTOR_BOUNDS;
284	}
285	/* ok */
286	if (ppvGC)
287	*ppvGC = pvFlat;
288	return VINF_SUCCESS;
289
290	default:
291	return VERR_INVALID_SELECTOR;
292
293	}
294	}
295	}
296	# ifndef IN_RING0
297	else
298	# endif
299	#endif /* !IN_RC */
300	#ifndef IN_RING0
301	{
302	X86DESC Desc;
303
304	PVM pVM = pVCpu->CTX_SUFF(pVM);
305	if (!(Sel & X86_SEL_LDT))
306	{
307	if ( !(fFlags & SELMTOFLAT_FLAGS_HYPER)
308	&& (unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.GuestGdtr.cbGdt)
309	return VERR_INVALID_SELECTOR;
310	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
311	}
312	else
313	{
314	if ((unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.cbLdtLimit)
315	return VERR_INVALID_SELECTOR;
316
317	/** @todo handle LDT page(s) not present! */
318	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
319	Desc = paLDT[Sel >> X86_SEL_SHIFT];
320	}
321
322	/* calc limit. */
323	u32Limit = X86DESC_LIMIT(Desc);
324	if (Desc.Gen.u1Granularity)
325	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
326
327	/* calc address assuming straight stuff. */
328	pvFlat = (RTGCPTR)((RTGCUINTPTR)Addr + X86DESC_BASE(Desc));
329
330	/* Cut the address to 32 bits. */
331	Assert(!CPUMIsGuestInLongMode(pVCpu));
332	pvFlat &= 0xffffffff;
333
334	u1Present = Desc.Gen.u1Present;
335	u1Granularity = Desc.Gen.u1Granularity;
336	u1DescType = Desc.Gen.u1DescType;
337	u4Type = Desc.Gen.u4Type;
338
339	/*
340	* Check if present.
341	*/
342	if (u1Present)
343	{
344	/*
345	* Type check.
346	*/
347	# define BOTH(a, b) ((a << 16) \| b)
348	switch (BOTH(u1DescType, u4Type))
349	{
350
351	/** Read only selector type. */
352	case BOTH(1,X86_SEL_TYPE_RO):
353	case BOTH(1,X86_SEL_TYPE_RO_ACC):
354	case BOTH(1,X86_SEL_TYPE_RW):
355	case BOTH(1,X86_SEL_TYPE_RW_ACC):
356	case BOTH(1,X86_SEL_TYPE_EO):
357	case BOTH(1,X86_SEL_TYPE_EO_ACC):
358	case BOTH(1,X86_SEL_TYPE_ER):
359	case BOTH(1,X86_SEL_TYPE_ER_ACC):
360	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
361	{
362	/** @todo fix this mess */
363	}
364	/* check limit. */
365	if ((RTGCUINTPTR)Addr > u32Limit)
366	return VERR_OUT_OF_SELECTOR_BOUNDS;
367	/* ok */
368	if (ppvGC)
369	*ppvGC = pvFlat;
370	return VINF_SUCCESS;
371
372	case BOTH(1,X86_SEL_TYPE_EO_CONF):
373	case BOTH(1,X86_SEL_TYPE_EO_CONF_ACC):
374	case BOTH(1,X86_SEL_TYPE_ER_CONF):
375	case BOTH(1,X86_SEL_TYPE_ER_CONF_ACC):
376	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
377	{
378	/** @todo fix this mess */
379	}
380	/* check limit. */
381	if ((RTGCUINTPTR)Addr > u32Limit)
382	return VERR_OUT_OF_SELECTOR_BOUNDS;
383	/* ok */
384	if (ppvGC)
385	*ppvGC = pvFlat;
386	return VINF_SUCCESS;
387
388	case BOTH(1,X86_SEL_TYPE_RO_DOWN):
389	case BOTH(1,X86_SEL_TYPE_RO_DOWN_ACC):
390	case BOTH(1,X86_SEL_TYPE_RW_DOWN):
391	case BOTH(1,X86_SEL_TYPE_RW_DOWN_ACC):
392	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
393	{
394	/** @todo fix this mess */
395	}
396	/* check limit. */
397	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
398	return VERR_OUT_OF_SELECTOR_BOUNDS;
399	if ((RTGCUINTPTR)Addr <= u32Limit)
400	return VERR_OUT_OF_SELECTOR_BOUNDS;
401
402	/* ok */
403	if (ppvGC)
404	*ppvGC = pvFlat;
405	return VINF_SUCCESS;
406
407	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_AVAIL):
408	case BOTH(0,X86_SEL_TYPE_SYS_LDT):
409	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_BUSY):
410	case BOTH(0,X86_SEL_TYPE_SYS_286_CALL_GATE):
411	case BOTH(0,X86_SEL_TYPE_SYS_TASK_GATE):
412	case BOTH(0,X86_SEL_TYPE_SYS_286_INT_GATE):
413	case BOTH(0,X86_SEL_TYPE_SYS_286_TRAP_GATE):
414	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_AVAIL):
415	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_BUSY):
416	case BOTH(0,X86_SEL_TYPE_SYS_386_CALL_GATE):
417	case BOTH(0,X86_SEL_TYPE_SYS_386_INT_GATE):
418	case BOTH(0,X86_SEL_TYPE_SYS_386_TRAP_GATE):
419	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
420	{
421	/** @todo fix this mess */
422	}
423	/* check limit. */
424	if ((RTGCUINTPTR)Addr > u32Limit)
425	return VERR_OUT_OF_SELECTOR_BOUNDS;
426	/* ok */
427	if (ppvGC)
428	*ppvGC = pvFlat;
429	return VINF_SUCCESS;
430
431	default:
432	return VERR_INVALID_SELECTOR;
433
434	}
435	# undef BOTH
436	}
437	}
438	#endif /* !IN_RING0 */
439	return VERR_SELECTOR_NOT_PRESENT;
440	}
441
442
443	#ifndef IN_RING0
444	/**
445	* Converts a GC selector based address to a flat address.
446	*
447	* Some basic checking is done, but not all kinds yet.
448	*
449	* @returns VBox status
450	* @param pVCpu Pointer to the VMCPU.
451	* @param eflags Current eflags
452	* @param Sel Selector part.
453	* @param Addr Address part.
454	* @param pHiddenSel Hidden selector register (can be NULL)
455	* @param fFlags SELMTOFLAT_FLAGS_*
456	* GDT entires are valid.
457	* @param ppvGC Where to store the GC flat address.
458	* @param pcb Where to store the bytes from *ppvGC which can be accessed according to
459	* the selector. NULL is allowed.
460	* @remarks Don't use when in long mode.
461	*/
462	VMMDECL(int) SELMToFlatBySelEx(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr, PCCPUMSELREGHID pHiddenSel, uint32_t fFlags, PRTGCPTR ppvGC, uint32_t *pcb)
463	{
464	Assert(!CPUMIsGuestInLongMode(pVCpu)); /* DON'T USE! */
465
466	/*
467	* Deal with real & v86 mode first.
468	*/
469	if ( eflags.Bits.u1VM
470	\|\| CPUMIsGuestInRealMode(pVCpu))
471	{
472	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
473	if (ppvGC)
474	{
475	if ( pHiddenSel
476	&& CPUMAreHiddenSelRegsValid(pVCpu))
477	*ppvGC = (RTGCPTR)(pHiddenSel->u64Base + uFlat);
478	else
479	*ppvGC = (RTGCPTR)(((RTGCUINTPTR)Sel << 4) + uFlat);
480	}
481	if (pcb)
482	*pcb = 0x10000 - uFlat;
483	return VINF_SUCCESS;
484	}
485
486
487	uint32_t u32Limit;
488	RTGCPTR pvFlat;
489	uint32_t u1Present, u1DescType, u1Granularity, u4Type;
490
491	/** @todo when we're in 16 bits mode, we should cut off the address as well.. */
492	if ( pHiddenSel
493	&& CPUMAreHiddenSelRegsValid(pVCpu))
494	{
495	u1Present = pHiddenSel->Attr.n.u1Present;
496	u1Granularity = pHiddenSel->Attr.n.u1Granularity;
497	u1DescType = pHiddenSel->Attr.n.u1DescType;
498	u4Type = pHiddenSel->Attr.n.u4Type;
499
500	u32Limit = pHiddenSel->u32Limit;
501	pvFlat = (RTGCPTR)(pHiddenSel->u64Base + (RTGCUINTPTR)Addr);
502
503	if ( !pHiddenSel->Attr.n.u1Long
504	\|\| !CPUMIsGuestInLongMode(pVCpu))
505	{
506	/* AMD64 manual: compatibility mode ignores the high 32 bits when calculating an effective address. */
507	pvFlat &= 0xffffffff;
508	}
509	}
510	else
511	{
512	X86DESC Desc;
513
514	PVM pVM = pVCpu->CTX_SUFF(pVM);
515	if (!(Sel & X86_SEL_LDT))
516	{
517	if ( !(fFlags & SELMTOFLAT_FLAGS_HYPER)
518	&& (unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.GuestGdtr.cbGdt)
519	return VERR_INVALID_SELECTOR;
520	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
521	}
522	else
523	{
524	if ((unsigned)(Sel & X86_SEL_MASK) >= pVM->selm.s.cbLdtLimit)
525	return VERR_INVALID_SELECTOR;
526
527	/** @todo handle LDT page(s) not present! */
528	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
529	Desc = paLDT[Sel >> X86_SEL_SHIFT];
530	}
531
532	/* calc limit. */
533	u32Limit = X86DESC_LIMIT(Desc);
534	if (Desc.Gen.u1Granularity)
535	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
536
537	/* calc address assuming straight stuff. */
538	pvFlat = (RTGCPTR)((RTGCUINTPTR)Addr + X86DESC_BASE(Desc));
539
540	/* Cut the address to 32 bits. */
541	Assert(!CPUMIsGuestInLongMode(pVCpu));
542	pvFlat &= 0xffffffff;
543
544	u1Present = Desc.Gen.u1Present;
545	u1Granularity = Desc.Gen.u1Granularity;
546	u1DescType = Desc.Gen.u1DescType;
547	u4Type = Desc.Gen.u4Type;
548	}
549
550	/*
551	* Check if present.
552	*/
553	if (u1Present)
554	{
555	/*
556	* Type check.
557	*/
558	#define BOTH(a, b) ((a << 16) \| b)
559	switch (BOTH(u1DescType, u4Type))
560	{
561
562	/** Read only selector type. */
563	case BOTH(1,X86_SEL_TYPE_RO):
564	case BOTH(1,X86_SEL_TYPE_RO_ACC):
565	case BOTH(1,X86_SEL_TYPE_RW):
566	case BOTH(1,X86_SEL_TYPE_RW_ACC):
567	case BOTH(1,X86_SEL_TYPE_EO):
568	case BOTH(1,X86_SEL_TYPE_EO_ACC):
569	case BOTH(1,X86_SEL_TYPE_ER):
570	case BOTH(1,X86_SEL_TYPE_ER_ACC):
571	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
572	{
573	/** @todo fix this mess */
574	}
575	/* check limit. */
576	if ((RTGCUINTPTR)Addr > u32Limit)
577	return VERR_OUT_OF_SELECTOR_BOUNDS;
578	/* ok */
579	if (ppvGC)
580	*ppvGC = pvFlat;
581	if (pcb)
582	*pcb = u32Limit - (uint32_t)Addr + 1;
583	return VINF_SUCCESS;
584
585	case BOTH(1,X86_SEL_TYPE_EO_CONF):
586	case BOTH(1,X86_SEL_TYPE_EO_CONF_ACC):
587	case BOTH(1,X86_SEL_TYPE_ER_CONF):
588	case BOTH(1,X86_SEL_TYPE_ER_CONF_ACC):
589	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
590	{
591	/** @todo fix this mess */
592	}
593	/* check limit. */
594	if ((RTGCUINTPTR)Addr > u32Limit)
595	return VERR_OUT_OF_SELECTOR_BOUNDS;
596	/* ok */
597	if (ppvGC)
598	*ppvGC = pvFlat;
599	if (pcb)
600	*pcb = u32Limit - (uint32_t)Addr + 1;
601	return VINF_SUCCESS;
602
603	case BOTH(1,X86_SEL_TYPE_RO_DOWN):
604	case BOTH(1,X86_SEL_TYPE_RO_DOWN_ACC):
605	case BOTH(1,X86_SEL_TYPE_RW_DOWN):
606	case BOTH(1,X86_SEL_TYPE_RW_DOWN_ACC):
607	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
608	{
609	/** @todo fix this mess */
610	}
611	/* check limit. */
612	if (!u1Granularity && (RTGCUINTPTR)Addr > (RTGCUINTPTR)0xffff)
613	return VERR_OUT_OF_SELECTOR_BOUNDS;
614	if ((RTGCUINTPTR)Addr <= u32Limit)
615	return VERR_OUT_OF_SELECTOR_BOUNDS;
616
617	/* ok */
618	if (ppvGC)
619	*ppvGC = pvFlat;
620	if (pcb)
621	*pcb = (RTGCUINTPTR)(u1Granularity ? 0xffffffff : 0xffff) - (RTGCUINTPTR)Addr + 1;
622	return VINF_SUCCESS;
623
624	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_AVAIL):
625	case BOTH(0,X86_SEL_TYPE_SYS_LDT):
626	case BOTH(0,X86_SEL_TYPE_SYS_286_TSS_BUSY):
627	case BOTH(0,X86_SEL_TYPE_SYS_286_CALL_GATE):
628	case BOTH(0,X86_SEL_TYPE_SYS_TASK_GATE):
629	case BOTH(0,X86_SEL_TYPE_SYS_286_INT_GATE):
630	case BOTH(0,X86_SEL_TYPE_SYS_286_TRAP_GATE):
631	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_AVAIL):
632	case BOTH(0,X86_SEL_TYPE_SYS_386_TSS_BUSY):
633	case BOTH(0,X86_SEL_TYPE_SYS_386_CALL_GATE):
634	case BOTH(0,X86_SEL_TYPE_SYS_386_INT_GATE):
635	case BOTH(0,X86_SEL_TYPE_SYS_386_TRAP_GATE):
636	if (!(fFlags & SELMTOFLAT_FLAGS_NO_PL))
637	{
638	/** @todo fix this mess */
639	}
640	/* check limit. */
641	if ((RTGCUINTPTR)Addr > u32Limit)
642	return VERR_OUT_OF_SELECTOR_BOUNDS;
643	/* ok */
644	if (ppvGC)
645	*ppvGC = pvFlat;
646	if (pcb)
647	pcb = 0xffffffff - (RTGCUINTPTR)pvFlat + 1; / Depends on the type.. fixme if we care. */
648	return VINF_SUCCESS;
649
650	default:
651	return VERR_INVALID_SELECTOR;
652
653	}
654	#undef BOTH
655	}
656	return VERR_SELECTOR_NOT_PRESENT;
657	}
658	#endif /* !IN_RING0 */
659
660
661	/**
662	* Validates and converts a GC selector based code address to a flat
663	* address when in real or v8086 mode.
664	*
665	* @returns VINF_SUCCESS.
666	* @param pVCpu Pointer to the VMCPU.
667	* @param SelCS Selector part.
668	* @param pHidCS The hidden CS register part. Optional.
669	* @param Addr Address part.
670	* @param ppvFlat Where to store the flat address.
671	*/
672	DECLINLINE(int) selmValidateAndConvertCSAddrRealMode(PVMCPU pVCpu, RTSEL SelCS, PCCPUMSELREGHID pHidCS, RTGCPTR Addr,
673	PRTGCPTR ppvFlat)
674	{
675	RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff;
676	if (!pHidCS \|\| !CPUMAreHiddenSelRegsValid(pVCpu))
677	uFlat += ((RTGCUINTPTR)SelCS << 4);
678	else
679	uFlat += pHidCS->u64Base;
680	*ppvFlat = (RTGCPTR)uFlat;
681	return VINF_SUCCESS;
682	}
683
684
685	#ifndef IN_RING0
686	/**
687	* Validates and converts a GC selector based code address to a flat
688	* address when in protected/long mode using the standard algorithm.
689	*
690	* @returns VBox status code.
691	* @param pVM Pointer to the VM.
692	* @param pVCpu Pointer to the VMCPU.
693	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
694	* A full selector can be passed, we'll only use the RPL part.
695	* @param SelCS Selector part.
696	* @param Addr Address part.
697	* @param ppvFlat Where to store the flat address.
698	* @param pcBits Where to store the segment bitness (16/32/64). Optional.
699	*/
700	DECLINLINE(int) selmValidateAndConvertCSAddrStd(PVM pVM, PVMCPU pVCpu, RTSEL SelCPL, RTSEL SelCS, RTGCPTR Addr,
701	PRTGCPTR ppvFlat, uint32_t *pcBits)
702	{
703	NOREF(pVCpu);
704	/** @todo validate limit! */
705	X86DESC Desc;
706	if (!(SelCS & X86_SEL_LDT))
707	Desc = pVM->selm.s.CTX_SUFF(paGdt)[SelCS >> X86_SEL_SHIFT];
708	else
709	{
710	/** @todo handle LDT page(s) not present! */
711	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
712	Desc = paLDT[SelCS >> X86_SEL_SHIFT];
713	}
714
715	/*
716	* Check if present.
717	*/
718	if (Desc.Gen.u1Present)
719	{
720	/*
721	* Type check.
722	*/
723	if ( Desc.Gen.u1DescType == 1
724	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
725	{
726	/*
727	* Check level.
728	*/
729	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
730	if ( !(Desc.Gen.u4Type & X86_SEL_TYPE_CONF)
731	? uLevel <= Desc.Gen.u2Dpl
732	: uLevel >= Desc.Gen.u2Dpl /* hope I got this right now... */
733	)
734	{
735	/*
736	* Limit check.
737	*/
738	uint32_t u32Limit = X86DESC_LIMIT(Desc);
739	if (Desc.Gen.u1Granularity)
740	u32Limit = (u32Limit << PAGE_SHIFT) \| PAGE_OFFSET_MASK;
741	if ((RTGCUINTPTR)Addr <= u32Limit)
742	{
743	*ppvFlat = (RTGCPTR)((RTGCUINTPTR)Addr + X86DESC_BASE(Desc));
744	/* Cut the address to 32 bits. */
745	*ppvFlat &= 0xffffffff;
746
747	if (pcBits)
748	pcBits = Desc.Gen.u1DefBig ? 32 : 16; /* @todo GUEST64 */
749	return VINF_SUCCESS;
750	}
751	return VERR_OUT_OF_SELECTOR_BOUNDS;
752	}
753	return VERR_INVALID_RPL;
754	}
755	return VERR_NOT_CODE_SELECTOR;
756	}
757	return VERR_SELECTOR_NOT_PRESENT;
758	}
759	#endif /* !IN_RING0 */
760
761
762	/**
763	* Validates and converts a GC selector based code address to a flat
764	* address when in protected/long mode using the standard algorithm.
765	*
766	* @returns VBox status code.
767	* @param pVCpu Pointer to the VMCPU.
768	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
769	* A full selector can be passed, we'll only use the RPL part.
770	* @param SelCS Selector part.
771	* @param Addr Address part.
772	* @param ppvFlat Where to store the flat address.
773	*/
774	DECLINLINE(int) selmValidateAndConvertCSAddrHidden(PVMCPU pVCpu, RTSEL SelCPL, RTSEL SelCS, PCCPUMSELREGHID pHidCS,
775	RTGCPTR Addr, PRTGCPTR ppvFlat)
776	{
777	/*
778	* Check if present.
779	*/
780	if (pHidCS->Attr.n.u1Present)
781	{
782	/*
783	* Type check.
784	*/
785	if ( pHidCS->Attr.n.u1DescType == 1
786	&& (pHidCS->Attr.n.u4Type & X86_SEL_TYPE_CODE))
787	{
788	/*
789	* Check level.
790	*/
791	unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, SelCS & X86_SEL_RPL);
792	if ( !(pHidCS->Attr.n.u4Type & X86_SEL_TYPE_CONF)
793	? uLevel <= pHidCS->Attr.n.u2Dpl
794	: uLevel >= pHidCS->Attr.n.u2Dpl /* hope I got this right now... */
795	)
796	{
797	/* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
798	if ( pHidCS->Attr.n.u1Long
799	&& CPUMIsGuestInLongMode(pVCpu))
800	{
801	*ppvFlat = Addr;
802	return VINF_SUCCESS;
803	}
804
805	/*
806	* Limit check. Note that the limit in the hidden register is the
807	* final value. The granularity bit was included in its calculation.
808	*/
809	uint32_t u32Limit = pHidCS->u32Limit;
810	if ((RTGCUINTPTR)Addr <= u32Limit)
811	{
812	*ppvFlat = (RTGCPTR)( (RTGCUINTPTR)Addr + pHidCS->u64Base );
813	return VINF_SUCCESS;
814	}
815	return VERR_OUT_OF_SELECTOR_BOUNDS;
816	}
817	Log(("Invalid RPL Attr.n.u4Type=%x cpl=%x dpl=%x\n", pHidCS->Attr.n.u4Type, uLevel, pHidCS->Attr.n.u2Dpl));
818	return VERR_INVALID_RPL;
819	}
820	return VERR_NOT_CODE_SELECTOR;
821	}
822	return VERR_SELECTOR_NOT_PRESENT;
823	}
824
825
826	#ifdef IN_RC
827	/**
828	* Validates and converts a GC selector based code address to a flat address.
829	*
830	* This is like SELMValidateAndConvertCSAddr + SELMIsSelector32Bit but with
831	* invalid hidden CS data. It's customized for dealing efficiently with CS
832	* at GC trap time.
833	*
834	* @returns VBox status code.
835	* @param pVCpu Pointer to the VMCPU.
836	* @param eflags Current eflags
837	* @param SelCPL Current privilege level. Get this from SS - CS might be
838	* conforming! A full selector can be passed, we'll only
839	* use the RPL part.
840	* @param SelCS Selector part.
841	* @param Addr Address part.
842	* @param ppvFlat Where to store the flat address.
843	* @param pcBits Where to store the 64-bit/32-bit/16-bit indicator.
844	*/
845	VMMDECL(int) SELMValidateAndConvertCSAddrGCTrap(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS, RTGCPTR Addr, PRTGCPTR ppvFlat, uint32_t *pcBits)
846	{
847	if ( eflags.Bits.u1VM
848	\|\| CPUMIsGuestInRealMode(pVCpu))
849	{
850	*pcBits = 16;
851	return selmValidateAndConvertCSAddrRealMode(pVCpu, SelCS, NULL, Addr, ppvFlat);
852	}
853	Assert(!CPUMAreHiddenSelRegsValid(pVCpu));
854	return selmValidateAndConvertCSAddrStd(pVCpu->CTX_SUFF(pVM), pVCpu, SelCPL, SelCS, Addr, ppvFlat, pcBits);
855	}
856	#endif /* IN_RC */
857
858
859	/**
860	* Validates and converts a GC selector based code address to a flat address.
861	*
862	* @returns VBox status code.
863	* @param pVCpu Pointer to the VMCPU.
864	* @param eflags Current eflags
865	* @param SelCPL Current privilege level. Get this from SS - CS might be conforming!
866	* A full selector can be passed, we'll only use the RPL part.
867	* @param SelCS Selector part.
868	* @param pHiddenSel The hidden CS selector register.
869	* @param Addr Address part.
870	* @param ppvFlat Where to store the flat address.
871	*/
872	VMMDECL(int) SELMValidateAndConvertCSAddr(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS, PCCPUMSELREGHID pHiddenCSSel,
873	RTGCPTR Addr, PRTGCPTR ppvFlat)
874	{
875	if ( eflags.Bits.u1VM
876	\|\| CPUMIsGuestInRealMode(pVCpu))
877	return selmValidateAndConvertCSAddrRealMode(pVCpu, SelCS, pHiddenCSSel, Addr, ppvFlat);
878
879	#ifdef IN_RING0
880	Assert(CPUMAreHiddenSelRegsValid(pVCpu));
881	#else
882	/** @todo when we're in 16 bits mode, we should cut off the address as well? (like in selmValidateAndConvertCSAddrRealMode) */
883	if (!CPUMAreHiddenSelRegsValid(pVCpu) \|\| !pHiddenCSSel)
884	return selmValidateAndConvertCSAddrStd(pVCpu->CTX_SUFF(pVM), pVCpu, SelCPL, SelCS, Addr, ppvFlat, NULL);
885	#endif
886	return selmValidateAndConvertCSAddrHidden(pVCpu, SelCPL, SelCS, pHiddenCSSel, Addr, ppvFlat);
887	}
888
889
890	#ifndef IN_RING0
891	/**
892	* Return the cpu mode corresponding to the (CS) selector
893	*
894	* @returns DISCPUMODE according to the selector type (16, 32 or 64 bits)
895	* @param pVM Pointer to the VM.
896	* @param pVCpu Pointer to the VMCPU.
897	* @param Sel The selector.
898	*/
899	static DISCPUMODE selmGetCpuModeFromSelector(PVM pVM, PVMCPU pVCpu, RTSEL Sel)
900	{
901	Assert(!CPUMAreHiddenSelRegsValid(pVCpu));
902
903	/** @todo validate limit! */
904	X86DESC Desc;
905	if (!(Sel & X86_SEL_LDT))
906	Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT];
907	else
908	{
909	/** @todo handle LDT page(s) not present! */
910	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.CTX_SUFF(pvLdt) + pVM->selm.s.offLdtHyper);
911	Desc = paLDT[Sel >> X86_SEL_SHIFT];
912	}
913	return (Desc.Gen.u1DefBig) ? DISCPUMODE_32BIT : DISCPUMODE_16BIT;
914	}
915	#endif /* !IN_RING0 */
916
917
918	/**
919	* Return the cpu mode corresponding to the (CS) selector
920	*
921	* @returns DISCPUMODE according to the selector type (16, 32 or 64 bits)
922	* @param pVCpu Pointer to the VMCPU.
923	* @param eflags Current eflags register
924	* @param Sel The selector.
925	* @param pHiddenSel The hidden selector register.
926	*/
927	VMMDECL(DISCPUMODE) SELMGetCpuModeFromSelector(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL Sel, PCCPUMSELREGHID pHiddenSel)
928	{
929	#ifdef IN_RING0
930	Assert(CPUMAreHiddenSelRegsValid(pVCpu));
931	NOREF(eflags); NOREF(Sel);
932	#else /* !IN_RING0 */
933	if (!CPUMAreHiddenSelRegsValid(pVCpu))
934	{
935	/*
936	* Deal with real & v86 mode first.
937	*/
938	if ( eflags.Bits.u1VM
939	\|\| CPUMIsGuestInRealMode(pVCpu))
940	return DISCPUMODE_16BIT;
941
942	return selmGetCpuModeFromSelector(pVCpu->CTX_SUFF(pVM), pVCpu, Sel);
943	}
944	#endif /* !IN_RING0 */
945	if ( pHiddenSel->Attr.n.u1Long
946	&& CPUMIsGuestInLongMode(pVCpu))
947	return DISCPUMODE_64BIT;
948
949	/* Else compatibility or 32 bits mode. */
950	return pHiddenSel->Attr.n.u1DefBig ? DISCPUMODE_32BIT : DISCPUMODE_16BIT;
951	}
952
953
954	/**
955	* Returns Hypervisor's Trap 08 (\#DF) selector.
956	*
957	* @returns Hypervisor's Trap 08 (\#DF) selector.
958	* @param pVM Pointer to the VM.
959	*/
960	VMMDECL(RTSEL) SELMGetTrap8Selector(PVM pVM)
961	{
962	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
963	}
964
965
966	/**
967	* Sets EIP of Hypervisor's Trap 08 (\#DF) TSS.
968	*
969	* @param pVM Pointer to the VM.
970	* @param u32EIP EIP of Trap 08 handler.
971	*/
972	VMMDECL(void) SELMSetTrap8EIP(PVM pVM, uint32_t u32EIP)
973	{
974	pVM->selm.s.TssTrap08.eip = u32EIP;
975	}
976
977
978	/**
979	* Sets ss:esp for ring1 in main Hypervisor's TSS.
980	*
981	* @param pVM Pointer to the VM.
982	* @param ss Ring1 SS register value. Pass 0 if invalid.
983	* @param esp Ring1 ESP register value.
984	*/
985	void selmSetRing1Stack(PVM pVM, uint32_t ss, RTGCPTR32 esp)
986	{
987	Assert((ss & 1) \|\| esp == 0);
988	pVM->selm.s.Tss.ss1 = ss;
989	pVM->selm.s.Tss.esp1 = (uint32_t)esp;
990	}
991
992
993	#ifndef IN_RING0
994	/**
995	* Gets ss:esp for ring1 in main Hypervisor's TSS.
996	*
997	* Returns SS=0 if the ring-1 stack isn't valid.
998	*
999	* @returns VBox status code.
1000	* @param pVM Pointer to the VM.
1001	* @param pSS Ring1 SS register value.
1002	* @param pEsp Ring1 ESP register value.
1003	*/
1004	VMMDECL(int) SELMGetRing1Stack(PVM pVM, uint32_t *pSS, PRTGCPTR32 pEsp)
1005	{
1006	Assert(pVM->cCpus == 1);
1007	PVMCPU pVCpu = &pVM->aCpus[0];
1008
1009	if (pVM->selm.s.fSyncTSSRing0Stack)
1010	{
1011	RTGCPTR GCPtrTss = pVM->selm.s.GCPtrGuestTss;
1012	int rc;
1013	VBOXTSS tss;
1014
1015	Assert(pVM->selm.s.GCPtrGuestTss && pVM->selm.s.cbMonitoredGuestTss);
1016
1017	# ifdef IN_RC
1018	bool fTriedAlready = false;
1019
1020	l_tryagain:
1021	PVBOXTSS pTss = (PVBOXTSS)(uintptr_t)GCPtrTss;
1022	rc = MMGCRamRead(pVM, &tss.ss0, &pTss->ss0, sizeof(tss.ss0));
1023	rc \|= MMGCRamRead(pVM, &tss.esp0, &pTss->esp0, sizeof(tss.esp0));
1024	# ifdef DEBUG
1025	rc \|= MMGCRamRead(pVM, &tss.offIoBitmap, &pTss->offIoBitmap, sizeof(tss.offIoBitmap));
1026	# endif
1027
1028	if (RT_FAILURE(rc))
1029	{
1030	if (!fTriedAlready)
1031	{
1032	/* Shadow page might be out of sync. Sync and try again */
1033	/** @todo might cross page boundary */
1034	fTriedAlready = true;
1035	rc = PGMPrefetchPage(pVCpu, (RTGCPTR)GCPtrTss);
1036	if (rc != VINF_SUCCESS)
1037	return rc;
1038	goto l_tryagain;
1039	}
1040	AssertMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
1041	return rc;
1042	}
1043
1044	# else /* !IN_RC */
1045	/* Reading too much. Could be cheaper than two separate calls though. */
1046	rc = PGMPhysSimpleReadGCPtr(pVCpu, &tss, GCPtrTss, sizeof(VBOXTSS));
1047	if (RT_FAILURE(rc))
1048	{
1049	AssertReleaseMsgFailed(("Unable to read TSS structure at %08X\n", GCPtrTss));
1050	return rc;
1051	}
1052	# endif /* !IN_RC */
1053
1054	# ifdef LOG_ENABLED
1055	uint32_t ssr0 = pVM->selm.s.Tss.ss1;
1056	uint32_t espr0 = pVM->selm.s.Tss.esp1;
1057	ssr0 &= ~1;
1058
1059	if (ssr0 != tss.ss0 \|\| espr0 != tss.esp0)
1060	Log(("SELMGetRing1Stack: Updating TSS ring 0 stack to %04X:%08X\n", tss.ss0, tss.esp0));
1061
1062	Log(("offIoBitmap=%#x\n", tss.offIoBitmap));
1063	# endif
1064	/* Update our TSS structure for the guest's ring 1 stack */
1065	selmSetRing1Stack(pVM, tss.ss0 \| 1, (RTGCPTR32)tss.esp0);
1066	pVM->selm.s.fSyncTSSRing0Stack = false;
1067	}
1068
1069	*pSS = pVM->selm.s.Tss.ss1;
1070	*pEsp = (RTGCPTR32)pVM->selm.s.Tss.esp1;
1071
1072	return VINF_SUCCESS;
1073	}
1074	#endif /* !IN_RING0 */
1075
1076
1077	/**
1078	* Returns Guest TSS pointer
1079	*
1080	* @returns Pointer to the guest TSS, RTRCPTR_MAX if not being monitored.
1081	* @param pVM Pointer to the VM.
1082	*/
1083	VMMDECL(RTGCPTR) SELMGetGuestTSS(PVM pVM)
1084	{
1085	return (RTGCPTR)pVM->selm.s.GCPtrGuestTss;
1086	}
1087
1088
1089	#ifndef IN_RING0
1090
1091	/**
1092	* Gets the hypervisor code selector (CS).
1093	* @returns CS selector.
1094	* @param pVM Pointer to the VM.
1095	*/
1096	VMMDECL(RTSEL) SELMGetHyperCS(PVM pVM)
1097	{
1098	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
1099	}
1100
1101
1102	/**
1103	* Gets the 64-mode hypervisor code selector (CS64).
1104	* @returns CS selector.
1105	* @param pVM Pointer to the VM.
1106	*/
1107	VMMDECL(RTSEL) SELMGetHyperCS64(PVM pVM)
1108	{
1109	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64];
1110	}
1111
1112
1113	/**
1114	* Gets the hypervisor data selector (DS).
1115	* @returns DS selector.
1116	* @param pVM Pointer to the VM.
1117	*/
1118	VMMDECL(RTSEL) SELMGetHyperDS(PVM pVM)
1119	{
1120	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
1121	}
1122
1123
1124	/**
1125	* Gets the hypervisor TSS selector.
1126	* @returns TSS selector.
1127	* @param pVM Pointer to the VM.
1128	*/
1129	VMMDECL(RTSEL) SELMGetHyperTSS(PVM pVM)
1130	{
1131	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS];
1132	}
1133
1134
1135	/**
1136	* Gets the hypervisor TSS Trap 8 selector.
1137	* @returns TSS Trap 8 selector.
1138	* @param pVM Pointer to the VM.
1139	*/
1140	VMMDECL(RTSEL) SELMGetHyperTSSTrap08(PVM pVM)
1141	{
1142	return pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1143	}
1144
1145	/**
1146	* Gets the address for the hypervisor GDT.
1147	*
1148	* @returns The GDT address.
1149	* @param pVM Pointer to the VM.
1150	* @remark This is intended only for very special use, like in the world
1151	* switchers. Don't exploit this API!
1152	*/
1153	VMMDECL(RTRCPTR) SELMGetHyperGDT(PVM pVM)
1154	{
1155	/*
1156	* Always convert this from the HC pointer since we can be
1157	* called before the first relocation and have to work correctly
1158	* without having dependencies on the relocation order.
1159	*/
1160	return (RTRCPTR)MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3);
1161	}
1162
1163	#endif /* !IN_RING0 */
1164
1165	/**
1166	* Gets info about the current TSS.
1167	*
1168	* @returns VBox status code.
1169	* @retval VINF_SUCCESS if we've got a TSS loaded.
1170	* @retval VERR_SELM_NO_TSS if we haven't got a TSS (rather unlikely).
1171	*
1172	* @param pVM Pointer to the VM.
1173	* @param pVCpu Pointer to the VMCPU.
1174	* @param pGCPtrTss Where to store the TSS address.
1175	* @param pcbTss Where to store the TSS size limit.
1176	* @param pfCanHaveIOBitmap Where to store the can-have-I/O-bitmap indicator. (optional)
1177	*/
1178	VMMDECL(int) SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap)
1179	{
1180	NOREF(pVM);
1181
1182	/*
1183	* The TR hidden register is always valid.
1184	*/
1185	CPUMSELREGHID trHid;
1186	RTSEL tr = CPUMGetGuestTR(pVCpu, &trHid);
1187	if (!(tr & X86_SEL_MASK))
1188	return VERR_SELM_NO_TSS;
1189
1190	*pGCPtrTss = trHid.u64Base;
1191	pcbTss = trHid.u32Limit + (trHid.u32Limit != UINT32_MAX); / be careful. */
1192	if (pfCanHaveIOBitmap)
1193	*pfCanHaveIOBitmap = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1194	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1195	return VINF_SUCCESS;
1196	}
1197
1198
1199
1200	/**
1201	* Notification callback which is called whenever there is a chance that a CR3
1202	* value might have changed.
1203	* This is called by PGM.
1204	*
1205	* @param pVM Pointer to the VM.
1206	* @param pVCpu Pointer to the VMCPU.
1207	*/
1208	VMMDECL(void) SELMShadowCR3Changed(PVM pVM, PVMCPU pVCpu)
1209	{
1210	/** @todo SMP support!! */
1211	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
1212	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu);
1213	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/SELMAll.cpp@ 41829

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